Perovskite / silicon tandem solar cell and method for manufacturing the same

Abstract

The application provides a perovskite / crystalline silicon laminated solar cell with a full silicon wafer size and a preparation method thereof. The perovskite / crystalline silicon laminated solar cell comprises a silicon substrate cell and a perovskite cell which are sequentially stacked, and the perovskite cell comprises a perovskite layer. In the perovskite / crystalline silicon laminated solar cell with a full silicon wafer size, the thickness of the central region of the perovskite layer is less than the thickness of the peripheral region, the conduction between the recombination layer and the window layer can be prevented, the area damage caused by the mask is reduced, and the electrical performance of the perovskite / crystalline silicon laminated solar cell with a full silicon wafer size is ensured. The front transparent conductive layer or the rear transparent conductive layer does not use a mask or uses a very small mask, the effective area is the same as the total area or has a very small difference, and this is helpful for the welding and packaging of subsequent component processes.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of solar cells, and particularly relates to a perovskite / crystalline silicon laminated solar cell with a full wafer size and a preparation method thereof. BACKGROUND

[0002] Organic-inorganic hybrid perovskite solar cells are widely concerned as a new type of high-efficiency and low-cost solar cells worldwide. In just a few years, the photoelectric conversion efficiency of small-area single-junction perovskite cells has rapidly increased from 3.8% in 2009 to more than 26%, and the photoelectric conversion efficiency of small-area perovskite / silicon heterojunction laminated cells has also reached more than 34%. The rapid efficiency development has made it the focus of current photovoltaic research institutions and enterprises. Compared with traditional thin-film solar cells (copper indium gallium selenide, cadmium telluride, etc.), perovskite solar cells have the advantages of high conversion efficiency, simple preparation process, and low cost potential, and have become the most promising thin-film solar cell technology. By adjusting the composition ratio of the precursor solution, the spectral response cutoff wavelength of the solar cell can be controlled, making it the most ideal top cell absorbing layer material.

[0003] Silicon heterojunction solar cell technology has the advantages of simple process, low preparation temperature, high conversion efficiency, and symmetrical structure, and is considered as the third generation of battery technology after PERC cells. The high infrared band absorption, strong weak light effect, and p-i-n matching structure of the silicon heterojunction cell make it one of the best choices for bottom cells. The "perovskite / silicon heterojunction" laminated cell structure formed by perovskite cells (top cells) and silicon-based heterojunction cells (bottom cells) can realize the spectral distribution and absorption of sunlight, and is expected to obtain higher conversion efficiency.

[0004] Current perovskite / silicon heterojunction laminated cells mainly target small-area devices, and the substrate size is generally 2cm x 2cm. The effective area of 1cm x 1cm in the center is tested by a mask method. In the perovskite / silicon heterojunction laminated cell, the window layer is generally a TCO material prepared by a PVD process, and the perovskite top cell and the silicon-based heterojunction bottom cell are connected by a composite layer, which is also a TCO material prepared by a PVD process. The window layer and the composite layer are isolated by the perovskite layer to achieve insulation. Due to the use of a mask method, the area defined by the window layer and the composite layer only needs to be greater than or equal to the effective area, and does not need to reach the edge of the substrate.

[0005] However, with the development of technology, the perovskite / silicon-based heterojunction stacked battery of full wafer size has become the main research object at present, although the previous mask method to define the effective area can still meet the electrical performance test requirements, but it has been unable to meet the future component packaging requirements. When the component is packaged, the perovskite / silicon-based heterojunction stacked battery needs to be tested for electrical performance on the whole wafer area without a mask, so on the perovskite / silicon-based heterojunction stacked battery of full wafer size, each film layer needs to be as close to the full wafer size as possible. Since the window layer and the composite layer are both TCO materials prepared by PVD process, the PVD process will have a certain plating, which also greatly increases the probability of direct contact between the window layer and the composite layer, resulting in the risk of short circuit of the perovskite / silicon-based heterojunction stacked battery of full wafer size. SUMMARY

[0006] In view of the problems existing in the prior art, the present application provides a perovskite / silicon stacked solar cell of full wafer size and a preparation method thereof.

[0007] Specifically, the present application relates to the following aspects:

[0008] In one aspect, the present application provides a perovskite / silicon stacked solar cell of full wafer size, comprising a silicon-based base cell and a perovskite cell which are sequentially stacked, wherein the perovskite cell comprises a perovskite layer;

[0009] The perovskite layer completely covers the silicon-based base cell.

[0010] The perovskite layer comprises a central region and a peripheral region, the central region refers to a region on the silicon substrate with a projection distance from the edge of the silicon-based base cell greater than or equal to 2mm, and the peripheral region refers to a region on the silicon substrate with a projection distance from the edge of the silicon-based base cell less than 2mm, wherein the average thickness of the central region is less than the average thickness of the peripheral region.

[0011] Further, the difference between the average thickness of the peripheral region and the average thickness of the central region is greater than or equal to 100nm and less than or equal to 4000nm, preferably greater than or equal to 200nm and less than or equal to 2000nm.

[0012] Further, the peripheral region comprises a first peripheral region and a second peripheral region, the first peripheral region refers to a region on the silicon substrate with a projection distance from the edge of the silicon-based base cell greater than 1mm and less than 2mm, and the second peripheral region refers to a region on the silicon substrate with a projection distance from the edge of the silicon-based base cell less than or equal to 1mm.

[0013] The difference between the average thickness of the first peripheral region and the average thickness of the central region is greater than or equal to 100 nm and less than or equal to 2000 nm, preferably greater than or equal to 200 nm and less than or equal to 1000 nm;

[0014] The difference between the average thickness of the second peripheral region and the average thickness of the central region is greater than or equal to 200 nm and less than or equal to 4000 nm, preferably greater than or equal to 400 nm and less than or equal to 2000 nm.

[0015] Further, the perovskite / crystalline silicon tandem solar cell further comprises a composite layer between the silicon substrate cell and the perovskite cell, the inner edge of the mask region of the composite layer on the silicon substrate projects a distance from the edge of the silicon substrate cell less than or equal to 1 mm.

[0016] Further, the perovskite cell comprises a hole transport layer, a perovskite layer, an electron transport layer and a front transparent conductive layer arranged in sequence.

[0017] Further, the inner edge of the mask region of the front transparent conductive layer on the silicon substrate projects a distance from the edge of the silicon substrate cell less than or equal to 1 mm.

[0018] Further, the perovskite layer further extends to the side of the perovskite / crystalline silicon tandem solar cell to cover at least part of the side of the composite layer and the silicon substrate cell.

[0019] Further, the perovskite layer further extends to the side of the perovskite / crystalline silicon tandem solar cell to cover at least part of the side of the hole transport layer.

[0020] Further, the perovskite layer further extends to partially cover at least part of the back of the silicon substrate cell.

[0021] Further, the silicon substrate cell is a heterojunction cell, a tunnel oxide passivated contact cell, or a back contact cell.

[0022] Further, the heterojunction cell comprises an N-type amorphous silicon layer, a first intrinsic amorphous silicon layer, an N-type crystalline silicon substrate, a second intrinsic amorphous silicon layer, a P-type amorphous silicon layer and a back transparent conductive layer arranged in sequence.

[0023] Further, the inner edge of the mask region of the back transparent conductive layer on the silicon substrate projects a distance from the edge of the silicon substrate cell less than or equal to 1 mm.

[0024] Further, the N-type crystalline silicon substrate is a whole or half piece of silicon wafer of M6, M10 or M12.

[0025] In another aspect, the present application also provides a perovskite / crystalline silicon tandem solar cell, comprising any one of the above-mentioned perovskite / crystalline silicon tandem solar cells.

[0026] In another aspect, the present application also provides a method for preparing a full wafer size perovskite / crystalline silicon tandem solar cell, comprising the following steps:

[0027] preparing a silicon substrate cell;

[0028] forming a composite layer and a hole transport layer on the silicon substrate cell in sequence;

[0029] preparing a perovskite layer on the hole transport layer, so that the perovskite layer completely covers the silicon substrate cell;

[0030] forming an electron transport layer and a front transparent conductive layer on the perovskite layer in sequence;

[0031] wherein the perovskite layer comprises a central region and a peripheral region, the central region refers to a region on the silicon substrate with a projection distance from the edge of the silicon substrate cell greater than or equal to 2 mm, and the peripheral region refers to a region on the silicon substrate with a projection distance from the edge of the silicon substrate cell less than 2 mm, wherein the average thickness of the central region is less than the average thickness of the peripheral region.

[0032] Further, the projection distance of the mask region of the composite layer on the silicon substrate from the edge of the silicon substrate cell is less than or equal to 1 mm.

[0033] Further, the projection distance of the mask region of the front transparent conductive layer on the silicon substrate from the edge of the silicon substrate cell is less than or equal to 1 mm.

[0034] Further, the perovskite layer is prepared by slot coating, doctor blade coating, spray coating, inkjet printing, transfer printing or screen printing.

[0035] Further, the perovskite / crystalline silicon tandem solar cell prepared by the method is any one of the above-mentioned perovskite / crystalline silicon tandem solar cells.

[0036] The central region thickness of the perovskite layer in the full wafer size perovskite / crystalline silicon tandem solar cell of the present application is less than the peripheral region thickness, which can prevent the conduction of the composite layer and the window layer, thereby reducing the area damage caused by the mask and ensuring the electrical performance of the full wafer size perovskite / crystalline silicon tandem solar cell. The front transparent conductive layer or the rear transparent conductive layer of the present application does not use a mask or has a very small mask, and the effective area is the same as the total area or has a very small difference, which is helpful for the subsequent welding and packaging of the module process. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1A schematic diagram of a calculation method for the average thickness of a perovskite layer of a perovskite tandem cell having a perovskite structure bottom cell;

[0038] Figure 2 A schematic diagram of a perovskite / silicon-based heterojunction tandem cell structure of Comparative Example 1;

[0039] Figure 3 A schematic diagram of a perovskite / silicon-based heterojunction tandem cell structure of Comparative Example 2;

[0040] Figure 4 A schematic diagram of a perovskite / silicon-based heterojunction tandem cell structure of Example 1;

[0041] Figure 5 A schematic diagram of a perovskite / silicon-based heterojunction tandem cell structure of Example 2;

[0042] Figure 6 A schematic diagram of a perovskite / silicon-based heterojunction tandem cell structure of Example 3;

[0043] Figure 7 A schematic diagram of a structure of a perovskite layer surface of a perovskite tandem cell.

[0044] Reference signs:

[0045] 1-1 N-type crystalline silicon substrate, 1-2 first intrinsic amorphous silicon layer, 1-3 P-type amorphous silicon layer, 1-4 N-type amorphous silicon layer, 1-5 rear transparent conductive layer, 1-6 second intrinsic amorphous silicon layer, 2-1 composite layer, 3-1 hole transport layer, 3-2 perovskite layer, 3-3 electron transport layer, 3-4 front transparent conductive layer, 4-1 front metal electrode, 4-2 rear metal electrode, 6-1 central region, 6-2 first peripheral region, 6-3 second peripheral region. DETAILED DESCRIPTION

[0046] The present application will be further described with reference to the following examples. It should be understood that the examples are only for further illustrating and explaining the present application, and are not intended to limit the present application.

[0047] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present application, illustrative methods and materials are described below. However, if there is a conflict between the definitions in the specification including that of the preceding claimed application and that of the prior art, the specification, including that of the preceding claimed application, is intended to prevail. Furthermore, all patents, patent applications, publications, and descriptions mentioned herein are incorporated by reference in their entirety for the

[0048] In the present application, the average thickness is the average of the thicknesses measured at two or more test points in the corresponding region. When measuring the average thickness of the perovskite layer, for example, two, three, four, five, six, seven, eight, nine, or ten or more test points can be randomly selected in the corresponding region of the perovskite layer, such as the central region or the peripheral region, to measure and calculate the average thickness. These test points can be at any location in the central region or the peripheral region, or they can be dispersed in a certain area, such as being dispersed in an area of 1 mm 2 , 2 mm 2 , 3 mm 2 , 5 mm 2 , 7 mm 2 , 9 mm 2 , 1 cm 2 , 2 cm 2 , 3 cm 2 , 4 cm 2 , 5 cm 2 , 6 cm 2 , 7 cm 2 , 8 cm 2 , 9 cm 2 , 10 cm 2 , etc.

[0049] In the present application, the thickness of the perovskite layer can be measured by methods known in the art for measuring thickness, for example, by SEM.

[0050] In a specific embodiment, the silicon substrate cell has a textured structure, and the thickness of the perovskite layer is not uniform at different locations. When measuring the thickness of the perovskite layer, the thinnest location from the tip of the pyramid to the upper surface of the perovskite layer within the field of view is denoted as Tmin, and the thickest location from the base of the pyramid to the upper surface of the perovskite layer within the field of view is denoted as Tmax, and the average thickness of the perovskite layer is (Tmin+Tmax) / 2. As shown in FIG. A of Figure 1 , Tmin is 566 nm, Tmax is 1070 nm, and the average thickness is 818 nm. As shown in FIG. B of Figure 1 , Tmin is 770 nm, Tmax is 1260 nm, and the average thickness is 1015 nm. As shown in FIG. C of Figure 1 , Tmin is 960 nm, Tmax is 1600 nm, and the average thickness is 1280 nm.

[0051] Those skilled in the art can understand that, for a silicon substrate cell with a non-textured structure, the average thickness of the perovskite layer can be measured by selecting the average of the thicknesses measured at two or more test points as described above, or by using the measurement method described above for the textured structure.

[0052] In the prior art, when a full-silicon wafer size perovskite / silicon-based heterojunction stacked cell is prepared, the edge region is relatively thin or not completely covered, and the composite layer and the window layer are conductive. To prevent conduction between the window layer and the composite layer, two implementation methods are generally used: one is to mask the window layer and the composite layer, which loses a certain power generation area. This method reduces the effective power generation area and reduces the power generation efficiency of the full-silicon wafer size perovskite / silicon-based heterojunction stacked cell; the other is not to mask the window layer and the composite layer, and to cut the edge after all processes are completed. This method damages the edge passivation layer of the bottom cell, causing serious leakage of the bottom cell and affecting the power generation efficiency of the full-silicon wafer size perovskite / silicon-based heterojunction stacked cell. The second method sometimes performs special passivation or insulation treatment on the cut edge to reduce the conduction between the window layer and the composite layer, but the passivation effect needs to be further verified.

[0053] To solve the problems in the prior art, the present application provides a full-silicon wafer size perovskite / crystalline silicon stacked solar cell. The full-silicon wafer size perovskite / crystalline silicon stacked solar cell described in the present application refers to a perovskite layer completely covering a silicon base cell.

[0054] As shown in Figures 2-6 The perovskite / crystalline silicon stacked solar cell of the present application includes a silicon base cell and a perovskite cell which are sequentially stacked, wherein the perovskite cell includes a perovskite layer. Further, the perovskite / crystalline silicon stacked solar cell further includes a composite layer 2-1 located between the silicon base cell and the perovskite cell. The perovskite cell includes a hole transport layer 3-1, a perovskite layer 3-2, an electron transport layer 3-3, and a front transparent conductive layer 3-4 (i.e., the window layer mentioned herein) which are sequentially stacked.

[0055] The perovskite layer 3-2 completely covers the silicon base cell. As can be understood by those skilled in the art, in general, the composite layer 2-1 completely covers the silicon base cell, the hole transport layer 3-1 completely covers the composite layer 2-1, and the perovskite layer 3-2 completely covers the hole transport layer. As shown in Figure 7 The perovskite layer 3-2 includes a central region 6-1 and a peripheral region, the central region 6-1 refers to a region on the silicon base with a projection distance from the edge of the silicon base cell greater than or equal to 2 mm, and the peripheral region refers to a region on the silicon base with a projection distance from the edge of the silicon base cell less than 2 mm, wherein the average thickness of the central region 6-1 is less than the average thickness of the peripheral region.

[0056] The thickness of the center region of the perovskite layer 3-2 is less than the thickness of the peripheral region, which prevents the conduction of the two conductive layers on the perovskite (for example, the composite layer 2-1 and the window layer), thereby reducing the area damage caused by the mask and improving the overall conversion efficiency of the perovskite / crystalline silicon stacked solar cell.

[0057] In one specific embodiment, the difference between the average thickness of the peripheral region and the average thickness of the center region is greater than or equal to 100 nm and less than or equal to 4000 nm, for example, it can be 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1500 nm, 1600 nm, 1700 nm, 1800 nm, 1900 nm, 2000 nm, 2100 nm, 2200 nm, 2300 nm, 2400 nm, 2500 nm, 2600 nm, 2700 nm, 2800 nm, 2900 nm, 3000 nm, 3100 nm, 3200 nm, 3300 nm, 3400 nm, 3500 nm, 3600 nm, 3700 nm, 3800 nm, 3900 nm, 4000 nm, and any value between these values.

[0058] In one specific embodiment, the difference between the average thickness of the peripheral region and the average thickness of the center region is greater than or equal to 200 nm and less than or equal to 2000 nm.

[0059] As shown in Figure 7 Further, in order to reduce the difficulty of the preparation process, the peripheral region further includes a first peripheral region 6-2 and a second peripheral region 6-3, the first peripheral region 6-2 refers to a region on the silicon substrate with a projected distance from the edge of the silicon substrate cell greater than 1 mm and less than 2 mm, and the second peripheral region 6-3 refers to a region on the silicon substrate with a projected distance from the edge of the silicon substrate cell less than or equal to 1 mm.

[0060] In one specific embodiment, the difference between the average thickness of the first peripheral region 6-2 and the average thickness of the central region 6-1 is greater than or equal to 100 nm and less than or equal to 2000 nm, for example, it can be 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1500 nm, 1600 nm, 1700 nm, 1800 nm, 1900 nm, 2000 nm, and any value between these values; the difference between the average thickness of the second peripheral region 6-3 and the average thickness of the central region 6-1 is greater than or equal to 200 nm and less than or equal to 4000 nm, for example, it can be 200 nm. 0nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm, 1100nm, 1200nm, 1300nm, 1400nm, 1500nm, 1600nm, 1700nm, 1800nm, 1900nm, 2000nm, 2100nm, 2200nm, 2300nm, 2400nm, 2500nm, 2600nm, 2700nm, 2800nm, 2900nm, 3000nm, 3100nm, 3200nm, 3300nm, 3400nm, 3500nm, 3600nm, 3700nm, 3800nm, 3900nm, 4000nm, and any value between these values.

[0061] In one specific embodiment, the difference between the average thickness of the first peripheral region 6-2 and the average thickness of the central region 6-1 is greater than or equal to 200 nm and less than or equal to 1000 nm, and the difference between the average thickness of the second peripheral region 6-3 and the average thickness of the central region 6-1 is greater than or equal to 400 nm and less than or equal to 2000 nm.

[0062] Furthermore, such as Figure 4 and Figure 5 As shown, the perovskite layer 3-2 can also extend to the side of the perovskite / crystalline silicon tandem solar cell to cover at least a portion of the hole transport layer 3-1, the composite layer 2-1, and the side of the silicon substrate cell.

[0063] like Figure 5 As shown, when the above extension degree is relatively high, the perovskite layer 3-2 can be further extended to partially cover at least a portion of the back side of the silicon substrate cell.

[0064] When the perovskite layer 3-2 forms a certain coverage on the edge and back of the tandem cell, the insulation effect between the window layer and the back transparent conductive layer can be achieved at the same time, thereby further reducing the risk of short circuit of the tandem cell and improving the stability of the preparation process.

[0065] In one specific embodiment, the inner edge of the mask area of the front transparent conductive layer 3-4 projects on the silicon substrate at a distance from the edge of the silicon substrate cell, i.e., the width of the mask area is less than or equal to 1 mm, for example, it can be 1 mm, 900 nm, 800 nm, 700 nm, 600 nm, 500 nm, 400 nm, 300 nm, 200 nm, 100 nm, 50 nm, 20 nm, 10 nm, 0, and any value between these values.

[0066] In one specific embodiment, the inner edge of the mask area of the composite layer 2-1 projects on the silicon substrate at a distance from the edge of the silicon substrate cell, i.e., the width of the mask area is less than or equal to 1 mm, for example, it can be 1 mm, 900 nm, 800 nm, 700 nm, 600 nm, 500 nm, 400 nm, 300 nm, 200 nm, 100 nm, 50 nm, 20 nm, 10 nm, 0, and any value between these values.

[0067] The silicon substrate cell of the present application can be various silicon substrate cells suitable for perovskite tandem cells in the art, such as heterojunction cells, tunnel oxide passivation contact cells, or back contact cells.

[0068] In one specific embodiment, the silicon substrate cell is a heterojunction cell, such as Figures 2-6 As shown, it comprises an N-type amorphous silicon layer 1-4, a first intrinsic amorphous silicon layer 1-2, an N-type crystalline silicon substrate 1-1, a second intrinsic amorphous silicon layer 1-6, a P-type amorphous silicon layer 1-3, and a back transparent conductive layer 1-5, which are sequentially stacked.

[0069] Among them, the N-type crystalline silicon substrate can be various models and sizes known in the art, such as a whole or half of a silicon wafer of M6, M10, or M12.

[0070] In one specific embodiment, the inner edge of the mask area of the back transparent conductive layer 1-5 projects on the silicon substrate at a distance from the edge of the silicon substrate cell, i.e., the width of the mask area is less than or equal to 1 mm, for example, it can be 1 mm, 900 nm, 800 nm, 700 nm, 600 nm, 500 nm, 400 nm, 300 nm, 200 nm, 100 nm, 50 nm, 20 nm, 10 nm, 0, and any value between these values.

[0071] The projection distance of the mask area of the front transparent conductive layer 3-4, the composite layer 2-1, or the rear transparent conductive layer 1-5 on the silicon substrate is less than or equal to 1 mm from the edge of the silicon substrate cell, so that the effective area is the same as or slightly different from the total area, which can reduce the impact on the power generation area. Moreover, the front transparent conductive layer 2-1 or the rear transparent conductive layer 1-5 of the present application does not use a mask or the mask is very small, which is helpful for the subsequent assembly process of welding and packaging.

[0072] The materials and thicknesses of the composite layer 2-1, the hole transport layer 3-1, the electron transport layer 3-3, and the front transparent conductive layer 3-4 of the present application can all use conventional materials and thicknesses in the art, which are not further limited here.

[0073] Specifically, the material of the hole transport layer is organic or inorganic. When it is organic, the hole transport layer is Spiro-TTB, Spiro-OMeTAD, Spiro-TAD, PTAA, or PEDOT-PSS. When the hole transport layer is inorganic, the material of the hole transport layer is NiO x , NiMgO x , CoO, FeO, NiMgO x , V2O5, MoO3, Cr2O3, or a Cu(l)-containing compound.

[0074] The composite layer can enable the photo-generated carriers to cross from the perovskite layer to the silicon substrate cell, and is usually selected from one or more stacked layers of TCO materials such as ITO, IWO, IZO, ITiO, AZO, GZO, FTO, IWO, and graphene.

[0075] The material of the electron transport layer is generally C60, PCBM, SnO2, etc.

[0076] The perovskite layer generally has a band gap of 1.6 eV or more, and the material can be selected from substances with an ABX3 structure, where A is selected from one or more of Cs, Rb, CH3NH3, HC(NH2)2, CH3(CH2)3NH3, (C6H5)(CH2)2NH3; B is selected from any one of Pb, Sn, and Ge; and X is halogen. Preferably, A is of the type of inorganic and organic ion hybridization, such as (Cs 0.15 FA 0.85 )Pb(I 0.7 Br 0.3 )3, etc.

[0077] Further, a buffer layer can be provided between the perovskite layer 3-2 and the hole transport layer 3-1 to improve the conversion efficiency or stability of the cell.

[0078] The surface of the front transparent conductive layer 3-4 can also be provided with an anti-reflection film layer to improve the photoelectric conversion efficiency of the perovskite / silicon heterojunction stacked solar cell.

[0079] The application also provides a photovoltaic module comprising any of the perovskite / crystalline silicon stacked solar cells described above.

[0080] The application also provides a method for preparing a full-silicon wafer-sized perovskite / crystalline silicon stacked solar cell, comprising the following steps:

[0081] Preparation of a silicon substrate cell;

[0082] Sequential formation of a composite layer and a hole transport layer on the silicon substrate cell;

[0083] Preparation of a perovskite layer on the hole transport layer, so that the perovskite layer completely covers the silicon substrate cell;

[0084] Sequential preparation of an electron transport layer and a front transparent conductive layer on the perovskite layer;

[0085] The perovskite layer comprises a central region and a peripheral region, the central region refers to a region on the silicon substrate with a projection distance from the edge of the silicon substrate cell greater than or equal to 2 mm, and the peripheral region refers to a region on the silicon substrate with a projection distance from the edge of the silicon substrate cell less than 2 mm, wherein the average thickness of the central region is less than the average thickness of the peripheral region.

[0086] The perovskite layer can be prepared by slot coating, doctor blade coating, spray coating, inkjet printing, transfer printing or screen printing, as long as the average thickness of the central region is less than the average thickness of the peripheral region.

[0087] In a specific embodiment, the perovskite layer is prepared by slot coating. Using slot coating process, the material utilization rate is about 95%. On the one hand, it can reduce material waste and save material cost. On the other hand, it can reduce environmental pollution caused by perovskite solution scrap.

[0088] In a specific embodiment, the front transparent conductive layer is prepared such that the projection distance of the mask area of the front transparent conductive layer on the silicon substrate from the edge of the silicon substrate cell is less than or equal to 1 mm.

[0089] In a specific embodiment, the composite layer is prepared such that the projection distance of the mask area of the composite layer on the silicon substrate from the edge of the silicon substrate cell is less than or equal to 1 mm.

[0090] In one specific embodiment, the perovskite / crystalline silicon tandem solar cell prepared by the preparation method is any one of the perovskite / crystalline silicon tandem solar cells described above.

[0091] Examples

[0092] Test method of average thickness: Since the silicon-based substrate cell has a textured structure, the thickness of the perovskite layer at different positions is not uniform. When testing the thickness of the perovskite layer, the thinnest position of the pyramid tip to the upper surface of the perovskite layer within the field of view is recorded as Tmin, and the thickest position of the pyramid bottom to the upper surface of the perovskite layer within the field of view is recorded as Tmax, and the average thickness of the perovskite layer is (Tmin+Tmax) / 2. The thickness is measured by SEM.

[0093] Comparative Example 1

[0094] Large-area perovskite / silicon-based heterojunction tandem cell with large-size mask for each TCO layer is as shown in Figure 2 The specific preparation method is as follows.

[0095] 1.1, Preparation of the bottom cell.

[0096] 1.1.1, N-type crystalline silicon substrate 1-1

[0097] Commercial M10 size (182 mm x 182 mm) N-type silicon wafer with resistivity of 5 Ω·cm and thickness of 170 μm is used. The silicon wafer is subjected to polishing, texturing and cleaning procedures in sequence to obtain a small textured surface with a textured pyramid height of ≤2 μm.

[0098] 1.1.2, Intrinsic amorphous silicon layer

[0099] PECVD is used to deposit 5 nm of intrinsic amorphous silicon passivation layer on both sides of the silicon wafer to form front and back passivation layer films, i.e. first intrinsic amorphous silicon layer 1-2 and second intrinsic amorphous silicon layer 1-6.

[0100] 1.1.3, N-type amorphous silicon layer 1-4

[0101] PECVD is used to deposit 5 nm of N-type amorphous silicon layer with phosphorus doping (doping concentration 10 19-20 cm -3 ) on the front side of the silicon wafer to form a front field structure;

[0102] 1.1.4, P-type amorphous silicon layer 1-3

[0103] PECVD is used to deposit 5 nm of P-type amorphous silicon layer with boron doping (doping concentration 10 19-20 cm -3 ) on the back side of the silicon wafer to form a back emitter structure.

[0104] 1.1.5, Back transparent conductive layer 1-5

[0105] A 120nm ITO layer is prepared by magnetron sputtering method to realize the collection and transmission of photo-generated carriers to the back metal electrode. A pre-designed mask plate is used when preparing the back transparent conductive layer, so that the back transparent conductive layer is patterned according to the design scheme, and the patterned size is 160mm x 160mm.

[0106] 1.1.6, Composite layer 2-1

[0107] A 10nm ITO layer is prepared by magnetron sputtering method to realize the crossing of photo-generated carriers from the perovskite layer to the silicon heterojunction. A pre-designed mask plate is used when preparing the composite layer, so that the composite layer is patterned according to the design scheme, and the patterned size is 160mm x 160mm. The position of the composite layer is symmetrically opposite to the back transparent conductive layer, i.e. the center point of the projection position of the composite layer, the center point of the back transparent conductive layer and the center point of the silicon wafer coincide, and the shapes of the composite layer, the back transparent conductive layer and the silicon wafer are similar patterns.

[0108] 1.2, Top cell preparation

[0109] 1.2.1, Hole transport layer 3-1

[0110] A 30nm NiO layer is prepared by magnetron sputtering as a hole transport layer. x

[0111] 1.2.2, Perovskite layer 3-2

[0112] The perovskite layer generally has a band gap of about 1.65eV, and a (Cs 0.15 FA 0.85 )Pb(I 0.7 Br 0.3 )3 component system is selected. The appropriate materials are weighed according to the molar ratio and dissolved in a mixed solution of DMF and DMSO with a concentration of 1.5M. Then a spin coating process is used, the rotation speed is set to 1500rpm, and the spin coating time is 30s. After coating, rapid vacuum treatment is performed, and then the sample is taken out and placed on a 100℃ hot stage for annealing for 30min to obtain the perovskite layer 3-2.

[0113] Due to the shear force and centrifugal force of spin coating, the battery prepared by this method has no thick edge effect, and the middle region is thicker than the edge region. According to SEM test, the average thickness of the perovskite layer at the center position of the center region is 1500nm, the average thickness of the perovskite layer at a distance of 2mm from the edge is 700nm, and the average thickness of the perovskite layer at a distance of 1mm from the edge is 500nm.

[0114] 1.2.3, Electron transport layer 3-3

[0115] ​First, a 25nm C layer was prepared by evaporation. 60 Then, a 16nm TiO2 layer was prepared by ALD at 105℃ for 160 cycles to realize the vertical transport of carriers.

[0116] 1.2.4, front transparent conductive layer 3-4

[0117] IZO was prepared by magnetron sputtering to form a 100nm front transparent conductive film and anti-reflection film, so as to realize the horizontal transport of electrons to the front metal electrode 4-1. A pre-designed mask was used when preparing the front transparent conductive layer, so that the front transparent conductive layer was patterned according to the design scheme, and the patterned size was 160mm x 160mm. The position of the composite layer was symmetric to the back transparent conductive layer, i.e. the center point of the projection position of the composite layer, the center point of the back transparent conductive layer and the center point of the silicon wafer coincided, and the shapes of the composite layer, the back transparent conductive layer and the silicon wafer were similar patterns.

[0118] 1.2.5, front metal electrode 4-1 and back metal electrode 4-2

[0119] Silver grid lines with a height of 40μm were printed on the upper and lower surfaces by screen printing as the front metal electrode 4-1 and the back metal electrode 4-2 to collect current and form a complete perovskite / silicon heterojunction stacked solar cell.

[0120] 1.2.6, adding a surface anti-reflection film layer on the front transparent conductive layer, and preparing a 120nm SiN layer by electron beam evaporation x to improve the photoelectric conversion efficiency of the perovskite / silicon heterojunction stacked solar cell.

[0121] Comparative Example 2

[0122] The perovskite layer was prepared by conventional spin coating, and the large-area perovskite / silicon-based heterojunction stacked solar cell with small-size mask of each TCO layer was as shown in Figure 3 The specific preparation method is as follows.

[0123] 2.1, preparation of the bottom cell.

[0124] 2.1.1-2.1.4 are the same as 1.1.1-1.1.4.

[0125] 2.1.5, back transparent conductive layer 1-5

[0126] A 120nm ITO layer was prepared by magnetron sputtering to realize the collection and transport of photo-generated carriers to the back metal electrode. A pre-designed mask was used when preparing the back transparent conductive layer, so that the back transparent conductive layer was patterned according to the design scheme, and the patterned size was 180mm x 180mm.

[0127] 2.1.6, composite layer 2-1

[0128] A 10 nm ITO layer prepared by magnetron sputtering method is used to realize the crossing of photo-generated carriers from the perovskite layer to the silicon heterojunction. A pre-designed mask plate is used when preparing the composite layer, so that the composite layer is patterned according to the design scheme, and the patterned size is 180 mm x 180 mm. The position of the composite layer is relatively symmetrical to the back transparent conductive layer, that is, the center point of the projection position of the composite layer, the center point of the back transparent conductive layer and the center point of the silicon wafer coincide, and the shapes of the composite layer, the back transparent conductive layer and the silicon wafer are similar patterns.

[0129] 2.2, top cell preparation, same as 1.2.

[0130] 2.2.1-2.2.3, same as 1.1.1-1.2.3.

[0131] According to the SEM test, the average thickness of the perovskite layer at the center position of the center area is 1500 nm, the average thickness of the perovskite layer at a distance of 2 mm from the edge is 700 nm, and the average thickness of the perovskite layer at a distance of 1 mm from the edge is 500 nm.

[0132] 2.2.4, front transparent conductive layer 3-4

[0133] IZO of 100 nm is prepared by magnetron sputtering method to form a front transparent conductive film and an anti-reflection film, so as to realize the lateral transport of electrons to the front metal electrode 4-1. A pre-designed mask plate is used when preparing the front transparent conductive layer, so that the front transparent conductive layer is patterned according to the design scheme, and the patterned size is 180 mm x 180 mm. The position of the composite layer is relatively symmetrical to the back transparent conductive layer, that is, the center point of the projection position of the composite layer, the center point of the back transparent conductive layer and the center point of the silicon wafer coincide, and the shapes of the composite layer, the back transparent conductive layer and the silicon wafer are similar patterns.

[0134] 2.2.5, same as 1.2.5.

[0135] 2.2.6, same as 1.2.6.

[0136] Example 1

[0137] A large-area perovskite / silicon-based heterojunction tandem cell is shown in Figure 4 The perovskite layer has a thick edge, and the specific preparation method is as follows.

[0138] 3.1, bottom cell preparation.

[0139] 3.1.1-3.1.4, same as 1.1.1-1.1.4.

[0140] 3.1.5, back transparent conductive layer 1-5

[0141] A 120 nm ITO layer is prepared by a magnetron sputtering method to realize the collection and transmission of photo-generated carriers to the back metal electrode. A pre-designed mask plate is used when the transparent conductive layer is prepared, so that the rear transparent conductive layer is patterned according to the design scheme, and the patterned rear transparent conductive layer is ≤0.5 mm away from the edge of the silicon wafer substrate.

[0142] 3.1.6, composite layer 2-1

[0143] A 10 nm ITO layer is prepared by a magnetron sputtering method to realize the crossing of photo-generated carriers from the perovskite layer to the silicon heterojunction. A pre-designed mask plate is used when the composite layer is prepared, so that the composite layer is patterned according to the design scheme, and the outermost edge of the patterned composite layer is ≤0.5 mm away from the edge of the silicon wafer substrate.

[0144] 3.2, top cell preparation

[0145] 3.2.1, same as 1.2.1.

[0146] 3.2.2, perovskite layer 3-2.

[0147] The perovskite layer is selected from (Cs 0.15 FA 0.85 )Pb(I 0.7 Br 0.3 )3 component system, and appropriate materials are weighed according to the molar ratio and dissolved in a mixed solution of DMF and DMSO with a concentration of 1.0 M. Then a slot coating process is used, and the coating width of the slot coating knife head is 180 mm, which is slightly smaller than the full silicon wafer size of 182 mm. The liquid feeding speed is set to 15 μL / s, the knife head advancing speed is 12 mm / s, and the perovskite precursor is coated on the bottom cell, then vacuumized quickly, and taken out to be annealed on a 100℃ hot stage for 30 min to obtain the perovskite layer. During the quick vacuumization process, by designing the gas field (gas is extracted from below or around to ensure that the gas above the perovskite layer flows from the center to the periphery), the solvent in the edge region of the perovskite liquid film can have a greater evaporation speed, so that the thickness of the perovskite in the edge region is greater than that in the center region.

[0148] According to SEM test, the average thickness of the perovskite layer in the center region more than 2 mm away from the edge is 700 nm, the average thickness of the perovskite layer in the first peripheral region more than 1 mm and less than 2 mm away from the edge is 900 nm, and the average thickness of the perovskite layer in the second peripheral region less than or equal to 1 mm away from the edge is 1500 nm.

[0149] 3.2.3, same as 1.2.3.

[0150] 3.2.4, front transparent conductive layer 3-4

[0151] IZO of 100 nm is prepared by magnetron sputtering method to form front transparent conductive film and anti-reflection film, so as to realize electronic lateral transport to front metal electrode 4-1. When the front transparent conductive layer is prepared, a pre-designed mask plate is used, so that the front and rear transparent conductive layers are patterned according to the design scheme, and the outermost edge of the patterned front transparent conductive layer is ≤0.5 mm away from the edge of the silicon wafer substrate.

[0152] 3.2.5, same as 1.2.5.

[0153] 3.2.6, same as 1.2.6.

[0154] Example 2

[0155] Large-area perovskite / silicon-based heterojunction tandem cell is shown in Figure 5 The perovskite layer covers the edge region, and the specific preparation method is as follows.

[0156] 4.1, bottom cell preparation. Same as 3.1

[0157] 4.2, top cell preparation.

[0158] 4.2.1, same as 1.2.1.

[0159] 4.2.2, perovskite layer 3-2

[0160] The perovskite layer is selected from (Cs 0.15 FA 0.85 )Pb(I 0.7 Br 0.3 )3 component system, and appropriate materials are weighed according to the molar ratio and dissolved in a mixed solution of DMF and DMSO with a concentration of 1.0 M. Then a slot coating process is used, and the coating width of the slot coating knife head is 182 mm, which is the same as the size of the full silicon wafer. The liquid feeding speed is set to 15 μL / s, the knife head advancing speed is 11 mm / s, and the perovskite precursor is coated on the bottom cell, then rapid vacuum treatment is carried out, and after taking out, it is placed on a 100℃ hot table for annealing for 30 min to obtain the perovskite layer. During the rapid vacuum treatment, through the design of gas field (gas is extracted from below or around to ensure that the gas above the perovskite layer flows from the center to the periphery), the solvent in the edge region of the perovskite liquid film can have a greater evaporation speed, so that the thickness of the perovskite in the edge region is greater than that in the center region. At this time, the edge region is thicker than the middle region, and the perovskite layer covers the edge region.

[0161] The average thickness of the perovskite layer in the central region more than 2 mm from the edge is 700 nm, the average thickness of the perovskite layer in the first peripheral region more than 1 mm and less than 2 mm from the edge is 900 nm, the average thickness of the perovskite layer in the second peripheral region less than or equal to 1 mm from the edge is 1200 nm, and the average thickness of the side perovskite layer is 500 nm.

[0162] 4.2.3-4.2.6, same as 3.2.3-3.2.6.

[0163] Example 3

[0164] A large-area perovskite / silicon-based heterojunction stacked cell is as shown in Figure 6 The perovskite layer covers the edge region and a small part is plated around the back of the silicon wafer. The specific preparation method is as follows.

[0165] 5.1, preparation of the bottom cell. Same as 3.1

[0166] 5.2, preparation of the top cell.

[0167] 5.2.1, same as 1.2.1.

[0168] 5.2.2, perovskite layer 3-2

[0169] The perovskite layer is selected from the (Cs 0.15 FA 0.85 )Pb(I 0.7 Br 0.3 )3 component system, and appropriate materials are weighed according to the molar ratio and dissolved in a mixed solution of DMF and DMSO with a concentration of 1.0 M. Then a slot coating process is used, and the coating width of the slot coating head is 184 mm, which is slightly larger than the size of 182 mm of the full silicon wafer. The liquid feeding speed is set to 15 μL / s, the head moving speed is 10 mm / s, and the perovskite precursor is coated on the bottom cell, then rapid vacuum treatment is carried out, and after taking out, it is placed on a 100℃ hot table for annealing for 30 min to obtain the perovskite layer. During the rapid vacuum treatment, through the design of the gas field (gas is extracted from below or around to ensure that the gas above the perovskite layer flows from the center to the periphery), the solvent in the edge region of the perovskite liquid film can have a greater evaporation speed, so that the thickness of the perovskite in the edge region is greater than that in the central region. At this time, the edge region is thicker than the central region, and the perovskite layer bypasses the edge region and partially covers the transparent conductive layer 1-5, and the covered area is ≤1 mm from the edge.

[0170] The average thickness of the perovskite layer in the central region greater than 2 mm from the edge is 700 nm, the average thickness of the perovskite layer in the first peripheral region greater than 1 mm and less than 2 mm from the edge is 800 nm, the average thickness of the perovskite layer in the second peripheral region less than or equal to 1 mm from the edge is 1000 nm, the average thickness of the side perovskite layer is 500 nm, and the average thickness of the perovskite layer in the local coating area of the rear transparent conductive layer 1-5 is 1000 nm.

[0171] 4.2.3-4.2.6, same as 3.2.3-3.2.6.

[0172] The electrical performance of the laminated solar cells prepared in Examples 1-3 and Comparative Examples 1-2 was measured, and the results are shown in Table 1.

[0173] Table 1

[0174] Electrical performance parameters Comparative Example 1 Comparative Example 2 Example 1 Example 2 Example 3 Isc(A) 4.941 6.233 6.393 6.413 6.373 Voc(V) 1.99 1.72 1.99 1.98 1.99 FF(%) 81.03 67.31 79.56 79.67 79.61 Pmax(W) 7.967 7.216 10.121 10.116 10.096 Effective area (cm 2 )]]> 256 324 331.23 331.23 331.23 Eff 有效 (%)]] 31.12 22.27 30.56 30.54 30.48 Total area (cm 2 ) 331.23 331.23 331.23 331.23 331.23 Eff 总 (%)]] 24.05 21.78 30.56 30.54 30.48

[0175] As can be seen from Table 1, if only the effective area is considered, the TCO layer after masking can achieve insulation between the recombination layer and the window layer, and the laminated cell also has high conversion efficiency. However, considering the total area, the perovskite / silicon-based heterojunction laminated cell after masking has no advantage in conversion efficiency. If a conventional spin coating process is used to prepare a large-area perovskite / silicon-based heterojunction laminated cell, the perovskite layer in the edge region is too thin to completely cover, making it difficult to achieve complete insulation between the recombination layer and the window layer, resulting in serious leakage. In the case where the TCO is not masked, the conversion efficiency of the full-silicon wafer perovskite / silicon-based heterojunction laminated cell is greatly affected.

[0176] The full-silicon wafer perovskite / silicon-based heterojunction laminated cell of the present application can achieve complete insulation between the recombination layer and the window layer, and whether the TCO layer is masked has little effect on the conversion efficiency of the effective area. The full-silicon wafer perovskite / silicon-based heterojunction laminated cell prepared in this way minimizes the masked area of the window layer, thereby increasing the effective area of the laminated cell and improving the overall conversion efficiency of the cell, and has the advantage of conversion efficiency of the full-silicon wafer area.

[0177] In addition, since the perovskite layer has a relatively thick thickness in the peripheral region, and even forms a certain coverage on the edge and back (Examples 2 and 3), the insulation effect between the window layer TCO layer and the rear transparent conductive layer can be achieved at the same time, thereby further reducing the risk of short circuit of the laminated cell and improving the stability of the preparation process.

Claims

1. A perovskite / crystalline silicon tandem solar cell of full silicon wafer size, comprising a silicon substrate cell and a perovskite cell stacked sequentially, wherein the perovskite cell includes a perovskite layer; The perovskite layer completely covers the silicon substrate cell; The perovskite layer includes a central region and a peripheral region. The central region refers to the area on the silicon substrate from which the projection is at least 2 mm from the edge of the silicon substrate cell. The peripheral region refers to the area on the silicon substrate from which the projection is at least 2 mm from the edge of the silicon substrate cell. The average thickness of the central region is less than the average thickness of the peripheral region. The perovskite / crystalline silicon tandem solar cell further includes a composite layer located between the silicon substrate cell and the perovskite cell; The perovskite layer also extends to the side of the perovskite / crystalline silicon tandem solar cell to cover at least a portion of the side of the composite layer and the silicon substrate cell.

2. The perovskite / crystalline silicon tandem solar cell according to claim 1, wherein the difference between the average thickness of the peripheral region and the average thickness of the central region is greater than or equal to 100 nm and less than or equal to 4000 nm.

3. The perovskite / crystalline silicon tandem solar cell according to claim 2, wherein the difference between the average thickness of the peripheral region and the average thickness of the central region is greater than or equal to 200 nm and less than or equal to 2000 nm.

4. The perovskite / crystalline silicon tandem solar cell according to claim 1 or 2, wherein the peripheral region includes a first peripheral region and a second peripheral region, the first peripheral region being a region whose projection on the silicon substrate is greater than 1 mm and less than 2 mm from the edge of the silicon substrate cell, and the second peripheral region being a region whose projection on the silicon substrate is less than or equal to 1 mm from the edge of the silicon substrate cell. The difference between the average thickness of the first peripheral region and the average thickness of the central region is greater than or equal to 100 nm and less than or equal to 2000 nm; The difference between the average thickness of the second peripheral region and the average thickness of the central region is greater than or equal to 200 nm and less than or equal to 4000 nm.

5. The perovskite / crystalline silicon tandem solar cell according to claim 4, wherein the difference between the average thickness of the first peripheral region and the average thickness of the central region is greater than or equal to 200 nm and less than or equal to 1000 nm.

6. The perovskite / crystalline silicon tandem solar cell according to claim 4, wherein the difference between the average thickness of the second peripheral region and the average thickness of the central region is greater than or equal to 400 nm and less than or equal to 2000 nm.

7. The perovskite / crystalline silicon tandem solar cell according to claim 1 or 2, wherein the projection of the inner edge of the mask region of the composite layer onto the silicon substrate is less than or equal to 1 mm from the edge of the silicon substrate cell.

8. The perovskite / crystalline silicon tandem solar cell according to claim 1 or 2, wherein the perovskite cell comprises a hole transport layer, a perovskite layer, an electron transport layer and a front transparent conductive layer stacked sequentially.

9. The perovskite / crystalline silicon tandem solar cell according to claim 8, wherein the projection of the inner edge of the mask region of the front transparent conductive layer onto the silicon substrate is less than or equal to 1 mm from the edge of the silicon substrate cell.

10. The perovskite / crystalline silicon tandem solar cell of claim 8, wherein the perovskite layer further extends to the side of the perovskite / crystalline silicon tandem solar cell to cover at least a portion of the side of the hole transport layer.

11. The perovskite / crystalline silicon tandem solar cell of claim 1, wherein the perovskite layer further extends to partially cover at least a portion of the back side of the silicon substrate cell.

12. The perovskite / crystalline silicon tandem solar cell according to claim 1 or 2, wherein the silicon substrate cell is a heterojunction cell, a tunnel oxide passivated contact cell, or a back contact cell.

13. The perovskite / crystalline silicon tandem solar cell according to claim 12, wherein the heterojunction cell comprises an N-type amorphous silicon layer, a first intrinsic amorphous silicon layer, an N-type crystalline silicon substrate, a second intrinsic amorphous silicon layer, a P-type amorphous silicon layer, and a back transparent conductive layer, which are sequentially stacked.

14. The perovskite / crystalline silicon tandem solar cell according to claim 13, wherein the projection of the inner edge of the mask region of the rear transparent conductive layer onto the silicon substrate is less than or equal to 1 mm from the edge of the silicon substrate cell.

15. The perovskite / crystalline silicon tandem solar cell according to claim 1 or 2, wherein the N-type crystalline silicon substrate is a whole or half of an M6, M10, or M12 silicon wafer.

16. A photovoltaic module comprising any one of claims 1-15 perovskite / crystalline silicon tandem solar cells.

17. A method for fabricating a perovskite / crystalline silicon tandem solar cell with an all-silicon wafer size, comprising the following steps: Fabrication of silicon-based solar cells; A composite layer and a hole transport layer are sequentially formed on the silicon substrate solar cell; A perovskite layer is prepared on the hole transport layer such that the perovskite layer completely covers the silicon substrate cell, and the perovskite layer also extends to the side of the perovskite / crystalline silicon tandem solar cell to cover at least a portion of the composite layer and the side of the silicon substrate cell. An electron transport layer and a front transparent conductive layer are sequentially fabricated on the perovskite layer; The perovskite layer includes a central region and a peripheral region. The central region is the area on the silicon substrate from which the projection is at least 2 mm from the edge of the silicon substrate cell. The peripheral region is the area on the silicon substrate from which the projection is at least 2 mm from the edge of the silicon substrate cell. The average thickness of the central region is less than the average thickness of the peripheral region.

18. The preparation method according to claim 17, wherein the distance between the projection of the mask region of the composite layer on the silicon substrate and the edge of the silicon substrate cell is less than or equal to 1 mm.

19. The fabrication method according to claim 17 or 18, wherein the distance between the projection of the mask region of the front transparent conductive layer on the silicon substrate and the edge of the silicon substrate cell is less than or equal to 1 mm.

20. The preparation method according to claim 17 or 18, wherein the perovskite layer is prepared by slot coating, blade coating, spray coating, inkjet printing, transfer printing or screen printing.

21. The preparation method according to claim 17 or 18, wherein the perovskite / crystalline silicon tandem solar cell prepared by the preparation method is the perovskite / crystalline silicon tandem solar cell according to any one of claims 1-15.

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