High-order passive filter with capacitive internal tapping technology

Abstract

A high-order filter with a capacitive internal tapping technique is disclosed. The filter includes an inductor and a first resonant circuit, and the first resonant circuit includes a first portion of the inductor and a first capacitor. The first resonant circuit is configured to attenuate a first frequency component of an input signal that is higher than a cut-off frequency to generate a filtered signal. The filter further includes a second resonant circuit that is coupled in parallel with the first resonant circuit and includes the first portion of the inductor and a second capacitor. The second resonant circuit is configured to attenuate the first frequency component of the input signal to generate the filtered signal. A third resonant circuit includes a second portion of the inductor and a third capacitor, wherein the third resonant circuit is configured to attenuate a second frequency component of the filtered signal that is higher than the cut-off frequency to generate an output signal.

Description

Technical Field

[0001] This disclosure relates to electrical / electronic circuits and, more particularly, to passive filter circuits. Background Art

[0002] Filters are widely used in a variety of electronic circuits. Filters can be classified as active filters and passive filters, or as analog filters and digital filters. Active filters include one or more active components (e.g., transistors), while passive filters use passive components such as inductors and capacitors to implement. Digital filters typically include multiple delay units and corresponding taps. Analog filters can be implemented in a variety of passive component arrangements.

[0003] Filters can also be defined by order. For example, the order of a digital filter can be defined by the number of delay elements used therein. The order of an analog filter is defined by the number of poles in its transfer function. Higher-order filters generally provide higher attenuation outside the filter's passband. For example, a first-order filter provides approximately 6 decibels (dB) of attenuation per octave outside its passband. A fifth-order filter provides approximately 30 dB of attenuation per octave outside its passband. Thus, the order of the filter can be adjusted according to the desired amount of attenuation. Summary of the Invention

[0004] Disclosed is a high-order filter having a capacitive center-tap technique. In one embodiment, a filter includes an inductor and a first resonant circuit that includes a first portion of the inductor and a first capacitor. The first resonant circuit is configured to attenuate a first frequency component of an input signal that is higher than a cut-off frequency to generate a filtered signal. The filter further includes a second resonant circuit that is coupled in parallel with the first resonant circuit and includes the first portion of the inductor and a second capacitor. The second resonant circuit is configured to attenuate the first frequency component of the input signal to generate the filtered signal. A third resonant circuit includes a second portion of the inductor and a third capacitor, wherein the third resonant circuit is configured to attenuate a second frequency component of the filtered signal that is higher than the cut-off frequency to generate an output signal. Brief Description of the Drawings

[0005] The following detailed description refers to the accompanying drawings, which are briefly described now.

[0006] Figure 1 is a schematic diagram of one embodiment of a filter circuit having a tapped inductor.

[0007] Figure 2 is a schematic diagram of another embodiment of a filter circuit having a tapped inductor.

[0008] Figure 3Schematic diagram of another embodiment of a filter circuit with a tapped inductor.

[0009] Figure 4 Schematic diagram of another embodiment of a filter circuit with a tapped inductor.

[0010] Figure 5 Illustration of one embodiment of a pair of wound inductors.

[0011] Figure 6 Illustration of one embodiment of a system utilizing a filter according to the present disclosure.

[0012] Figure 7 Flowchart of one embodiment of a method for operating a filter.

[0013] Figure 8 Block diagram of one embodiment of an example system. Detailed Description

[0014] Many analog filters that use passive components require inductors. The order of an analog filter can be defined by the number of poles in the filter transfer function. Due to the higher gain roll-off at the bandwidth frequency, higher-order filters are often desired, where the gain roll-off (attenuation) occurs at a higher rate relative to lower-order filters. Higher-order analog filters using passive components require multiple inductors and capacitors. However, this consumes a larger amount of circuit area on the chip, especially for inductors. Therefore, in the case of passive analog filters, there is a trade-off between the filter order and the area.

[0015] The present disclosure utilizes the recognition that the tapped capacitor method can increase the effective order of a filter without increasing the inductor area. Accordingly, a center-tapped passive filter with a resonant circuit is disclosed. The circuit includes a capacitor having a first terminal coupled to an input node and a second terminal that is center-tapped in an inductor to create a resonant circuit. This structure is repeated in a differential filter including coupled inductors (i.e., sharing the same magnetic core). Impedance matching capacitors are provided on the input and output sections such that the characteristic impedance entering and leaving the filter is matched. Another capacitor is coupled to the center tap (or between two center taps in a differential embodiment) to control the flatness of the response. As a result of this arrangement, a response of a higher-order filter (e.g., 5th order) with very sharp out-of-band rejection can be obtained while consuming significantly less area compared to other filters of the same order.

[0016] The following discussion begins with a description of several different embodiments and their details. These embodiments include single-ended and differential filters. Then a diagram of an embodiment of a wound inductor as implemented on an integrated circuit die is discussed. Thereafter, systems that utilize filters in the transmission and reception of radio signals / reflections are discussed. Then a method for operating a filter in accordance with the present disclosure is described, and thereafter example systems in which the filter can be utilized (along with the previously discussed systems) are discussed.

[0017] Filter with Capacitive Tapping Technology :

[0018] Figure 1 FIG. 8 is a schematic diagram of an embodiment of a filter circuit having a tapped inductor. In the illustrated embodiment, filter 100 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, and an inductor L1. The inductor L1 in the illustrated embodiment includes a center tap 110 that provides a center connection to each of capacitors C1 and C2. In the illustrated embodiment, a first resonant circuit 101 is formed by capacitor C1 and a portion of inductor L1. A second resonant circuit is formed by C2 and the same portion of L1 as the first resonant circuit (the left side of center tap 110). A third resonant circuit 103 is formed by the other portion of inductor L1 (the right side of center tap 110) and capacitor C3. It should be noted that each capacitor in the illustrated embodiment can be implemented as a capacitor bank and can be subject to a certain amount of tuning prior to operation.

[0019] Filter 100 is a passive filter that is configured to provide filtering of signals received at an input (In) that are above a cut-off frequency. The first resonant circuit 101 and the second resonant circuit 102 of filter 100 are configured to filter a first frequency component that is above the cut-off frequency. The third resonant circuit 103 filters a second frequency component that is above the cut-off frequency, where the frequency of the second frequency component is greater than the frequency of the first frequency component.

[0020] Using this arrangement, filter 100 in this particular embodiment forms a fifth-order single-ended filter. Compared to other fifth-order passive filters that utilize two capacitor / inductor pairs, filter 100 as shown here implements the same filtering with fewer components (i.e., three capacitors and a single inductor). Using this configuration, the filter can have a roll-off of 30 dB or more per octave above the cut-off frequency, despite using fewer components and a smaller area.

[0021] Figure 2Schematic diagram of another embodiment of a single-ended passive filter. The filter 200 in the illustrated embodiment includes a resonant circuit 201 (a part of C1 and L1), a resonant circuit 202 (a part of C2 and L1), and a resonant circuit 203 (a part of C3 and L1). The illustrated embodiment also includes an impedance matching capacitor C4. Note that, similar to the embodiment discussed above, Figure 2 any or all of the capacitors shown therein may be implemented as capacitor banks, and furthermore, the capacitance provided by these banks may be subject to tuning.

[0022] Figure 1 The illustrated embodiment shows C1 and C2 coupled to the center tap of L1, while the filter 200 shown here shows C1 and C2 coupled to another (non-center) tap point in the inductor L1. Changing the tap point from the center of the inductor L1 can change the frequency response of the filter 200. This results in the first part of the inductor (left side of the tap) having a first size and the second part of the inductor (right side of the tap) having a different second size. Thus, the frequency components attenuated by the first and second resonant circuits are relative to Figure 1 the illustrated embodiment may be different.

[0023] During Figure 2 the operation of the embodiment, current may flow through C4 or through a part of C1 and L1. The tap of the inductor L1 effectively creates two inductors, where the inductance of each inductor depends on the actual tap point. In the illustrated embodiment, the filter may be tuned by adjusting the capacitance of C1. At the same time, the value of C4 can be selected to optimize the transfer function of the filter and to make the response as flat as possible. Note that, Figure 1 the illustrated embodiment may also have a capacitor connected as C4 as Figure 2 shown.

[0024] This disclosure contemplates that the frequency response of various embodiments of the filters described herein may be changed during operation. Figure 3FIG. is a schematic diagram of another embodiment of a filter circuit having a tapped inductor. In the embodiment shown, filter 300 includes inductor L1, capacitors C3 and C4, and capacitor banks 310 and 320. Capacitors C3 and C4 may also be implemented as capacitor banks, but may also be implemented as discrete capacitors. Switch S1 is coupled between each of the tap points on capacitor bank 310 and the tap points on L1. Similarly, switch S2 is coupled between each of the tap points on capacitor bank 320 and the tap points on L1. Tuning control circuit 350 is coupled to provide control signals to switches S1 and S2 and capacitor banks 310 and 320. Using these control signals, the tuning control circuit can control the amount of capacitance provided by capacitor banks 310 and 320 and can also control the amount of inductance contributed to its corresponding resonant circuit. This can enable fine tuning of the response of filter 300.

[0025] Note that in some embodiments, the response of filter 300 may be adjusted dynamically during operation. In other embodiments, the tuning control circuit may set the switches to their corresponding tap points and set the capacitor banks to their respective values prior to operation. Additionally, in some embodiments, switches S1 and S2 may be set independently of each other, such as the corresponding capacitance values provided by capacitor banks 310 and 320. This in turn may allow the configuration shown to implement a higher order filter than a similar non-configurable embodiment.

[0026] Figure 4 FIG. is a schematic diagram of another embodiment of a filter circuit having a tapped inductor. In the embodiment shown, filter 400 is implemented as a differential filter including two inductors L1 and L2. The inductors of this embodiment are coupled inductors and thus share the same magnetic core. A discussion of one embodiment of such an inductor that can be used to implement filter 400 is provided below with reference to Figure 5 FIG.

[0027] Filter 400 includes capacitor C11 and inductor L1 in the first part of the filter, while the second part includes C41 and L2. Capacitors C12, C13, and C14 are coupled between the first and second parts of the circuit. Capacitor C12 is coupled to the center tap of both inductors L1 and L2. Note that embodiments similar to those discussed above with reference to Figure 2 and Figure 3 where the capacitor is coupled to a tap in the inductor at a point other than the center tap are possible and contemplated. Additionally, embodiments such as Figure 3 including a tuning circuit that can set or vary the specific point of the inductor tap can also be incorporated into a differential filter such as Figure 4 shown in FIG. It should also be noted that any one or all of the capacitors may be implemented as a capacitor bank rather than as a discrete capacitor or a capacitor with a fixed value.

[0028] In the illustrated embodiments, the differential inductors L1 and L2 are embedded together to utilize the mutual magnetic coupling between the two inductors and reduce the amount of chip area consumed. Additionally, Figure 4 the switched capacitor method shown in blocks the current at a specific band of the resonant frequency, forcing the filter roll-off to drop rapidly. The additional arms of the resonant circuit formed by inductors L1, L2, and C4 can attenuate the direct-through resonance through capacitor C13 and the corresponding coupled portions of L1 and L2. As previously described, the filter 400 can be generalized to add additional switch points within the inductor and further increase the order of the filter.

[0029] Inductor Arrangement :

[0030] Figure 5 FIG. is an illustration of an embodiment of a wound inductor implemented on an integrated circuit die or substrate. In the illustrated embodiment, inductors L1 and L2 are wound around each other, where the two inductors are differentiated from each other by the hatched lines shown in their respective portions. The various portions of the inductor can utilize different metal layers to allow the different portions to cross each other without connection. The inductor can also be switched on different metal layers. In various embodiments of filters utilizing inductors as shown in Figure 5 FIG., the switch points can be inside the helix on one or more of the different branches of each.

[0031] Since inductors L1 and L2 are wound as shown here, they share a magnetic core and there is mutual magnetic coupling during operation. This arrangement thus allows for significant area savings

[0032] RF Sensing System :

[0033] Figure 6 FIG. is a block diagram of an embodiment of a radio frequency (RF) sensing system utilizing an embodiment of a filter as disclosed herein. As Figure 6 shown in FIG., the RF sensing system 600 can be used as a small radar system, emitting a radio transmission and then processing its reflections to obtain data.

[0034] In the illustrated embodiment, the RF sensing system 600 includes a digital-to-analog converter (DAC) 605 that is coupled to receive a digital word. The digital word is converted by the DAC 605 into an analog signal and provided to a filter 601. The filter 601 in the illustrated embodiment is a filter having first, second, and third resonant circuits according to the various embodiments described above. Additionally, the filter 601 can be a single-ended or differential filter. According to an embodiment in the present disclosure, the filter can be implemented as a higher-order filter (e.g., fifth order or higher) while using a minimal amount of circuit area. The filter 601 outputs the filtered analog signal.

[0035] The analog front end (AFE) / transmitter 615 in the embodiment is configured to receive the analog filtered signal and perform various functions ending with the transmission of a corresponding radio signal. In one embodiment, the AFE / transmitter can include circuitry such as a low-noise amplifier, a local oscillator, and the like. In some embodiments, the filtered analog signal can be upconverted by circuitry implementing a direct conversion architecture or alternatively a heterodyne architecture. The radio signal can be transmitted via an antenna 620.

[0036] On the receiving side, the reflected radio signal can be received by a receiver 650 via an antenna 640. Similar to the transmitter 615, the receiver 650 can include various circuitry such as a low-noise amplifier, a local oscillator, and the like. Circuitry for downconverting the received signal to a baseband signal can also be present in the receiver 650. In one embodiment, an analog signal can be output from the receiver 650 to various other circuitry for post-processing. The present disclosure also contemplates that the receiver 650 can include an analog-to-digital converter (ADC) to convert the received analog signal into a digital value for further post-processing.

[0037] It should be noted that although some of the circuitry discussed above may have been implemented using NMOS and PMOS transistors, the present disclosure is not intended to limit embodiments within its scope to these types of devices. Thus, in addition to the various MOSFET types discussed above, the present disclosure also contemplates embodiments using non-planar devices such as FinFETs, GAAFETs (gate-all-around FETs), and other types. Embodiments implemented using bipolar devices are also possible and contemplated. The present disclosure also contemplates that devices in various embodiments of the circuitry discussed herein can be implemented using technologies that are speculative at the time of this writing. These technologies include (but are not limited to) graphene transistors, carbon nanotube transistors, gallium arsenide transistors, and the like. The use of memristors in certain circuit structures is also contemplated.

[0038] Method for Operating a Passive Filter with Capacitive Tapping :

[0039] Figure 7FIG. 0 is a flow diagram of one embodiment of a method for operating a passive filter in accordance with the present disclosure. Method 700 may be performed by any of the filter embodiments discussed above and may be used in a wide variety of applications. However, embodiments of passive filters that are capable of performing Method 700 but are not explicitly disclosed herein are considered to fall within the scope of the present disclosure.

[0040] Method 700 includes attenuating a first frequency component of an input signal that is higher than a cut-off frequency using a first resonant circuit and a second resonant circuit to generate a filtered signal, where the first resonant circuit includes a first capacitor and a first portion of an inductor, and where the second resonant circuit includes a second capacitor and the first portion of the inductor (block 705). Method 700 also includes attenuating a second frequency component of the filtered signal that is higher than the cut-off frequency using a third resonant circuit to generate an output signal, where the third resonant circuit includes a third capacitor and a second portion of the inductor (block 710).

[0041] In various embodiments, in a circuit for performing Method 700, the first capacitor is coupled in parallel with the first portion of the inductor. Similarly, in the circuit for performing Method 700, the second capacitor is coupled in series with the first portion of the inductor, the third capacitor is coupled in series with the second portion of the inductor, and a fourth capacitor is coupled between an input of the first resonant circuit and a ground supply node.

[0042] Method 700 may also include attenuating a third frequency component of the filtered signal that is higher than the cut-off frequency using a fourth resonant circuit to generate an output signal. The fourth resonant circuit in a filter arranged to perform Method 700 includes a fourth capacitor and a third portion of an inductor.

[0043] Example System :

[0044] Turning now to Figure 8 , which shows a block diagram of one embodiment of a system 800 that may incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, system 800 includes at least one instance of a system-on-chip (SoC) 806, which may include various types of processing units such as a central processing unit (CPU), a graphics processing unit (GPU), or other communication structures, as well as interfaces to memory and input / output devices. In some embodiments, one or more processors in SoC 806 include multiple execution lanes and instruction issue queues. In various embodiments, SoC 806 is coupled to an external memory 802, peripherals 804, and a power supply 808.

[0045] A power supply 808 is also provided that supplies a power supply voltage to the SoC 806 and one or more power supply voltages to the memory 802 and / or the peripherals 804. In various embodiments, the power supply 808 represents a battery (e.g., a rechargeable battery in a smart phone, laptop computer, or tablet computer or other device). In some embodiments, there are more than one instance of the SoC 806 (and also more than one external memory 802).

[0046] The memory 802 is any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, etc., and / or low power versions of SDRAM, such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to a circuit board to form a memory module, such as a single in-line memory module (SIMM), dual in-line memory module (DIMM), etc. Alternatively, the device may be mounted with the SoC or integrated circuit in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip module configuration.

[0047] The system 800 in the illustrated embodiment may include one or more specific implementations of the passive filter as described above in the SoC 806 or the peripherals 804. It is also contemplated that embodiments of radio systems that transmit using reflected radio (such as Figure 6 discussed in) may be implemented in the system 800, for example, in the peripherals 800. The passive filter discussed above may also be implemented in various other types of radio systems, some of which are briefly discussed in the following paragraphs.

[0048] Depending on the type of the system 800, the peripherals 804 include any desired circuitry. For example, in one embodiment, the peripherals 804 include devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, global positioning system, etc. In some embodiments, the peripherals 804 also include additional memory, including RAM storage, solid state storage, or disk storage. The peripherals 804 include user interface devices such as a display screen, including a touch display screen or a multi-touch display screen, a keyboard or other input device, a microphone, a speaker, etc.

[0049] As shown, system 800 is shown to have applications in a wide range of fields. For example, system 800 can be used as part of the chips, circuits, components, etc. of a desktop computer 810, a laptop computer 820, a tablet computer 830, a cellular or mobile phone 840, or a television 850 (or a set-top box coupled to a television). Also shown are a smartwatch and a health monitoring device 860. In some embodiments, the smartwatch 860 can include various general computing-related functions. For example, the smartwatch 860 can provide access to email, cellular service, the user's calendar, etc. In various embodiments, the health monitoring device can be a dedicated medical device or otherwise include dedicated health-related functionality. For example, the health monitoring device can monitor the user's vital signs, track the user's proximity to other users for epidemiological social distancing purposes, contact tracing, provide communication to emergency services in the event of a health crisis, etc. In various embodiments, the aforementioned smartwatch may or may not include some or any health monitoring-related functions. Other wearable devices are also envisioned, such as devices worn around the neck, devices implantable in the human body, glasses designed to provide augmented and / or virtual reality experiences, etc.

[0050] System 800 can also be used as part of a cloud-based service 870. For example, the previously mentioned devices and / or other devices can access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Further still, system 800 can be used in one or more devices in a home other than those previously mentioned. For example, household appliances can monitor and detect notable situations. For example, various devices in the home (e.g., a refrigerator, a cooling system, etc.) can monitor the status of the device and, in the event of detecting a specific event, should provide an alert to the homeowner (or, for example, a repair agency). Alternatively, a thermostat can monitor the temperature in the home and can automate the adjustment of the heating / cooling system based on the homeowner's reaction history to various situations. Figure 8 Also shown in the application of system 800 to various modes of transportation. For example, system 800 can be used in the control and / or entertainment systems of airplanes, trains, buses, rental cars, private cars, watercraft from private boats to cruise ships, small motorcycles (for rental or private use), etc. In various cases, system 800 can be used to provide automated guidance (e.g., self-driving vehicles), general system control, etc. Any number of these and many other embodiments are possible and envisioned. Note that Figure 8 the devices and applications shown are only illustrative and are not intended to be limiting. Other devices are possible and envisioned.

[0051] ***

[0052] This disclosure includes references to "an embodiment" or "embodiments" (e.g., "some embodiments" or "various embodiments"). An embodiment is a different specific implementation or instance of the disclosed concept. References to "an embodiment", "one embodiment", "a particular embodiment", etc. do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the substance or scope of this disclosure.

[0053] This disclosure may discuss potential advantages that may result from the disclosed embodiments. Not all specific implementations of these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular specific implementation realizes an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why a specific implementation that falls within the scope of the claims may not exhibit some or all of the disclosed advantages. For example, a particular specific implementation may include other circuitry outside the scope of this disclosure that, in combination with one of the disclosed embodiments, negates or diminishes one or more of the disclosed advantages. Additionally, suboptimal design implementation of a particular specific implementation (e.g., a specific implementation technique or tool) may also negate or diminish the disclosed advantages. Even assuming a specific implementation of the technology, the realization of the advantages may still depend on other factors, such as the circumstances of the environment in which the specific implementation is deployed. For example, the input provided to a particular specific implementation may prevent one or more of the problems addressed in this disclosure from occurring on a particular occasion, and as a result, the benefits of its solution may not be realized. Given the existence of possible factors outside this disclosure, it is hereby expressly stated that any potential advantages described herein should not be construed as claim limitations that must be met to prove infringement. Instead, the identification of such potential advantages is intended to illustrate the types of improvements available to designers who benefit from this disclosure. Permanently describing such advantages (e.g., stating that a particular advantage "may occur") is not intended to convey doubt as to whether such advantages can actually be realized, but rather to recognize the technical reality that the realization of such advantages typically depends on additional factors.

[0054] Unless otherwise stated, embodiments are non - restrictive. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even in cases where only a single example is described with respect to a particular feature. The embodiments disclosed in this invention are intended to be illustrative rather than restrictive, without any contrary statement in this disclosure. Thus, this application is intended to allow claims that cover the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those of ordinary skill in the art who are aware of the beneficial effects of this disclosure.

[0055] For example, the features in the present application can be combined in any suitable manner. Thus, during the prosecution of the present application (or an application claiming priority therefrom), new claims can be made directed to any such combinations of features. Specifically, with reference to the appended claims, the features of a dependent claim can, where appropriate, be combined with the features of other dependent claims, including claims that depend from other independent claims. Similarly, the features from corresponding independent claims can be combined where appropriate.

[0056] Accordingly, although the appended dependent claims may be drafted such that each dependent claim depends from a single other claim, additional dependencies are contemplated. Any combination of dependent claims consistent with the present disclosure is contemplated, and such combinations can be claimed in the present patent application or in another patent application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0057] Where appropriate, claims drafted in one format or statutory type (e.g., apparatus) are also contemplated as being intended to support corresponding claims in another format or statutory type (e.g., method).

[0058] ***

[0059] Because the present disclosure is a legal document, various terms and phrases are subject to administrative and judicial interpretation. Notice is hereby given that the following paragraphs, and the definitions provided throughout the present disclosure, will be used to determine how claims drafted based on the present disclosure are to be interpreted.

[0060] References to items in the singular form (i.e., a noun or noun phrase preceded by "a," "an," or "the") are intended to mean "one or more" unless the context clearly dictates otherwise. Thus, without accompanying context, a reference to an "item" in a claim does not exclude additional instances of that item. A "plurality" of items means a group of two or more items.

[0061] The word "can" is used herein in an enabling sense (i.e., having the potential to, being able to), rather than in a mandatory sense (i.e., must).

[0062] The terms "comprising" and "including" and their forms are open-ended and mean "including but not limited to."

[0063] When the term "or" is used in the context of a list of options in this disclosure, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the statement "x or y" is equivalent to "x or y, or both", and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0064] The statements "w, x, y, or z, or any combination thereof" or "...at least one of w, x, y, and z" are intended to cover all possibilities of individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "...at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in that list of elements. This phrase should not be construed as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0065] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels for a feature (e.g., "first circuit", "second circuit", "specific circuit", "given circuit", etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels "first", "second", and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to a feature.

[0066] The phrase "based on" is used to describe one or more factors that affect a determination. This term does not exclude the possibility that additional factors may affect the determination. That is, the determination may be based solely on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "determine A based on B". This phrase specifies that B is a factor used to determine A or that B affects the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor such as C. This phrase is also intended to cover embodiments where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on".

[0067] The phrases "responsive to" and "responsive" describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may affect or otherwise trigger the effect, either in conjunction with or independent of the specified factors. That is, the effect may be responsive only to these factors, or it may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "perform A responsive to B". This phrase specifies that B is the factor that triggers the performance of A or triggers a particular result of A. This phrase does not exclude the possibility that the performance of A may also be responsive to some other factor, such as C. This phrase also does not exclude the possibility that the performance of A may be performed in response to B and C in combination. This phrase is also intended to cover embodiments in which A is performed responsive only to B. As used herein, the phrase "responsive" is synonymous with the phrase "responsive at least in part". Similarly, the phrase "responsive to" is synonymous with the phrase "responsive at least in part to".

[0068] ***

[0069] Within this disclosure, different entities (which may variously be referred to as "units", "circuits", other components, etc.) may be described or claimed as "configured to" perform one or more tasks or operations. This expression - [entity] [configured to [perform one or more tasks]] - is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a certain task even if the structure is not currently being operated. Thus, an entity described or represented as "configured to" perform a certain task refers to a physical thing for implementing that task, such as a device, a circuit, a system having a processor unit, and a memory storing executable program instructions, etc. This phrase is not used herein to refer to intangible things.

[0070] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations even if not specifically stated.

[0071] The term "configured to" is not intended to mean "configurable to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, that unprogrammed FPGA may be "configurable to" perform that function. After appropriate programming, the FPGA may then be considered "configured to" perform a particular function.

[0072] For the purposes of U.S. patent applications based on this disclosure, stating in a claim that a structure is "configured to" perform one or more tasks is expressly intended to claim the claim element NoReference is made to 35 U.S.C. § 112(f). If an applicant wishes to rely on 35 U.S.C. § 112(f) during the prosecution of a U.S. patent application based on the present disclosure, it will use the "means for [performing a function]" construction to recite an element of a claim.

[0073] In the present disclosure, different "circuits" may be described. These circuits constitute hardware, which includes various types of circuit elements such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memories, embedded dynamic random access memories), programmable logic arrays, etc. The circuits may be custom designed or taken from a standard library. In various embodiments, the circuits may optionally include digital components, analog components, or a combination of both. Certain types of circuits may generally be referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units also refer to circuits.

[0074] Thus, the disclosed circuits / units / components and other elements illustrated in the figures and described herein include hardware elements such as those described in the preceding paragraphs. In many cases, the internal arrangement of the hardware elements within a particular circuit may be specified by describing the function of the circuit. For example, a particular "decoding unit" may be described as performing the function of "processing the opcode of an instruction and routing the instruction to one or more of a plurality of functional units", which means that the decoding unit "is configured to" perform that function. For a person skilled in the art of computing, this functional specification is sufficient to imply a set of possible structures for the circuit.

[0075] In various embodiments, as described in the preceding paragraphs, circuits, cells, and other elements may be defined by the functions or operations they are configured to perform. The arrangement relative to each other and such circuits / cells / components and the way they interact form the microarchitecture definition of the hardware, which is ultimately fabricated in an integrated circuit or programmed into an FPGA to form the physical implementation of the microarchitecture definition. Thus, the microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitecture definition. That is, a person skilled in the art having a microarchitecture definition provided according to the present disclosure can, without undue experimentation and using the application of an ordinary skilled person, implement the structure by encoding the description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. HDL descriptions are often expressed in a way that can appear functional. However, to those skilled in the art, the HDL description is a way to transform the structure of a circuit, cell, or component into the next level of implementation details. Such HDL descriptions can take the form of behavioral code (which is typically non-synthesizable), register transfer language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL descriptions can be sequentially synthesized for a cell library designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain the final design database that is sent to the factory to generate masks and ultimately produce the integrated circuit. Some hardware circuits or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuits. The integrated circuit can include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as the interconnects between the transistors and circuit elements. Some embodiments can implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements can be used in some embodiments. Alternatively, the HDL design can be synthesized into a programmable logic array such as a field programmable gate array (FPGA) and implemented in the FPGA. This decoupling between the design of a set of circuits and the subsequent lower-level implementation of those circuits typically results in a situation where the circuit or logic designer never specifies a particular set of structures for the lower-level implementation beyond the description of what the circuit is configured to do, as the process is performed at different stages of the circuit implementation process.

[0076] The fact that many different low-level combinations of circuit elements can be used to implement the same specifications of a circuit results in a large number of equivalent structures for that circuit. As noted, these low-level circuit implementations can vary depending on changes in manufacturing technology, the foundry selected to fabricate the integrated circuit, the cell library provided for a particular project, and the like. In many cases, the selection of these different implementations through different design tools or methods can be arbitrary.

[0077] In addition, for a given implementation, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Thus, the sheer volume of this information makes it impractical to provide a complete narrative of the low-level structures for implementing a single implementation, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of circuits using functional shorthand commonly used in the industry.

[0078] Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. It is intended that the following claims be interpreted to cover all such variations and modifications.

Claims

1. An apparatus, comprising: an inductor; a first resonant circuit including a first portion of the inductor and a first capacitor, wherein the first resonant circuit is configured to attenuate a first frequency component of an input signal that is higher than a cut-off frequency to generate a filtered signal; a second resonant circuit coupled to the first resonant circuit and including the first portion of the inductor and a second capacitor, wherein the second capacitor is coupled in series with the first portion of the inductor, and wherein the second resonant circuit is configured to attenuate the first frequency component of the input signal to generate the filtered signal; and a third resonant circuit including a second portion of the inductor and a third capacitor, wherein the third resonant circuit is configured to attenuate a second frequency component of the filtered signal that is higher than the cut-off frequency to generate an output signal.

2. The apparatus according to claim 1, wherein the first capacitor is coupled in parallel with the first portion of the inductor.

3. The apparatus according to claim 1, further comprising a radio sensing circuit including a filter, the filter including the inductor and the first, second, and third resonant circuits, and the apparatus further comprising: a digital-to-analog converter (DAC) configured to convert a digital word into an analog signal, wherein the DAC is coupled to supply the analog signal to the filter; and an analog front-end circuit coupled to receive a filtered version of the analog signal from the filter and configured to transmit a radio frequency signal based on the analog signal.

4. The apparatus according to claim 1, wherein the third capacitor is coupled in series with the second portion of the inductor.

5. The apparatus according to claim 1, further comprising a fourth capacitor coupled between an input of the first resonant circuit and a ground supply node.

6. The apparatus according to claim 1, further comprising a fourth resonant circuit including a third portion of the inductor and a fourth capacitor, wherein the fourth resonant circuit is configured to attenuate a third frequency component of the filtered signal that is higher than the cut-off frequency.

7. The apparatus according to claim 1, wherein the first portion of the inductor has a first size, and wherein the second portion of the inductor has a second size different from the first size.

8. The apparatus according to claim 1, wherein the inductor includes a plurality of programmable tap points, and wherein the first capacitor and the second capacitor are coupled to the inductor at a common tap point among the plurality of programmable tap points.

9. The apparatus according to claim 8, further comprising a control circuit configured to select a particular one of the programmable tap points for coupling to the first capacitor and the second capacitor.

10. A method, comprising: Attenuating a first frequency component of an input signal that is higher than a cut-off frequency by using a first resonant circuit and a second resonant circuit to generate a filtered signal, wherein the first resonant circuit includes a first capacitor and a first portion of an inductor, and wherein the second resonant circuit includes a second capacitor and the first portion of the inductor, wherein the second capacitor is serially coupled with the first portion of the inductor; and Attenuating a second frequency component of the filtered signal that is higher than the cut-off frequency by using a third resonant circuit to generate an output signal, wherein the third resonant circuit includes a third capacitor and a second portion of the inductor.

11. The method according to claim 10, wherein the first capacitor is shunt-coupled with the first portion of the inductor.

12. The method according to claim 10, further comprising attenuating a third frequency component of the filtered signal that is higher than the cut-off frequency by using a fourth resonant circuit to generate the output signal, wherein the fourth resonant circuit includes a fourth capacitor and a third portion of the inductor.

13. The method according to claim 10, wherein the third capacitor is serially coupled with the second portion of the inductor.

14. The method according to claim 10, wherein the fourth capacitor is coupled between an input portion of the first resonant circuit and a ground supply node.

15. An apparatus, comprising: A filter circuit configured to attenuate frequency components of a differential input signal that are higher than a cut-off frequency to generate a differential output signal, wherein the filter circuit includes: A first inductor coupled between a first input port of the filter circuit and a first output port of the filter circuit; A second inductor coupled between a second input port of the filter circuit and a second output port of the filter circuit, wherein the second inductor is wound inside the first inductor; A first capacitor bank coupled between the first input port and a first tap point of the first inductor; A second capacitor bank coupled between the second input port and a second tap point of the second inductor; A third capacitor bank coupled between the first tap point and the second tap point; and A fourth capacitor bank coupled between the first output port and the second output port.

16. The apparatus according to claim 15, further comprising a control circuit configured to select the first tap point and the second tap point.

17. The apparatus according to claim 15, wherein the filter circuit further includes a fifth capacitor bank coupled between the first input port and the second input port.

18. The apparatus according to claim 17, wherein the filter circuit further includes a fifth capacitor bank coupled between a third tap point of the first inductor and a fourth tap point of the second inductor.

19. The apparatus according to claim 17, wherein the first capacitor bank and the second capacitor bank each include a first plurality of capacitors and a second plurality of capacitors, and wherein the first capacitor bank and the second capacitor bank are configured to provide different capacitance values based on one or more control signals.

20. The apparatus according to claim 19, further comprising a control circuit configured to adjust the respective capacitance values based on the one or more control signals.

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