Flip-flop circuit and pixel driving circuit

Abstract

The present disclosure provides a flip-flop circuit and a pixel driving circuit, and belongs to the technical field of circuits. The flip-flop circuit comprises an AND gate having a first input end, a second input end and an output end, the AND gate being configured to control the output end to output a clock signal according to the potentials of the first input end and the second input end, the potential of the clock signal jumping between a first power supply voltage and a second power supply voltage; an input control sub-circuit configured to transmit the first power supply voltage or the second power supply voltage to at least one of the first input end and the second input end in response to an input control signal; and a duty cycle adjustment sub-circuit configured to adjust the duty cycle of the clock signal in response to a data voltage control signal.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of circuit, and particularly relates to a flip-flop circuit and a pixel driving circuit. BACKGROUND

[0002] PAM is the main gray scale driving mode of existing display products. With the continuous development of a series of display technologies such as LCD, OLED, LED and QD, the shortcomings of PAM driving such as high power consumption, large heat generation and inability to realize low gray scale display are increasingly prominent. Therefore, PWM gray scale driving mode is introduced on the basis of PAM to improve these problems. After introducing PWM driving mode, the complexity of the driving circuit is greatly increased, which is not conducive to the development of high PPI, narrow frame and other high technologies. At the same time, complex process will bring yield reduction and further increase cost. The existing PWM driving frequency is low, which has certain stimulation to human eyes, and needs to be further improved to realize healthy display. At present, PWM driving mode is full-screen driving, or a fixed duty cycle timing signal is introduced in the pixel driving circuit, which is matched with PAM driving to realize low gray scale display. The above two circuit design methods increase the complexity of the driving circuit, and at the same time do not improve the problems of high power consumption and large heat generation. In view of the above problems, it is urgent to develop a new type of gray scale driving circuit to adapt to the development of display technology. SUMMARY

[0003] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provide a flip-flop circuit and a pixel driving circuit.

[0004] In a first aspect, the present disclosure provides a flip-flop circuit, comprising: an AND gate having a first input end, a second output end and an output end, the AND gate being configured to control the output end to output a clock signal according to the potentials of the first input end and the second input end, the potential of the clock signal jumping between a first power supply voltage and a second power supply voltage;

[0005] an input control sub-circuit configured to transmit the first power supply voltage or the second power supply voltage to at least one of the first input end and the second input end in response to an input control signal;

[0006] a duty cycle adjustment sub-circuit configured to adjust the duty cycle of the clock signal in response to a data voltage control signal.

[0007] The duty cycle adjustment sub-circuit comprises a control module and a duty cycle adjustment module; and a connection node between the control module and the duty cycle adjustment sub-circuit is a first node.

[0008] The control module is configured to control the potential of the first node by the first power supply voltage or the second power supply voltage in response to the data voltage control signal.

[0009] The duty cycle adjustment module is configured to adjust a duty cycle of the clock signal output by the output terminal according to the first node potential.

[0010] The flip-flop circuit further comprises a reset sub-circuit configured to be responsive to a reset signal and reset the first node through the reset signal.

[0011] The reset sub-circuit comprises a second transistor, a control electrode of the second transistor being connected to a first electrode thereof and a reset signal terminal, and a second electrode of the second transistor being connected to the first node.

[0012] The first input terminal of the AND gate is electrically connected to a first power voltage terminal through the input sub-circuit, and the second input terminal of the AND gate is directly connected to the first power voltage terminal; and the duty cycle adjustment module is connected to the first input terminal of the AND gate.

[0013] The first input terminal and the second input terminal of the AND gate are both connected to the first power voltage terminal through the input sub-circuit.

[0014] The input sub-circuit comprises a first transistor, the duty cycle adjustment module comprises a third transistor, a first capacitor and a second capacitor, the control module comprises a fourth transistor, the first transistor has the same switching characteristic as the third transistor, and the third transistor and the fourth transistor have opposite switching characteristics.

[0015] The control electrode of the first transistor is connected to an input control signal terminal, the first electrode of the first transistor is connected to the first power voltage terminal, and the second electrode of the first transistor is connected to the first input terminal.

[0016] The control electrode of the third transistor is electrically connected to the first node and a first terminal of the second capacitor, the first electrode of the third transistor is connected to a second power voltage terminal and a second terminal of the second capacitor, the second electrode of the third transistor is connected to the first terminal of the first capacitor and the first input terminal of the AND gate, and the second terminal of the first capacitor is connected to the first power voltage terminal or the second power voltage terminal.

[0017] The control electrode of the fourth transistor is connected to a data voltage control terminal, the first electrode of the fourth transistor is connected to the first power voltage terminal, and the second electrode of the fourth transistor is connected to the first node.

[0018] The input sub-circuit comprises a first transistor, the duty cycle adjustment module comprises a third transistor, a first capacitor and a second capacitor, the control module comprises a fourth transistor, a ninth transistor and a tenth transistor, the first transistor, the third transistor and the ninth transistor have the same switching characteristic, and the third transistor, the fourth transistor and the tenth transistor have opposite switching characteristics.

[0019] The control electrode of the first transistor is connected with an input control signal end, the first electrode is connected with the first power supply voltage end, and the second electrode is connected with the first input end;

[0020] The control electrode of the third transistor is electrically connected with the first node and the first end of the second capacitor, the first electrode is connected with the second power supply voltage end, and the second electrode is connected with the first end of the first capacitor and the first input end of the AND gate; the second end of the first capacitor is connected with the first power supply voltage end or the second power supply voltage end, and the second end of the second capacitor is connected with the second power supply voltage end;

[0021] The control electrode of the fourth transistor is connected with a data voltage control end, the first electrode is connected with the first power supply voltage end and the second electrode of the tenth transistor, and the second electrode is connected with the first electrode of the ninth transistor and the first electrode of the tenth transistor;

[0022] The control electrode of the ninth transistor is connected with a reset signal end, and the second electrode is connected with the first node;

[0023] The control electrode of the tenth transistor is connected with the first input end of the AND gate.

[0024] The first input end of the AND gate is directly connected with the first power supply voltage end, the second input end of the AND gate is electrically connected with the first power supply voltage end through the input sub-circuit, and the duty cycle adjustment module is electrically connected with the second input end of the AND gate.

[0025] The input sub-circuit includes a first transistor, the duty cycle adjustment module includes a third transistor, a first capacitor and a second capacitor, the control module includes a fourth transistor, the switching characteristics of the first transistor and the third transistor are the same, and the switching characteristics of the third transistor and the fourth transistor are opposite;

[0026] The control electrode of the first transistor is connected with an input control signal end, the first electrode is connected with the first power supply voltage end, and the second electrode is connected with the second input end;

[0027] The control electrode of the third transistor is electrically connected with the first node and the first end of the second capacitor, the first electrode is connected with the second power supply voltage end, and the second electrode is connected with the first end of the first capacitor and the first input end of the AND gate; the second end of the first capacitor is connected with the second power supply voltage end, and the second end of the second capacitor is connected with the second power supply voltage end;

[0028] The control electrode of the fourth transistor is connected with a data voltage control end, the first electrode is connected with the first power supply voltage end, and the second electrode is connected with the first node.

[0029] The input sub-circuit comprises a first transistor; the duty cycle adjustment module comprises a third transistor, a first capacitor and a second capacitor; the control module comprises a fourth transistor, a ninth transistor and a tenth transistor; the first transistor, the third transistor and the ninth transistor have the same switching characteristic, and the third transistor, the fourth transistor and the tenth transistor have opposite switching characteristics.

[0030] The control electrode of the first transistor is connected with an input control signal end, the first electrode is connected with the first power supply voltage end, and the second electrode is connected with the second input end.

[0031] The control electrode of the third transistor is electrically connected with a first node and a first end of a second capacitor, the first electrode is connected with a second power supply voltage end, and the second electrode is connected with the first end of the first capacitor and a second input end of the AND gate; the second end of the first capacitor is connected with the first power supply voltage end or the second power supply voltage end, and the second end of the second capacitor is connected with the second power supply voltage end.

[0032] The control electrode of the fourth transistor is connected with a data voltage control end, the first electrode is connected with the first power supply voltage end and the second electrode of the tenth transistor, and the second electrode is connected with the first electrode of the ninth transistor and the first electrode of the tenth transistor.

[0033] The control electrode of the ninth transistor is connected with a reset signal end, and the second electrode is connected with the first node.

[0034] The control electrode of the tenth transistor is connected with the second input end of the AND gate.

[0035] The AND gate comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; the fifth transistor and the sixth transistor have the same switching characteristic, the seventh transistor and the eighth transistor have the same switching characteristic, and the fifth transistor and the seventh transistor have opposite switching characteristics.

[0036] The control electrode of the fifth transistor is connected with the control electrode of the eighth transistor, serving as a first input end of the AND gate, the first electrode is connected with the first power supply voltage end, and the second electrode is connected with the first electrode of the sixth transistor.

[0037] The control electrode of the sixth transistor is connected with the control electrode of the seventh transistor, serving as a second input end of the AND gate, the second electrode of the sixth transistor is connected with the second electrode of the seventh transistor and the second electrode of the eighth transistor, serving as a signal output end of the AND gate.

[0038] The first electrode of the seventh transistor is connected with the first electrode of the eighth transistor and the second power supply voltage end.

[0039] The AND gate includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the fifth transistor and the sixth transistor have the same switching characteristics, the seventh transistor and the eighth transistor have the same switching characteristics, and the fifth transistor and the seventh transistor have opposite switching characteristics.

[0040] The control electrode of the fifth transistor and the control electrode of the eighth transistor are connected to each other as the first input terminal of the AND gate. The first terminal is connected to the second power supply voltage terminal, and the second terminal is connected to the first terminal of the sixth transistor.

[0041] The control terminal of the sixth transistor and the control connection of the seventh transistor serve as the second input terminal of the AND gate. The second terminal of the sixth transistor is connected to the second terminal of the seventh transistor and the second terminal of the eighth transistor, serving as the signal output terminal of the AND gate.

[0042] The first terminal of the seventh transistor is connected to the first terminal of the eighth transistor and the first power supply voltage terminal.

[0043] The first input terminal of the AND gate is electrically connected to the second power supply voltage terminal through the input sub-circuit, and the second input terminal of the AND gate is directly connected to the first power supply voltage terminal; the duty cycle adjustment module is electrically connected to the first input terminal of the AND gate.

[0044] The first and second input terminals of the AND gate are both electrically connected to the second power supply voltage terminal through an input sub-circuit.

[0045] The input sub-circuit includes a first transistor; the duty cycle adjustment module includes a third transistor, a first capacitor, and a second capacitor; the control module includes a fourth transistor; the first transistor and the third transistor have the same switching characteristics, and the third transistor and the fourth transistor have opposite switching characteristics.

[0046] The control electrode of the first transistor is connected to the input control signal terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the first input terminal.

[0047] The control electrode of the third transistor is electrically connected to the first node and the first terminal of the second capacitor. The first electrode is connected to the second power supply voltage terminal, and the second electrode is connected to the first terminal of the first capacitor and the first input terminal of the AND gate. The second terminal of the first capacitor is connected to either the first power supply voltage terminal or the second power supply voltage terminal, and the second terminal of the second capacitor is connected to the second power supply voltage terminal.

[0048] The control electrode of the fourth transistor is connected to the data voltage control terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the first node.

[0049] The input sub-circuit includes a first transistor; the duty cycle adjustment module includes a third transistor, a first capacitor, and a second capacitor; the control module includes a fourth transistor, a ninth transistor, and a tenth transistor; the first transistor, the third transistor, and the ninth transistor have the same switching characteristics, while the third transistor, the fourth transistor, and the tenth transistor have opposite switching characteristics.

[0050] The control electrode of the first transistor is connected to the input control signal terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the first input terminal.

[0051] The control electrode of the third transistor is electrically connected to the first node and the first terminal of the second capacitor. The first electrode is connected to the second power supply voltage terminal, and the second electrode is connected to the first terminal of the first capacitor and the first input terminal of the AND gate. The second terminal of the first capacitor is connected to either the first power supply voltage terminal or the second power supply voltage terminal, and the second terminal of the second capacitor is connected to the second power supply voltage terminal.

[0052] The control electrode of the fourth transistor is connected to the data voltage control terminal, the first electrode is connected to the first power supply voltage terminal and the second electrode of the tenth transistor, and the second electrode is connected to the first electrode of the ninth transistor and the first electrode of the tenth transistor.

[0053] The control electrode of the ninth transistor is connected to the reset signal terminal, and the second electrode is connected to the first node;

[0054] The control electrode of the tenth transistor is connected to the first input terminal of the AND gate.

[0055] The first input terminal of the AND gate is connected to the first power supply voltage terminal, and the second input terminal of the AND gate is electrically connected to the second power supply voltage terminal through the input sub-circuit; the duty cycle adjustment module is electrically connected to the second input terminal of the AND gate.

[0056] The input sub-circuit includes a first transistor; the duty cycle adjustment module includes a third transistor, a first capacitor, and a second capacitor; the control module includes a fourth transistor; the first transistor and the third transistor have the same switching characteristics, and the third transistor and the fourth transistor have opposite switching characteristics.

[0057] The control electrode of the first transistor is connected to the input control signal terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the second input terminal.

[0058] The control electrode of the third transistor is electrically connected to the first node and the first terminal of the second capacitor. The first electrode is connected to the second power supply voltage terminal, and the second electrode is connected to the first terminal of the first capacitor and the first input terminal of the AND gate. The second terminal of the first capacitor is connected to the second power supply voltage terminal, and the second terminal of the second capacitor is also connected to the second power supply voltage terminal.

[0059] The control electrode of the fourth transistor is connected to the data voltage control terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the first node.

[0060] The input sub-circuit includes a first transistor; the duty cycle adjustment module includes a third transistor, a first capacitor, and a second capacitor; the control module includes a fourth transistor, a ninth transistor, and a tenth transistor; the first transistor, the third transistor, and the ninth transistor have the same switching characteristics, while the third transistor, the fourth transistor, and the tenth transistor have opposite switching characteristics.

[0061] The control electrode of the first transistor is connected to the input control signal terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the second input terminal.

[0062] The control electrode of the third transistor is electrically connected to the first node and the first terminal of the second capacitor. The first electrode is connected to the second power supply voltage terminal, and the second electrode is connected to the first terminal of the first capacitor and the second input terminal of the AND gate. The second terminal of the first capacitor is connected to either the first power supply voltage terminal or the second power supply voltage terminal, and the second terminal of the second capacitor is connected to the second power supply voltage terminal.

[0063] The control electrode of the fourth transistor is connected to the data voltage control terminal, the first electrode is connected to the first power supply voltage terminal and the second electrode of the tenth transistor, and the second electrode is connected to the first electrode of the ninth transistor and the first electrode of the tenth transistor.

[0064] The control electrode of the ninth transistor is connected to the reset signal terminal, and the second electrode is connected to the first node;

[0065] The control electrode of the tenth transistor is connected to the second input terminal of the AND gate.

[0066] The AND gate includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the fifth transistor and the sixth transistor have the same switching characteristics, the seventh transistor and the eighth transistor have the same switching characteristics, and the fifth transistor and the seventh transistor have opposite switching characteristics.

[0067] The control electrode of the fifth transistor is connected to the control electrode of the eighth transistor, serving as the first input terminal of the AND gate. The first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the first electrode of the sixth transistor.

[0068] The control terminal of the sixth transistor and the control connection of the seventh transistor serve as the second input terminal of the AND gate. The second terminal of the sixth transistor is connected to the second terminal of the seventh transistor and the second terminal of the eighth transistor, serving as the signal output terminal of the AND gate.

[0069] The first terminal of the seventh transistor is connected to the first terminal of the eighth transistor and the second power supply voltage terminal.

[0070] The AND gate includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the fifth transistor and the sixth transistor have the same switching characteristics, the seventh transistor and the eighth transistor have the same switching characteristics, and the fifth transistor and the seventh transistor have opposite switching characteristics.

[0071] The control electrode of the fifth transistor and the control electrode of the eighth transistor are connected to each other as the first input terminal of the AND gate. The first terminal is connected to the second power supply voltage terminal, and the second terminal is connected to the first terminal of the sixth transistor.

[0072] The control terminal of the sixth transistor and the control connection of the seventh transistor serve as the second input terminal of the AND gate. The second terminal of the sixth transistor is connected to the second terminal of the seventh transistor and the second terminal of the eighth transistor, serving as the signal output terminal of the AND gate.

[0073] The first terminal of the seventh transistor is connected to the first terminal of the eighth transistor and the first power supply voltage terminal.

[0074] Secondly, embodiments of this disclosure provide a pixel driving circuit, which includes a driving transistor and a trigger circuit; wherein the control electrode of the driving transistor is connected to the trigger circuit; and the trigger circuit is any of the trigger circuits described above. Attached Figure Description

[0075] Figure 1 This is a schematic diagram of a trigger circuit for a first example of an embodiment of this disclosure.

[0076] Figure 2 This is a schematic diagram of a trigger circuit for a second example of an embodiment of this disclosure.

[0077] Figure 3 This is a schematic diagram of a trigger circuit for a third example of an embodiment of this disclosure.

[0078] Figure 4 This is a schematic diagram of a trigger circuit for a fourth example of an embodiment of this disclosure.

[0079] Figure 5This is a schematic diagram of a trigger circuit for a fifth example of an embodiment of this disclosure.

[0080] Figure 6 This is a schematic diagram of a trigger circuit for a sixth example of an embodiment of this disclosure.

[0081] Figure 7 This is a schematic diagram of a trigger circuit for a seventh example of an embodiment of this disclosure.

[0082] Figure 8 This is a schematic diagram of a trigger circuit for an eighth example of an embodiment of this disclosure.

[0083] Figure 9 This is a schematic diagram of a trigger circuit for a ninth example of an embodiment of this disclosure.

[0084] Figure 10 This is a schematic diagram of a trigger circuit for a tenth example of an embodiment of this disclosure.

[0085] Figure 11 This is a schematic diagram of a trigger circuit for an eleventh example of an embodiment of this disclosure.

[0086] Figure 12 This is a schematic diagram of a trigger circuit for a twelfth example of an embodiment of this disclosure.

[0087] Figure 13 This is a schematic diagram of a trigger circuit for a thirteenth example of an embodiment of this disclosure.

[0088] Figure 14 This is a schematic diagram of a trigger circuit for the fourteenth example of an embodiment of this disclosure.

[0089] Figure 15 This is a schematic diagram of a trigger circuit for a fifteenth example of an embodiment of this disclosure.

[0090] Figure 16 This is a schematic diagram of a trigger circuit for a sixteenth example of an embodiment of this disclosure.

[0091] Figure 17 This is a schematic diagram of a trigger circuit for the seventeenth example of an embodiment of this disclosure.

[0092] Figure 18 This is a schematic diagram of a trigger circuit for the eighteenth example of an embodiment of this disclosure.

[0093] Figure 19 This is a schematic diagram of a trigger circuit for a nineteenth example of an embodiment of this disclosure.

[0094] Figure 20 This is a schematic diagram of a trigger circuit for the twentieth example of an embodiment of this disclosure.

[0095] Figure 21 This is a schematic diagram of a trigger circuit for a twenty-first example of an embodiment of the present disclosure.

[0096] Figure 22 This is a schematic diagram of a trigger circuit for a twenty-second example of an embodiment of the present disclosure.

[0097] Figure 23 This is a schematic diagram of a trigger circuit for a twenty-third example of an embodiment of this disclosure.

[0098] Figure 24 This is a schematic diagram of a trigger circuit for the twenty-fourth example of an embodiment of this disclosure.

[0099] Figure 25 The simulation results are shown for the touchpad circuits of examples one through six.

[0100] Figure 26 The simulation results are shown for the touchpad circuits of examples seven through twelfth.

[0101] Figure 27 The simulation results are shown for the touch controller circuits of Examples 13 to 18.

[0102] Figure 28 The simulation results are shown for the touchpad circuits of Examples 19 to 24.

[0103] Figure 29 This is a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure. Detailed Implementation

[0104] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0105] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0106] Before describing the embodiments of this disclosure, it should be noted that in the embodiments of this disclosure, the first power supply voltage is greater than the second power supply voltage. For example, the first power supply voltage is 8V, and the second power supply voltage is -8V. That is, the first power supply voltage is a high-level signal compared to the second power supply voltage, and the second power supply voltage is a low-level signal compared to the first power supply voltage. The first power supply voltage terminal and the second power supply voltage terminal mentioned in the following embodiments are respectively used to provide the first power supply voltage and the second power supply voltage. The input control signal and reset signal mentioned in the following embodiments are both high-frequency scanning signals.

[0107] In a first aspect, embodiments of this disclosure provide a trigger circuit with duty cycle adjustment function, the trigger circuit including an AND gate, an input control sub-circuit, and a duty cycle adjustment sub-circuit.

[0108] The AND gate has a first input, a second input, and an output. It is configured to control the output to output a clock signal based on the potentials of its first and second inputs. The clock signal's potential transitions between a first power supply voltage and a second power supply voltage. In this configuration, the AND gate can output a clock signal that transitions between the first and second power supply voltages.

[0109] The input control sub-circuit is configured to transmit either a first power supply voltage or a second power supply voltage to at least one of a first input terminal and a second input terminal in response to an input control signal. That is, if the input control sub-circuit is connected to the first input terminal, the input control signal controls whether the first or second power supply voltage it receives can be transmitted to the first input terminal; if the input control sub-circuit is connected to the second input terminal, the input control signal controls whether the first or second power supply voltage it receives can be transmitted to the second input terminal.

[0110] The duty cycle adjustment sub-circuit is configured to adjust the duty cycle of the clock signal in response to the data voltage control signal. In other words, the data voltage control signal can control the duration of the first and second power supply voltages output by the AND gate in each clock cycle.

[0111] The trigger circuit provided in this embodiment is equipped with a duty cycle adjustment sub-circuit, which can generate a clock signal with an adjustable duty cycle. In this case, the trigger circuit can be applied to a pixel driving circuit to control the turn-on time of the driving transistor according to the clock signal generated by the trigger circuit, thereby controlling the luminous brightness of the light-emitting device.

[0112] In some examples, the duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module; the connection node between the control module and the duty cycle adjustment subcircuit is a first node. The control module is configured to charge the first node with a first power supply voltage in response to a data voltage control signal. The duty cycle adjustment module is configured to adjust the duty cycle of the clock signal output from its output terminal according to the potential of the first node.

[0113] Furthermore, the touch controller circuit in this embodiment not only includes the above-described structure, but also includes a reset sub-circuit. This reset sub-circuit responds to a reset signal and resets the first node using the reset signal. That is, the first node is reset before each clock cycle of the clock signal begins, thereby ensuring that the duty cycle of each clock cycle can be precisely adjusted.

[0114] Furthermore, the reset sub-circuit may include a second transistor; the control terminal of the second transistor is connected to its first terminal and the reset signal terminal, and its second terminal is connected to the first node. The reset signal terminal is configured to receive a reset signal. In this embodiment, the reset signal is a high-frequency signal. The timing of this reset signal is opposite to that of the input control signal; for example, if the input control signal is low-level signal / high-level signal = 0.1μs / 99.9μs, the reset signal is low-level signal / high-level signal = 99.9μs / 0.1μs.

[0115] To make the touch controller circuit in the embodiments of this disclosure clearer, the touch controller circuit in the embodiments of this disclosure will be specifically described below with reference to specific examples.

[0116] First example: Figure 1 This is a schematic diagram of a trigger circuit according to a first example of an embodiment of this disclosure; as shown... Figure 1 As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A of the AND gate is electrically connected to the first power supply voltage terminal VDD through the input subcircuit, and the second input terminal B of the AND gate is directly connected to the first power supply voltage terminal VDD. The duty cycle adjustment module is connected to the first input terminal A of the AND gate.

[0117] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first transistor M1, third transistor M3, fifth transistor M5, and sixth transistor M6 have the same switching characteristics; the second transistor M2, fourth transistor M4, seventh transistor M7, and eighth transistor M8 have the same switching characteristics, but different switching characteristics from the first transistor. In this example, the first transistor M1, third transistor M3, fifth transistor M5, and sixth transistor M6 are N-type transistors, while the second transistor M2, fourth transistor M4, seventh transistor M7, and eighth transistor M8 are P-type transistors.

[0118] For details, please refer to... Figure 1The first transistor M1 has its first terminal connected to the first power supply voltage terminal VDD. Its second terminal is connected to the control terminals of the fifth transistor M5 and the eighth transistor M8, serving as the first input terminal A of an AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the second power supply voltage terminal VSS and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the first input terminal A of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the first power supply voltage terminal VDD. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the first power supply voltage terminal VDD. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is connected to the first power supply voltage terminal VDD, the control terminal of the seventh transistor M7, and the first plate of the first capacitor C1, serving as the second input terminal B of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are connected to the second power supply voltage terminal VSS. The second terminal of the first capacitor C1 is connected to the first power supply voltage terminal VDD, and the second terminal of the second capacitor C2 is connected to the first node.

[0119] The following simulation uses an example where the first power supply voltage is 8V, the second power supply voltage is -8V; the input control signal timing is 12V for the high level signal and -12V for the low level signal, with a period H = 100μs and a duty cycle of high level signal / low level signal = 0.1μs / 99.9μs; the reset signal timing is 12V for the high level signal and -20V for the low level signal, with a period H = 100μs and a duty cycle of high level signal / low level signal = 99.9μs / 0.1μs; the data voltage control signal Datastep = [7.42V, 7.4V, 7.3V, 7.2V, 7.1V, 7V, 7.42V, 6.9V, 6.8V, 6.7V]; the first capacitor C1 = 20fF; and the second capacitor C2 = 20pF. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0120] The operation of the first example flip-flop circuit will be described next. (Continue referring to...) Figure 1 The steps for generating each clock cycle signal of the clock signal using the touchpad circuit in the first example include:

[0121] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a low-level signal, and the first node is reset to -20V. During this stage, the third transistor M3 is turned off.

[0122] In the second stage, the reset signal at the HF_Reset terminal is a high-level signal, and the input control signal written at the HF_Input terminal is also a high-level signal, turning on the first transistor M1. At this time, both the first input terminal A and the second input terminal B of the AND gate are at the first power supply voltage, i.e., high-level signals. Therefore, the output terminal HF_Output of the AND gate outputs a high-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree to which the fourth transistor M4 is turned on, the charging speed of the first node is controlled.

[0123] In the third stage, after time t, the fourth transistor M4 charges the control electrode of the third transistor M3 until the potential of the first node minus the second power supply voltage is greater than the threshold voltage of the third transistor M3, that is, VQ-VSS>Vth. The third transistor M3 turns on, and the second power supply voltage sets the first input terminal A of the AND gate to the second power supply voltage, that is, a low-level signal, through the third transistor M3. At this time, the output terminal HF_Output of the AND gate outputs a low-level signal.

[0124] In the fourth stage, the reset signal at the HF_Reset terminal is a low-level signal, the first node is reset to -20V, the third transistor M3 is turned off in this stage, the first input terminal A of the AND gate remains at a low level, and the output terminal HF_Output continuously outputs a low-level signal.

[0125] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 charges the control electrode of the third transistor M3 to the first node potential minus the second power supply voltage is greater than the threshold voltage of the third transistor M3 for a period of time, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0126] Second example: Figure 2 This is a schematic diagram of a trigger circuit according to a second example of an embodiment of this disclosure; as shown... Figure 2As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A of the AND gate is directly electrically connected to the first power supply voltage terminal VDD, and the second input terminal B of the AND gate is connected to the first power supply voltage terminal VDD through the input subcircuit. The duty cycle adjustment module is connected to the second input terminal B of the AND gate.

[0127] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first transistor M1, third transistor M3, fifth transistor M5, and sixth transistor M6 have the same switching characteristics; the second transistor M2, fourth transistor M4, seventh transistor M7, and eighth transistor M8 have the same switching characteristics, but different switching characteristics from the first transistor. In this example, the first transistor M1, third transistor M3, fifth transistor M5, and sixth transistor M6 are N-type transistors, while the second transistor M2, fourth transistor M4, seventh transistor M7, and eighth transistor M8 are P-type transistors.

[0128] For details, please refer to... Figure 2The first transistor M1 has its first terminal connected to the first power supply voltage terminal VDD. Its second terminal is connected to the control terminals of the sixth transistor M6 and the seventh transistor M7, serving as the second input terminal B of an AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the second power supply voltage terminal VSS and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the second input terminal B of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the first power supply voltage terminal VDD. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the first power supply voltage terminal VDD. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The control terminal of the fifth transistor M5 is connected to the control terminal of the eighth transistor M8, serving as the second input terminal B of an AND gate directly connected to the first power supply voltage terminal VDD. The second terminal of the sixth transistor M6 is connected to the first terminal of the seventh transistor M7 and the second terminal of the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are also connected to the second power supply voltage terminal VSS. The second terminal of the first capacitor C1 is connected to the second power supply voltage terminal VSS, and the second terminal of the second capacitor C2 is connected to the first node.

[0129] The following simulation uses an example where the first power supply voltage is 8V, the second power supply voltage is -8V; the input control signal timing is 12V for the high level signal and -12V for the low level signal, with a period H = 100μs and a duty cycle of high level signal / low level signal = 0.1μs / 99.9μs; the reset signal timing is 12V for the high level signal and -20V for the low level signal, with a period H = 100μs and a duty cycle of high level signal / low level signal = 99.9μs / 0.1μs; the data voltage control signal Datastep = [7.42V, 7.4V, 7.3V, 7.2V, 7.1V, 7V, 6.9V, 6.8V, 6.7V]; the first capacitor C1 = 20fF; and the second capacitor C2 = 20pF. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0130] The operation of the second example flip-flop circuit will now be described. (Continue referring to...) Figure 2 The steps for generating each clock cycle signal of the clock signal using the touchpad circuit in the second example include:

[0131] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a low-level signal, and the first node is reset to -20V. During this stage, the third transistor M3 is turned off.

[0132] In the second stage, the reset signal at the HF_Reset terminal is a high-level signal, and the input control signal written at the HF_Input terminal is also a high-level signal, turning on the first transistor M1. At this time, both the first input terminal A and the second input terminal B of the AND gate are at the first power supply voltage, i.e., high-level signals. Therefore, the output terminal HF_Output of the AND gate outputs a high-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree to which the fourth transistor M4 is turned on, the charging speed of the first node is controlled.

[0133] In the third stage, after time t, the fourth transistor M4 charges the control electrode of the third transistor M3 until the potential of the first node minus the second power supply voltage is greater than the threshold voltage of the third transistor M3, that is, VQ-VSS>Vth. The third transistor M3 turns on, and the second power supply voltage sets the first input terminal A of the AND gate to the second power supply voltage, that is, a low-level signal, through the third transistor M3. At this time, the output terminal HF_Output of the AND gate outputs a low-level signal.

[0134] In the fourth stage, the reset signal at the HF_Reset terminal is a low-level signal, the first node is reset to -20V, the third transistor M3 is turned off in this stage, the second input terminal B of the AND gate remains at a low level, and the output terminal HF_Output continuously outputs a low-level signal.

[0135] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 charges the control electrode of the third transistor M3 to the first node potential minus the second power supply voltage is greater than the threshold voltage of the third transistor M3 for a period of time, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0136] The third example: Figure 3 This is a schematic diagram of a trigger circuit according to a third example of an embodiment of this disclosure; as shown Figure 3As shown, the touchscreen circuit includes an AND gate, an input control sub-circuit, a duty cycle adjustment sub-circuit, and a reset sub-circuit. The duty cycle adjustment sub-circuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment sub-circuit is the first node, and the reset sub-circuit is connected to the first node. The first input terminal A and the second input terminal B of the AND gate are electrically connected to the first power supply voltage terminal VDD through the input sub-circuit.

[0137] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first transistor M1, third transistor M3, fifth transistor M5, and sixth transistor M6 have the same switching characteristics; the second transistor M2, fourth transistor M4, seventh transistor M7, and eighth transistor M8 have the same switching characteristics, but different switching characteristics from the first transistor. In this example, the first transistor M1, third transistor M3, fifth transistor M5, and sixth transistor M6 are N-type transistors, while the second transistor M2, fourth transistor M4, seventh transistor M7, and eighth transistor M8 are P-type transistors.

[0138] For details, please refer to... Figure 3The first transistor M1 has its first terminal connected to the first power supply voltage terminal VDD. Its second terminal is connected to the control terminals of the fifth transistor M5 and the eighth transistor M8, serving as the first input terminal A of an AND gate. Simultaneously, the second terminal of the first transistor M1 is also connected to the control terminals of the sixth transistor M6 and the seventh transistor M7, serving as the second input terminal B of the AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the second power supply voltage terminal VSS and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the first input terminal A of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the first power supply voltage terminal VDD. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the first power supply voltage terminal VDD. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is connected to the first power supply voltage terminal VDD, the control terminal of the seventh transistor M7, and the first plate of the first capacitor C1, serving as the second input terminal B of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are connected to the second power supply voltage terminal VSS. The second terminal of the first capacitor C1 is connected to the first power supply voltage terminal VDD, and the second terminal of the second capacitor C2 is connected to the first node.

[0139] The following simulation uses an example where the first power supply voltage is 8V, the second power supply voltage is -8V; the input control signal timing is 12V for the high level signal and -12V for the low level signal, with a period H = 100μs and a duty cycle of high level signal / low level signal = 0.1μs / 99.9μs; the reset signal timing is 12V for the high level signal and -20V for the low level signal, with a period H = 100μs and a duty cycle of high level signal / low level signal = 99.9μs / 0.1μs; the data voltage control signal Datastep = [7.42V, 7.4V, 7.3V, 7.2V, 7.1V, 7V, 7.42V, 6.9V, 6.8V, 6.7V]; the first capacitor C1 = 20fF; and the second capacitor C2 = 20pF. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0140] The operation of the third example flip-flop circuit will be described next. (Continue referring to...)Figure 3 The steps for generating each clock cycle signal of the clock signal using the touchpad circuit in the third example include:

[0141] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a low-level signal, and the first node is reset to -20V. During this stage, the third transistor M3 is turned off.

[0142] In the second stage, the reset signal at the HF_Reset terminal is a high-level signal, and the input control signal written at the HF_Input terminal is also a high-level signal, turning on the first transistor M1. At this time, both the first input terminal A and the second input terminal B of the AND gate are at the first power supply voltage, i.e., high-level signals. Therefore, the output terminal HF_Output of the AND gate outputs a high-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree to which the fourth transistor M4 is turned on, the charging speed of the first node is controlled.

[0143] In the third stage, after time t, the fourth transistor M4 charges the control electrode of the third transistor M3 until the potential of the first node minus the second power supply voltage is greater than the threshold voltage of the third transistor M3, that is, VQ-VSS>Vth. The third transistor M3 turns on, and the second power supply voltage sets the first input terminal A of the AND gate to the second power supply voltage, that is, a low-level signal, through the third transistor M3. At this time, the output terminal HF_Output of the AND gate outputs a low-level signal.

[0144] In the fourth stage, the reset signal at the HF_Reset terminal is a low-level signal, the first node is reset to -20V, the third transistor M3 is turned off in this stage, the first input terminal A of the AND gate remains at a low level, and the output terminal HF_Output continuously outputs a low-level signal.

[0145] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 charges the control electrode of the third transistor M3 to the first node potential minus the second power supply voltage is greater than the threshold voltage of the third transistor M3 for a period of time, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0146] Fourth example: Figure 4 This is a schematic diagram of a trigger circuit according to a fourth example of an embodiment of this disclosure; as shown Figure 4As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A of the AND gate is electrically connected to the first power supply voltage terminal VDD through the input subcircuit, and the second input terminal B of the AND gate is directly connected to the first power supply voltage terminal VDD. The duty cycle adjustment module is connected to the first input terminal A of the AND gate.

[0147] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first transistor M1, third transistor M3, fifth transistor M5, and sixth transistor M6 have the same switching characteristics; the second transistor M2, fourth transistor M4, seventh transistor M7, and eighth transistor M8 have the same switching characteristics, but different switching characteristics from the first transistor. In this example, the first transistor M1, third transistor M3, fifth transistor M5, and sixth transistor M6 are N-type transistors, while the second transistor M2, fourth transistor M4, seventh transistor M7, and eighth transistor M8 are P-type transistors.

[0148] For details, please refer to... Figure 4The first transistor M1 has its first terminal connected to the first power supply voltage terminal VDD. Its second terminal is connected to the control terminals of the fifth transistor M5 and the eighth transistor M8, serving as the first input terminal A of an AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the second power supply voltage terminal VSS and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the first input terminal A of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the first power supply voltage terminal VDD. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the second power supply voltage terminal VSS. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is connected to the first power supply voltage terminal VDD, the control terminal of the seventh transistor M7, and the first plate of the first capacitor C1, serving as the second input terminal B of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are connected to the first power supply voltage terminal VDD. The second terminal of the first capacitor C1 is connected to the second power supply voltage terminal VSS, and the second terminal of the second capacitor C2 is connected to the first node.

[0149] The following simulation uses an example where the first power supply voltage is 8V, the second power supply voltage is -8V; the input control signal timing is 12V for the high level signal and -12V for the low level signal, with a period H = 100μs and a duty cycle of high level signal / low level signal = 0.1μs / 99.9μs; the reset signal timing is 12V for the high level signal and -20V for the low level signal, with a period H = 100μs and a duty cycle of high level signal / low level signal = 99.9μs / 0.1μs; the data voltage control signal Datastep = [7.42V, 7.4V, 7.3V, 7.2V, 7.1V, 7V, 7.42V, 6.9V, 6.8V, 6.7V]; the first capacitor C1 = 20fF; and the second capacitor C2 = 20pF. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0150] The operation of the fourth example flip-flop circuit will be described next. (Continue referring to...) Figure 4 The steps for generating each clock cycle signal of the clock signal using the touchpad circuit in the fourth example include:

[0151] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a low-level signal, and the first node is reset to -20V. During this stage, the third transistor M3 is turned off.

[0152] In the second stage, the reset signal at the HF_Reset terminal is a high-level signal, and the input control signal written at the HF_Input terminal is also a high-level signal, turning on the first transistor M1. At this time, both the first input terminal A and the second input terminal B of the AND gate are at the first power supply voltage, i.e., high-level signals. Therefore, the output terminal HF_Output of the AND gate outputs a low-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree to which the fourth transistor M4 is turned on, the charging speed of the first node is controlled.

[0153] In the third stage, after time t, the fourth transistor M4 charges the control electrode of the third transistor M3 until the potential of the first node minus the second power supply voltage is greater than the threshold voltage of the third transistor M3, that is, VQ-VSS>Vth. The third transistor M3 turns on, and the second power supply voltage sets the first input terminal A of the AND gate to the second power supply voltage, that is, a low-level signal, through the third transistor M3. The fifth transistor M5 turns off, and the eighth transistor M8 turns on. At this time, the output terminal HF_Output of the AND gate outputs the first power supply voltage, that is, a high-level signal.

[0154] In the fourth stage, the reset signal at the reset signal terminal HF_Reset is a low-level signal, the first node is reset to -20V, the third transistor M3 is turned off in this stage, the first input terminal A of the AND gate remains a low-level signal, and the output terminal HF_Output continuously outputs a high-level signal.

[0155] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 charges the control electrode of the third transistor M3 to the first node potential minus the second power supply voltage is greater than the threshold voltage of the third transistor M3 for a period of time, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0156] Fifth example: Figure 5 This is a schematic diagram of a trigger circuit according to a fifth example of an embodiment of this disclosure; as shown Figure 5As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A of the AND gate is directly electrically connected to the first power supply voltage terminal VDD, and the second input terminal B of the AND gate is connected to the first power supply voltage terminal VDD through the input subcircuit. The duty cycle adjustment module is connected to the second input terminal B of the AND gate.

[0157] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first transistor M1, third transistor M3, fifth transistor M5, and sixth transistor M6 have the same switching characteristics; the second transistor M2, fourth transistor M4, seventh transistor M7, and eighth transistor M8 have the same switching characteristics, but different switching characteristics from the first transistor. In this example, the first transistor M1, third transistor M3, fifth transistor M5, and sixth transistor M6 are N-type transistors, while the second transistor M2, fourth transistor M4, seventh transistor M7, and eighth transistor M8 are P-type transistors.

[0158] For details, please refer to... Figure 5The first transistor M1 has its first terminal connected to the first power supply voltage terminal VDD. Its second terminal is connected to the control terminals of the sixth transistor M6 and the seventh transistor M7, serving as the second input terminal B of an AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the second power supply voltage terminal VSS and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the second input terminal B of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the first power supply voltage terminal VDD. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the second power supply voltage terminal VSS. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The control terminal of the fifth transistor M5 is connected to the control terminal of the eighth transistor M8, serving as the second input terminal B of an AND gate, directly connected to the first power supply voltage terminal VDD. The second terminal of the sixth transistor M6 is connected to the first terminal of the seventh transistor M7 and the second terminal of the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are simultaneously connected to the first power supply voltage terminal VDD. The second terminal of the first capacitor C1 is connected to the first power supply voltage terminal VDD, and the second terminal of the second capacitor C2 is connected to the first node.

[0159] The following simulation of the touchpad circuit in the fifth example uses the following parameters: a first power supply voltage of 8V, a second power supply voltage of -8V; a high-level signal of 12V and a low-level signal of -12V in the timing of the input control signal, a period of H = 100μs, and a duty cycle of high-level signal / low-level signal = 0.1μs / 99.9μs; a high-level signal of 12V and a low-level signal of -20V in the timing of the reset signal, a period of H = 100μs, and a duty cycle of high-level signal / low-level signal = 99.9μs / 0.1μs; a data voltage control signal Datastep = [7.42V, 7.4V, 7.3V, 7.2V, 7.1V, 7V, 7.42V, 6.9V, 6.8V, 6.7V]; a first capacitor C1 = 20fF; and a second capacitor C2 = 20pF. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0160] The operation of the fifth example flip-flop circuit will be described next. (Continue referring to...) Figure 5 The steps for generating each clock cycle signal of the clock signal using the touchscreen circuit in the fifth example include:

[0161] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a low-level signal, and the first node is reset to -20V. During this stage, the third transistor M3 is turned off.

[0162] In the second stage, the reset signal at the HF_Reset terminal is a high-level signal, and the input control signal written at the HF_Input terminal is also a high-level signal, turning on the first transistor M1. At this time, both the first input terminal A and the second input terminal B of the AND gate are at the first power supply voltage, i.e., high-level signals. Therefore, the output terminal HF_Output of the AND gate outputs the second power supply voltage, i.e., a low-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree to which the fourth transistor M4 is turned on, the charging speed of the first node is controlled.

[0163] In the third stage, after time t, the fourth transistor M4 charges the control electrode of the third transistor M3 until the potential of the first node minus the second power supply voltage is greater than the threshold voltage of the third transistor M3, that is, VQ-VSS>Vth. The third transistor M3 turns on, and the second power supply voltage sets the first input terminal A of the AND gate to the second power supply voltage, that is, a low-level signal, through the third transistor M3. At this time, the seventh transistor M7 turns off, the eighth crystal turns on, and the output terminal HF_Output of the AND gate outputs the first power supply voltage, that is, a high-level signal.

[0164] In the fourth stage, the reset signal at the HF_Reset terminal is a low-level signal, the first node is reset to -20V, the third transistor M3 is turned off, the second input terminal B of the AND gate remains a low-level signal, and the output terminal HF_Output continuously outputs a high-level signal.

[0165] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 charges the control electrode of the third transistor M3 to the first node potential minus the second power supply voltage is greater than the threshold voltage of the third transistor M3 for a period of time, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0166] Sixth example: Figure 6 This is a schematic diagram of a trigger circuit according to a sixth example of an embodiment of this disclosure; as shown Figure 6As shown, the touchscreen circuit includes an AND gate, an input control sub-circuit, a duty cycle adjustment sub-circuit, and a reset sub-circuit. The duty cycle adjustment sub-circuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment sub-circuit is the first node, and the reset sub-circuit is connected to the first node. The first input terminal A and the second input terminal B of the AND gate are electrically connected to the first power supply voltage terminal VDD through the input sub-circuit.

[0167] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first transistor M1, third transistor M3, fifth transistor M5, and sixth transistor M6 have the same switching characteristics; the second transistor M2, fourth transistor M4, seventh transistor M7, and eighth transistor M8 have the same switching characteristics, but different switching characteristics from the first transistor. In this example, the first transistor M1, third transistor M3, fifth transistor M5, and sixth transistor M6 are N-type transistors, while the second transistor M2, fourth transistor M4, seventh transistor M7, and eighth transistor M8 are P-type transistors.

[0168] For details, please refer to... Figure 6The first transistor M1 has its first terminal connected to the first power supply voltage terminal VDD. Its second terminal is connected to the control terminals of the fifth transistor M5 and the eighth transistor M8, serving as the first input terminal A of an AND gate. Simultaneously, the second terminal of the first transistor M1 is also connected to the control terminals of the sixth transistor M6 and the seventh transistor M7, serving as the second input terminal B of the AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the second power supply voltage terminal VSS and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the first input terminal A of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the first power supply voltage terminal VDD. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the second power supply voltage terminal VSS. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is connected to the first power supply voltage terminal VDD, the control terminal of the seventh transistor M7, and the first plate of the first capacitor C1, serving as the second input terminal B of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are connected to the first power supply voltage terminal VDD. The second terminal of the first capacitor C1 is connected to the second power supply voltage terminal VSS, and the second terminal of the second capacitor C2 is connected to the first node.

[0169] The following simulation uses an example where the first power supply voltage is 8V, the second power supply voltage is -8V; the input control signal timing is 12V for the high level signal and -12V for the low level signal, with a period H = 100μs and a duty cycle of high level signal / low level signal = 0.1μs / 99.9μs; the reset signal timing is 12V for the high level signal and -20V for the low level signal, with a period H = 100μs and a duty cycle of high level signal / low level signal = 99.9μs / 0.1μs; the data voltage control signal Datastep = [7.42V, 7.4V, 7.3V, 7.2V, 7.1V, 7V, 7.42V, 6.9V, 6.8V, 6.7V]; the first capacitor C1 = 20fF; and the second capacitor C2 = 20pF. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0170] The operation of the sixth example flip-flop circuit will be described next. (Continue referring to...)Figure 6 The steps for generating each clock cycle signal of the clock signal using the touchpad circuit in the sixth example include:

[0171] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a low-level signal, and the first node is reset to -20V. During this stage, the third transistor M3 is turned off.

[0172] In the second stage, the reset signal at the HF_Reset terminal is a high-level signal, and the input control signal written at the HF_Input terminal is also a high-level signal, turning on the first transistor M1. At this time, both the first input terminal A and the second input terminal B of the AND gate are at the first power supply voltage, i.e., high-level signals. Therefore, the output terminal HF_Output of the AND gate outputs the second power supply voltage, i.e., a low-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree to which the fourth transistor M4 is turned on, the charging speed of the first node is controlled.

[0173] In the third stage, after time t, the fourth transistor M4 charges the control electrode of the third transistor M3 until the potential of the first node minus the second power supply voltage is greater than the threshold voltage of the third transistor M3, that is, VQ-VSS>Vth. The third transistor M3 turns on, and the second power supply voltage sets the first input terminal A of the AND gate to the second power supply voltage, that is, a low-level signal, through the third transistor M3. At this time, the fifth transistor M5 turns off, the eighth crystal turns on, and the output terminal HF_Output of the AND gate outputs the first power supply voltage, that is, a high-level signal.

[0174] In the fourth stage, the reset signal at the reset signal terminal HF_Reset is a low-level signal, the first node is reset to -20V, the third transistor M3 is turned off in this stage, the first input terminal A of the AND gate remains a low-level signal, and the output terminal HF_Output continuously outputs a high-level signal.

[0175] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 charges the control electrode of the third transistor M3 to the first node potential minus the second power supply voltage is greater than the threshold voltage of the third transistor M3 for a period of time, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0176] Seventh example: Figure 7 This is a schematic diagram of a trigger circuit according to a seventh example of an embodiment of this disclosure; as shown Figure 7As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A of the AND gate is electrically connected to the first power supply voltage terminal VDD through the input subcircuit, and the second input terminal B of the AND gate is directly connected to the first power supply voltage terminal VDD. The duty cycle adjustment module is connected to the first input terminal A of the AND gate.

[0177] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4, a ninth transistor M9, and a tenth transistor M10. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first transistor M1, third transistor M3, fifth transistor M5, sixth transistor M6, and ninth transistor M9 have the same switching characteristics; the second transistor M2, fourth transistor M4, seventh transistor M7, eighth transistor M8, and tenth transistor M10 have the same switching characteristics, but different switching characteristics from the first transistor. In this example, the first transistor M1, third transistor M3, fifth transistor M5, sixth transistor M6, and ninth transistor M9 are N-type transistors, while the second transistor M2, fourth transistor M4, seventh transistor M7, eighth transistor M8, and tenth transistor M10 are P-type transistors.

[0178] For details, please refer to... Figure 7The first transistor M1 has its first terminal connected to the first power supply voltage terminal VDD. Its second terminal is connected to the control terminals of the fifth transistor M5 and the eighth transistor M8, serving as the first input terminal A of an AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the second power supply voltage terminal VSS and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the first input terminal A of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the first power supply voltage terminal VDD. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the first power supply voltage terminal VDD. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is connected to the first power supply voltage terminal VDD, the control terminal of the seventh transistor M7, and the first plate of the first capacitor C1, serving as the second input terminal B of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are connected to the second power supply voltage terminal VSS. The first terminal of the ninth transistor M9 is connected to the second terminal of the fourth transistor M4 and the first terminal of the tenth transistor M10. The second terminal of the ninth transistor M9 is connected to the first node, and the control terminal of the ninth transistor M9 is connected to the reset signal terminal HF_Reset. The second terminal of the tenth transistor M10 is connected to the first power supply voltage, and the control terminal of the tenth transistor M10 is connected to the first input terminal A of the AND gate. The second terminal of the first capacitor C1 is connected to the first power supply voltage terminal VDD, and the second terminal of the second capacitor C2 is connected to the first node.

[0179] The following simulation uses an example with the following parameters: a first power supply voltage of 8V, a second power supply voltage of -8V; a high-level signal of 12V and a low-level signal of -12V in the timing of the input control signal, a period of H = 100μs, and a duty cycle of high-level signal / low-level signal = 0.1μs / 99.9μs; a reset signal with a high-level signal of 12V and a low-level signal of -20V, a period of H = 100μs, and a duty cycle of high-level signal / low-level signal = 99.9μs / 0.1μs; a data voltage control signal Datastep = [7.43V, 7.42V, 7.3V, 7.2V, 7.1V, 7V, 6.8V, 6.7V]; a first capacitor C1 = 200fF; and a second capacitor C2 = 2pF. It should be understood that these parameters can be adjusted according to actual needs in the actual use of the product.

[0180] The operation of the seventh example flip-flop circuit will now be described. (Continue referring to...) Figure 7 The steps for generating each clock cycle signal of the clock signal using the touchscreen circuit in the seventh example include:

[0181] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a low-level signal, the second transistor M2 is turned on, the ninth transistor M9 is turned off, the first node is reset to -20V, and the third transistor M3 is turned off during this stage.

[0182] In the second stage, the reset signal at the HF_Reset terminal is a high-level signal, the second transistor M2 is turned off, the ninth transistor M9 is turned on, and the input control signal written at the HF_Input terminal is a high-level signal, turning on the first transistor M1. At this time, the first input terminal A and the second input terminal B of the AND gate are both the first power supply voltage, i.e., high-level signals. Therefore, the output terminal HF_Output of the AND gate outputs a high-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree of activation of the fourth transistor M4, the charging speed of the first node is controlled.

[0183] In the third stage, after time t, the fourth transistor M4 charges the control electrode of the third transistor M3 until the potential of the first node minus the second power supply voltage is greater than the threshold voltage of the third transistor M3, i.e., VQ - VSS > Vth. The third transistor M3 then turns on, and the second power supply voltage sets the first input terminal A of the AND gate to the second power supply voltage, i.e., a low-level signal, through the third transistor M3. The fifth transistor M5 turns off, the eighth transistor M8 turns on, and the output terminal HF_Output of the AND gate outputs a low-level signal. Simultaneously, the tenth transistor M10 turns on, the first node charges rapidly, and the third transistor M3 is fully turned on.

[0184] In the fourth stage, the reset signal at the HF_Reset terminal is a low-level signal, the first node is reset to -20V, the third transistor M3 is turned off in this stage, the first input terminal A of the AND gate remains at a low level, and the output terminal HF_Output continuously outputs a low-level signal.

[0185] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 charges the control electrode of the third transistor M3 to the first node potential minus the second power supply voltage is greater than the threshold voltage of the third transistor M3 for a period of time, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0186] Eighth example: Figure 8 This is a schematic diagram of the trigger circuit of the eighth example of the embodiments of this disclosure; as shown Figure 8 As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A of the AND gate is electrically connected to the first power supply voltage terminal VDD through the input subcircuit, and the second input terminal B of the AND gate is directly connected to the first power supply voltage terminal VDD. The duty cycle adjustment module is connected to the first input terminal A of the AND gate.

[0187] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4, a ninth transistor M9, and a tenth transistor M10. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first transistor M1, third transistor M3, fifth transistor M5, sixth transistor M6, and ninth transistor M9 have the same switching characteristics; the second transistor M2, fourth transistor M4, seventh transistor M7, eighth transistor M8, and tenth transistor M10 have the same switching characteristics, but different switching characteristics from the first transistor. In this example, the first transistor M1, third transistor M3, fifth transistor M5, sixth transistor M6, and ninth transistor M9 are N-type transistors, while the second transistor M2, fourth transistor M4, seventh transistor M7, eighth transistor M8, and tenth transistor M10 are P-type transistors.

[0188] For details, please refer to... Figure 8The first transistor M1 has its first terminal connected to the first power supply voltage terminal VDD. Its second terminal is connected to the control terminals of the sixth transistor M6 and the seventh transistor M7, serving as the second input terminal B of an AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the second power supply voltage terminal VSS and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the second input terminal B of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the first power supply voltage terminal VDD. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the first power supply voltage terminal VDD. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The control terminal of the fifth transistor M5 is connected to the control terminal of the eighth transistor M8, serving as the first input terminal A of an AND gate, and is electrically connected to the first power supply voltage terminal VDD. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is also connected to the first plate of the first capacitor C1. The second terminals of the seventh transistor M7 and the first terminals of the eighth transistor M8 are connected, and both are connected to the second power supply voltage terminal VSS. The first terminal of the ninth transistor M9 is connected to the second terminals of the fourth transistor M4 and the tenth transistor M10. The second terminal of the ninth transistor M9 is connected to the first node, and its control terminal is connected to the reset signal terminal HF_Reset. The second terminal of the tenth transistor M10 is connected to the first power supply voltage, and its control terminal is connected to the second input terminal B of the AND gate. The second terminal of the first capacitor C1 is connected to the second power supply voltage terminal VSS, and the second terminal of the second capacitor C2 is connected to the first node.

[0189] The following simulation of the touchpad circuit in the eighth example is based on the following parameters: a first power supply voltage of 8V, a second power supply voltage of -8V; a high-level signal of 12V and a low-level signal of -12V in the timing of the input control signal, a period of H = 100μs, and a duty cycle of high-level signal / low-level signal = 0.1μs / 99.9μs; a high-level signal of 12V and a low-level signal of -20V in the timing of the reset signal, a period of H = 100μs, and a duty cycle of high-level signal / low-level signal = 99.9μs / 0.1μs; a data voltage control signal Datastep = [7.43V, 7.42V, 7.3V, 7.2V, 7.1V, 7V, 6.8V, 6.7V], a first capacitor C1 = 200fF, and a second capacitor C2 = 2pF. It should be understood that the above parameters can be adjusted according to actual needs in the actual use of the product.

[0190] The operation of the eighth example flip-flop circuit will now be described. (Continue referring to...) Figure 8 The steps for generating each clock cycle signal of the clock signal using the touchpad circuit in the eighth example include:

[0191] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a low-level signal, the second transistor M2 is turned on, the ninth transistor M9 is turned off, the first node is reset to -20V, and the third transistor M3 is turned off during this stage.

[0192] In the second stage, the reset signal at the HF_Reset terminal is a high-level signal, the second transistor M2 is turned off, the ninth transistor M9 is turned on, and the input control signal written at the HF_Input terminal is a high-level signal, turning on the first transistor M1. At this time, the first input terminal A and the second input terminal B of the AND gate are both the first power supply voltage, i.e., high-level signals. Therefore, the output terminal HF_Output of the AND gate outputs a high-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree of activation of the fourth transistor M4, the charging speed of the first node is controlled.

[0193] In the third stage, after time t, the fourth transistor M4 charges the control electrode of the third transistor M3 until the potential of the first node minus the second power supply voltage is greater than the threshold voltage of the third transistor M3, i.e., VQ - VSS > Vth. The third transistor M3 then turns on, and the second power supply voltage sets the first input terminal A of the AND gate to the second power supply voltage, i.e., a low-level signal, through the third transistor M3. The sixth transistor M6 turns off, the seventh transistor M7 turns on, and the output terminal HF_Output of the AND gate outputs a low-level signal. Simultaneously, the tenth transistor M10 turns on, the first node charges rapidly, and the third transistor M3 is fully turned on.

[0194] In the fourth stage, the reset signal at the HF_Reset terminal is a low-level signal, the first node is reset to -20V, the third transistor M3 is turned off in this stage, the second input terminal B of the AND gate remains at a low level, and the output terminal HF_Output continuously outputs a low-level signal.

[0195] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 charges the control electrode of the third transistor M3 to the first node potential minus the second power supply voltage is greater than the threshold voltage of the third transistor M3 for a period of time, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0196] Ninth example: Figure 9 This is a schematic diagram of a trigger circuit according to a ninth example of an embodiment of this disclosure; as shown Figure 9 As shown, the touchscreen circuit includes an AND gate, an input control sub-circuit, a duty cycle adjustment sub-circuit, and a reset sub-circuit. The duty cycle adjustment sub-circuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment sub-circuit is the first node, and the reset sub-circuit is connected to the first node. The first input terminal A and the second input terminal B of the AND gate are electrically connected to the first power supply voltage terminal VDD through the input sub-circuit.

[0197] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4, a ninth transistor M9, and a tenth transistor M10. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first transistor M1, third transistor M3, fifth transistor M5, sixth transistor M6, and ninth transistor M9 have the same switching characteristics; the second transistor M2, fourth transistor M4, seventh transistor M7, eighth transistor M8, and tenth transistor M10 have the same switching characteristics, but different switching characteristics from the first transistor. In this example, the first transistor M1, third transistor M3, fifth transistor M5, sixth transistor M6, and ninth transistor M9 are N-type transistors, while the second transistor M2, fourth transistor M4, seventh transistor M7, eighth transistor M8, and tenth transistor M10 are P-type transistors.

[0198] For details, please refer to... Figure 9The first transistor M1 has its first terminal connected to the first power supply voltage terminal VDD. Its second terminal is connected to the control terminals of the fifth transistor M5 and the eighth transistor M8, serving as the first input terminal A of an AND gate. Simultaneously, the second terminal of the first transistor M1 is also connected to the control terminals of the sixth transistor M6 and the seventh transistor M7, serving as the second input terminal B of the AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the second power supply voltage terminal VSS and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the first input terminal A of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the first power supply voltage terminal VDD. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the first power supply voltage terminal VDD. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is connected to the first power supply voltage terminal VDD, the control terminal of the seventh transistor M7, and the first plate of the first capacitor C1, serving as the second input terminal B of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are connected to the second power supply voltage terminal VSS. The first terminal of the ninth transistor M9 is connected to the second terminal of the fourth transistor M4 and the first terminal of the tenth transistor M10. The second terminal of the ninth transistor M9 is connected to the first node, and the control terminal of the ninth transistor M9 is connected to the reset signal terminal HF_Reset. The second terminal of the tenth transistor M10 is connected to the first power supply voltage, and the control terminal of the tenth transistor M10 is connected to the first input terminal A of the AND gate. The second terminal of the first capacitor C1 is connected to the first power supply voltage terminal VDD, and the second terminal of the second capacitor C2 is connected to the first node.

[0199] The following simulation uses an example with the following parameters: a first power supply voltage of 8V, a second power supply voltage of -8V; a high-level signal of 12V and a low-level signal of -12V in the timing of the input control signal, a period of H = 100μs, and a duty cycle of high-level signal / low-level signal = 0.1μs / 99.9μs; a reset signal with a high-level signal of 12V and a low-level signal of -20V, a period of H = 100μs, and a duty cycle of high-level signal / low-level signal = 99.9μs / 0.1μs; a data voltage control signal Datastep = [7.43V, 7.42V, 7.3V, 7.2V, 7.1V, 7V, 6.8V, 6.7V]; a first capacitor C1 = 200fF; and a second capacitor C2 = 2pF. It should be understood that these parameters can be adjusted according to actual needs in the actual use of the product.

[0200] The operation of the ninth example flip-flop circuit will now be described. (Continue referring to...) Figure 9 The steps for generating each clock cycle signal of the clock signal using the touchscreen circuit in the ninth example include:

[0201] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a low-level signal, the second transistor M2 is turned on, the ninth transistor M9 is turned off, the first node is reset to -20V, and the third transistor M3 is turned off during this stage.

[0202] In the second stage, the reset signal at the HF_Reset terminal is a high-level signal, the second transistor M2 is turned off, the ninth transistor M9 is turned on, and the input control signal written at the HF_Input terminal is a high-level signal, turning on the first transistor M1. At this time, the first input terminal A and the second input terminal B of the AND gate are both the first power supply voltage, i.e., high-level signals. Therefore, the output terminal HF_Output of the AND gate outputs a high-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree of activation of the fourth transistor M4, the charging speed of the first node is controlled.

[0203] In the third stage, after time t, the fourth transistor M4 charges the control electrode of the third transistor M3 until the potential of the first node minus the second power supply voltage is greater than the threshold voltage of the third transistor M3, i.e., VQ - VSS > Vth. The third transistor M3 then turns on, and the second power supply voltage sets the first input terminal A of the AND gate to the second power supply voltage, i.e., a low-level signal, through the third transistor M3. The fifth transistor M5 and the sixth transistor M6 turn off, while the seventh transistor M7 and the eighth transistor M8 turn on. The output terminal HF_Output of the AND gate outputs a low-level signal. Simultaneously, the tenth transistor M10 turns on, the first node charges rapidly, and the third transistor M3 is fully turned on.

[0204] In the fourth stage, the reset signal at the HF_Reset terminal is a low-level signal, the first node is reset to -20V, the third transistor M3 is turned off in this stage, the first input terminal A of the AND gate remains at a low level, and the output terminal HF_Output continuously outputs a low-level signal.

[0205] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 charges the control electrode of the third transistor M3 to the first node potential minus the second power supply voltage is greater than the threshold voltage of the third transistor M3 for a period of time, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0206] Tenth example: Figure 10 This is a schematic diagram of a trigger circuit according to a tenth example of an embodiment of this disclosure; as shown... Figure 10 As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A of the AND gate is electrically connected to the first power supply voltage terminal VDD through the input subcircuit, and the second input terminal B of the AND gate is directly connected to the first power supply voltage terminal VDD. The duty cycle adjustment module is connected to the first input terminal A of the AND gate.

[0207] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4, a ninth transistor M9, and a tenth transistor M10. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first transistor M1, third transistor M3, fifth transistor M5, sixth transistor M6, and ninth transistor M9 have the same switching characteristics; the second transistor M2, fourth transistor M4, seventh transistor M7, eighth transistor M8, and tenth transistor M10 have the same switching characteristics, but different switching characteristics from the first transistor. In this example, the first transistor M1, third transistor M3, fifth transistor M5, sixth transistor M6, and ninth transistor M9 are N-type transistors, while the second transistor M2, fourth transistor M4, seventh transistor M7, eighth transistor M8, and tenth transistor M10 are P-type transistors.

[0208] For details, please refer to... Figure 10The first transistor M1 has its first terminal connected to the first power supply voltage terminal VDD. Its second terminal is connected to the control terminals of the fifth transistor M5 and the eighth transistor M8, serving as the first input terminal A of an AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the second power supply voltage terminal VSS and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the first input terminal A of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the first power supply voltage terminal VDD. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the second power supply voltage terminal VSS. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is connected to the first power supply voltage terminal VDD, the control terminal of the seventh transistor M7, and the first plate of the first capacitor C1, serving as the second input terminal B of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are connected to the first power supply voltage terminal VDD. The first terminal of the ninth transistor M9 is connected to the second terminal of the fourth transistor M4 and the first terminal of the tenth transistor M10. The second terminal of the ninth transistor M9 is connected to the first node, and the control terminal of the ninth transistor M9 is connected to the reset signal terminal HF_Reset. The second terminal of the tenth transistor M10 is connected to the first power supply voltage, and the control terminal of the tenth transistor M10 is connected to the first input terminal A of the AND gate. The second terminal of the first capacitor C1 is connected to the second power supply voltage terminal VSS, and the second terminal of the second capacitor C2 is connected to the first node.

[0209] The following simulation uses an example with the following parameters: a first power supply voltage of 8V, a second power supply voltage of -8V; a high-level signal of 12V and a low-level signal of -12V in the timing of the input control signal, a period of H = 100μs, and a duty cycle of high-level signal / low-level signal = 0.1μs / 99.9μs; a reset signal with a high-level signal of 12V and a low-level signal of -20V, a period of H = 100μs, and a duty cycle of high-level signal / low-level signal = 99.9μs / 0.1μs; a data voltage control signal Datastep = [7.43V, 7.42V, 7.3V, 7.2V, 7.1V, 7V, 6.8V, 6.7V]; a first capacitor C1 = 200fF; and a second capacitor C2 = 2pF. It should be understood that these parameters can be adjusted according to actual needs in the actual use of the product.

[0210] The operation of the tenth example flip-flop circuit will be described next. (Continue referring to...) Figure 10 The steps for generating each clock cycle signal of the clock signal using the touchscreen circuit in the tenth example include:

[0211] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a low-level signal, the second transistor M2 is turned on, the ninth transistor M9 is turned off, the first node is reset to -20V, and the third transistor M3 is turned off during this stage.

[0212] In the second stage, the reset signal at the HF_Reset terminal is a high-level signal, turning off the second transistor M2 and turning on the ninth transistor M9. The input control signal written at the HF_Input terminal is a high-level signal, turning on the first transistor M1. At this time, both the first input A and the second input B of the AND gate are at the first power supply voltage, i.e., high-level signals. Therefore, the fifth transistor M5 and the sixth transistor M6 are turned on, and the output terminal HF_Output of the AND gate outputs a low-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree of activation of the fourth transistor M4, the charging speed of the first node is controlled.

[0213] In the third stage, after time t, the fourth transistor M4 charges the control electrode of the third transistor M3 until the potential of the first node minus the second power supply voltage is greater than the threshold voltage of the third transistor M3, i.e., VQ - VSS > Vth. The third transistor M3 then turns on, and the second power supply voltage sets the first input terminal A of the AND gate to the second power supply voltage, i.e., a low-level signal, through the third transistor M3. The fifth transistor M5 turns off, the eighth transistor M8 turns on, and the output terminal HF_Output of the AND gate outputs a high-level signal. Simultaneously, the tenth transistor M10 turns on, the first node charges rapidly, and the third transistor M3 is fully turned on.

[0214] In the fourth stage, the reset signal at the reset signal terminal HF_Reset is a low-level signal, the first node is reset to -20V, the third transistor M3 is turned off in this stage, the first input terminal A of the AND gate remains a low-level signal, and the output terminal HF_Output continuously outputs a high-level signal.

[0215] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 charges the control electrode of the third transistor M3 to the first node potential minus the second power supply voltage is greater than the threshold voltage of the third transistor M3 for a period of time, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0216] Eleventh example: Figure 11 This is a schematic diagram of the trigger circuit of the eleventh example of the embodiments of this disclosure; as shown Figure 11 As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A of the AND gate is electrically connected to the first power supply voltage terminal VDD through the input subcircuit, and the second input terminal B of the AND gate is directly connected to the first power supply voltage terminal VDD. The duty cycle adjustment module is connected to the first input terminal A of the AND gate.

[0217] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4, a ninth transistor M9, and a tenth transistor M10. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first transistor M1, third transistor M3, fifth transistor M5, sixth transistor M6, and ninth transistor M9 have the same switching characteristics; the second transistor M2, fourth transistor M4, seventh transistor M7, eighth transistor M8, and tenth transistor M10 have the same switching characteristics, but different switching characteristics from the first transistor. In this example, the first transistor M1, third transistor M3, fifth transistor M5, sixth transistor M6, and ninth transistor M9 are N-type transistors, while the second transistor M2, fourth transistor M4, seventh transistor M7, eighth transistor M8, and tenth transistor M10 are P-type transistors.

[0218] For details, please refer to... Figure 11The first transistor M1 has its first terminal connected to the first power supply voltage terminal VDD. Its second terminal is connected to the control terminals of the sixth transistor M6 and the seventh transistor M7, serving as the second input terminal B of an AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the second power supply voltage terminal VSS and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the second input terminal B of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the first power supply voltage terminal VDD. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the second power supply voltage terminal VSS. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The control terminal of the fifth transistor M5 is connected to the control terminal of the eighth transistor M8, serving as the first input terminal A of an AND gate, and is electrically connected to the first power supply voltage terminal VDD. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is also connected to the first plate of the first capacitor C1. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are connected to the first power supply voltage terminal VDD. The first terminal of the ninth transistor M9 is connected to the second terminal of the fourth transistor M4 and the first terminal of the tenth transistor M10. The second terminal of the ninth transistor M9 is connected to the first node, and the control terminal of the ninth transistor M9 is connected to the reset signal terminal HF_Reset. The second terminal of the tenth transistor M10 is connected to the first power supply voltage, and the control terminal of the tenth transistor M10 is connected to the second input terminal B of the AND gate. The second terminal of the first capacitor C1 is connected to the first power supply voltage terminal VDD, and the second terminal of the second capacitor C2 is connected to the first node.

[0219] The following simulation of the touchpad circuit in the eleventh example is based on the following parameters: a first power supply voltage of 8V, a second power supply voltage of -8V; a high-level signal of 12V and a low-level signal of -12V in the timing of the input control signal, a period of H = 100μs, and a duty cycle of high-level signal / low-level signal = 0.1μs / 99.9μs; a high-level signal of 12V and a low-level signal of -20V in the timing of the reset signal, a period of H = 100μs, and a duty cycle of high-level signal / low-level signal = 99.9μs / 0.1μs; a data voltage control signal Datastep = [7.43V, 7.42V, 7.3V, 7.2V, 7.1V, 7V, 6.8V, 6.7V]; a first capacitor C1 = 200fF; and a second capacitor C2 = 2pF. It should be understood that the above parameters can be adjusted according to actual needs in the actual use of the product.

[0220] The operation of the eleventh example flip-flop circuit will be described next. (Continue referring to...) Figure 11 The steps for generating each clock cycle signal of the clock signal using the touchpad circuit in the eleventh example include:

[0221] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a low-level signal, the second transistor M2 is turned on, the ninth transistor M9 is turned off, the first node is reset to -20V, and the third transistor M3 is turned off during this stage.

[0222] In the second stage, the reset signal at the HF_Reset terminal is a high-level signal, the second transistor M2 is turned off, the ninth transistor M9 is turned on, and the input control signal written at the HF_Input terminal is a high-level signal, turning on the first transistor M1. At this time, the first input terminal A and the second input terminal B of the AND gate are both the first power supply voltage, i.e., high-level signals. The fifth transistor M5 and the sixth transistor M6 are turned on, so the output terminal HF_Output of the AND gate outputs a low-level signal. At the same time, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree of activation of the fourth transistor M4, the charging speed of the first node is controlled.

[0223] In the third stage, after time t, the fourth transistor M4 charges the control electrode of the third transistor M3 until the potential of the first node minus the second power supply voltage is greater than the threshold voltage of the third transistor M3, i.e., VQ - VSS > Vth. The third transistor M3 then turns on, and the second power supply voltage sets the first input terminal A of the AND gate to the second power supply voltage, i.e., a low-level signal, through the third transistor M3. The sixth transistor M6 turns off, the seventh transistor M7 turns on, and the output terminal HF_Output of the AND gate outputs a high-level signal. Simultaneously, the tenth transistor M10 turns on, the first node charges rapidly, and the third transistor M3 is fully turned on.

[0224] In the fourth stage, the reset signal at the HF_Reset terminal is a low-level signal, the first node is reset to -20V, the third transistor M3 is turned off in this stage, the second input terminal B of the AND gate remains at a low level, and the output terminal HF_Output continuously outputs a low-level signal.

[0225] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 charges the control electrode of the third transistor M3 to the first node potential minus the second power supply voltage is greater than the threshold voltage of the third transistor M3 for a period of time, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0226] Twelfth example: Figure 12 This is a schematic diagram of a trigger circuit according to the twelfth example of an embodiment of this disclosure; as shown Figure 12 As shown, the touchscreen circuit includes an AND gate, an input control sub-circuit, a duty cycle adjustment sub-circuit, and a reset sub-circuit. The duty cycle adjustment sub-circuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment sub-circuit is the first node, and the reset sub-circuit is connected to the first node. The first input terminal A and the second input terminal B of the AND gate are electrically connected to the first power supply voltage terminal VDD through the input sub-circuit.

[0227] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4, a ninth transistor M9, and a tenth transistor M10. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first transistor M1, third transistor M3, fifth transistor M5, sixth transistor M6, and ninth transistor M9 have the same switching characteristics; the second transistor M2, fourth transistor M4, seventh transistor M7, eighth transistor M8, and tenth transistor M10 have the same switching characteristics, but different switching characteristics from the first transistor. In this example, the first transistor M1, third transistor M3, fifth transistor M5, sixth transistor M6, and ninth transistor M9 are N-type transistors, while the second transistor M2, fourth transistor M4, seventh transistor M7, eighth transistor M8, and tenth transistor M10 are P-type transistors.

[0228] For details, please refer to... Figure 12The first transistor M1 has its first terminal connected to the first power supply voltage terminal VDD. Its second terminal is connected to the control terminals of the fifth transistor M5 and the eighth transistor M8, serving as the first input terminal A of an AND gate. Simultaneously, the second terminal of the first transistor M1 is also connected to the control terminals of the sixth transistor M6 and the seventh transistor M7, serving as the second input terminal B of the AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the second power supply voltage terminal VSS and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the first input terminal A of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the first power supply voltage terminal VDD. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the second power supply voltage terminal VSS. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is connected to the first power supply voltage terminal VDD, the control terminal of the seventh transistor M7, and the first plate of the first capacitor C1, serving as the second input terminal B of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are connected to the first power supply voltage terminal VDD. The first terminal of the ninth transistor M9 is connected to the second terminal of the fourth transistor M4 and the first terminal of the tenth transistor M10. The second terminal of the ninth transistor M9 is connected to the first node, and the control terminal of the ninth transistor M9 is connected to the reset signal terminal HF_Reset. The second terminal of the tenth transistor M10 is connected to the first power supply voltage, and the control terminal of the tenth transistor M10 is connected to the first input terminal A of the AND gate. The second terminal of the first capacitor C1 is connected to the second power supply voltage terminal VSS, and the second terminal of the second capacitor C2 is connected to the first node.

[0229] The following simulation uses an example with the following parameters: a first power supply voltage of 8V, a second power supply voltage of -8V; a high-level signal of 12V and a low-level signal of -12V in the timing of the input control signal, a period of H = 100μs, and a duty cycle of high-level signal / low-level signal = 0.1μs / 99.9μs; a reset signal with a high-level signal of 12V and a low-level signal of -20V, a period of H = 100μs, and a duty cycle of high-level signal / low-level signal = 99.9μs / 0.1μs; a data voltage control signal Datastep = [7.43V, 7.42V, 7.3V, 7.2V, 7.1V, 7V, 6.8V, 6.7V]; a first capacitor C1 = 200fF; and a second capacitor C2 = 2pF. It should be understood that these parameters can be adjusted according to actual needs in the actual use of the product.

[0230] The operation of the twelfth example flip-flop circuit will be described next. (Continue referring to...) Figure 12 The steps for generating each clock cycle signal of the clock signal using the touchscreen circuit in the twelfth example include:

[0231] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a low-level signal, the second transistor M2 is turned on, the ninth transistor M9 is turned off, the first node is reset to -20V, and the third transistor M3 is turned off during this stage.

[0232] In the second stage, the reset signal at the HF_Reset terminal is a high-level signal, the second transistor M2 is turned off, the ninth transistor M9 is turned on, and the input control signal written at the HF_Input terminal is a high-level signal, turning on the first transistor M1. At this time, the first input terminal A and the second input terminal B of the AND gate are both the first power supply voltage, i.e., high-level signals. Therefore, the output terminal HF_Output of the AND gate outputs a high-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree of activation of the fourth transistor M4, the charging speed of the first node is controlled.

[0233] In the third stage, after time t, the fourth transistor M4 charges the control electrode of the third transistor M3 until the potential of the first node minus the second power supply voltage is greater than the threshold voltage of the third transistor M3, i.e., VQ - VSS > Vth. The third transistor M3 then turns on, and the second power supply voltage sets the first input terminal A of the AND gate to the second power supply voltage, i.e., a low-level signal, through the third transistor M3. The fifth transistor M5 and the sixth transistor M6 turn off, while the seventh transistor M7 and the eighth transistor M8 turn on. The output terminal HF_Output of the AND gate outputs a low-level signal. Simultaneously, the tenth transistor M10 turns on, the first node charges rapidly, and the third transistor M3 is fully turned on.

[0234] In the fourth stage, the reset signal at the HF_Reset terminal is a low-level signal, the first node is reset to -20V, the third transistor M3 is turned off in this stage, the first input terminal A of the AND gate remains at a low level, and the output terminal HF_Output continuously outputs a low-level signal.

[0235] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 charges the control electrode of the third transistor M3 to the first node potential minus the second power supply voltage is greater than the threshold voltage of the third transistor M3 for a period of time, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0236] The thirteenth example: Figure 13 This is a schematic diagram of the trigger circuit of the thirteenth example of the embodiments of this disclosure; as shown Figure 13 As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A of the AND gate is electrically connected to the second power supply voltage terminal VSS through the input subcircuit, and the second input terminal B of the AND gate is directly connected to the first power supply voltage terminal VDD. The duty cycle adjustment module is connected to the first input terminal A of the AND gate.

[0237] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The second transistor M2, fourth transistor M4, fifth transistor M5, and sixth transistor M6 have the same switching characteristics; the first transistor M1, third transistor M3, seventh transistor M7, and eighth transistor M8 have the same switching characteristics, but different switching characteristics from the second transistor. In this example, the second transistor M2, fourth transistor M4, fifth transistor M5, and sixth transistor M6 are N-type transistors, while the first transistor M1, third transistor M3, seventh transistor M7, and eighth transistor M8 are P-type transistors.

[0238] For details, please refer to... Figure 13 The first transistor M1 has its first terminal connected to the second power supply voltage terminal VSS. Its second terminal is connected to the control terminals of the fifth transistor M5 and the eighth transistor M8, serving as the first input terminal A of an AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the first power supply voltage terminal VDD and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the first input terminal A of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the second power supply voltage terminal VSS. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the first power supply voltage terminal VDD. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is connected to the first power supply voltage terminal VDD, the control terminal of the seventh transistor M7, and the first plate of the first capacitor C1, serving as the second input terminal B of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are connected to the second power supply voltage terminal VSS. The second terminal of the first capacitor C1 is connected to the first power supply voltage terminal VDD, and the second terminal of the second capacitor C2 is connected to the first node.

[0239] The following assumes a first power supply voltage of 8V and a second power supply voltage of -8V; in the timing of the input control signals, the high-level signal is 12V, the low-level signal is -12V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 0.1μs / 99.9μs; in the timing of the reset signal, the high-level signal is 12V, the low-level signal is -20V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 99.9μs. / 0.1μs; Data voltage control signal Datastep=[-7.55V, -7.5V, -7.45V, -7.4V, -7.3V, -7.2V, -7.1V, -6.9V, -6.7V], first capacitor C1=200fF, second capacitor C2=2pF. Taking the thirteenth example as an example, the touch circuit is simulated. It should be understood that in the actual use of the product, the above parameters can be adjusted according to the actual needs.

[0240] The operation of the thirteenth example flip-flop circuit will be described next. (Continue referring to...) Figure 13 The steps for generating each clock cycle signal of the clock signal using the touchscreen circuit in the thirteenth example include:

[0241] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a high-level signal, and the first node is reset to 20V. During this stage, the third transistor M3 is turned off.

[0242] In the second stage, the reset signal at the HF_Reset terminal is a low-level signal, and the input control signal written at the HF_Input terminal is also a low-level signal. The first transistor M1 is turned on. At this time, the first input A and the second input B of the AND gate are both at the second power supply voltage. The fifth transistor M5 is turned off, and the eighth transistor M8 is turned on. Therefore, the output terminal HF_Output of the AND gate outputs a low-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree to which the fourth transistor M4 is turned on, the charging speed of the first node is controlled.

[0243] In the third stage, after time t, the fourth transistor M4 discharges to the control electrode of the third transistor M3 until the potential of the first node minus the first power supply voltage is less than the threshold voltage of the third transistor M3, that is, VQ-VDD<Vth. The third transistor M3 turns on, and the first power supply voltage sets the first input terminal A of the AND gate to the first power supply voltage, that is, a high-level signal, through the third transistor M3. The fifth transistor M5 turns on, and at this time, the output terminal HF_Output of the AND gate outputs a high-level signal.

[0244] In the fourth stage, the reset signal at the reset signal terminal HF_Reset is a low-level signal, the first node is reset to 20V, the third transistor M3 is turned off in this stage, the first input terminal A of the AND gate remains a low-level signal, and the output terminal HF_Output continuously outputs a high-level signal.

[0245] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 charges the control electrode of the third transistor M3 to the potential of the first node minus the first power supply voltage is less than the threshold voltage of the third transistor M3 for a period of time, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0246] Fourteenth example: Figure 14 This is a schematic diagram of the trigger circuit of the fourteenth example of the embodiments of this disclosure; as shown Figure 14 As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A of the AND gate is directly electrically connected to the first power supply voltage terminal VDD, and the second input terminal B of the AND gate is connected to the second power supply voltage terminal VSS through the input subcircuit. The duty cycle adjustment module is connected to the second input terminal B of the AND gate.

[0247] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The second transistor M2, fourth transistor M4, fifth transistor M5, and sixth transistor M6 have the same switching characteristics; the first transistor M1, third transistor M3, seventh transistor M7, and eighth transistor M8 have the same switching characteristics, but different switching characteristics from the second transistor. In this example, the second transistor M2, fourth transistor M4, fifth transistor M5, and sixth transistor M6 are N-type transistors, while the first transistor M1, third transistor M3, seventh transistor M7, and eighth transistor M8 are P-type transistors.

[0248] For details, please refer to... Figure 14The first transistor M1 has its first terminal connected to the second power supply voltage terminal VSS. Its second terminal is connected to the control terminals of the sixth transistor M6 and the seventh transistor M7, serving as the second input terminal B of an AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the first power supply voltage terminal VDD and the second terminal of the second capacitor C2. Its second terminal is connected to the first terminal of the first capacitor C1 and the second input terminal B of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the second power supply voltage terminal VSS. Its second terminal is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the first power supply voltage terminal VDD. Its second terminal is connected to the first terminal of the sixth transistor M6. The control terminal of the fifth transistor M5 is connected to the control terminal of the eighth transistor M8, serving as the second input terminal B of an AND gate, directly connected to the first power supply voltage terminal VDD. The second terminal of the sixth transistor M6 is connected to the first terminal of the seventh transistor M7 and the second terminal of the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are simultaneously connected to the second power supply voltage terminal VSS. The second terminal of the first capacitor C1 is connected to the first power supply voltage terminal VDD, and the second terminal of the second capacitor C2 is connected to the first node.

[0249] The following assumes a first power supply voltage of 8V and a second power supply voltage of -8V; in the timing of the input control signals, the high-level signal is 12V, the low-level signal is -12V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 0.1μs / 99.9μs; in the timing of the reset signal, the high-level signal is 12V, the low-level signal is -20V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 99.9μs. / 0.1μs; Data voltage control signal Datastep=[-7.55V, -7.5V, -7.45V, -7.4V, -7.3V, -7.2V, -7.1V, -6.9V, -6.7V], first capacitor C1=200fF, second capacitor C2=2pF. Taking the touch circuit in the fourteenth example as an example, it should be understood that the above parameters can be adjusted according to actual needs in the actual use of the product.

[0250] The operation of the fourteenth example flip-flop circuit will now be described. (Continue referring to...) Figure 14 The steps for generating each clock cycle signal of the clock signal using the touchpad circuit in the fourteenth example include:

[0251] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a high-level signal, and the first node is reset to 20V. During this stage, the third transistor M3 is turned off.

[0252] In the second stage, the reset signal at the HF_Reset terminal is a low-level signal, and the input control signal written at the HF_Input terminal is also a low-level signal. The first transistor M1 is turned on. At this time, the first input A and the second input B of the AND gate are both at the second power supply voltage. The sixth transistor M6 is turned off, and the seventh transistor M7 is turned on. Therefore, the output terminal HF_Output of the AND gate outputs a low-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree to which the fourth transistor M4 is turned on, the charging speed of the first node is controlled.

[0253] In the third stage, after time t, the fourth transistor M4 discharges to the control electrode of the third transistor M3 until the potential of the first node minus the first power supply voltage is less than the threshold voltage of the third transistor M3, that is, VQ-VDD<Vth. The third transistor M3 turns on, and the first power supply voltage sets the second input terminal B of the AND gate to the first power supply voltage, that is, a high-level signal, through the third transistor M3. The sixth transistor M6 turns on, and at this time, the output terminal HF_Output of the AND gate outputs a high-level signal.

[0254] In the fourth stage, the reset signal at the reset signal terminal HF_Reset is a low-level signal, the first node is reset to 20V, the third transistor M3 is turned off in this stage, the first input terminal A of the AND gate remains a low-level signal, and the output terminal HF_Output continuously outputs a high-level signal.

[0255] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 charges the control electrode of the third transistor M3 to the potential of the first node minus the first power supply voltage is less than the threshold voltage of the third transistor M3 for a period of time, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0256] The fifteenth example: Figure 15 This is a schematic diagram of a trigger circuit according to the fifteenth example of an embodiment of this disclosure; as shown Figure 15As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A and the second input terminal B of the AND gate are electrically connected to the second power supply voltage terminal VSS through the input subcircuit.

[0257] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The second transistor M2, fourth transistor M4, fifth transistor M5, and sixth transistor M6 have the same switching characteristics; the first transistor M1, third transistor M3, seventh transistor M7, and eighth transistor M8 have the same switching characteristics, but different switching characteristics from the second transistor. In this example, the second transistor M2, fourth transistor M4, fifth transistor M5, and sixth transistor M6 are N-type transistors, while the first transistor M1, third transistor M3, seventh transistor M7, and eighth transistor M8 are P-type transistors.

[0258] For details, please refer to... Figure 15The first transistor M1 has its first terminal connected to the second power supply voltage terminal VSS. Its second terminal is connected to the control terminals of the fifth transistor M5 and the eighth transistor M8, serving as the first input terminal A of an AND gate. Simultaneously, the second terminal of the first transistor M1 is also connected to the control terminals of the sixth transistor M6 and the seventh transistor M7, serving as the second input terminal B of the AND gate. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the first power supply voltage terminal VDD and the second terminal of the second capacitor C2. Its second terminal is connected to the first terminal of the first capacitor C1 and the first input terminal A of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the second power supply voltage terminal VSS. Its second terminal is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the second power supply voltage terminal VSS. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is connected to the first power supply voltage terminal VDD, the control terminal of the seventh transistor M7, and the first plate of the first capacitor C1, serving as the second input terminal B of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are connected to the first power supply voltage terminal VDD. The second terminal of the first capacitor C1 is connected to the first power supply voltage terminal VDD, and the second terminal of the second capacitor C2 is connected to the first node.

[0259] The following assumes a first power supply voltage of 8V and a second power supply voltage of -8V; in the timing of the input control signals, the high-level signal is 12V, the low-level signal is -12V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 0.1μs / 99.9μs; in the timing of the reset signal, the high-level signal is 12V, the low-level signal is -20V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 99.9μs. / 0.1μs; Data voltage control signal Datastep=[-7.55V, -7.5V, -7.45V, -7.4V, -7.3V, -7.2V, -7.1V, -6.9V, -6.7V], first capacitor C1=200fF, second capacitor C2=2pF. Taking the touch circuit in the fifteenth example as an example, it should be understood that the above parameters can be adjusted according to actual needs in the actual use of the product.

[0260] The operation of the fifteenth example flip-flop circuit will now be described. (Continue referring to...) Figure 15The steps for generating each clock cycle signal of the clock signal using the touchscreen circuit in the fifteenth example include:

[0261] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a high-level signal, and the first node is reset to 20V. During this stage, the third transistor M3 is turned off.

[0262] In the second stage, the reset signal at the HF_Reset terminal is a low-level signal, and the input control signal written at the HF_Input terminal is also a low-level signal. The first transistor M1 is turned on. At this time, the first input A and the second input B of the AND gate are both at the second power supply voltage. The fifth transistor M5 and the sixth transistor M6 are both turned off, while the seventh transistor M7 and the eighth transistor M8 are both turned on. Therefore, the output terminal HF_Output of the AND gate outputs a low-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree to which the fourth transistor M4 is turned on, the charging speed of the first node is controlled.

[0263] In the third stage, after time t, the fourth transistor M4 discharges to the control electrode of the third transistor M3 until the potential of the first node minus the first power supply voltage is less than the threshold voltage of the third transistor M3, that is, VQ-VDD<Vth. The third transistor M3 turns on, and the first power supply voltage sets the first input terminal A of the AND gate to the first power supply voltage, that is, a high-level signal, through the third transistor M3. The fifth transistor M5 turns on, and at this time, the output terminal HF_Output of the AND gate outputs a high-level signal.

[0264] In the fourth stage, the reset signal at the reset signal terminal HF_Reset is a low-level signal, the first node is reset to 20V, the third transistor M3 is turned off in this stage, the first input terminal A of the AND gate remains a low-level signal, and the output terminal HF_Output continuously outputs a high-level signal.

[0265] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 charges the control electrode of the third transistor M3 to the potential of the first node minus the first power supply voltage is less than the threshold voltage of the third transistor M3 for a period of time, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0266] Sixteenth example: Figure 16 This is a schematic diagram of a trigger circuit according to the sixteenth example of an embodiment of this disclosure; as shown Figure 16As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A of the AND gate is electrically connected to the second power supply voltage terminal VSS through the input subcircuit, and the second input terminal B of the AND gate is directly connected to the first power supply voltage terminal VDD. The duty cycle adjustment module is connected to the first input terminal A of the AND gate.

[0267] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The second transistor M2, fourth transistor M4, fifth transistor M5, and sixth transistor M6 have the same switching characteristics; the first transistor M1, third transistor M3, seventh transistor M7, and eighth transistor M8 have the same switching characteristics, but different switching characteristics from the second transistor. In this example, the second transistor M2, fourth transistor M4, fifth transistor M5, and sixth transistor M6 are N-type transistors, while the first transistor M1, third transistor M3, seventh transistor M7, and eighth transistor M8 are P-type transistors.

[0268] For details, please refer to... Figure 16The first transistor M1 has its first terminal connected to the second power supply voltage terminal VSS. Its second terminal is connected to the control terminals of the fifth transistor M5 and the eighth transistor M8, serving as the first input terminal A of an AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the first power supply voltage terminal VDD and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the first input terminal A of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the second power supply voltage terminal VSS. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the second power supply voltage terminal VSS. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is connected to the first power supply voltage terminal VDD, the control terminal of the seventh transistor M7, and the first plate of the first capacitor C1, serving as the second input terminal B of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are connected to the first power supply voltage terminal VDD. The second terminal of the first capacitor C1 is connected to the second power supply voltage terminal VSS, and the second terminal of the second capacitor C2 is connected to the first node.

[0269] The following assumes a first power supply voltage of 8V and a second power supply voltage of -8V; in the timing of the input control signals, the high-level signal is 12V, the low-level signal is -12V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 0.1μs / 99.9μs; in the timing of the reset signal, the high-level signal is 12V, the low-level signal is -20V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 99.9μs. / 0.1μs; Data voltage control signal Datastep=[-7.55V, -7.5V, -7.45V, -7.4V, -7.3V, -7.2V, -7.1V, -6.9V, -6.7V], first capacitor C1=200fF, second capacitor C2=2pF. Taking the sixteenth example, the touch circuit is simulated. It should be understood that in the actual use of the product, the above parameters can be adjusted according to the actual needs.

[0270] The operation of the sixteenth example flip-flop circuit will be described next. (Continue referring to...) Figure 16 The steps for generating each clock cycle signal of the clock signal using the touchscreen circuit in the sixteenth example include:

[0271] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a high-level signal, and the first node is reset to 20V. During this stage, the third transistor M3 is turned off.

[0272] In the second stage, the reset signal at the HF_Reset terminal is a low-level signal, and the input control signal written at the HF_Input terminal is also a low-level signal. The first transistor M1 is turned on. At this time, the first input A of the AND gate is the second power supply voltage, and the second input B is the first power supply voltage. The fifth transistor M5 is turned off, and the eighth transistor M8 is turned on. Therefore, the output terminal HF_Output of the AND gate outputs a high-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree to which the fourth transistor M4 is turned on, the charging speed of the first node is controlled.

[0273] In the third stage, after time t, the fourth transistor M4 discharges to the control electrode of the third transistor M3 until the potential of the first node minus the first power supply voltage is less than the threshold voltage of the third transistor M3, that is, VQ-VDD<Vth. The third transistor M3 turns on, and the first power supply voltage sets the first input terminal A of the AND gate to the first power supply voltage, that is, a high-level signal, through the third transistor M3. The fifth transistor M5 turns on, and at this time, the output terminal HF_Output of the AND gate outputs a low-level signal.

[0274] In the fourth stage, the reset signal at the reset signal terminal HF_Reset is a low-level signal, the first node is reset to 20V, the third transistor M3 is turned off, the first input terminal A of the AND gate remains at a low level, the eighth transistor M8 is turned on, and the output terminal HF_Output continuously outputs a high-level signal.

[0275] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 discharges to the control electrode of the third transistor M3 for the duration from the potential of the first node to the first power supply voltage being less than the threshold voltage of the third transistor M3, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0276] Seventeenth example: Figure 17 This is a schematic diagram of the trigger circuit of the seventeenth example of the embodiments of this disclosure; as shown Figure 17As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A of the AND gate is directly electrically connected to the first power supply voltage terminal VDD, and the second input terminal B of the AND gate is connected to the second power supply voltage terminal VSS through the input subcircuit. The duty cycle adjustment module is connected to the second input terminal B of the AND gate.

[0277] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The second transistor M2, fourth transistor M4, fifth transistor M5, and sixth transistor M6 have the same switching characteristics; the first transistor M1, third transistor M3, seventh transistor M7, and eighth transistor M8 have the same switching characteristics, but different switching characteristics from the second transistor. In this example, the second transistor M2, fourth transistor M4, fifth transistor M5, and sixth transistor M6 are N-type transistors, while the first transistor M1, third transistor M3, seventh transistor M7, and eighth transistor M8 are P-type transistors.

[0278] For details, please refer to... Figure 17The first transistor M1 has its first terminal connected to the second power supply voltage terminal VSS. Its second terminal is connected to the control terminals of the sixth transistor M6 and the seventh transistor M7, serving as the second input terminal B of an AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the first power supply voltage terminal VDD and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the second input terminal B of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the second power supply voltage terminal VSS. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the second power supply voltage terminal VSS. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The control terminal of the fifth transistor M5 is connected to the control terminal of the eighth transistor M8, serving as the second input terminal B of an AND gate, directly connected to the first power supply voltage terminal VDD. The second terminal of the sixth transistor M6 is connected to the first terminal of the seventh transistor M7 and the second terminal of the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are simultaneously connected to the first power supply voltage terminal VDD. The second terminal of the first capacitor C1 is connected to the first power supply voltage terminal VDD, and the second terminal of the second capacitor C2 is connected to the first node.

[0279] The following assumes a first power supply voltage of 8V and a second power supply voltage of -8V; in the timing of the input control signals, the high-level signal is 12V, the low-level signal is -12V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 0.1μs / 99.9μs; in the timing of the reset signal, the high-level signal is 12V, the low-level signal is -20V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 99.9μs. / 0.1μs; Data voltage control signal Datastep=[-7.55V, -7.5V, -7.45V, -7.4V, -7.3V, -7.2V, -7.1V, -6.9V, -6.7V], first capacitor C1=200fF, second capacitor C2=2pF. Taking the touch circuit in the seventeenth example as an example, it should be understood that the above parameters can be adjusted according to actual needs in the actual use of the product.

[0280] The operation of the seventeenth example flip-flop circuit will be described next. (Continue referring to...) Figure 17 The steps for generating each clock cycle signal of the clock signal using the touchscreen circuit in the seventeenth example include:

[0281] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a high-level signal, and the first node is reset to 20V. During this stage, the third transistor M3 is turned off.

[0282] In the second stage, the reset signal at the HF_Reset terminal is a low-level signal, and the input control signal written at the HF_Input terminal is also a low-level signal. The first transistor M1 is turned on. At this time, the first input A of the AND gate is the first power supply voltage, and the second input B is the second power supply voltage. The sixth transistor M6 is turned off, and the seventh transistor M7 is turned on. Therefore, the output terminal HF_Output of the AND gate outputs a high-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree to which the fourth transistor M4 is turned on, the charging speed of the first node is controlled.

[0283] In the third stage, after time t, the fourth transistor M4 charges the control electrode of the third transistor M3 to the potential of the first node minus the first power supply voltage, which is less than the threshold voltage of the third transistor M3, i.e., VQ-VDD<Vth. The third transistor M3 turns on, and the first power supply voltage sets the second input terminal B of the AND gate to the first power supply voltage, i.e., a high-level signal, through the third transistor M3. The sixth transistor M6 turns on, and at this time, the output terminal HF_Output of the AND gate outputs a low-level signal.

[0284] In the fourth stage, the reset signal at the HF_Reset terminal is a low-level signal, the first node is reset to 20V, the third transistor M3 is turned off, the second input terminal B of the AND gate remains at a low level, the seventh transistor M7 is turned on, and the output terminal HF_Output continuously outputs a high-level signal.

[0285] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 charges the control electrode of the third transistor M3 to the potential of the first node minus the first power supply voltage is less than the threshold voltage of the third transistor M3 for a period of time, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0286] Eighteenth example: Figure 18 This is a schematic diagram of a trigger circuit according to the eighteenth example of an embodiment of this disclosure; as shown Figure 18As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A and the second input terminal B of the AND gate are electrically connected to the second power supply voltage terminal VSS through the input subcircuit.

[0287] Among them, continue to refer to Figure 18 The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 have the same switching characteristics; the first transistor M1, the third transistor M3, the seventh transistor M7, and the eighth transistor M8 have the same switching characteristics, but different switching characteristics from the second transistor. In this example, the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are N-type transistors, and the first transistor M1, the third transistor M3, the seventh transistor M7, and the eighth transistor M8 are P-type transistors.

[0288] Specifically, the first terminal of the first transistor M1 is connected to the second power supply voltage terminal VSS. The second terminal of the first transistor M1 is connected to the control terminals of the fifth transistor M5 and the eighth transistor M8, serving as the first input terminal A of the AND gate. Simultaneously, the second terminal of the first transistor M1 is also connected to the control terminals of the sixth transistor M6 and the seventh transistor M7, serving as the second input terminal B of the AND gate. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the first power supply voltage terminal VDD and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the first input terminal A of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the second power supply voltage terminal VSS. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the second power supply voltage terminal VSS. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is connected to the first power supply voltage terminal VDD, the control terminal of the seventh transistor M7, and the first plate of the first capacitor C1, serving as the second input terminal B of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are connected to the first power supply voltage terminal VDD. The second terminal of the first capacitor C1 is connected to the second power supply voltage terminal VSS, and the second terminal of the second capacitor C2 is connected to the first node.

[0289] The following assumes a first power supply voltage of 8V and a second power supply voltage of -8V; in the timing of the input control signals, the high-level signal is 12V, the low-level signal is -12V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 0.1μs / 99.9μs; in the timing of the reset signal, the high-level signal is 12V, the low-level signal is -20V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 99.9μs. / 0.1μs; Data voltage control signal Datastep=[-7.55V, -7.5V, -7.45V, -7.4V, -7.3V, -7.2V, -7.1V, -6.9V, -6.7V], first capacitor C1=200fF, second capacitor C2=2pF. Taking the touch circuit in the eighteenth example as an example, it should be understood that the above parameters can be adjusted according to actual needs in the actual use of the product.

[0290] The operation of the eighteenth example flip-flop circuit will be described next. (Continue referring to...) Figure 18The steps for generating each clock cycle signal of the clock signal using the touchscreen circuit in the eighteenth example include:

[0291] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a high-level signal, and the first node is reset to 20V. During this stage, the third transistor M3 is turned off.

[0292] In the second stage, the reset signal at the HF_Reset terminal is a low-level signal, and the input control signal written at the HF_Input terminal is also a low-level signal. The first transistor M1 is turned on. At this time, the first input A and the second input B of the AND gate are both at the second power supply voltage. The fifth transistor M5 and the sixth transistor M6 are turned off, while the seventh transistor M7 and the eighth transistor M8 are turned on. Therefore, the output terminal HF_Output of the AND gate outputs a high-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree to which the fourth transistor M4 is turned on, the charging speed of the first node is controlled.

[0293] In the third stage, after time t, the fourth transistor M4 discharges to the control electrode of the third transistor M3 until the potential of the first node minus the first power supply voltage is less than the threshold voltage of the third transistor M3, that is, VQ-VDD<Vth. The third transistor M3 turns on, and the first power supply voltage sets the first input terminal A of the AND gate to the first power supply voltage, that is, a high-level signal, through the third transistor M3. The fifth transistor M5 turns on, and at this time, the output terminal HF_Output of the AND gate outputs a low-level signal.

[0294] In the fourth stage, the reset signal at the reset signal terminal HF_Reset is a low-level signal, the first node is reset to 20V, the third transistor M3 is turned off, the first input terminal A of the AND gate remains at a low level, the eighth transistor M8 is turned on, and the output terminal HF_Output continuously outputs a high-level signal.

[0295] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 discharges to the control electrode of the third transistor M3 for the duration from the potential of the first node to the first power supply voltage being less than the threshold voltage of the third transistor M3, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0296] Nineteenth example: Figure 19 This is a schematic diagram of a trigger circuit according to the nineteenth example of an embodiment of this disclosure; as shown Figure 19As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A of the AND gate is electrically connected to the second power supply voltage terminal VSS through the input subcircuit, and the second input terminal B of the AND gate is directly connected to the first power supply voltage terminal VDD. The duty cycle adjustment module is connected to the first input terminal A of the AND gate.

[0297] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4, a ninth transistor M9, and a tenth transistor M10. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The second transistor M2, fourth transistor M4, fifth transistor M5, sixth transistor M6, and tenth transistor M10 have the same switching characteristics; the first transistor M1, third transistor M3, seventh transistor M7, eighth transistor M8, and ninth transistor M9 have the same switching characteristics, but different switching characteristics from the second transistor. In this example, the second transistor M2, fourth transistor M4, fifth transistor M5, sixth transistor M6, and tenth transistor M10 are N-type transistors, while the first transistor M1, third transistor M3, seventh transistor M7, eighth transistor M8, and ninth transistor M9 are P-type transistors.

[0298] For details, please refer to... Figure 19The first transistor M1 has its first terminal connected to the second power supply voltage terminal VSS. Its second terminal is connected to the control terminals of the fifth transistor M5 and the eighth transistor M8, serving as the first input terminal A of an AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the first power supply voltage terminal VDD and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the first input terminal A of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the second power supply voltage terminal VSS. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the first power supply voltage terminal VDD. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is connected to the first power supply voltage terminal VDD, the control terminal of the seventh transistor M7, and the first plate of the first capacitor C1, serving as the second input terminal B of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are connected to the first power supply voltage terminal VDD. The first terminal of the ninth transistor M9 is connected to the second terminal of the fourth transistor M4 and the first terminal of the tenth transistor M10. The second terminal of the ninth transistor M9 is connected to the first node, and the control terminal of the ninth transistor M9 is connected to the reset signal terminal HF_Reset. The second terminal of the tenth transistor M10 is connected to the second power supply voltage, and the control terminal of the tenth transistor M10 is connected to the first input terminal A of the AND gate. The second terminal of the first capacitor C1 is connected to the first power supply voltage terminal VDD, and the second terminal of the second capacitor C2 is connected to the first node.

[0299] The following assumes a first power supply voltage of 8V and a second power supply voltage of -8V; in the timing of the input control signals, the high-level signal is 12V, the low-level signal is -12V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 0.1μs / 99.9μs; in the timing of the reset signal, the high-level signal is 12V, the low-level signal is -20V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 99.9μs. / 0.1μs; Data voltage control signal Datastep=[-7.55V, -7.5V, -7.45V, -7.4V, -7.3V, -7.2V, -7.1V, -6.9V, -6.7V], first capacitor C1=200fF, second capacitor C2=2pF. Taking the touch circuit in the nineteenth example as an example, it should be understood that the above parameters can be adjusted according to actual needs in the actual use of the product.

[0300] The operation of the nineteenth example flip-flop circuit will now be described. (Continue referring to...) Figure 19 The steps for generating each clock cycle signal of the clock signal using the touchscreen circuit in the nineteenth example include:

[0301] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a high-level signal, and the first node is reset to 20V. During this stage, the third transistor M3 is turned off.

[0302] In the second stage, the reset signal at the HF_Reset terminal is a low-level signal, the second transistor M2 is turned off, the ninth transistor M9 is turned on, and the input control signal written at the HF_Input terminal is a low-level signal, turning on the first transistor M1. At this time, the first input A of the AND gate is the second power supply voltage, and the second input B is the first power supply voltage. The fifth transistor M5 is turned off, and the eighth transistor M8 is turned on. Therefore, the output terminal HF_Output of the AND gate outputs a low-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree of activation of the fourth transistor M4, the charging speed of the first node is controlled.

[0303] In the third stage, after time t, the fourth transistor M4 discharges to the control electrode of the third transistor M3 until the potential of the first node minus the first power supply voltage is less than the threshold voltage of the third transistor M3, that is, VQ-VDD<Vth. The third transistor M3 turns on, and the first power supply voltage sets the first input terminal A of the AND gate to the first power supply voltage, that is, a high-level signal, through the third transistor M3. The fifth transistor M5 turns on, and at this time, the output terminal HF_Output of the AND gate outputs a high-level signal.

[0304] In the fourth stage, the reset signal at the reset signal terminal HF_Reset is a low-level signal, the first node is reset to 20V, the third transistor M3 is turned off, the first input terminal A of the AND gate remains at a high level, the fifth transistor M5 is turned on, and the output terminal HF_Output continuously outputs a high-level signal.

[0305] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 discharges to the control electrode of the third transistor M3 for the duration from the potential of the first node to the first power supply voltage being less than the threshold voltage of the third transistor M3, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0306] Twentieth example: Figure 20 This is a schematic diagram of a trigger circuit according to the twentieth example of an embodiment of this disclosure; as shown Figure 20 As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A of the AND gate is directly electrically connected to the first power supply voltage terminal VDD, and the second input terminal B of the AND gate is connected to the second power supply voltage terminal VSS through the input subcircuit. The duty cycle adjustment module is connected to the second input terminal B of the AND gate.

[0307] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4, a ninth transistor M9, and a tenth transistor M10. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 have the same switching characteristics; the first transistor M1, the third transistor M3, the seventh transistor M7, and the eighth transistor M8 have the same switching characteristics, but different switching characteristics from the second transistor. In this example, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the tenth transistor M10 are N-type transistors, while the first transistor M1, the third transistor M3, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are P-type transistors.

[0308] For details, please refer to... Figure 20The first transistor M1 has its first terminal connected to the second power supply voltage terminal VSS. Its second terminal is connected to the control terminals of the sixth transistor M6 and the seventh transistor M7, serving as the second input terminal B of an AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the first power supply voltage terminal VDD and the second terminal of the second capacitor C2. Its second terminal is connected to the first terminal of the first capacitor C1 and the second input terminal B of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the second power supply voltage terminal VSS. Its second terminal is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the first power supply voltage terminal VDD. Its second terminal is connected to the first terminal of the sixth transistor M6. The control terminal of the fifth transistor M5 is connected to the control terminal of the eighth transistor M8, serving as the second input terminal B of an AND gate, directly connected to the first power supply voltage terminal VDD. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The second terminals of the seventh transistor M7 and the first terminals of the eighth transistor M8 are also connected, both connected to the second power supply voltage terminal VSS. The first terminal of the ninth transistor M9 is connected to the second terminals of the fourth transistor M4 and the tenth transistor M10. The second terminal of the ninth transistor M9 is connected to the first node, and its control terminal is connected to the reset signal terminal HF_Reset. The second terminal of the tenth transistor M10 is connected to the second power supply voltage, and its control terminal is connected to the second input terminal B of the AND gate. The second terminal of the first capacitor C1 is connected to the second power supply voltage terminal VSS, and the second terminal of the second capacitor C2 is connected to the first node.

[0309] The following assumes a first power supply voltage of 8V and a second power supply voltage of -8V; in the timing of the input control signals, the high-level signal is 12V, the low-level signal is -12V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 0.1μs / 99.9μs; in the timing of the reset signal, the high-level signal is 12V, the low-level signal is -20V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 99.9μs. / 0.1μs; Data voltage control signal Datastep=[-7.55V, -7.5V, -7.45V, -7.4V, -7.3V, -7.2V, -7.1V, -6.9V, -6.7V], first capacitor C1=200fF, second capacitor C2=2pF. Taking the twentieth example, the touch circuit is simulated. It should be understood that in the actual use of the product, the above parameters can be adjusted according to the actual needs.

[0310] The operation of the twentieth example flip-flop circuit will now be described. (Continue referring to...) Figure 20 The steps for generating each clock cycle signal of the clock signal using the touchscreen circuit in the twentieth example include:

[0311] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a high-level signal, and the first node is reset to 20V. During this stage, the third transistor M3 is turned off.

[0312] In the second stage, the reset signal at the HF_Reset terminal is a low-level signal, the second transistor M2 is turned off, the ninth transistor M9 is turned on, and the input control signal written at the HF_Input terminal is a low-level signal, turning on the first transistor M1. At this time, the first input A of the AND gate is the first power supply voltage, and the second input B is the second power supply voltage. The sixth transistor M6 is turned off, and the seventh transistor M7 is turned on. Therefore, the output terminal HF_Output of the AND gate outputs a low-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree of activation of the fourth transistor M4, the charging speed of the first node is controlled.

[0313] In the third stage, after time t, the fourth transistor M4 discharges to the control electrode of the third transistor M3 until the potential of the first node minus the first power supply voltage is less than the threshold voltage of the third transistor M3, that is, VQ-VDD<Vth. The third transistor M3 turns on, and the first power supply voltage sets the first input terminal A of the AND gate to the first power supply voltage, that is, a high-level signal, through the third transistor M3. The fifth transistor M5 turns on, and at this time, the output terminal HF_Output of the AND gate outputs a high-level signal.

[0314] In the fourth stage, the reset signal at the HF_Reset terminal is a low-level signal, the first node is reset to 20V, the third transistor M3 is turned off, the second input terminal B of the AND gate remains at a high level, the sixth transistor M6 is turned on, and the output terminal HF_Output continuously outputs a high-level signal.

[0315] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 discharges to the control electrode of the third transistor M3 for the duration from the potential of the first node to the first power supply voltage being less than the threshold voltage of the third transistor M3, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0316] Example number twenty-first: Figure 21 This is a schematic diagram of a trigger circuit according to the twenty-first example of an embodiment of this disclosure; as shown Figure 21 As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A and the second input terminal B of the AND gate are electrically connected to the second power supply voltage terminal VSS through the input subcircuit.

[0317] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The second transistor M2, fourth transistor M4, fifth transistor M5, and sixth transistor M6 have the same switching characteristics; the first transistor M1, third transistor M3, seventh transistor M7, and eighth transistor M8 have the same switching characteristics, but different switching characteristics from the second transistor. In this example, the second transistor M2, fourth transistor M4, fifth transistor M5, and sixth transistor M6 are N-type transistors, while the first transistor M1, third transistor M3, seventh transistor M7, and eighth transistor M8 are P-type transistors.

[0318] For details, please refer to... Figure 21The first transistor M1 has its first terminal connected to the second power supply voltage terminal VSS. Its second terminal is connected to the control terminals of the fifth transistor M5 and the eighth transistor M8, serving as the first input terminal A of an AND gate. Simultaneously, the second terminal of the first transistor M1 is also connected to the control terminals of the sixth transistor M6 and the seventh transistor M7, serving as the second input terminal B of the AND gate. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the first power supply voltage terminal VDD and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the first input terminal A of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the second power supply voltage terminal VSS. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the first power supply voltage terminal VDD. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is connected to the first power supply voltage terminal VDD, the control terminal of the seventh transistor M7, and the first plate of the first capacitor C1, serving as the second input terminal B of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are connected to the second power supply voltage terminal VSS. The first terminal of the ninth transistor M9 is connected to the second terminal of the fourth transistor M4 and the first terminal of the tenth transistor M10. The second terminal of the ninth transistor M9 is connected to the first node, and the control terminal of the ninth transistor M9 is connected to the reset signal terminal HF_Reset. The second terminal of the tenth transistor M10 is connected to the second power supply voltage, and the control terminal of the tenth transistor M10 is connected to the first input terminal A of the AND gate. The second terminal of the first capacitor C1 is connected to the first power supply voltage terminal VDD, and the second terminal of the second capacitor C2 is connected to the first node.

[0319] The following assumes a first power supply voltage of 8V and a second power supply voltage of -8V; in the timing of the input control signals, the high-level signal is 12V, the low-level signal is -12V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 0.1μs / 99.9μs; in the timing of the reset signal, the high-level signal is 12V, the low-level signal is -20V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 99.9μs. / 0.1μs; Data voltage control signal Datastep=[-7.55V, -7.5V, -7.45V, -7.4V, -7.3V, -7.2V, -7.1V, -6.9V, -6.7V], first capacitor C1=200fF, second capacitor C2=2pF. Taking the touch circuit in the twenty-first example as an example, it should be understood that the above parameters can be adjusted according to actual needs in the actual use of the product.

[0320] The operation of the twenty-first example flip-flop circuit will now be described. (Continue referring to...) Figure 21 The steps for generating each clock cycle signal of the clock signal using the touchpad circuit in the twenty-first example include:

[0321] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a high-level signal, and the first node is reset to 20V. During this stage, the third transistor M3 is turned off.

[0322] In the second stage, the reset signal at the HF_Reset terminal is a low-level signal, the second transistor M2 is turned off, the ninth transistor M9 is turned on, and the input control signal written at the HF_Input terminal is a low-level signal, turning on the first transistor M1. At this time, the first input terminal A and the second input terminal B of the AND gate are both at the second power supply voltage. The fifth transistor M5 and the sixth transistor M6 are turned off, and the seventh transistor M7 and the eighth transistor M8 are turned on. Therefore, the output terminal HF_Output of the AND gate outputs a low-level signal. At the same time, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree of activation of the fourth transistor M4, the charging speed of the first node is controlled.

[0323] In the third stage, after time t, the fourth transistor M4 discharges to the control electrode of the third transistor M3 until the potential of the first node minus the first power supply voltage is less than the threshold voltage of the third transistor M3, that is, VQ-VDD<Vth. The third transistor M3 turns on, and the first power supply voltage sets the first input terminal A of the AND gate to the first power supply voltage, that is, a high-level signal, through the third transistor M3. The fifth transistor M5 turns on, and at this time, the output terminal HF_Output of the AND gate outputs a high-level signal.

[0324] In the fourth stage, the reset signal at the reset signal terminal HF_Reset is a low-level signal, the first node is reset to 20V, the third transistor M3 is turned off, the first input terminal A of the AND gate remains at a high level, the fifth transistor M5 is turned on, and the output terminal HF_Output continuously outputs a high-level signal.

[0325] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 discharges to the control electrode of the third transistor M3 for the duration from the potential of the first node to the first power supply voltage being less than the threshold voltage of the third transistor M3, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0326] Example number twenty-second: Figure 22 This is a schematic diagram of a trigger circuit according to the twenty-second example of an embodiment of this disclosure; as shown Figure 22 As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A of the AND gate is electrically connected to the second power supply voltage terminal VSS through the input subcircuit, and the second input terminal B of the AND gate is directly connected to the first power supply voltage terminal VDD. The duty cycle adjustment module is connected to the first input terminal A of the AND gate.

[0327] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4, a ninth transistor M9, and a tenth transistor M10. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The second transistor M2, fourth transistor M4, fifth transistor M5, sixth transistor M6, and tenth transistor M10 have the same switching characteristics; the first transistor M1, third transistor M3, seventh transistor M7, eighth transistor M8, and ninth transistor M9 have the same switching characteristics, but different switching characteristics from the second transistor. In this example, the second transistor M2, fourth transistor M4, fifth transistor M5, sixth transistor M6, and tenth transistor M10 are N-type transistors, while the first transistor M1, third transistor M3, seventh transistor M7, eighth transistor M8, and ninth transistor M9 are P-type transistors.

[0328] For details, please refer to... Figure 22The first transistor M1 has its first terminal connected to the second power supply voltage terminal VSS. Its second terminal is connected to the control terminals of the fifth transistor M5 and the eighth transistor M8, serving as the first input terminal A of an AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the first power supply voltage terminal VDD and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the first input terminal A of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the second power supply voltage terminal VSS. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the second power supply voltage terminal VSS. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is connected to the first power supply voltage terminal VDD, the control terminal of the seventh transistor M7, and the first plate of the first capacitor C1, serving as the second input terminal B of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are connected to the first power supply voltage terminal VDD. The first terminal of the ninth transistor M9 is connected to the second terminal of the fourth transistor M4 and the first terminal of the tenth transistor M10. The second terminal of the ninth transistor M9 is connected to the first node, and the control terminal of the ninth transistor M9 is connected to the reset signal terminal HF_Reset. The second terminal of the tenth transistor M10 is connected to the second power supply voltage, and the control terminal of the tenth transistor M10 is connected to the first input terminal A of the AND gate. The second terminal of the first capacitor C1 is connected to the second power supply voltage terminal VSS, and the second terminal of the second capacitor C2 is connected to the first node.

[0329] The following assumes a first power supply voltage of 8V and a second power supply voltage of -8V; in the timing of the input control signals, the high-level signal is 12V, the low-level signal is -12V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 0.1μs / 99.9μs; in the timing of the reset signal, the high-level signal is 12V, the low-level signal is -20V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 99.9μs. / 0.1μs; Data voltage control signal Datastep=[-7.55V, -7.5V, -7.45V, -7.4V, -7.3V, -7.2V, -7.1V, -6.9V, -6.7V], first capacitor C1=200fF, second capacitor C2=2pF. Taking the touch circuit in the twenty-second example as an example, it should be understood that the above parameters can be adjusted according to actual needs in the actual use of the product.

[0330] The operation of the twenty-second example flip-flop circuit will now be described. (Continue referring to...) Figure 22 The steps for generating each clock cycle signal of the clock signal using the touchscreen circuit in the twenty-second example include:

[0331] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a high-level signal, and the first node is reset to 20V. During this stage, the third transistor M3 is turned off.

[0332] In the second stage, the reset signal at the HF_Reset terminal is low, the second transistor M2 is off, the ninth transistor M9 is on, and the input control signal written at the HF_Input terminal is low, turning on the first transistor M1. At this time, the first input A of the AND gate is the second power supply voltage, and the second input B is the first power supply voltage. The fifth transistor M5 is off, and the eighth transistor M8 is on, so the output HF_Output of the AND gate outputs a high-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the on / off state of the fourth transistor M4, the charging speed of the first node is controlled.

[0333] In the third stage, after time t, the fourth transistor M4 discharges to the control electrode of the third transistor M3 until the potential of the first node minus the first power supply voltage is less than the threshold voltage of the third transistor M3, that is, VQ-VDD<Vth. The third transistor M3 turns on, and the first power supply voltage sets the first input terminal A of the AND gate to the first power supply voltage, that is, a high-level signal, through the third transistor M3. The fifth transistor M5 turns on, and at this time, the output terminal HF_Output of the AND gate outputs a low-level signal.

[0334] In the fourth stage, the reset signal at the reset signal terminal HF_Reset is a low-level signal, the first node is reset to 20V, the third transistor M3 is turned off, the first input terminal A of the AND gate remains at a high level, the fifth transistor M5 is turned on, and the output terminal HF_Output continuously outputs a high-level signal.

[0335] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 discharges to the control electrode of the third transistor M3 for the duration from the potential of the first node to the first power supply voltage being less than the threshold voltage of the third transistor M3, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0336] Example number twenty-third: Figure 23 This is a schematic diagram of a trigger circuit according to the twenty-third example of an embodiment of this disclosure; as shown Figure 23 As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A of the AND gate is directly electrically connected to the first power supply voltage terminal VDD, and the second input terminal B of the AND gate is connected to the second power supply voltage terminal VSS through the input subcircuit. The duty cycle adjustment module is connected to the second input terminal B of the AND gate.

[0337] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4, a ninth transistor M9, and a tenth transistor M10. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 have the same switching characteristics; the first transistor M1, the third transistor M3, the seventh transistor M7, and the eighth transistor M8 have the same switching characteristics, but different switching characteristics from the second transistor. In this example, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the tenth transistor M10 are N-type transistors, while the first transistor M1, the third transistor M3, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are P-type transistors.

[0338] For details, please refer to... Figure 23The first transistor M1 has its first terminal connected to the second power supply voltage terminal VSS. Its second terminal is connected to the control terminals of the sixth transistor M6 and the seventh transistor M7, serving as the second input terminal B of an AND gate. The control terminal of the first transistor M1 is connected to the input control signal terminal HF_Input. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the first power supply voltage terminal VDD and the second terminal of the second capacitor C2. The second terminal of the third transistor M3 is connected to the first terminal of the first capacitor C1 and the second input terminal B of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the second power supply voltage terminal VSS. The second terminal of the fourth transistor M4 is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the second power supply voltage terminal VSS. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The control terminal of the fifth transistor M5 is connected to the control terminal of the eighth transistor M8, serving as the second input terminal B of an AND gate, directly connected to the first power supply voltage terminal VDD. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The second terminals of the seventh transistor M7 and the first terminals of the eighth transistor M8 are also connected, both connected to the first power supply voltage terminal VDD. The first terminal of the ninth transistor M9 is connected to the second terminals of the fourth transistor M4 and the tenth transistor M10. The second terminal of the ninth transistor M9 is connected to the first node, and its control terminal is connected to the reset signal terminal HF_Reset. The second terminal of the tenth transistor M10 is connected to the second power supply voltage, and its control terminal is connected to the second input terminal B of the AND gate. The second terminal of the first capacitor C1 is connected to the second power supply voltage terminal VSS, and the second terminal of the second capacitor C2 is connected to the first node.

[0339] The following assumes a first power supply voltage of 8V and a second power supply voltage of -8V; in the timing of the input control signals, the high-level signal is 12V, the low-level signal is -12V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 0.1μs / 99.9μs; in the timing of the reset signal, the high-level signal is 12V, the low-level signal is -20V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 99.9μs. / 0.1μs; Data voltage control signal Datastep=[-7.55V, -7.5V, -7.45V, -7.4V, -7.3V, -7.2V, -7.1V, -6.9V, -6.7V], first capacitor C1=200fF, second capacitor C2=2pF. Taking the touch circuit in the twenty-third example as an example, it should be understood that the above parameters can be adjusted according to actual needs in the actual use of the product.

[0340] The operation of the twenty-third example flip-flop circuit will be described next. (Continue referring to...) Figure 23 The steps for generating each clock cycle signal of the clock signal using the touchscreen circuit in the twenty-third example include:

[0341] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a high-level signal, and the first node is reset to 20V. During this stage, the third transistor M3 is turned off.

[0342] In the second stage, the reset signal at the HF_Reset terminal is a low-level signal, the second transistor M2 is turned off, the ninth transistor M9 is turned on, and the input control signal written at the HF_Input terminal is a low-level signal, turning on the first transistor M1. At this time, the first input terminal A of the AND gate is the first power supply voltage, and the second input terminal B is the second power supply voltage. The sixth transistor M6 is turned off, and the seventh transistor M7 is turned on. Therefore, the output terminal HF_Output of the AND gate outputs a high-level signal. Simultaneously, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree of activation of the fourth transistor M4, the charging speed of the first node is controlled.

[0343] In the third stage, after time t, the fourth transistor M4 discharges to the control electrode of the third transistor M3 until the potential of the first node minus the first power supply voltage is less than the threshold voltage of the third transistor M3, that is, VQ-VDD<Vth. The third transistor M3 turns on, and the first power supply voltage sets the second input terminal B of the AND gate to the first power supply voltage, that is, a high-level signal, through the third transistor M3. The sixth transistor M6 turns on, and at this time, the output terminal HF_Output of the AND gate outputs a low-level signal.

[0344] In the fourth stage, the reset signal at the HF_Reset terminal is a low-level signal, the first node is reset to 20V, the third transistor M3 is turned off, the second input terminal B of the AND gate remains at a high level, the sixth transistor M6 is turned on, and the output terminal HF_Output continuously outputs a low-level signal.

[0345] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 discharges to the control electrode of the third transistor M3 for the duration from the potential of the first node to the first power supply voltage being less than the threshold voltage of the third transistor M3, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0346] Example number twenty-four: Figure 24 This is a schematic diagram of a trigger circuit according to the twenty-fourth example of an embodiment of this disclosure; as shown Figure 24 As shown, the touchscreen circuit includes an AND gate, an input control subcircuit, a duty cycle adjustment subcircuit, and a reset subcircuit. The duty cycle adjustment subcircuit includes a control module and a duty cycle adjustment module. The connection node between the control module and the duty cycle adjustment subcircuit is the first node, and the reset subcircuit is connected to the first node. The first input terminal A and the second input terminal B of the AND gate are electrically connected to the second power supply voltage terminal VSS through the input subcircuit.

[0347] The input control sub-circuit includes a first transistor M1. The reset sub-circuit includes a second transistor M2. The duty cycle adjustment module includes a third transistor M3, a first capacitor C1, and a second capacitor C2. The control module includes a fourth transistor M4. The AND gate includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The second transistor M2, fourth transistor M4, fifth transistor M5, and sixth transistor M6 have the same switching characteristics; the first transistor M1, third transistor M3, seventh transistor M7, and eighth transistor M8 have the same switching characteristics, but different switching characteristics from the second transistor. In this example, the second transistor M2, fourth transistor M4, fifth transistor M5, and sixth transistor M6 are N-type transistors, while the first transistor M1, third transistor M3, seventh transistor M7, and eighth transistor M8 are P-type transistors.

[0348] For details, please refer to... Figure 24The first transistor M1 has its first terminal connected to the second power supply voltage terminal VSS. Its second terminal is connected to the control terminals of the fifth transistor M5 and the eighth transistor M8, serving as the first input terminal A of an AND gate. Simultaneously, the second terminal of the first transistor M1 is also connected to the control terminals of the sixth transistor M6 and the seventh transistor M7, serving as the second input terminal B of the AND gate. The first terminal and control terminal of the second transistor M2 are both connected to the reset signal terminal HF_Reset. The second terminal of the second transistor M2 is connected to the first node. The first terminal of the third transistor M3 is connected to the first power supply voltage terminal VDD and the second terminal of the second capacitor C2. Its second terminal is connected to the first terminal of the first capacitor C1 and the first input terminal A of the AND gate. The control terminal of the third transistor M3 is connected to the first node. The first terminal of the fourth transistor M4 is connected to the second power supply voltage terminal VSS. Its second terminal is connected to the first node. The control terminal of the fourth transistor M4 is connected to the data voltage control terminal. The first terminal of the fifth transistor M5 is connected to the second power supply voltage terminal VSS. The second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The second terminal of the sixth transistor M6 is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8, serving as the output terminal HF_Output of the AND gate. The control terminal of the sixth transistor M6 is connected to the first power supply voltage terminal VDD, the control terminal of the seventh transistor M7, and the first plate of the first capacitor C1, serving as the second input terminal B of the AND gate. The second terminal of the seventh transistor M7 and the first terminal of the eighth transistor M8 are connected, and both are connected to the first power supply voltage terminal VDD. The first terminal of the ninth transistor M9 is connected to the second terminal of the fourth transistor M4 and the first terminal of the tenth transistor M10. The second terminal of the ninth transistor M9 is connected to the first node, and the control terminal of the ninth transistor M9 is connected to the reset signal terminal HF_Reset. The second terminal of the tenth transistor M10 is connected to the second power supply voltage, and the control terminal of the tenth transistor M10 is connected to the first input terminal A of the AND gate. The second terminal of the first capacitor C1 is connected to the second power supply voltage terminal VSS, and the second terminal of the second capacitor C2 is connected to the first node.

[0349] The following assumes a first power supply voltage of 8V and a second power supply voltage of -8V; in the timing of the input control signals, the high-level signal is 12V, the low-level signal is -12V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 0.1μs / 99.9μs; in the timing of the reset signal, the high-level signal is 12V, the low-level signal is -20V, the period H = 100μs, and the duty cycle is low-level signal / high-level signal = 99.9μs. / 0.1μs; Data voltage control signal Datastep=[-7.55V, -7.5V, -7.45V, -7.4V, -7.3V, -7.2V, -7.1V, -6.9V, -6.7V], first capacitor C1=200fF, second capacitor C2=2pF. Taking the touch circuit in the twenty-fourth example as an example, it should be understood that the above parameters can be adjusted according to actual needs in the actual use of the product.

[0350] The operation of the twenty-fourth example flip-flop circuit will now be described. (Continue referring to...) Figure 24 The steps for generating each clock cycle signal of the clock signal using the touchscreen circuit in the twenty-fourth example include:

[0351] In the first stage, which is the beginning of the clock cycle, the reset signal HF_Reset is written as a high-level signal, and the first node is reset to 20V. During this stage, the third transistor M3 is turned off.

[0352] In the second stage, the reset signal at the HF_Reset terminal is a low-level signal, the second transistor M2 is turned off, the ninth transistor M9 is turned on, and the input control signal written at the HF_Input terminal is a low-level signal, turning on the first transistor M1. At this time, the first input terminal A of the AND gate is the second power supply voltage, and the second input terminal B is also the second power supply voltage. The fifth transistor M5 and the sixth transistor M6 are turned off, and the seventh transistor M7 and the eighth transistor M8 are turned on. Therefore, the output terminal HF_Output of the AND gate outputs a high-level signal. At the same time, the data voltage control signal written at the Datastep terminal is written to the control electrode of the fourth transistor M4. By controlling the degree of activation of the fourth transistor M4, the charging speed of the first node is controlled.

[0353] In the third stage, after time t, the fourth transistor M4 discharges to the control electrode of the third transistor M3 until the potential of the first node minus the first power supply voltage is less than the threshold voltage of the third transistor M3, that is, VQ-VDD<Vth. The third transistor M3 turns on, and the first power supply voltage sets the first input terminal A of the AND gate to the first power supply voltage, that is, a high-level signal, through the third transistor M3. The fifth transistor M5 turns on, and at this time, the output terminal HF_Output of the AND gate outputs a low-level signal.

[0354] In the fourth stage, the reset signal at the HF_Reset terminal is a low-level signal, the first node is reset to 20V, the third transistor M3 is turned off, the first input terminal A of the AND gate remains at a high level, the fifth transistor M5 is turned on, and the output terminal HF_Output continuously outputs a low-level signal.

[0355] It can be seen that the opening degree of the fourth transistor M4 is controlled by the data voltage control signal, which controls the charging speed of the first node. The fourth transistor M4 discharges to the control electrode of the third transistor M3 for the duration from the potential of the first node to the first power supply voltage being less than the threshold voltage of the third transistor M3, which is also the time for the AND gate output terminal HF_Output to output a high-level signal. By adjusting the magnitude of the data voltage control signal, clock signals with different duty cycles can be obtained.

[0356] For the touch controller circuits in the above twenty-four examples, each transistor used can be any one of amorphous silicon, polycrystalline silicon, low-temperature polycrystalline silicon, or oxide.

[0357] For the above examples, the simulation conditions in each example are followed, and the width-to-length ratio of the transistor is W / L = 5 / 5.

[0358] Reference Figure 25 From the simulation results of the touchpad circuits in examples one through six, it can be seen that when the data voltage control signal Datastep = [7.42V, 7.4V, 7.3V, 7.2V, 7.1V, 7V, 6.9V, 6.8V, 6.7V], the duty cycle (high voltage / cycle H) of the corresponding generated clock cycle is as follows: Examples one through three: [85%, 80%, 51%, 34%, 25%, 18.5%, 14.5%, 11.5%, 9.5%]; Examples four through six: [22.5%, 29.5%, 55.5%, 70%, 78.3%, 83.7%, 87.2%, 89.7%, 91.6%].

[0359] Reference Figure 26From the simulation results of the touchpad circuits in examples seven through twelfth, it can be seen that when the data voltage control signal Datastep = [7.43V, 7.42V, 7.4V, 7.3V, 7.2V, 7.1V, 7V, 6.8V, 6.7V], the duty cycle (high voltage / cycle H) of the corresponding generated clock cycle is as follows: Examples seven through nine: [75%, 65.6%, 60.7%, 40.3%, 28.1%, 20.7%, 16%, 10.3%, 8.5%]; Examples ten through twelfth: [25%, 38.6%, 43.5%, 61.6%, 72.8%, 29.9%, 84.5%, 89.9%, 91.6%].

[0360] Reference Figure 27 From the simulation results of the touchpad circuits in Examples 13 to 18, it can be seen that when the data voltage control signal Datastep = [-7.55V, -7.5V, -7.45V, -7.4V, -7.3V, -7.2V, -7.1V, -6.9V, -6.7V], the duty cycle (high voltage / cycle H) of the corresponding generated clock cycle is as follows: Examples 13 to 15: [16%, 33.6%, 41%, 47.5%, 60.4%, 68%, 74.6%, 83%, 88%]; Examples 16 to 18: [84.6%, 67.1%, 59.7%, 53%, 42.2%, 34.3%, 28.1%, 19.7%, 14.3%].

[0361] Reference Figure 28 From the simulation results of the touchpad circuits in Examples 19 to 24, it can be seen that when the data voltage control signal Datastep = [-7.55V, -7.5V, -7.45V, -7.4V, -7.3V, -7.2V, -7.1V, -6.9V, -6.7V], the duty cycle (high voltage / cycle H) of the corresponding generated clock cycle is as follows: Examples 19 to 21: [27.1%, 46.6%, 51.9%, 56.8%, 64.9%, 71.3%, 76.1%, 83.1%, 87.5%]; Examples 21 to 24: [72.7%, 52.8%, 47.3%, 42.6%, 34.8%, 28.6%, 23.7%, 16.9%, 12.4%].

[0362] The second aspect: Figure 29 This is a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure; as shown Figure 29As shown, this embodiment of the present disclosure provides a pixel driving circuit, which includes a driving transistor DTFT and a trigger circuit connected to the control electrode of the driving transistor. The trigger circuit can be any of the aforementioned trigger circuits. The first electrode of the driving transistor DTFT is connected to a first driving circuit terminal, the second electrode of the driving transistor DTFT is connected to the first electrode of the light-emitting device to be driven, and the second electrode of the light-emitting device to be driven is connected to a second driving power supply terminal. Because this driving circuit is simple, the voltage at the first driving power supply terminal is approximately 3-5V. In some examples, the light-emitting device includes, but is not limited to, LEDs or OLEDs.

[0363] For the pixel driving current, when the driving transistor DTFT is turned on, the current drives the light-emitting device to emit light; when the driving transistor DTFT is turned off, the light emission stops. The signal output from the AND gate of the trigger circuit HF_Output is written into the control terminal of the driving transistor DTFT in the light-emitting circuit. By adjusting the duty cycle of the clock signal, the on-time of the driving transistor DTFT can be adjusted to achieve grayscale display. When the duty cycle is low, the driving transistor DTFT has a short on-time and a short light emission time, displaying a low grayscale; when the duty cycle is high, the driving transistor DTFT has a long on-time and a long light emission time, displaying a high grayscale. In this embodiment of the present disclosure, grayscale display is achieved by fixing the light-emitting device at one or a few stable brightness levels. Low grayscale is achieved by controlling the light emission time, avoiding the problem of unstable low brightness of the light-emitting device.

[0364] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A trigger circuit, comprising: An AND gate having a first input, a second input, and an output, the AND gate being configured to control the output to output a clock signal based on the potentials of the first input and the second input, the potential of the clock signal switching between a first power supply voltage and a second power supply voltage; An input control sub-circuit is configured to transmit either the first power supply voltage or the second power supply voltage to at least one of the first input terminal and the second input terminal in response to an input control signal. A duty cycle adjustment sub-circuit, which includes a control module and a duty cycle adjustment module; The connection node between the control module and the duty cycle adjustment sub-circuit is the first node; The control module is configured to control the potential of the first node in response to a data voltage control signal via the first power supply voltage or the second power supply voltage. The duty cycle adjustment module is configured to adjust the duty cycle of the clock signal output from the output terminal according to the potential of the first node.

2. The trigger circuit according to claim 1, wherein, It also includes a reset sub-circuit configured to respond to a reset signal and reset the first node via the reset signal.

3. The trigger circuit according to claim 2, wherein, The reset sub-circuit includes a second transistor; the control terminal of the second transistor is connected to its first terminal and the reset signal terminal, and the second terminal is connected to the first node.

4. The trigger circuit according to claim 2, wherein, The first input terminal of the AND gate is electrically connected to the first power supply voltage terminal through the input control sub-circuit, and the second input terminal of the AND gate is directly connected to the first power supply voltage terminal; the duty cycle adjustment module is connected to the first input terminal of the AND gate.

5. The trigger circuit according to claim 2, wherein, The first and second input terminals of the AND gate are both connected to the first power supply voltage terminal through the input control sub-circuit.

6. The trigger circuit according to claim 4 or 5, wherein, The input control sub-circuit includes a first transistor; the duty cycle adjustment module includes a third transistor, a first capacitor, and a second capacitor; the control module includes a fourth transistor; the first transistor and the third transistor have the same switching characteristics, and the third transistor and the fourth transistor have opposite switching characteristics. The control electrode of the first transistor is connected to the input control signal terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the first input terminal. The control electrode of the third transistor is electrically connected to the first node and the first terminal of the second capacitor. The first electrode is connected to the second power supply voltage terminal and the second terminal of the second capacitor. The second electrode is connected to the first terminal of the first capacitor and the first input terminal of the AND gate. The second terminal of the first capacitor is connected to either the first power supply voltage terminal or the second power supply voltage terminal. The control electrode of the fourth transistor is connected to the data voltage control terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the first node.

7. The trigger circuit according to claim 4 or 5, wherein, The input control sub-circuit includes a first transistor; the duty cycle adjustment module includes a third transistor, a first capacitor, and a second capacitor; the control module includes a fourth transistor, a ninth transistor, and a tenth transistor; the first transistor, the third transistor, and the ninth transistor have the same switching characteristics, while the third transistor, the fourth transistor, and the tenth transistor have opposite switching characteristics. The control electrode of the first transistor is connected to the input control signal terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the first input terminal. The control electrode of the third transistor is electrically connected to the first node and the first terminal of the second capacitor. The first electrode is connected to the second power supply voltage terminal, and the second electrode is connected to the first terminal of the first capacitor and the first input terminal of the AND gate. The second terminal of the first capacitor is connected to either the first power supply voltage terminal or the second power supply voltage terminal, and the second terminal of the second capacitor is connected to the second power supply voltage terminal. The control electrode of the fourth transistor is connected to the data voltage control terminal, the first electrode is connected to the first power supply voltage terminal and the second electrode of the tenth transistor, and the second electrode is connected to the first electrode of the ninth transistor and the first electrode of the tenth transistor. The control electrode of the ninth transistor is connected to the reset signal terminal, and the second electrode is connected to the first node; The control electrode of the tenth transistor is connected to the first input terminal of the AND gate.

8. The trigger circuit according to claim 2, wherein, The first input terminal of the AND gate is directly connected to the first power supply voltage terminal, and the second input terminal of the AND gate is electrically connected to the first power supply voltage terminal through the input control sub-circuit; the duty cycle adjustment module is electrically connected to the second input terminal of the AND gate.

9. The trigger circuit according to claim 8, wherein, The input control sub-circuit includes a first transistor; the duty cycle adjustment module includes a third transistor, a first capacitor, and a second capacitor; the control module includes a fourth transistor; the first transistor and the third transistor have the same switching characteristics, and the third transistor and the fourth transistor have opposite switching characteristics. The control electrode of the first transistor is connected to the input control signal terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the second input terminal. The control electrode of the third transistor is electrically connected to the first node and the first terminal of the second capacitor. The first electrode is connected to the second power supply voltage terminal, and the second electrode is connected to the first terminal of the first capacitor and the first input terminal of the AND gate. The second terminal of the first capacitor is connected to the second power supply voltage terminal, and the second terminal of the second capacitor is also connected to the second power supply voltage terminal. The control electrode of the fourth transistor is connected to the data voltage control terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the first node.

10. The trigger circuit according to claim 8, wherein, The input control sub-circuit includes a first transistor; the duty cycle adjustment module includes a third transistor, a first capacitor, and a second capacitor; the control module includes a fourth transistor, a ninth transistor, and a tenth transistor; the first transistor, the third transistor, and the ninth transistor have the same switching characteristics, while the third transistor, the fourth transistor, and the tenth transistor have opposite switching characteristics. The control electrode of the first transistor is connected to the input control signal terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the second input terminal. The control electrode of the third transistor is electrically connected to the first node and the first terminal of the second capacitor. The first electrode is connected to the second power supply voltage terminal, and the second electrode is connected to the first terminal of the first capacitor and the second input terminal of the AND gate. The second terminal of the first capacitor is connected to either the first power supply voltage terminal or the second power supply voltage terminal, and the second terminal of the second capacitor is connected to the second power supply voltage terminal. The control electrode of the fourth transistor is connected to the data voltage control terminal, the first electrode is connected to the first power supply voltage terminal and the second electrode of the tenth transistor, and the second electrode is connected to the first electrode of the ninth transistor and the first electrode of the tenth transistor. The control electrode of the ninth transistor is connected to the reset signal terminal, and the second electrode is connected to the first node; The control electrode of the tenth transistor is connected to the second input terminal of the AND gate.

11. The trigger circuit according to any one of claims 4, 5, and 8, wherein, The AND gate includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the fifth transistor and the sixth transistor have the same switching characteristics, the seventh transistor and the eighth transistor have the same switching characteristics, and the fifth transistor and the seventh transistor have opposite switching characteristics. The control electrode of the fifth transistor is connected to the control electrode of the eighth transistor, serving as the first input terminal of the AND gate. The first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the first electrode of the sixth transistor. The control terminal of the sixth transistor and the control connection of the seventh transistor serve as the second input terminal of the AND gate. The second terminal of the sixth transistor is connected to the second terminal of the seventh transistor and the second terminal of the eighth transistor, serving as the signal output terminal of the AND gate. The first terminal of the seventh transistor is connected to the first terminal of the eighth transistor and the second power supply voltage terminal.

12. The trigger circuit according to any one of claims 4, 5, and 8, wherein, The AND gate includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the fifth transistor and the sixth transistor have the same switching characteristics, the seventh transistor and the eighth transistor have the same switching characteristics, and the fifth transistor and the seventh transistor have opposite switching characteristics. The control electrode of the fifth transistor and the control electrode of the eighth transistor are connected to each other as the first input terminal of the AND gate. The first terminal is connected to the second power supply voltage terminal, and the second terminal is connected to the first terminal of the sixth transistor. The control terminal of the sixth transistor and the control connection of the seventh transistor serve as the second input terminal of the AND gate. The second terminal of the sixth transistor is connected to the second terminal of the seventh transistor and the second terminal of the eighth transistor, serving as the signal output terminal of the AND gate. The first terminal of the seventh transistor is connected to the first terminal of the eighth transistor and the first power supply voltage terminal.

13. The trigger circuit according to claim 2, wherein, The first input terminal of the AND gate is electrically connected to the second power supply voltage terminal through the input control sub-circuit, and the second input terminal of the AND gate is directly connected to the first power supply voltage terminal; the duty cycle adjustment module is electrically connected to the first input terminal of the AND gate.

14. The trigger circuit according to claim 2, wherein, The first and second input terminals of the AND gate are both electrically connected to the second power supply voltage terminal through the input control sub-circuit.

15. The trigger circuit according to claim 13 or 14, wherein, The input control sub-circuit includes a first transistor; the duty cycle adjustment module includes a third transistor, a first capacitor, and a second capacitor; the control module includes a fourth transistor; the first transistor and the third transistor have the same switching characteristics, and the third transistor and the fourth transistor have opposite switching characteristics. The control electrode of the first transistor is connected to the input control signal terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the first input terminal. The control electrode of the third transistor is electrically connected to the first node and the first terminal of the second capacitor. The first electrode is connected to the second power supply voltage terminal, and the second electrode is connected to the first terminal of the first capacitor and the first input terminal of the AND gate. The second terminal of the first capacitor is connected to either the first power supply voltage terminal or the second power supply voltage terminal, and the second terminal of the second capacitor is connected to the second power supply voltage terminal. The control electrode of the fourth transistor is connected to the data voltage control terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the first node.

16. The trigger circuit according to claim 13 or 14, wherein, The input control sub-circuit includes a first transistor; the duty cycle adjustment module includes a third transistor, a first capacitor, and a second capacitor; the control module includes a fourth transistor, a ninth transistor, and a tenth transistor; the first transistor, the third transistor, and the ninth transistor have the same switching characteristics, while the third transistor, the fourth transistor, and the tenth transistor have opposite switching characteristics. The control electrode of the first transistor is connected to the input control signal terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the first input terminal. The control electrode of the third transistor is electrically connected to the first node and the first terminal of the second capacitor. The first electrode is connected to the second power supply voltage terminal, and the second electrode is connected to the first terminal of the first capacitor and the first input terminal of the AND gate. The second terminal of the first capacitor is connected to either the first power supply voltage terminal or the second power supply voltage terminal, and the second terminal of the second capacitor is connected to the second power supply voltage terminal. The control electrode of the fourth transistor is connected to the data voltage control terminal, the first electrode is connected to the first power supply voltage terminal and the second electrode of the tenth transistor, and the second electrode is connected to the first electrode of the ninth transistor and the first electrode of the tenth transistor. The control electrode of the ninth transistor is connected to the reset signal terminal, and the second electrode is connected to the first node; The control electrode of the tenth transistor is connected to the first input terminal of the AND gate.

17. The trigger circuit according to claim 2, wherein, The first input terminal of the AND gate is connected to the first power supply voltage terminal, and the second input terminal of the AND gate is electrically connected to the second power supply voltage terminal through the input control sub-circuit; the duty cycle adjustment module is electrically connected to the second input terminal of the AND gate.

18. The trigger circuit according to claim 17, wherein, The input control sub-circuit includes a first transistor; the duty cycle adjustment module includes a third transistor, a first capacitor, and a second capacitor; the control module includes a fourth transistor; the first transistor and the third transistor have the same switching characteristics, and the third transistor and the fourth transistor have opposite switching characteristics. The control electrode of the first transistor is connected to the input control signal terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the second input terminal. The control electrode of the third transistor is electrically connected to the first node and the first terminal of the second capacitor. The first electrode is connected to the second power supply voltage terminal, and the second electrode is connected to the first terminal of the first capacitor and the first input terminal of the AND gate. The second terminal of the first capacitor is connected to the second power supply voltage terminal, and the second terminal of the second capacitor is also connected to the second power supply voltage terminal. The control electrode of the fourth transistor is connected to the data voltage control terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the first node.

19. The trigger circuit according to claim 18, wherein, The input control sub-circuit includes a first transistor; the duty cycle adjustment module includes a third transistor, a first capacitor, and a second capacitor; the control module includes a fourth transistor, a ninth transistor, and a tenth transistor; the first transistor, the third transistor, and the ninth transistor have the same switching characteristics, while the third transistor, the fourth transistor, and the tenth transistor have opposite switching characteristics. The control electrode of the first transistor is connected to the input control signal terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the second input terminal. The control electrode of the third transistor is electrically connected to the first node and the first terminal of the second capacitor. The first electrode is connected to the second power supply voltage terminal, and the second electrode is connected to the first terminal of the first capacitor and the second input terminal of the AND gate. The second terminal of the first capacitor is connected to either the first power supply voltage terminal or the second power supply voltage terminal, and the second terminal of the second capacitor is connected to the second power supply voltage terminal. The control electrode of the fourth transistor is connected to the data voltage control terminal, the first electrode is connected to the first power supply voltage terminal and the second electrode of the tenth transistor, and the second electrode is connected to the first electrode of the ninth transistor and the first electrode of the tenth transistor. The control electrode of the ninth transistor is connected to the reset signal terminal, and the second electrode is connected to the first node; The control electrode of the tenth transistor is connected to the second input terminal of the AND gate.

20. The trigger circuit according to any one of claims 13, 14, and 17, wherein, The AND gate includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the fifth transistor and the sixth transistor have the same switching characteristics, the seventh transistor and the eighth transistor have the same switching characteristics, and the fifth transistor and the seventh transistor have opposite switching characteristics. The control electrode of the fifth transistor is connected to the control electrode of the eighth transistor, serving as the first input terminal of the AND gate. The first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the first electrode of the sixth transistor. The control terminal of the sixth transistor and the control connection of the seventh transistor serve as the second input terminal of the AND gate. The second terminal of the sixth transistor is connected to the second terminal of the seventh transistor and the second terminal of the eighth transistor, serving as the signal output terminal of the AND gate. The first terminal of the seventh transistor is connected to the first terminal of the eighth transistor and the second power supply voltage terminal.

21. The trigger circuit according to any one of claims 13, 14, and 17, wherein, The AND gate includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the fifth transistor and the sixth transistor have the same switching characteristics, the seventh transistor and the eighth transistor have the same switching characteristics, and the fifth transistor and the seventh transistor have opposite switching characteristics. The control electrode of the fifth transistor and the control electrode of the eighth transistor are connected to each other as the first input terminal of the AND gate. The first terminal is connected to the second power supply voltage terminal, and the second terminal is connected to the first terminal of the sixth transistor. The control terminal of the sixth transistor and the control connection of the seventh transistor serve as the second input terminal of the AND gate. The second terminal of the sixth transistor is connected to the second terminal of the seventh transistor and the second terminal of the eighth transistor, serving as the signal output terminal of the AND gate. The first terminal of the seventh transistor is connected to the first terminal of the eighth transistor and the first power supply voltage terminal.

22. A pixel driving circuit, comprising a driving transistor and a trigger circuit; wherein the control electrode of the driving transistor is connected to the trigger circuit; and the trigger circuit is the trigger circuit according to any one of claims 1-21.

Images