Multi-bit multiplication and addition operation circuit based on 6T-SRAM and its control method

Abstract

The present application relates to a multi-bit multiplication and addition circuit based on 6T-SRAM and a control method thereof. The circuit includes multiple 6T-SRAM cells, a control unit, and a calculation unit. The multiple 6T-SRAM cells are arranged in parallel and respectively controlled by different word lines. The first ends of the multiple 6T-SRAM cells are connected to the same first local bit line, and the second ends of the multiple 6T-SRAM cells are connected to the same second local bit line. The calculation unit includes fifth to eighth PMOS transistors and seventh to tenth NMOS transistors. The source of the fifth PMOS transistor and the drain of the eighth NMOS transistor are signal output nodes, the drain of the seventh PMOS transistor and the drain of the eighth PMOS transistor are used to receive variable-level signals, and the gate of the ninth NMOS transistor and the gate of the tenth NMOS transistor are signal input nodes. The gate of the fifth PMOS transistor and the gate of the eighth NMOS transistor are connected to the second local bit line and the first local bit line respectively through the control unit, and the control unit is used to implement switch control. The storage unit and the calculation unit are configured together to realize in-memory calculation, greatly improving the calculation speed.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a multi-bit multiplication and addition circuit based on 6T-SRAM and a control method thereof. Background Art

[0002] With the development of the times, artificial intelligence technology has been widely used. During its use, the requirements for computing efficiency and energy consumption are getting higher and higher. In the traditional von Neumann architecture, the computing module and the storage module are separated. When data is needed, it is necessary to read the data from the memory to the computing module for use. The current development process of the computing power of the computing module has far exceeded the development process of the memory access speed. A large amount of running time and power consumption are used for data access, and very little is actually used for computing.

[0003] In order to address the problem that the computing circuit and storage circuit are separated in the traditional von Neumann architecture, which in turn limits the computing speed, more solutions are currently needed. Summary of the Invention

[0004] The present invention provides a multi-bit multiplication and addition operation circuit based on 6T-SRAM and a control method thereof to solve the problem that the operation circuit and the storage circuit are separated in the traditional von Neumann architecture, which in turn limits the operation speed.

[0005] In a first aspect, the present invention provides a multi-bit multiplication and addition circuit based on 6T-SRAM, the circuit comprising a plurality of 6T-SRAM units, a control unit, and a calculation unit;

[0006] The plurality of 6T-SRAM cells are arranged in parallel and are respectively controlled by different word lines, the first ends of the plurality of 6T-SRAM cells are connected to the same first local bit line, and the second ends of the plurality of 6T-SRAM cells are connected to the same second local bit line;

[0007] The calculation unit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor and a tenth NMOS transistor, the source and drain of the fifth PMOS transistor are respectively connected to the drain and source of the seventh NMOS transistor, the source and drain of the sixth PMOS transistor are respectively connected to the drain and source of the eighth NMOS transistor, the source and drain of the seventh PMOS transistor are respectively connected to the drain and source of the ninth NMOS transistor, the source and drain of the eighth PMOS transistor are respectively connected to the drain and source of the tenth NMOS transistor, the source of the seventh PMOS transistor is connected to the drain of the fifth PMOS transistor, the source of the eighth PMOS transistor is connected to the drain of the sixth PMOS transistor, the gate of the seventh NMOS transistor is connected to the gate of the eighth NMOS transistor, and the gate of the sixth PMOS transistor is connected to the gate of the fifth PMOS transistor;

[0008] The source of the fifth PMOS transistor and the drain of the eighth NMOS transistor are signal output nodes, the drain of the seventh PMOS transistor and the drain of the eighth PMOS transistor are used to receive variable level signals, and the gate of the ninth NMOS transistor and the gate of the tenth NMOS transistor are signal input nodes;

[0009] The gate of the fifth PMOS transistor and the gate of the eighth NMOS transistor are respectively connected to the second local bit line and the first local bit line through the control unit, and the control unit is used to implement switch control.

[0010] In a second aspect, the present invention provides a control method for a multi-bit multiplication and addition circuit based on 6T-SRAM, which is applied to the multi-bit multiplication and addition circuit based on 6T-SRAM described in the first aspect. The control method includes a multi-bit multiplication and addition operation step, and the multi-bit multiplication and addition operation step includes:

[0011] Connecting a first signal and a second signal to the gate of a ninth NMOS transistor and a gate of a tenth NMOS transistor, respectively, wherein the first signal and the second signal represent a first 2-bit number and a second 2-bit number, respectively;

[0012] Outputting a result signal of a multi-bit multiplication and addition operation through the source of the fifth PMOS transistor and the drain of the eighth NMOS transistor, wherein the result signal of the multi-bit multiplication and addition operation is obtained by adding the product of the first 2-bit number and the second 2-bit number and the first 1-bit weight respectively;

[0013] Among them, when the first storage node is at a high level, the second storage node is at a low level, and the indeterminate level signal is at a high level, the first 1-bit weight is +1; when the first storage node is at a high level, the second storage node is at a low level, and the indeterminate level signal is at a low level, the first 1-bit weight is -1; when the first storage node is at a low level and the second storage node is at a high level, the first 1-bit weight is 0.

[0014] In a third aspect, the present invention provides a computing chip that integrates the multi-bit multiplication and addition computing circuit based on 6T-SRAM described in the first aspect.

[0015] In a fourth aspect, the present invention provides a computing module encapsulated with the computing chip described in the third aspect.

[0016] In a fifth aspect, the present invention provides an electronic device comprising the computing module described in the fourth aspect.

[0017] Compared with related technologies, the multi-bit multiplication and addition operation circuit based on 6T-SRAM provided by the present invention configures multiple storage units and a computing unit together to realize in-memory calculation. Compared with the structure where the operation circuit and the storage circuit are separated, the operation speed is greatly improved, and the problem that the operation circuit and the storage circuit are separated in the traditional von Neumann architecture, which in turn limits the operation speed, is solved.

[0018] The details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a diagram illustrating a multi-bit multiplication and addition circuit based on 6T-SRAM in some embodiments of the present invention;

[0020] Figure 2 is a diagram of the structure of a storage unit in some embodiments of the present invention;

[0021] Figure 3 is the signal timing of a multi-bit multiplication and addition circuit based on 6T-SRAM in some embodiments of the present invention;

[0022] Figure 4 is a diagram of multi-bit multiplication and addition results of a multi-bit multiplication and addition circuit based on 6T-SRAM in some embodiments of the present invention;

[0023] Figure 5 is a schematic diagram representing an input signal in some embodiments of the present invention;

[0024] Figure 6 4 is a diagram illustrating the structure of a 6T-SRAM-based computing module in some embodiments of the present invention. DETAILED DESCRIPTION

[0025] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0026] Unless otherwise defined, the technical terms or scientific terms involved in this application should have the general meaning understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "an", "a", "the", "these" and the like in this application do not indicate quantitative restrictions, and they can be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "plurality" involved in this application refers to two or more. "And / or" describes the relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. Generally, the character " / " indicates that the related objects are in an "or" relationship. The terms "first," "second," "third," etc. used in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0027] In an embodiment of the present invention, a multi-bit multiplication and addition circuit based on 6T-SRAM is provided.

[0028] like Figure 1 and Figure 2 As shown, the circuit includes multiple 6T-SRAM cells (storage cells), a control unit and a calculation unit.

[0029] Multiple 6T-SRAM cells are arranged in parallel and are controlled by different word lines WL. The first ends of the multiple 6T-SRAM cells are connected to the same first local bit line BL, and the second ends of the multiple 6T-SRAM cells are connected to the same second local bit line BLB. For example, there can be eight 6T-SRAM cells.

[0030] In some embodiments, the 6T-SRAM cell includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4; the source and drain of the first PMOS transistor P1 are respectively connected to the power supply VDD and the drain of the first NMOS transistor N1, the source and drain of the second PMOS transistor P2 are respectively connected to the power supply VDD and the drain of the second NMOS transistor N2, the gate of the first PMOS transistor P1 and the gate of the first NMOS transistor N1 are both connected to the drain of the second PMOS transistor P2 and form The first storage node Q, the gate of the second PMOS transistor P2 and the gate of the second NMOS transistor N2 are all connected to the drain of the first PMOS transistor P1 and constitute the second storage node QB, the source of the first NMOS transistor N1 and the source node of the second NMOS transistor N2 are both grounded to VSS, the source and drain of the third NMOS transistor N3 are respectively connected to the second local bit line BLB and the second storage node QB, the source and drain of the fourth NMOS transistor N4 are respectively connected to the first local bit line BL and the first storage node Q, and the gate of the third NMOS transistor N3 and the gate of the fourth NMOS transistor N4 are connected to the same word line WL.

[0031] The calculation unit includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9 and a tenth NMOS transistor N10. The source and drain of the fifth PMOS transistor P5 are respectively connected to the drain and source of the seventh NMOS transistor N7, the source and drain of the sixth PMOS transistor P6 are respectively connected to the drain and source of the eighth NMOS transistor N8, and the source of the seventh PMOS transistor P7 is respectively connected to the drain and source of the eighth NMOS transistor N8. The gate electrode and drain electrode of the seventh NMOS tube N7 are connected to the drain and source electrode of the eighth NMOS tube N8, respectively. The source and drain electrode of the eighth PMOS tube P8 are connected to the drain and source electrode of the tenth NMOS tube N10, respectively. The source electrode of the seventh PMOS tube P7 is connected to the drain electrode of the fifth PMOS tube P5, the source electrode of the eighth PMOS tube P8 is connected to the drain electrode of the sixth PMOS tube P6, the gate electrode of the seventh NMOS tube N7 is connected to the gate electrode of the eighth NMOS tube N8, and the gate electrode of the sixth PMOS tube P6 is connected to the gate electrode of the fifth PMOS tube P5.

[0032] The source of the fifth PMOS transistor P5 and the drain of the eighth NMOS transistor N8 are signal output nodes (for outputting the result signal VS). The drains of the seventh PMOS transistor P7 and the eighth PMOS transistor P8 are used to receive the variable-level signal X. The gates of the ninth NMOS transistor N9 and the tenth NMOS transistor N10 are signal input nodes (for receiving input signals IN1 and IN2, respectively). The gates of the seventh PMOS transistor P7 and the eighth PMOS transistor P8 are used to receive inverted input signals IN1N and IN2N, respectively. IN1N is the opposite of IN1, and IN2N is the opposite of IN2.

[0033] The gate of the fifth PMOS transistor P5 and the gate of the eighth NMOS transistor N8 are connected to the second local bit line BLB and the first local bit line BL respectively through a control unit. The control unit is used to implement switch control.

[0034] The control unit includes a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6; the drain and source of the fifth NMOS transistor N5 are respectively connected to the second local bit line BLB and the gate of the fifth PMOS transistor P5, the source and drain of the fourth PMOS transistor P4 are respectively connected to the first local bit line BL and the gate of the eighth NMOS transistor N8, the source and drain of the third PMOS transistor P3 are respectively connected to the second global bit line GBLB and the gate of the fifth PMOS transistor P5, and the source and drain of the sixth NMOS transistor N6 are respectively connected to the first global bit line GBL and the gate of the eighth NMOS transistor N8; the gate of the fifth NMOS transistor N5 is used to receive the first calculation control signal CEN, the gate of the fourth PMOS transistor P4 is used to receive the second calculation control signal CENB, the gate of the sixth NMOS transistor N6 is used to receive the first pre-control signal RAP, and the gate of the third PMOS transistor P3 is used to receive the second pre-control signal RAPB.

[0035] In the above technical solution, multiple storage units and a computing unit are configured together to realize in-memory computing. Compared with the structure in which the computing circuit and the storage circuit are separated, the computing speed is greatly improved, and the problem that the computing circuit and the storage circuit are separated in the traditional von Neumann architecture, which in turn limits the computing speed, is solved.

[0036] The following describes a multi-bit multiplication and addition circuit based on 6T-SRAM, using eight 6T-SRAM cells as an example. For ease of description, various components, signals, and signal lines are described using their corresponding character labels. A high signal level is represented by the number 1, and a low signal level is represented by the number 0.

[0037] In the above technical solution, a circuit structure for multi-bit multiplication and addition based on 6T-SRAM is provided, which is used to realize the multi-bit multiplication and addition function in memory. Figure 1 The circuit structure includes: a storage unit (6T-SRAM unit), a control unit, and a computing unit. The storage unit is used to store weights, and the computing unit is used to perform basic operations. Eight storage units are connected to a control unit and a computing unit. A control unit includes two PMOS transistors and two NMOS transistors, and a computing unit includes four PMOS transistors and four NMOS transistors. The local bit lines BLB and BL of multiple storage units are connected together (multiple storage units share the same local bit lines BLB and BL), and the global bit lines GBLB and GBL of the entire array are connected together (multiple circuit structures share the same global bit lines GBLB and GBL).

[0038] Specifically, refer to Figure 2 The 6T-SRAM cell includes four NMOS transistors and two PMOS transistors. The four NMOS transistors are sequentially denoted as N1-N4, and the two PMOS transistors are sequentially denoted as P1-P2. P1, P2, N1, and N2 have a cross-coupling structure, i.e., the gate of P1 is electrically connected to the gate of N1, the drain of P1 is electrically connected to the drain of N1, the gate of P2 is electrically connected to the gate of N2, the drain of P2 is electrically connected to the drain of N2, the gate of P1 is electrically connected to the drain of P2, and the gate of P2 is electrically connected to the drain of P1, so that the data of the storage nodes Q and QB are latched. P1 and P2 act as pull-up transistors, i.e., the source of P1 is electrically connected to the source of P2 and to VDD, thereby opening the Q and QB nodes to the power supply path. N1 and N2 act as pull-down transistors, i.e., the source of N1 is electrically connected to the source of N2 and to VSS, thereby opening the Q and QB nodes to the ground path. The two storage nodes Q and QB are connected to bit lines BLB and BL respectively through N3 and N4, which are controlled by word lines WL. N1, N2, N3, N4, P1, and P2 form a 6Tcell, which serves as a storage unit.

[0039] See Figure 2 The multi-bit multiplication and addition circuit based on 6T-SRAM includes a storage unit, a control unit, and a calculation unit. The storage unit is used to store weights, the calculation control unit is used to control the start and stop of calculations, and the calculation unit is used to perform multiplication and addition operations.

[0040] More specifically, the connection relationship between the transistors in the 6T-SRAM unit, the control unit, and the computing unit is as follows:

[0041] The gate of P1 is electrically connected to the gate of N1, the drain of N4, and the drain of P2, and the drain of P1 is electrically connected to the drain of N1 and the drain of N3.

[0042] The gate of P2 is electrically connected to the gate of N2, the drain of N3, and the drain of P1, and the drain of P2 is electrically connected to the drain of N2 and the drain of N4.

[0043] The gate of P3 is connected to the precharge control signal RAPB, the drain of P3 is electrically connected to the source of N5 and the gate of P5, and the source of P3 is connected to the global bit line GBLB.

[0044] The gate of P4 is connected to the calculation control signal CENB, the source of P4 is electrically connected to the local bit line BL, and the drain of P4 is electrically connected to the gate of N8 and the drain of N6.

[0045] The gate of P5 is electrically connected to the source of N5, the source of P5 is electrically connected to the drain of N7, the drain of N8, and the source of P6, and the drain of P5 is electrically connected to the source of N7, the drain of N9, and the source of P7.

[0046] The gate of P6 is electrically connected to the source of N5, the drain of P6 is electrically connected to the source of N8, the source of P8, and the drain of N10, and the source of P6 is electrically connected to the source of P5, the drain of N7, and the drain of N8.

[0047] The gate of P7 is connected to the input signal IN1N, the source of P7 is electrically connected to the drain of P5 and the drain of N9, and the drain of P7 is electrically connected to the source of N9.

[0048] The gate of P8 is connected to the input signal IN2N, the source of P8 is electrically connected to the source of N8 and the drain of P6, and the drain of P8 is electrically connected to the source of N10.

[0049] The gate of N1 is electrically connected to the gate of P1, the drain of P2, and the drain of N4. The drain of N1 is electrically connected to the drain of P1, the drain of N3, and the gate of N2.

[0050] The gate of N2 is electrically connected to the gate of P2, the drain of P1, and the drain of N3. The drain of N2 is electrically connected to the drain of P2, the drain of N4, and the gate of N1.

[0051] The drain of N3 is electrically connected to the drain of N1 and the gate of N2 , the gate of N3 is electrically connected to the word line WL, and the source of N3 is electrically connected to the bit line BLB.

[0052] The drain of N4 is electrically connected to the drain of N2 and the gate of N1 , the gate of N4 is electrically connected to the word line WL, and the source of N4 is electrically connected to the bit line BL.

[0053] The gate of N5 is connected to the calculation control signal CEN, the drain of N5 is electrically connected to the local bit line BLB, and the source of N5 is electrically connected to the gate of P5 and the drain of P3.

[0054] The gate of N6 is connected to the pre-control signal RAP, the drain of N6 is electrically connected to the source of P4 and the gate of N8, and the source of N6 is connected to the global bit line GBL.

[0055] The gate of N7 is electrically connected to the source of P4, the source of N7 is electrically connected to the drain of P5, the drain of N9, and the source of P7, and the drain of N7 is electrically connected to the drain of N8, the source of P5, and the source of P6.

[0056] The gate of N8 is electrically connected to the drain of P4 and the drain of N6. The drain of N8 is electrically connected to the source of P6, the source of P5, and the drain of N7. The source of N8 is electrically connected to the drain of P6, the source of P8, and the drain of N10.

[0057] The gate of N9 is connected to the input signal IN1, the drain of N9 is electrically connected to the source of P7, the source of N7, and the drain of P5, and the source of N9 is electrically connected to the drain of P7.

[0058] The gate of N10 is connected to the input signal IN2 , the drain of N10 is electrically connected to the source of N8 and the drain of P6 , and the source of N10 is electrically connected to the drain of P8 .

[0059] Based on the above 6T-SRAM, a multi-bit multiplication and addition circuit structure is built. In this structure, eight memory cells share the same bit lines BL and BLB, and the entire column shares the same global bit lines GBL and GBLB.

[0060] The circuit structure provided in this embodiment has three operating modes, namely, SRAM mode, multiplication-accumulation mode, and multi-bit multiplication-addition mode.

[0061] 1.SRAM mode

[0062] Reference Figure 1 , taking the structure of a single 6T-SRAM as an example:

[0063] (1) Keep operating.

[0064] While the memory cell is holding data, the word line WL remains at a low level, causing N3 and N4 to be turned off, and the bit lines BL and BLB to be precharged to a high level. The internal circuit remains in its initial state and the circuit does not work.

[0065] (2) Write operation.

[0066] In the data writing stage, the word line WL of the 6T-SRAM cell being written is set to a high level, the calculation control signal CEN is set to a high level, the calculation control signal CENB is set to a high level, the pre-control signals RAPB and RAP are set to a low level and a high level respectively. If the global bit line GBL is a high level and the global bit line GBLB is a low level, "1" is written to the memory cell through P3, P4, N5, and N6; if the global bit line GBL is a low level and the global bit line GBLB is a high level, "0" is written to the memory cell through P3, P4, N5, and N6.

[0067] (3) Read operation.

[0068] In the data reading stage, first, the word lines WL0-WL7 of all storage cells are low, the global bit lines GBL and GBLB are set to high, and the control signals RAPB and CENB are set to low, the control signals RAP and CEN are set to high, and after BLB and BL are all pre-charged to high levels, the word line WL of the storage cell being read is turned on; if the data stored in the circuit is "0", that is, "Q=0, QB=1", the global bit line GBL is discharged to the ground through N6 and P4, and a voltage difference is generated between the global bit lines GBLB and GBL, and "0" is output through the sense amplifier SA; if the data stored in the circuit is "1", that is, "Q=1, QB=0", the global bit line GBLB is discharged to the ground through N5 and P3, and a voltage difference is generated between the global bit lines GBLB and GBL, and "1" is output through the sense amplifier SA.

[0069] 2. Multiply-accumulate mode

[0070] See circuit diagram Figure 1 , see the timing diagram Figure 3 , the gates of transistors N9 and N10 serve as the data input of the circuit, and the storage nodes Q and QB serve as the weights; the input signals IN1 and IN2 represent the high and low bits of the 2-bit input respectively; when IN1=0, IN2=0, the 2-bit data represented by the input is "00"; when IN1=0, IN2=1, the 2-bit data represented by the input is "01"; when IN1=1, IN2=0, the 2-bit data represented by the input is "10"; when IN1=1, IN2=1, the 2-bit data represented by the input is "11"; when the storage node Q=1, QB=0, and X=VDD, the Weight is "1"; when the storage node Q=0, QB=1, and X=VDD, the Weight is "0".

[0071] When the input is "00", the result VS is VDD regardless of the value stored in the weight; when the weight is "0", the result VS is VDD regardless of the input value; when the input is "01" and the weight is "1", the result VS is VDD-1ΔV; when the input is "10" and the weight is "1", the result VS is VDD-2ΔV; when the input is "11" and the weight is "1", the result VS is VDD-3ΔV.

[0072] 3. Multi-bit multiplication and addition mode

[0073] The gates of transistors N9 and N10 serve as the data inputs of the circuit, and the storage nodes Q and QB serve as weights. The input signals IN1 and IN2 use different high-level durations to represent different 2-bit numbers. Figure 5 For example, when the input signal is continuously at a low level, it represents "00", when the input signal is continuously at a high level for 100ps, it represents "01", when the input signal is continuously at a high level for 200ps, it represents "10", and when the input signal is continuously at a high level for 300ps, it represents "11"; when the storage node Q=1, QB=0, and X=1, the Weight is "+1"; when the storage node Q=1, QB=0, and X=0, the Weight is "-1"; when the storage node Q=0, QB=1, and X=0 / 1, the Weight is "0".

[0074] The initial value of the result signal VS is set to 1 / 2VDD. If IN1 and IN2 are both low, N5, N10, P5, and P6 are in the off state. At this time, no matter what the value of Weight is, the multiplication and addition result is "0".

[0075] If IN1 is high and IN2 is low, N9 and P7 are in the on state, N10 and P8 are in the off state, and the Weight is "+1", when the IN1 turn-on time is 1Δt, the multiplication and addition result is that VS increases by 1ΔV, that is, VS is 1 / 2VDD+1ΔV. When the IN1 turn-on time is 2Δt, the multiplication and addition result is that VS increases by 2ΔV, that is, VS is 1 / 2VDD+2ΔV. When the IN1 turn-on time is 3Δt, the multiplication and addition result is that VS increases by 3ΔV, that is, VS is 1 / 2VDD+3ΔV.

[0076] If IN1 is low and IN2 is high, N9 and 75 are in the off state, N10 and P8 are in the on state, and the weight is "+1", when the IN2 turn-on time is 1Δt, the multiplication and addition result is that VS increases by 1ΔV, that is, VS is 1 / 2VDD+1ΔV. When the IN2 turn-on time is 2Δt, the multiplication and addition result is that VS increases by 2ΔV, that is, VS is 1 / 2VDD+2ΔV. When the IN2 turn-on time is 3Δt, the multiplication and addition result is that VS increases by 3ΔV, that is, VS is 1 / 2VDD+3ΔV.

[0077] If IN1 is high, IN2 is high, N9 and P7 are in the on state, N10 and P8 are in the on state, and the Weight is "+1", when the IN1 turn-on time is 1Δt and the IN2 turn-on time is 1Δt, the multiplication and addition result is that VS increases by 2ΔV, that is, VS is 1 / 2VDD+2ΔV; when the IN1 turn-on time is 1Δt and the IN2 turn-on time is 2Δt, the multiplication and addition result is that VS increases by 3ΔV, that is, VS is 1 / 2VDD+3ΔV; when the IN1 turn-on time is 1Δt and the IN2 turn-on time is 3Δt, the multiplication and addition result is that VS increases by 4ΔV, that is, VS is 1 / 2VDD+4ΔV.

[0078] If IN1 is high, IN2 is high, N9 and P7 are in the on state, N10 and P8 are in the on state, and the Weight is "+1", when the IN1 turn-on time is 2Δt and the IN2 turn-on time is 1Δt, the multiplication and addition result is that VS increases by 3ΔV, that is, VS is 1 / 2VDD+3ΔV; when the IN1 turn-on time is 2Δt and the IN2 turn-on time is 2Δt, the multiplication and addition result is that VS increases by 4ΔV, that is, VS is 1 / 2VDD+4ΔV; when the IN1 turn-on time is 2Δt and the IN2 turn-on time is 3Δt, the multiplication and addition result is that VS increases by 5ΔV, that is, VS is 1 / 2VDD+5ΔV.

[0079] If IN1 is high, IN2 is high, N9 and P7 are in the on state, N10 and P8 are in the on state, and the Weight is "+1", when the IN1 turn-on time is 3Δt and the IN2 turn-on time is 1Δt, the multiplication and addition result is that VS increases by 4ΔV, that is, VS is 1 / 2VDD+4ΔV; when the IN1 turn-on time is 3Δt and the IN2 turn-on time is 2Δt, the multiplication and addition result is that VS increases by 5ΔV, that is, VS is 1 / 2VDD+5ΔV; when the IN1 turn-on time is 3Δt and the IN2 turn-on time is 3Δt, the multiplication and addition result is that VS increases by 6ΔV, that is, VS is 1 / 2VDD+6ΔV.

[0080] If IN1 is high and IN2 is low, N9 and P7 are in the on state, N10 and P8 are in the off state, and the weight is "-1", when the IN1 turn-on time is 1Δt, the multiplication and addition result is that VS decreases by 1ΔV, that is, VS is 1 / 2VDD-1ΔV. When the IN1 turn-on time is 2Δt, the multiplication and addition result is that VS decreases by 2ΔV, that is, VS is 1 / 2VDD-2ΔV. When the IN1 turn-on time is 3Δt, the multiplication and addition result is that VS decreases by 3ΔV, that is, VS is 1 / 2VDD-3ΔV.

[0081] If IN1 is low and IN2 is high, N9 and P7 are in the off state, N10 and P8 are in the on state, and the weight is "-1", when the IN2 turn-on time is 1Δt, the multiplication and addition result is that VS decreases by 1ΔV, that is, VS is 1 / 2VDD-1ΔV. When the IN2 turn-on time is 2Δt, the multiplication and addition result is that VS decreases by 2ΔV, that is, VS is 1 / 2VDD-2ΔV. When the IN2 turn-on time is 3Δt, the multiplication and addition result is that VS decreases by 3ΔV, that is, VS is 1 / 2VDD-3ΔV.

[0082] If IN1 is high, IN2 is high, N9 and P7 are in the on state, N10 and P8 are in the on state, and the weight is "-1", when the IN1 turn-on time is 1Δt and the IN2 turn-on time is 1Δt, the multiplication and addition result is that VS decreases by 2ΔV, that is, VS is 1 / 2VDD-2ΔV; when the IN1 turn-on time is 1Δt and the IN2 turn-on time is 2Δt, the multiplication and addition result is that VS decreases by 3ΔV, that is, VS is 1 / 2VDD-3ΔV; when the IN1 turn-on time is 1Δt and the IN2 turn-on time is 3Δt, the multiplication and addition result is that VS decreases by 4ΔV, that is, VS is 1 / 2VDD-4ΔV.

[0083] If IN1 is high, IN2 is high, N9 and P7 are in the on state, N10 and P8 are in the on state, and the weight is "-1", when the IN1 turn-on time is 2Δt and the IN2 turn-on time is 1Δt, the multiplication and addition result is that VS decreases by 3ΔV, that is, VS is 1 / 2VDD-3ΔV; when the IN1 turn-on time is 2Δt and the IN2 turn-on time is 2Δt, the multiplication and addition result is that VS decreases by 4ΔV, that is, VS is 1 / 2VDD-4ΔV; when the IN1 turn-on time is 2Δt and the IN2 turn-on time is 3Δt, the multiplication and addition result is that VS decreases by 5ΔV, that is, VS is 1 / 2VDD-5ΔV.

[0084] If IN1 is high, IN2 is high, N9 and P7 are in the on state, N10 and P8 are in the on state, and the weight is "-1", when the IN1 turn-on time is 3Δt and the IN2 turn-on time is 1Δt, the multiplication and addition result is that VS decreases by 4ΔV, that is, VS is 1 / 2VDD-4ΔV; when the IN1 turn-on time is 3Δt and the IN2 turn-on time is 2Δt, the multiplication and addition result is that VS decreases by 5ΔV, that is, VS is 1 / 2VDD-5ΔV; when the IN1 turn-on time is 3Δt and the IN2 turn-on time is 3Δt, the multiplication and addition result is that VS decreases by 6ΔV, that is, VS is 1 / 2VDD-6ΔV.

[0085] When the storage node Q=0, QB=1, that is, the weight is "0", no matter what the input signals IN1 and IN2 are, the multiplication and addition result VS is not discharged or charged to the ground and remains at the initial value 1 / 2VDD, which means that the multiplication and addition result is 0.

[0086] It should be noted that the on-time of the signal mentioned above is the duration of the high level in the signal.

[0087] After simulating 32 calculation input combinations, the results are as follows Figure 4 shown.

[0088] In summary, the multi-bit multiplication and addition operation circuit based on 6T-SRAM provided by the present invention includes a storage unit and a local calculation circuit (control unit and calculation unit). The circuit structure of the present invention has two calculation functions. Function 1: multiplication and accumulation operation, a local calculation circuit can multiply 2 bits (circuit input) and 1 bit (weight), and can be applied to convolutional neural networks in conjunction with a shift register; Function 2: multi-bit multiplication and addition operation, a local calculation circuit can realize the multiplication of two 2 bits (circuit input) and 1 bit (weight) and then add them, which can be applied to grayscale edge detection of images.

[0089] Based on the multi-bit multiplication and addition circuit provided by the present invention, the present invention also provides a control method for the multi-bit multiplication and addition circuit based on 6T-SRAM, which is used to control the circuit to execute different working modes.

[0090] In some embodiments, the control method includes a multi-bit multiplication and addition operation step, a multiplication and accumulation operation step, and an access step, and the various steps are respectively used to control the circuit to execute a multi-bit multiplication and addition mode, a multiplication and accumulation mode, and an SRAM mode.

[0091] The steps of multi-bit multiplication and addition include:

[0092] The first signal and the second signal are connected to the gate of the ninth NMOS transistor and the gate of the tenth NMOS transistor respectively, and the first signal and the second signal represent a first 2-bit number and a second 2-bit number respectively.

[0093] The result signal of the multi-bit multiplication and addition operation is output through the source of the fifth PMOS tube and the drain of the eighth NMOS tube. The result signal of the multi-bit multiplication and addition operation is obtained by adding the product results of the first 2-bit number and the second 2-bit number and the first 1-bit weight respectively.

[0094] Among them, when the first storage node is at a high level, the second storage node is at a low level, and the indeterminate level signal is at a high level, the first 1-bit weight is +1; when the first storage node is at a high level, the second storage node is at a low level, and the indeterminate level signal is at a low level, the first 1-bit weight is -1; when the first storage node is at a low level and the second storage node is at a high level, the first 1-bit weight is 0.

[0095] The first signal and the second signal are respectively input signals IN1 and IN2 in a multi-bit multiplication and addition mode.

[0096] The control method further includes the multiplication and accumulation operation step comprising:

[0097] The third signal and the fourth signal are connected to the gate of the ninth NMOS transistor and the gate of the tenth NMOS transistor respectively. The third signal and the fourth signal represent the high digit and the low digit of the third 2-bit number respectively.

[0098] A result signal of the multiplication and accumulation operation is outputted through the source of the fifth PMOS transistor and the drain of the eighth NMOS transistor, and the result signal of the multiplication and accumulation operation is obtained by multiplying the third 2-bit number and the second 1-bit weight.

[0099] Among them, when the first storage node is at a high level, the second storage node is at a low level, and the indeterminate level signal is at a high level, the second 1-bit weight is 1; when the first storage node is at a low level, the second storage node is at a high level, and the indeterminate level signal is at a high level, the second 1-bit weight is 0.

[0100] The third signal and the fourth signal are input signals IN1 and IN2 in the multiplication-accumulation mode, respectively.

[0101] The access steps include:

[0102] When performing the hold operation in the SRAM mode, the word lines of each 6T-SRAM cell are configured to be low level;

[0103] When performing a write operation in the SRAM mode, the word line of the 6T-SRAM cell being written is configured to be high, the first calculation control signal and the second calculation control signal are configured to be high, and the first pre-control signal and the second pre-control signal are configured to be high and low respectively;

[0104] When performing a read operation in the SRAM mode, first configure the word line signal of each 6T-SRAM unit to a low level, configure the first global bit line and the second global bit line to be high, configure the second pre-control signal and the second calculation control signal to be low, configure the first pre-control signal and the first calculation control signal to be high, then pre-charge the first local bit line and the second local bit line to be high, and after the pre-charging is completed, configure the word line signal of each 6T-SRAM unit to be high.

[0105] The control method of the multi-bit multiplication and addition circuit in this embodiment can be specifically referred to the description of the working mode of the multi-bit multiplication and addition circuit, which will not be repeated here.

[0106] The present invention further provides an operation chip, which integrates the multi-bit multiplication and addition operation circuit based on 6T-SRAM provided by the present invention.

[0107] Reference Figure 6 The present invention also provides a computing module encapsulated with the computing chip provided by the present invention. Specifically, the encapsulated computing module is further provided with various pins, which are respectively used to transmit input signals IN1 and IN2, inverted input signals IN1N and IN2N, storage node signals QB and Q, calculation result signal VS, and variable level signal X.

[0108] The present invention also provides an electronic device, comprising the computing module provided by the present invention.

[0109] It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0110] Obviously, the accompanying drawings are merely examples or embodiments of the present application. A person skilled in the art can also apply the present application to other similar situations based on these drawings without inventive effort. Furthermore, it is understandable that, although the work involved in this development process may be complex and lengthy, certain design, manufacturing, or production changes based on the technical content disclosed in this application are merely routine technical means for a person skilled in the art and should not be considered to constitute a deficiency in the disclosure of the present application.

Claims

1. A multi-bit multiplication and addition circuit based on 6T-SRAM, characterized in that: The circuit includes multiple 6T-SRAM cells, a control unit, and a calculation unit; The plurality of 6T-SRAM cells are arranged in parallel and are respectively controlled by different word lines, the first ends of the plurality of 6T-SRAM cells are connected to the same first local bit line, and the second ends of the plurality of 6T-SRAM cells are connected to the same second local bit line; The calculation unit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor and a tenth NMOS transistor, the source and drain of the fifth PMOS transistor are respectively connected to the drain and source of the seventh NMOS transistor, the source and drain of the sixth PMOS transistor are respectively connected to the drain and source of the eighth NMOS transistor, the source and drain of the seventh PMOS transistor are respectively connected to the drain and source of the ninth NMOS transistor, the source and drain of the eighth PMOS transistor are respectively connected to the drain and source of the tenth NMOS transistor, the source of the seventh PMOS transistor is connected to the drain of the fifth PMOS transistor, the source of the eighth PMOS transistor is connected to the drain of the sixth PMOS transistor, the gate of the seventh NMOS transistor is connected to the gate of the eighth NMOS transistor, and the gate of the sixth PMOS transistor is connected to the gate of the fifth PMOS transistor; The source of the fifth PMOS transistor and the drain of the eighth NMOS transistor are signal output nodes, the drain of the seventh PMOS transistor and the drain of the eighth PMOS transistor are used to receive variable level signals, and the gate of the ninth NMOS transistor and the gate of the tenth NMOS transistor are signal input nodes; The gate of the fifth PMOS transistor and the gate of the eighth NMOS transistor are connected to the second local bit line and the first local bit line respectively through the control unit, and the control unit is used to implement switch control; The control unit includes a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor; The drain and source of the fifth NMOS transistor are respectively connected to the second local bit line and the gate of the fifth PMOS transistor, the source and drain of the fourth PMOS transistor are respectively connected to the first local bit line and the gate of the eighth NMOS transistor, the source and drain of the third PMOS transistor are respectively connected to the second global bit line and the gate of the fifth PMOS transistor, and the source and drain of the sixth NMOS transistor are respectively connected to the first global bit line and the gate of the eighth NMOS transistor; The gate of the fifth NMOS transistor is used to receive the first calculation control signal, the gate of the fourth PMOS transistor is used to receive the second calculation control signal, the gate of the sixth NMOS transistor is used to receive the first pre-control signal, and the gate of the third PMOS transistor is used to receive the second pre-control signal; The multi-bit multiplication and addition operation steps of the multi-bit multiplication and addition operation circuit include: Connecting a first signal and a second signal to the gate of a ninth NMOS transistor and a gate of a tenth NMOS transistor, respectively, the first signal and the second signal representing a first 2-bit number and a second 2-bit number, respectively; The result signal of the multi-bit multiplication and addition operation is output through the source of the fifth PMOS tube and the drain of the eighth NMOS tube. The result signal of the multi-bit multiplication and addition operation is obtained by adding the product results of the first 2-bit number and the second 2-bit number and the first 1-bit weight respectively.

2. The multi-bit multiplication and addition circuit based on 6T-SRAM according to claim 1, characterized in that: The 6T-SRAM unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; The source and drain of the first PMOS transistor are respectively connected to the power supply and the drain of the first NMOS transistor, the source and drain of the second PMOS transistor are respectively connected to the power supply and the drain of the second NMOS transistor, the gate of the first PMOS transistor and the gate of the first NMOS transistor are both connected to the drain of the second PMOS transistor and constitute a first storage node, the gate of the second PMOS transistor and the gate of the second NMOS transistor are both connected to the drain of the first PMOS transistor and constitute a second storage node, the source of the first NMOS transistor and the source node of the second NMOS transistor are both grounded, the source and drain of the third NMOS transistor are respectively connected to the second local bit line and the second storage node, the source and drain of the fourth NMOS transistor are respectively connected to the first local bit line and the first storage node, and the gate of the third NMOS transistor and the gate of the fourth NMOS transistor are connected to the same word line.

3. The multi-bit multiplication and addition circuit based on 6T-SRAM according to claim 1, characterized in that: There are eight 6T-SRAM cells.

4. A control method for a multi-bit multiplication and addition circuit based on 6T-SRAM, characterized in that: The multi-bit multiplication and addition circuit based on 6T-SRAM according to claim 2, wherein the control method includes a multi-bit multiplication and addition operation step, and the multi-bit multiplication and addition operation step includes: Connecting a first signal and a second signal to the gate of a ninth NMOS transistor and a gate of a tenth NMOS transistor, respectively, wherein the first signal and the second signal represent a first 2-bit number and a second 2-bit number, respectively; Outputting a result signal of a multi-bit multiplication and addition operation through the source of the fifth PMOS transistor and the drain of the eighth NMOS transistor, wherein the result signal of the multi-bit multiplication and addition operation is obtained by adding the product of the first 2-bit number and the second 2-bit number and the first 1-bit weight respectively; Among them, when the first storage node is at a high level, the second storage node is at a low level, and the indeterminate level signal is at a high level, the first 1-bit weight is +1; when the first storage node is at a high level, the second storage node is at a low level, and the indeterminate level signal is at a low level, the first 1-bit weight is -1; when the first storage node is at a low level and the second storage node is at a high level, the first 1-bit weight is 0.

5. The control method of the multi-bit multiplication and addition circuit based on 6T-SRAM according to claim 4, characterized in that: The control method further includes a multiplication-accumulation operation step, wherein the multiplication-accumulation operation step includes: Connecting a third signal and a fourth signal to the gate of the ninth NMOS transistor and the gate of the tenth NMOS transistor, respectively, wherein the third signal and the fourth signal represent the high-order digit and the low-order digit of the third 2-bit number, respectively; Outputting a result signal of a multiplication and accumulation operation through the source of the fifth PMOS transistor and the drain of the eighth NMOS transistor, where the result signal of the multiplication and accumulation operation is obtained by multiplying the third 2-bit number by the second 1-bit weight; Among them, when the first storage node is at a high level, the second storage node is at a low level, and the indeterminate level signal is at a high level, the second 1-bit weight is 1; when the first storage node is at a low level, the second storage node is at a high level, and the indeterminate level signal is at a high level, the second 1-bit weight is 0.

6. The control method of the multi-bit multiplication and addition circuit based on 6T-SRAM according to claim 4, characterized in that: The control method further includes an access step, wherein the access step includes: When performing the hold operation in the SRAM mode, the word lines of each 6T-SRAM cell are configured to be low level; When performing a write operation in the SRAM mode, the word line of the 6T-SRAM cell being written is configured to be high, the first calculation control signal and the second calculation control signal are configured to be high, and the first pre-control signal and the second pre-control signal are configured to be high and low respectively; When performing a read operation in the SRAM mode, first configure the word line signal of each 6T-SRAM unit to a low level, configure the first global bit line and the second global bit line to be high, configure the second pre-control signal and the second calculation control signal to be low, configure the first pre-control signal and the first calculation control signal to be high, then pre-charge the first local bit line and the second local bit line to be high, and after the pre-charging is completed, configure the word line signal of each 6T-SRAM unit to be high.

7. A computing chip, characterized in that: The multi-bit multiplication and addition circuit based on 6T-SRAM according to claim 1 or 2 is integrated.

8. A computing module, characterized in that: The computing chip according to claim 7 is packaged.

9. An electronic device, characterized in that: Includes the computing module according to claim 8.

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