Wafer-level packaging method, system, terminal and storage medium for multi-structure bumps

Abstract

The present application relates to a wafer-level packaging method, system, intelligent terminal and storage medium for multi-structure bumps, and relates to the field of chip packaging technology. The method includes: sputtering a TiCu layer on a dielectric layer of an integrated circuit wafer; coating a first photoresist layer of a first thickness on the TiCu layer, the first thickness matching the height of the first bump; forming a pattern of the first bump on the first photoresist layer; forming the first bump on the integrated circuit wafer; removing the first photoresist layer; coating a second photoresist layer of a second thickness on the TiCu layer, the structure of the second bump being different from that of the first bump; forming a pattern of the second bump on the second photoresist layer; forming the second bump on the integrated circuit wafer; removing the second photoresist layer and the TiCu layer to expose the first bump and the second bump; reflowing the integrated circuit wafer to obtain a packaged integrated circuit wafer. The present application has the effect of forming electrode bumps of various structures on an integrated circuit wafer of wafer-level packaging.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a wafer-level packaging method, system, intelligent terminal and storage medium for multiple structure bumps. Background Art

[0002] Wafer-level packaging is an advanced semiconductor packaging technology that completes chip packaging at the wafer level instead of packaging after individual chips are cut. This method is usually used to increase packaging density, reduce costs and shorten production cycles.

[0003] Related technology When performing wafer-level packaging, it is necessary to sequentially cover the surface of the aforementioned integrated circuit wafer with a dielectric layer, a seed layer, and a photoresist layer. The electrode pattern is transferred to the photoresist layer. Electrode bumps with a specific structure are electroplated through an electroplating process. Afterwards, the photoresist layer and the seed layer are removed to expose the electrode bumps. The integrated circuit wafer is cleaned and reflowed to obtain a packaged integrated circuit wafer.

[0004] With respect to the above-mentioned related technologies, the inventors believe that only one structure of electrode bumps can be formed on an integrated circuit wafer. During the chip development stage, if chips with multiple structures need to be compared, multiple wafers are required for packaging, which results in high material costs and time costs. Summary of the invention

[0005] In order to form electrode bumps of various structures on an integrated circuit wafer of wafer-level packaging, the present application provides a wafer-level packaging method, system, terminal and storage medium for multi-structure bumps.

[0006] In a first aspect, the present application provides a wafer-level packaging method for multi-structure bumps, which adopts the following technical solution:

[0007] A wafer-level packaging method for multiple structure bumps, comprising:

[0008] Sputtering to form a TiCu layer on the dielectric layer of the integrated circuit wafer, wherein the TiCu layer covers the surface of the integrated circuit wafer;

[0009] Coating a first photoresist layer of a first thickness on the TiCu layer, wherein the first thickness matches the height of the first bump;

[0010] forming a pattern of the first bumps on the first photoresist layer;

[0011] forming the first bump on the integrated circuit wafer;

[0012] removing the first photoresist layer;

[0013] Coating a second photoresist layer with a second thickness on the TiCu layer, wherein the second thickness matches the height of the second bump, the thickness of the second photoresist layer is greater than the height of the first bump, the height of the second bump is greater than the height of the first bump, and the structure of the second bump is different from that of the first bump;

[0014] forming a pattern of the second bumps on the second photoresist layer;

[0015] forming the second bump on the integrated circuit wafer;

[0016] removing the second photoresist layer and the TiCu layer to expose the first bump and the second bump;

[0017] The integrated circuit wafer is reflowed to obtain a packaged integrated circuit wafer.

[0018] By adopting the above technical solution, after a TiCu layer is sputtered on a dielectric layer of an integrated circuit wafer, a first photoresist layer of a first thickness is first coated to form a first bump on the first photoresist layer; the first photoresist layer is removed; and a second photoresist layer of a second thickness is then coated to form a second bump on the second photoresist layer. The above solution can form bumps of different structures on an integrated circuit wafer.

[0019] Optionally, a Cu layer is formed on the TiCu layer by sputtering, and the thickness of the Cu layer is half of the thickness of the Cu layer in the TiCu layer.

[0020] By adopting the above technical solution, when removing the first photoresist layer, the Cu on the surface of the TiCu layer will be corroded, thinned or damaged, affecting subsequent operations. After removing the first photoresist layer, a Cu layer can be sputtered to ensure the integrity of the TiCu layer.

[0021] Optionally, obtaining the seed layer thickness of the TiCu layer at various locations;

[0022] Determine whether there is a target area where the seed layer thickness is less than a preset thickness;

[0023] If yes, obtaining a first area distance between the target area and a projection area of ​​the second bump on the TiCu layer;

[0024] When the first area distance is less than a preset first distance influence value, extracting an average thickness of the TiCu layer in the target area;

[0025] According to the difference between the preset protection thickness and the average thickness, setting the sputtering thickness of the Cu layer;

[0026] The Cu layer is sputtered to form the Cu layer on the target area according to the sputtering thickness.

[0027] By adopting the above technical solution, the target area to be sputtered is clearly identified according to the thickness of the seed layer of the TiCu layer at various locations, and the target area is accurately sputtered, which can prevent the TiCu layer from having an overly thick area and save materials.

[0028] Optionally, detecting a second area distance between the target area and a projection area of ​​the first bump on the TiCu layer;

[0029] When the distance of the second area is less than a preset second distance influence value, determining an influence part on the first convex point according to the distance from the target area to the first convex point;

[0030] The affected portion on the first bump is subjected to sputtering treatment to form a conductive protective layer on the affected portion.

[0031] By adopting the above technical solution, a conductive protection layer is formed on the first bump, and when the Cu layer is sputtered on the TiCu layer, the first bump can be protected from the influence of sputtering, thereby protecting the first bump.

[0032] Optionally, when the height difference between the first convex point and the second convex point is less than a critical height difference, obtaining an actual boundary line of the graphic of the second convex point;

[0033] According to the actual boundary line and the preset effective distance, an etching area is formed, wherein the shortest distance from the boundary of the etching area to the actual boundary line is not less than the effective distance, and the etching area surrounds the pattern of the second convex point;

[0034] Setting an etching depth according to a difference between an actual thickness of the second photoresist layer and a recommended thickness;

[0035] According to the etching depth, the etching area is ion-beam-etched.

[0036] By adopting the above technical solution, when generating the second bump, the thickness of the second photoresist layer is required to be maintained within a certain range and not too thick. When the height difference between the first bump and the second bump is less than the critical height difference, it is easy to cause, so ion beam etching is performed on the etching area to ensure that the thickness of the second photoresist layer is not too thick, thereby ensuring the quality of the second bump.

[0037] Optionally, an etching direction is set according to the direction of the shortest directed line segment from the actual boundary line to the boundary of the etching area, and the etching direction forms a preset angle with the vertical downward direction;

[0038] Matching ion energy and etching time according to the etching direction and the etching depth;

[0039] The etching region is subjected to ion beam etching with the etching direction, the ion energy and the etching time as parameters. The etching sequence of the ion beam etching is from close to the actual boundary line to the boundary of the etching region.

[0040] By adopting the above technical solution, the etching direction and etching sequence of ion beam etching are controlled so that the thickness of the second photoresist layer at the actual boundary line is controlled within a certain range. Even if over-etching occurs in ion beam etching, it will not have a significant impact on the above thickness.

[0041] Optionally, after the ion beam etching is completed, the etching thickness of the second photoresist layer at each location of the actual boundary line is counted;

[0042] Calculating the actual variance and minimum thickness of the etching thickness;

[0043] When the minimum thickness is greater than the recommended thickness and the actual variance is greater than the preset variance, setting a corrected thickness according to the minimum thickness;

[0044] The etching region is ion-beam etched according to the modified thickness.

[0045] By adopting the above technical solution, the etched area is corrected by ion beam etching, and the thickness of the second photoresist layer in the etched area is controlled to ensure the quality of the second bump.

[0046] In a second aspect, the present application provides a wafer-level packaging system with multiple structure bumps, which adopts the following technical solution:

[0047] A wafer-level packaging system with multiple structure bumps, comprising:

[0048] An acquisition module, used to acquire a seed layer thickness, a preset thickness, a first distance influence value, a second distance influence value, an effective distance, a recommended thickness and a preset angle;

[0049] A memory for storing a program of any one of the above-mentioned wafer-level packaging methods for multi-structure bumps;

[0050] The program in the memory can be loaded and executed by the processor to implement any of the above-mentioned wafer-level packaging methods for multi-structure bumps.

[0051] By adopting the above technical solution, after a TiCu layer is sputtered on a dielectric layer of an integrated circuit wafer, a first photoresist layer of a first thickness is first coated to form a first bump on the first photoresist layer; the first photoresist layer is removed; and a second photoresist layer of a second thickness is then coated to form a second bump on the second photoresist layer. The above solution can form bumps of different structures on an integrated circuit wafer.

[0052] In a third aspect, the present application provides a smart terminal, which adopts the following technical solution:

[0053] An intelligent terminal comprises a memory and a processor, wherein the memory stores a computer program which can be loaded by the processor and execute any one of the above methods.

[0054] By adopting the above technical solution, after a TiCu layer is sputtered on a dielectric layer of an integrated circuit wafer, a first photoresist layer of a first thickness is first coated to form a first bump on the first photoresist layer; the first photoresist layer is removed; and a second photoresist layer of a second thickness is then coated to form a second bump on the second photoresist layer. The above solution can form bumps of different structures on an integrated circuit wafer.

[0055] In a fourth aspect, the present application provides a computer storage medium capable of storing a corresponding program, which has the characteristic of being easy to realize forming electrode bumps of various structures on an integrated circuit wafer of wafer-level packaging, and adopts the following technical solution:

[0056] A computer-readable storage medium stores a computer program that can be loaded by a processor and execute any of the above-mentioned wafer-level packaging methods for multi-structure bumps.

[0057] By adopting the above technical solution, after a TiCu layer is sputtered on a dielectric layer of an integrated circuit wafer, a first photoresist layer of a first thickness is first coated to form a first bump on the first photoresist layer; the first photoresist layer is removed; and a second photoresist layer of a second thickness is then coated to form a second bump on the second photoresist layer. The above solution can form bumps of different structures on an integrated circuit wafer.

[0058] In summary, the present application includes at least one of the following beneficial technical effects:

[0059] After a TiCu layer is formed on the dielectric layer of the integrated circuit wafer by sputtering, a first photoresist layer of a first thickness is first coated to form a first bump on the first photoresist layer; the first photoresist layer is removed; and a second photoresist layer of a second thickness is then coated to form a second bump on the second photoresist layer. The above scheme can form bumps of different structures on the integrated circuit wafer;

[0060] When removing the first photoresist layer, the Cu on the surface of the TiCu layer may be corroded, thinned or damaged, which may affect subsequent operations. After removing the first photoresist layer, a Cu layer may be sputtered to ensure the integrity of the TiCu layer.

[0061] When generating the second bump, the thickness of the second photoresist layer is required to be maintained within a certain range and not too thick. When the height difference between the first bump and the second bump is less than the critical height difference, it is easy to cause, so ion beam etching is performed on the etching area to ensure that the thickness of the second photoresist layer is not too thick, thereby ensuring the quality of the second bump. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 It is a schematic flow chart of a wafer-level packaging method for multi-structure bumps provided in an embodiment of the present application;

[0063] Figure 2 It is a schematic diagram of a wafer-level packaging method of multi-structure bumps provided in an embodiment of the present application;

[0064] Figure 3 is a schematic diagram of an integrated circuit wafer provided in an embodiment of the present application;

[0065] Figure 4 It is a schematic flow chart of a TiCu layer repair method provided in an embodiment of the present application;

[0066] Figure 5 It is a schematic flow chart of a wafer-level packaging method for multi-structure bumps provided in an embodiment of the present application;

[0067] Figure 6 It is a schematic flow chart of a method for correcting a second photoresist layer provided in an embodiment of the present application;

[0068] Figure 7 is a schematic diagram of ion beam etching provided in an embodiment of the present application;

[0069] Figure 8 It is a schematic flow chart of an ion beam etching method provided in an embodiment of the present application;

[0070] Fig. 9 It is a schematic flow chart of an etching method of a second photoresist layer provided in an embodiment of the present application;

[0071] Fig.10 It is a schematic diagram of a wafer-level packaging system with multiple structure bumps provided in an embodiment of the present application. DETAILED DESCRIPTION

[0072] In order to make the purpose, technical solutions and advantages of this application more clear, the following Figure 1 To Attachment Fig.10It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0073] The present application embodiment discloses a wafer-level packaging method for multiple structure bumps. Figure 1 , the method comprising:

[0074] Step S101: sputtering to form a TiCu layer on the dielectric layer of the integrated circuit wafer, wherein the TiCu layer covers the surface of the integrated circuit wafer.

[0075] The integrated circuit wafer has chip electrodes and circuit layout, the surface of the integrated circuit is covered with a passivation layer, and an opening is opened in the passivation layer, and the opening exposes the front side of the electrode. For example, please refer to Figure 2 The surface of the integrated circuit wafer 201 is covered with a passivation layer 203 , and the opening of the passivation layer 203 exposes the electrode 203 .

[0076] Please refer to Figure 2 Before this step, the integrated circuit wafer 201 is covered with a dielectric layer 202 , and the dielectric layer 202 serves as a buffer protection layer for the integrated circuit wafer 201 .

[0077] The TiCu layer is used as a barrier layer and a conductive layer of the integrated circuit wafer. The TiCu layer is conductive over the entire surface and is used to prepare for the subsequent electroplating step. The TiCu layer is also used as a seed layer to form a bump structure for the subsequent electroplating step.

[0078] The TiCu layer includes a Ti layer and a Cu layer. Exemplarily, the Ti layer is formed on the dielectric layer by sputtering, and then the Cu layer is formed on the Ti layer by sputtering.

[0079] Step S102: coating a first photoresist layer with a first thickness on the TiCu layer, wherein the first thickness matches the height of the first bump.

[0080] The first bump is a bump electrode, and the first bump is used to lead out an electrode on the integrated circuit wafer.

[0081] The first thickness of the first photoresist layer is greater than the height of the first bump, and the height difference between the first thickness and the height of the first bump is less than a first preset height difference, wherein the first preset height difference is a preset empirical value. If the first thickness of the first photoresist layer is less than the height of the first bump, then when the first bump is formed by electroplating, the first bump will overflow the first photoresist layer, causing the ball of the first bump to be larger or to form connected balls, affecting the quality of the first bump. If the height difference between the first thickness and the height of the first bump is greater than the first preset height difference, then when the first bump is formed by electroplating, a deep hole structure will be formed on the first photoresist layer, increasing the difficulty of electroplating, resulting in poor uniformity of the first bump and the phenomenon of high and low balls.

[0082] For example, please refer to Figure 2 , a first photoresist layer 205 with a first thickness is coated on the TiCu layer 204 .

[0083] Step S103: forming a pattern of first bumps on the first photoresist layer.

[0084] The pattern of the first bumps is formed by the openings on the first photoresist layer.

[0085] Optionally, a first mask is placed on the first photoresist layer, and the first photoresist layer is photolithographically processed through the first mask to form a pattern of first bumps. Further, the pattern of the first bumps exposes an electrode region on the TiCu layer, and the electrode region corresponds to a chip electrode on the integrated circuit wafer.

[0086] For example, please refer to Figure 2 A first photoresist opening is formed on the first photoresist layer to obtain a pattern of a first bump. The position of the first photoresist opening corresponds to the position of the chip electrode, and a projection of the first photoresist opening on the integrated circuit wafer overlaps with the chip electrode.

[0087] Step S104: forming a first bump on the integrated circuit wafer.

[0088] Optionally, a first bump is formed on the integrated circuit wafer through an electroplating process, and the first bump is located within a pattern of the first bump.

[0089] Optionally, through a ball planting process, an alloy solder ball is placed at the pattern of the first bump using a flux steel mesh and a ball planting steel mesh to obtain the first bump.

[0090] For example, please refer to Figure 2 , forming a first bump 206 in the first photoresist opening.

[0091] Step S105: removing the first photoresist layer.

[0092] Optionally, the first photoresist layer is removed by at least one of chemical removal, thermal removal, plasma removal or ultrasonic removal.

[0093] It should be noted that when removing the first photoresist layer, the TiCu layer needs to be retained.

[0094] For example, please refer to Figure 2 , remove the first photoresist layer 205 to expose the first bump 206 and the TiCu layer 204 .

[0095] Furthermore, during the process of electroplating to form the first bump and removing the first photoresist, the TiCu layer will be corroded, causing it to become thinner or damaged, which will increase the difficulty of subsequent electroplating to form the second bump, resulting in electroplating failure and poor electroplating uniformity. To solve this problem, this embodiment proposes two optional solutions:

[0096] 1. When executing step S101, increase the thickness of the Cu layer in the TiCu layer. Wherein, the increased thickness of the Cu layer needs to be controlled within a preset interval, and the endpoints of the preset interval are preset empirical values. In addition, the increased thickness of the Cu layer is greater than the maximum value within the preset interval, which will cause the Cu layer to be too thick, resulting in a larger bottom cut at the junction of the electroplated bump and the integrated circuit wafer, affecting the nodularity of the bump and the integrated circuit wafer. Moreover, TiCu needs to be removed by an etching process in subsequent steps, and an excessively thick Cu layer will cause the corrosion process to go deeper and damage the integrated circuit wafer. Exemplarily, assuming that the thickness of the Cu layer required for electroplating the bump is a, and the increased thickness of the Cu layer is b, b∈A, and A represents a preset interval, then the thickness of the sputtered Cu layer is a+b.

[0097] 2. Before performing step S106, a Cu layer is formed on the TiCu layer by sputtering, and the thickness of the Cu layer is half of the thickness of the Cu layer in the TiCu layer to ensure the integrity of the TiCu layer as a seed layer.

[0098] Step S106: coating a second photoresist layer of a second thickness on the TiCu layer, wherein the second thickness matches the height of the second bump, the thickness of the second photoresist layer is greater than the height of the first bump, the height of the second bump is greater than the height of the first bump, and the structure of the second bump is different from that of the first bump.

[0099] In the present application, there is a requirement for the manufacturing sequence of the bumps, which requires electroplating from low to high according to the height of the bumps, that is, electroplating the bumps with low height first, and then electroplating the bumps with high height.

[0100] The second thickness of the second photoresist layer is greater than the height of the second bump, and a height difference between the second thickness and the height of the second bump is less than a second preset height difference, wherein the second preset height difference is a preset empirical value.

[0101] The material of the second photoresist layer may be the same as or different from that of the first photoresist layer.

[0102] For example, please refer to Figure 2 , a second photoresist layer 207 with a second thickness is coated on the TiCu layer 204 .

[0103] Step S107: forming a pattern of second bumps on the second photoresist layer.

[0104] The pattern of the second bumps is formed by the openings in the second photoresist layer.

[0105] Optionally, a second mask is placed on the second photoresist layer; and the second photoresist layer is photolithographically processed through the second mask to form a pattern of second bumps.

[0106] For example, please refer to Figure 2 , a second photoresist opening is formed on the second photoresist layer 207 to obtain a pattern of a second bump.

[0107] Step S108: forming second bumps on the integrated circuit wafer.

[0108] Optionally, a second bump is formed on the integrated circuit wafer through an electroplating process, and the second bump is located within a second bump pattern.

[0109] Optionally, through a ball planting process, the alloy tin ball is placed at the pattern of the second bump using a flux steel mesh and a ball planting steel mesh to obtain the second bump.

[0110] For example, please refer to Figure 2 , forming a second bump 208 in the second photoresist opening.

[0111] In some other embodiments, the first bump and the second bump may be a combination of electroplated bumps and ball-planted bumps in addition to being a combination of electroplated bumps of different structures. The two bumps are similar in appearance, but the components that can be used for the two are different. For example, the first bump is an electroplated bump and the second bump is a ball-planted bump. The first bump is formed by an electroplating process, and its component combination is relatively limited. For example, its component may be Sn, SnAg, Cu, CuNi, etc. The second bump is formed by a ball-planting process, and its component may be a freely combined alloy component, for example, its component may be a SnAgCu alloy.

[0112] Furthermore, the first bump and the second bump obtained in the present application may be different in height or diameter, or may be different in Cu pillar and solder bump, in addition to the different structural types. For example, the first bump is Cupillar and the second bump is solder bump. In this case, the Cu pillar adopts FC packaging technology and the solder bump adopts SMT mounting technology.

[0113] It should be noted that, in this embodiment, if it is necessary to form more bumps with different structures on the integrated circuit wafer, step S106 to step S108 may be repeated.

[0114] Step S109: removing the second photoresist layer and the TiCu layer to expose the first bump and the second bump.

[0115] Optionally, the second photoresist layer is removed by at least one of chemical removal, thermal removal, plasma removal or ultrasonic removal.

[0116] Optionally, the TiCu layer is removed by an etching process.

[0117] For example, please refer to Figure 2 , remove the second photoresist layer and the TiCu layer to expose the first bump and the second bump.

[0118] Step S110: reflow the integrated circuit wafer to obtain a packaged integrated circuit wafer.

[0119] Optionally, after the integrated circuit has completed reflow, the integrated circuit wafer is ground and divided and taped to obtain a packaged integrated circuit wafer.

[0120] It should be noted that, in this embodiment, more types of bumps can be formed on the integrated wafer circuit, and the above steps S105 to S108 can be repeated, and the process of coating the photoresist layer and forming new bumps can be repeated while retaining the TiCu layer, so as to form more types of bumps on the integrated wafer circuit. Wherein, when coating the photoresist layer, it is necessary to ensure that the new photoresist layer can cover the existing bumps on the integrated circuit wafer.

[0121] Bumps of different structures can be on the same integrated circuit wafer or on different integrated circuit wafers. Figure 3 The structures of bumps 301, 302 and 303 are different from each other. Bumps 301, 302 and 303 are arranged on different integrated circuit wafers, and the integrated circuit wafers are divided by dividing lanes 304. Bumps 301, 302 and 303 can also be located on the same integrated circuit wafer.

[0122] In summary, after a TiCu layer is formed on a dielectric layer of an integrated circuit wafer by sputtering, a first photoresist layer of a first thickness is coated to form a first bump on the first photoresist layer; the first photoresist layer is removed; and a second photoresist layer of a second thickness is coated to form a second bump on the second photoresist layer. The above scheme can form bumps of different structures on an integrated circuit wafer.

[0123] In the following examples, when executing Figure 1 Before step S106 of the embodiment shown, the electroplating process and the removal of the first photoresist layer will cause corrosion to the Cu layer on the TiCu layer, affecting the quality of the subsequent second bump. Therefore, the thickness of the Cu layer needs to be controlled before executing step S106. The embodiment of the present application discloses a TiCu layer repair method. Figure 4 , the method comprising:

[0124] Step S401: obtaining the seed layer thickness of the TiCu layer at various locations.

[0125] Optionally, the surface of the TiCu layer is scanned to obtain distance information from the scanning device to the surface of the TiCu layer; and the seed layer thickness of the TiCu layer at various locations is obtained based on the distance information and the height of the scanning device relative to the integrated circuit chip.

[0126] Step S402: Determine whether there is a target area where the seed layer thickness is less than a preset thickness.

[0127] If there is a target area where the seed layer thickness is less than the preset thickness, step S403 is executed;

[0128] If there is no target area with a seed layer thickness less than the preset thickness, execute Figure 1 Step S106 of the illustrated embodiment.

[0129] The preset thickness is a preset empirical value.

[0130] Step S403: If yes, then obtain a first area distance between the target area and the projection area of ​​the second bump on the TiCu layer.

[0131] The first area distance refers to the shortest distance from the target area to the projection area of ​​the second bump on the TiCu layer.

[0132] Optionally, after determining the target area, the distances from each point on the boundary of the target area to the projection area of ​​the second bump on the TiCu layer are calculated; and the minimum value of the aforementioned distances is taken as the first area distance.

[0133] Step S404: when the first area distance is less than a preset first distance influence value, extracting the average thickness of the TiCu layer in the target area.

[0134] When the first area distance is less than the first distance influence value, it means that the target area will have an adverse effect on the formation of the second convex point. The first distance influence value is a preset empirical value, and relevant personnel can adjust the value of the first distance influence value according to actual needs.

[0135] Exemplarily, when the first area distance is less than a preset first distance influence value, the average value of the thickness of the TiCu layer in the target area is calculated to obtain the average thickness.

[0136] Step S405: setting the sputtering thickness of the Cu layer according to the difference between the preset protection thickness and the average thickness.

[0137] The protection thickness is an empirical value, and relevant personnel can adjust the value of the protection thickness according to actual needs.

[0138] Optionally, a difference between a preset protection thickness and an average thickness is calculated; and the difference is used as the sputtering thickness of the Cu layer in the target area.

[0139] Step S406: sputtering to form a Cu layer on the target area according to the sputtering thickness.

[0140] Optionally, the target area is used as a processing area for a metal sputtering process; a metal sputtering process is performed on the target area to form a Cu layer, so that the thickness of the Cu layer formed by sputtering in the target area is consistent with the sputtering thickness.

[0141] In summary, according to the thickness of the seed layer of the TiCu layer at various locations, the target area to be sputtered is clearly identified, and the target area is accurately sputtered, which can prevent the TiCu layer from having an overly thick area and save materials.

[0142] In the following examples, Figure 4 In the embodiment shown, after obtaining the target area, if the target area is close to the first bump, the metal sputtering process may damage the first bump, affecting the quality of the first bump. Therefore, the embodiment of the present application discloses a method for including the first bump. Figure 5 , the method comprising:

[0143] Step S501: detecting a second area distance between a target area and a projection area of ​​a first bump on the TiCu layer.

[0144] The second area distance refers to the shortest distance from the target area to the projection area of ​​the first bump on the TiCu layer.

[0145] Optionally, the distances from each point on the boundary of the target area to the projection area of ​​the first bump on the TiCu layer are calculated; and the minimum value of the aforementioned distances is taken as the first area distance.

[0146] Step S502: when the second area distance is less than a preset second distance influence value, determining an influence part on the first salient point according to the distance from the target area to the first salient point.

[0147] The second distance impact value is a preset empirical value, and the specific value of the second distance impact value can be adjusted according to actual needs.

[0148] Optionally, in the aforementioned step of sputtering to form a Cu layer on the target area according to the sputtering thickness, process parameters used in the sputtering process are obtained, and the process parameters include the type of metal used in the metal sputtering process, the ejection energy of the metal particles, the ejection direction of the metal particles, and the process duration. Determine the splashing trajectory of the metal particles and the estimated kinetic energy of the metal particles at each point on the splashing trajectory according to the process parameters. Count the intersection position of the splashing trajectory and the first bump. Predict the kinetic energy value of the metal particles at the intersection position. If the kinetic energy value is greater than a preset kinetic energy threshold, the corresponding intersection position is divided into the affected part. If the kinetic energy value is less than the preset kinetic energy threshold, the corresponding intersection position is not divided into the affected part.

[0149] In an optional method, the target endpoint of the line segment corresponding to the distance of the second area on the target area is obtained. A directed line segment is made from the target endpoint to the first convex point, so that the directed line segment intersects with the first convex point to form an intersection, wherein the direction of the directed line segment points to each point on the surface of the first convex point. If the number of intersections between a single directed line segment and the first convex point is greater than 1, the intersection close to the target endpoint is taken as the target intersection; the target intersections on all directed line segments are taken. According to the position of the target intersection on the first convex point, the affected part is determined.

[0150] Step S503: performing sputtering treatment on the affected portion of the first bump to form a conductive protective layer on the affected portion.

[0151] Exemplarily, the affected part on the first bump is subjected to sputtering treatment by a metal sputtering process, wherein the material of the conductive protection layer is the same as the material of the first bump, or the material of the conductive protection layer is a conductive material.

[0152] In summary, when a conductive protection layer is formed on the first bump and a Cu layer is formed on the TiCu layer by sputtering, the first bump can be protected from the influence of sputtering and the first bump can be protected.

[0153] In the following embodiments, when coating the second photoresist layer, it is necessary to strictly control the thickness of the second photoresist layer so that the second photoresist layer can well cover the first bump, and at the same time ensure that the thickness of the second photoresist layer is not too thick to prevent affecting the electroplating of the second bump. However, when the heights of the first bump and the second bump are relatively close, the two conditions that the second photoresist can well cover the first bump and the thickness of the second photoresist layer is not too thick may conflict. Therefore, the embodiment of the present application discloses a method for correcting the second photoresist layer. Figure 6 , the method comprising:

[0154] Step S601: when the height difference between the first convex point and the second convex point is less than the critical height difference, obtaining the actual boundary line of the figure of the second convex point.

[0155] The critical height difference is a preset fixed value and is related to the process parameters of the electroplating process and the material of the second photoresist layer.

[0156] Assume that the height of the first bump is p, and the height of the second bump is q, where q is greater than p. In order for the second photoresist layer to cover the first bump well, the thickness of the second photoresist layer is required to be at least m, where m is greater than p. However, in order to form a second bump of qualified quality, the thickness of the second photoresist layer is required not to exceed n, where n is greater than q. In actual production scenarios, when the height difference between the first bump and the second bump is less than the critical height difference, m is greater than n, resulting in a conflict between the two requirements.

[0157] The actual boundary line refers to the opening edge of the second bump pattern on the second photoresist layer. For example, please refer to Figure 7 The pattern of the second bump forms an opening 701 on the second photoresist layer, and the edge of the opening 701 forms an actual boundary line.

[0158] Step S602: forming an etching region according to the actual boundary line and the preset effective distance, wherein the shortest distance from the boundary of the etching region to the actual boundary line is not less than the effective distance, and the etching region surrounds the pattern of the second convex point.

[0159] The effective distance is a preset empirical value, and the value of the effective distance can be adjusted according to actual needs.

[0160] When forming the second bump by electroplating, the photoresist thickness in a certain area near the opening is required to be within the recommended thickness. That is, the shortest distance from the boundary of the etched area to the actual boundary line is not less than the effective distance. For example, please refer to Figure 7 , the shortest distance L from the edge of the etched area to the actual boundary line needs to reach the effective distance. If the shortest distance is less than the effective distance, a deep hole structure will be formed, which will increase the difficulty of electroplating, cause the uniformity of the second bump, and produce large and small balls.

[0161] Step S603: setting the etching depth according to the difference between the actual thickness of the second photoresist layer and the recommended thickness.

[0162] The recommended thickness is the thickness of the second photoresist used for electroplating to form the second bump.

[0163] Step S604: performing ion beam etching on the etching area according to the etching depth.

[0164] Exemplarily, according to the etching depth, ion beam etching is performed on the etching area so that the thickness of the second photoresist layer below the etching area reaches the recommended thickness.

[0165] In summary, when generating the second bump, the thickness of the second photoresist layer is required to be maintained within a certain range and not too thick. When the height difference between the first bump and the second bump is less than the critical height difference, it is easy to cause, so the etching area is ion-beam-etched to ensure that the thickness of the second photoresist layer is not too thick, thereby ensuring the quality of the second bump.

[0166] In the following examples, Figure 6 In the embodiment shown, ion beam etching is required for the etched area, but ion beam etching is prone to over-etching, resulting in a thinner thickness of the second photoresist layer, which affects the electroplating quality of the second bump. Therefore, the embodiment of the present application discloses a wafer-level packaging method for multi-structure bumps. Figure 8 , the method comprising:

[0167] Step S801: setting an etching direction according to the direction of the shortest directed line segment from the actual boundary line to the boundary of the etching area, wherein the etching direction forms a preset angle with the vertical downward direction.

[0168] Get the shortest directed line segment from the actual boundary line to the boundary of the etching area, wherein the shortest directed line segment is parallel to the horizontal plane, the intersection of the shortest directed line segment on the actual boundary line is the first intersection, and the intersection on the boundary of the etching area is the second intersection. Draw a vertical straight line vertically downward through the first intersection. The plane where the vertical straight line and the shortest directed line segment are located is the target plane. Rotate the shortest directed line segment downward in the target plane with the first intersection as the origin, and the rotation angle is the complementary angle of the preset angle to obtain the etching direction.

[0169] The etching direction can be split into a component along the direction of the shortest directed line segment from the actual boundary line to the boundary of the etching area and a component along the vertical downward direction.

[0170] Step S802: matching ion energy and etching time according to etching direction and etching depth.

[0171] Ion energy refers to the kinetic energy of the ions used in ion beam etching when they are ejected.

[0172] Etching time refers to the time required to etch the thickness of the etched area to the recommended thickness by ion beam etching.

[0173] In an optional implementation, the ion energy is set to a preset value. The unit etching amount of the ion beam etching is calculated according to the ion energy, and the unit etching amount is used to represent the etching depth of the ion beam etching per unit time. The etching time is obtained according to the unit etching amount and the etching depth.

[0174] In another optional implementation, the etching time is set to a preset value, the unit etching amount is calculated according to the etching time and the etching depth, and the ion energy is obtained according to the unit etching amount.

[0175] Step S803: performing ion beam etching on the etching area with etching direction, ion energy and etching time as parameters. The etching sequence of the ion beam etching is from close to the actual boundary line to the boundary of the etching area.

[0176] For example, please refer to Figure 7 When etching the etching area, the ion beam moves from a position close to the actual boundary line until it reaches the boundary of the etching area.

[0177] Furthermore, since the etching direction is at a preset angle to the vertical downward direction, and the etching sequence starts from near the actual boundary line and ends at the boundary of the etching area, even if over-etching occurs during the etching process, the thickness of the second photoresist layer near the pattern of the second bump will not be too thin, thereby ensuring the quality of the second bump obtained by electroplating.

[0178] In summary, by controlling the etching direction and etching sequence of ion beam etching, the thickness of the second photoresist layer at the actual boundary line is controlled within a certain range. Even if over-etching occurs in ion beam etching, it will not have a significant impact on the above thickness.

[0179] In the following embodiments, when the etching area is ion-beam-etched, the thickness of the second photoresist layer in the etching area can also be monitored in real time to avoid the thickness of the second etching area being too thick. Therefore, the embodiment of the present application discloses a wafer-level packaging method for multi-structure bumps. Fig. 9 , the method comprising:

[0180] Step S901: after the ion beam etching is completed, the etching thickness of the second photoresist layer at each location of the actual boundary line is counted.

[0181] The etching thickness refers to the thickness of the second photoresist layer after ion beam etching.

[0182] Optionally, the surface of the second photoresist layer at each location of the actual boundary line is scanned to obtain distance information from the scanning device to the second photoresist layer; based on the distance information and the height of the scanning device relative to the integrated circuit chip, the etching thickness of the second photoresist layer at the actual boundary line is obtained.

[0183] Step S902: Calculate the actual variance and minimum thickness of the etching thickness.

[0184] In some other implementations, the actual standard deviation of the etch thickness may also be calculated.

[0185] Step S903: When the minimum thickness is greater than the recommended thickness and the actual variance is greater than the preset variance, a corrected thickness is set according to the minimum thickness.

[0186] When the minimum thickness is less than the recommended thickness, it means that the thickness of the second photoresist layer is too thin, which will affect the subsequent electroplating of the second bump, so the integrated circuit wafer needs to be discarded.

[0187] When the minimum thickness is greater than the recommended thickness and the actual variance is not greater than the preset variance, it indicates that the thickness distribution of the second photoresist layer is uniform and the thickness of the second photoresist layer is close to the recommended thickness, and the step of forming a second bump on the integrated circuit wafer can be performed.

[0188] Optionally, a corrected thickness is obtained based on the difference between the minimum thickness and the recommended thickness.

[0189] Step S904: performing ion beam etching on the etching area according to the corrected thickness.

[0190] Exemplarily, the etched area is etched by an ion beam etching process, so that the thickness of the etched area is reduced by the correction thickness.

[0191] In summary, the etched area is corrected by ion beam etching, and the thickness of the second photoresist layer in the etched area is controlled to ensure the quality of the second bump.

[0192] Based on the same invention concept, please refer to Fig.10 The embodiment of the present application provides a wafer-level packaging system with multiple structure bumps, including:

[0193] An acquisition module 1001 is used to acquire a seed layer thickness, a preset thickness, a first distance influence value, a second distance influence value, an effective distance, a recommended thickness and a preset angle;

[0194] Memory 1002, used to store a program of any one of the above-mentioned wafer-level packaging methods for multi-structure bumps;

[0195] Processor 1003, the program in the memory can be loaded and executed by the processor to implement any of the above-mentioned wafer-level packaging methods for multi-structure bumps.

[0196] By adopting the above technical solution, after a TiCu layer is sputtered on a dielectric layer of an integrated circuit wafer, a first photoresist layer of a first thickness is first coated to form a first bump on the first photoresist layer; the first photoresist layer is removed; and a second photoresist layer of a second thickness is then coated to form a second bump on the second photoresist layer. The above solution can form bumps of different structures on an integrated circuit wafer.

[0197] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device and unit described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0198] An embodiment of the present application provides a computer-readable storage medium storing a computer program that can be loaded by a processor and execute a wafer-level packaging method for multiple structure bumps.

[0199] Computer storage media include, for example, USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks or optical disks, and other media that can store program codes.

[0200] Based on the same inventive concept, an embodiment of the present application provides an intelligent terminal, including a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and execute a wafer-level packaging method for multiple structure bumps.

[0201] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device and unit described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0202] The above are all preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. Any feature disclosed in this specification (including the abstract and drawings), unless otherwise stated, can be replaced by other equivalent or alternative features with similar purposes. That is, unless otherwise stated, each feature is only an example of a series of equivalent or similar features.

Claims

1. A wafer-level packaging method for multi-structure bumps, characterized in that: The method comprises: Sputtering a TiCu layer on a dielectric layer of an integrated circuit wafer, wherein the TiCu layer covers a surface of the integrated circuit wafer, wherein the TiCu layer includes a Ti layer and a Cu layer, wherein the sputtering of the TiCu layer on the dielectric layer of the integrated circuit wafer includes: sputtering the Ti layer on the dielectric layer, and sputtering the Cu layer on the Ti layer, wherein the TiCu layer is used as a seed layer; Coating a first photoresist layer of a first thickness on the TiCu layer, wherein the first thickness matches the height of the first bump; forming a pattern of the first bumps on the first photoresist layer; forming the first bump on the integrated circuit wafer; removing the first photoresist layer; sputtering to form a Cu layer on the TiCu layer; Coating a second photoresist layer with a second thickness on the TiCu layer, wherein the second thickness matches the height of the second bump, the thickness of the second photoresist layer is greater than the height of the first bump, the height of the second bump is greater than the height of the first bump, and the structure of the second bump is different from that of the first bump; forming a pattern of the second bumps on the second photoresist layer; When the height difference between the first convex point and the second convex point is less than a critical height difference, obtaining an actual boundary line of the figure of the second convex point; According to the actual boundary line and the preset effective distance, an etching area is formed, wherein the shortest distance from the boundary of the etching area to the actual boundary line is not less than the effective distance, and the etching area surrounds the pattern of the second convex point; Setting an etching depth according to a difference between an actual thickness of the second photoresist layer and a recommended thickness; According to the etching depth, performing ion beam etching on the etching area; forming the second bump on the integrated circuit wafer; removing the second photoresist layer and the TiCu layer to expose the first bump and the second bump; The integrated circuit wafer is reflowed to obtain a packaged integrated circuit wafer.

2. The wafer-level packaging method of multi-structure bumps according to claim 1, characterized in that: The method further comprises: Obtaining the seed layer thickness of the TiCu layer at various locations; Determine whether there is a target area where the seed layer thickness is less than a preset thickness; If yes, obtaining a first area distance between the target area and a projection area of ​​the second bump on the TiCu layer; When the first area distance is less than a preset first distance influence value, extracting an average thickness of the TiCu layer in the target area; According to the difference between the preset protection thickness and the average thickness, setting the sputtering thickness of the Cu layer; The Cu layer is sputtered to form the Cu layer on the target area according to the sputtering thickness.

3. The wafer-level packaging method of multi-structure bumps according to claim 2, characterized in that: The method further comprises: Detecting a second area distance between the target area and a projection area of ​​the first bump on the TiCu layer; When the distance of the second area is less than a preset second distance influence value, determining an influence part on the first convex point according to the distance from the target area to the first convex point; The affected portion on the first bump is subjected to sputtering treatment to form a conductive protective layer on the affected portion.

4. The wafer-level packaging method of multi-structure bumps according to claim 1, characterized in that: The step of performing ion beam etching on the etching area according to the etching depth comprises: According to the direction of the shortest directed line segment from the actual boundary line to the boundary of the etching area, an etching direction is set, wherein the etching direction forms a preset angle with the vertical downward direction; Matching ion energy and etching time according to the etching direction and the etching depth; The etching region is subjected to ion beam etching with the etching direction, the ion energy and the etching time as parameters. The etching sequence of the ion beam etching is from close to the actual boundary line to the boundary of the etching region.

5. The wafer-level packaging method of multi-structure bumps according to claim 1, characterized in that: The method further comprises: After the ion beam etching is completed, counting the etching thickness of the second photoresist layer at each location of the actual boundary line; Calculating the actual variance and minimum thickness of the etching thickness; When the minimum thickness is greater than the recommended thickness and the actual variance is greater than the preset variance, setting a corrected thickness according to the minimum thickness; The etching region is ion-beam etched according to the modified thickness.

6. A wafer-level packaging system with multiple structure bumps, characterized in that: The system comprises: An acquisition module, used to acquire a seed layer thickness, a preset thickness, a first distance influence value, a second distance influence value, an effective distance, a recommended thickness and a preset angle; A memory for storing a program of a wafer-level packaging method for multi-structure bumps according to any one of claims 1 to 5; The program in the memory can be loaded and executed by the processor to implement the wafer-level packaging method for multi-structure bumps as claimed in any one of claims 1 to 4.

7. An intelligent terminal, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program which can be loaded by the processor and executes any one of the methods of claims 1 to 5.

8. A computer-readable storage medium, characterized in that: A computer program is stored which can be loaded by a processor and execute the method according to any one of claims 1 to 5.

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