Semiconductor chips, semiconductor structures and semiconductor devices

Abstract

The present disclosure discloses a semiconductor chip, a semiconductor structure, and a semiconductor device. The semiconductor chip includes: a first identification transmission path extending through a substrate of the semiconductor chip in a direction perpendicular to the active surface of the semiconductor chip; a second identification transmission path extending through the substrate in a direction perpendicular to the active surface of the semiconductor chip and symmetrically distributed with the first identification transmission path about a central axis of the semiconductor chip, the central axis passing through the center of the semiconductor chip and parallel to the active surface; an identification decoding circuit coupled to the first identification transmission path or the second identification transmission path, the identification decoding circuit being configured to receive an identification signal and decode the identification signal to generate a data selection signal; wherein the semiconductor chip outputs data signals transmitted in the multiple data transmission paths to corresponding internal receiving circuits according to the data selection signal.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor chip, a semiconductor structure, and a semiconductor device. Background Art

[0002] As people's demand for electronic products develops towards miniaturization and multifunctionality, packaging technology is also developing towards high density and high integration. For example, at least two memory chips (dies) are three-dimensionally stacked and packaged in a direction perpendicular to the horizontal plane.

[0003] However, there are still many technical problems that need to be solved in the three-dimensional stacking structure, such as how to ensure that data is accurately transmitted to each chip in the three-dimensional stacking structure. Summary of the Invention

[0004] According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor chip, including:

[0005] A first identification transmission path passes through the substrate of the semiconductor chip in a direction perpendicular to the active surface of the semiconductor chip;

[0006] a second identification transmission path, penetrating the substrate in a direction perpendicular to the active surface of the semiconductor chip and symmetrically distributed with the first identification transmission path based on a central axis of the semiconductor chip, wherein the central axis passes through the center of the semiconductor chip and is parallel to the active surface;

[0007] an identification decoding circuit coupled to the first identification transmission path or the second identification transmission path, the identification decoding circuit being configured to receive an identification signal and decode the identification signal to generate a data selection signal;

[0008] The semiconductor chip outputs the data signals transmitted in the plurality of data transmission paths to the corresponding internal receiving circuits according to the data selection signal.

[0009] In some embodiments, the internal receiving circuit includes: a first data receiving circuit and a second data receiving circuit; wherein the first data receiving circuit is coupled to a first data selection circuit; and the second data receiving circuit is coupled to a second data selection circuit;

[0010] The plurality of data transmission paths include:

[0011] a first data transmission path, penetrating the substrate in a direction perpendicular to the active surface of the semiconductor chip; wherein the first data transmission path is configured to transmit a first data signal;

[0012] a second data transmission path extending through the substrate in a direction perpendicular to the active surface of the semiconductor chip and symmetrically distributed with the first data transmission path about the central axis; wherein the second data transmission path is configured to transmit a second data signal; the second data signal is different from the first data signal;

[0013] The first data selection circuit is coupled to the identification decoding circuit, the first data transmission path, and the second data transmission path, respectively; wherein the first data selection circuit is configured to output one of the first data signal or the second data signal to the first data receiving circuit according to the data selection signal;

[0014] The second data selection circuit is coupled to the identification decoding circuit, the first data transmission path and the second data transmission path respectively; wherein the second data selection circuit is configured to output the other of the first data signal or the second data signal to the second data receiving circuit according to the data selection signal.

[0015] In some embodiments, the first identification transmission path is configured to transmit a first identification signal;

[0016] The second identification transmission path is configured to transmit a second identification signal; wherein the second identification signal is different from the first identification signal.

[0017] In some embodiments, the first identification transmission path includes: a first connection pad located on the inactive surface of the semiconductor chip, a first path located in the substrate, and a first interconnection structure located on the active surface of the semiconductor chip; wherein the first connection pad, the first path, and the first interconnection structure are connected in sequence;

[0018] The second identification transmission path includes: a second connection pad located on the inactive surface of the semiconductor chip, a second path located in the substrate, and a second interconnection structure located on the active surface of the semiconductor chip; wherein the second connection pad, the second path, and the second interconnection structure are connected in sequence.

[0019] In some embodiments, the identification decoding circuit is coupled to the first interconnect structure or the second interconnect structure.

[0020] According to a second aspect of an embodiment of the present disclosure, there is provided a semiconductor structure, including:

[0021] Logic chips;

[0022] stacked structure,

[0023] The stack on the logic chip comprises: semiconductor chips No. 1 to No. 2N stacked in sequence; wherein the semiconductor chips No. 1 to No. 2N are identical memory chips; the inactive surface of the No. 1 semiconductor chip is bonded to the logic chip, and the active surface of the No. 2i semiconductor chip is bonded to the active surface of the No. 2i-1 semiconductor chip; N is a positive integer, and i is a positive integer less than or equal to N;

[0024] The semiconductor chip includes: a first identification transmission path, a second identification transmission path, and an identification decoding circuit; the first identification transmission path and the second identification transmission path penetrate the substrate of the semiconductor chip in a direction perpendicular to the active surface of the semiconductor chip, and are symmetrically distributed based on a central axis of the semiconductor chip, wherein the central axis passes through the center of the semiconductor chip and is parallel to the active surface; the identification decoding circuit is coupled to the first identification transmission path or the second identification transmission path, and the identification decoding circuit is configured to receive an identification signal, wherein the identification signal indicates that the semiconductor chip is the 2ith semiconductor chip or the 2i-1th semiconductor chip in the stacked structure;

[0025] Among them, the first identification transmission path of the 2i-1th semiconductor chip and the second identification transmission path of the 2i-th semiconductor chip are connected in sequence to form a first identification transmission channel; the second identification transmission path of the 2i-1th semiconductor chip and the first identification transmission path of the 2i-th semiconductor chip are connected in sequence to form a second identification transmission channel.

[0026] In some embodiments, the logic chip is configured to:

[0027] Outputting the first identification signal to the identification decoding circuit of the 2i-1th semiconductor chip through one of the first identification transmission channel and the second identification transmission channel;

[0028] A second identification signal is output to the identification decoding circuit of the 2i-th semiconductor chip through the other of the first identification transmission channel and the second identification transmission channel; wherein the second identification signal is different from the first identification signal.

[0029] In some embodiments, the identification decoding circuit is configured to: decode the first identification signal to generate a first data selection signal, or decode the second identification signal to generate a second data selection signal;

[0030] The second data selection signal is different from the first data selection signal.

[0031] In some embodiments, the semiconductor chip further comprises: a first data receiving circuit, a second data receiving circuit, a first data transmission path, a second data transmission path, a first data selection circuit, and a second data selection circuit; wherein the first data transmission path and the second data transmission path penetrate the substrate in a direction perpendicular to the active surface of the semiconductor chip and are symmetrically distributed about the central axis;

[0032] The first data selection circuit is coupled to the identification decoding circuit, the first data transmission path, the second data transmission path and the first data receiving circuit respectively;

[0033] The second data selection circuit is coupled to the identification decoding circuit, the first data transmission path, the second data transmission path and the second data receiving circuit respectively;

[0034] Among them, the first data transmission path of the 2i-1th semiconductor chip and the second data transmission path of the 2ith semiconductor chip are connected in sequence to form a first data transmission channel; the second data transmission path of the 2i-1th semiconductor chip and the first data transmission path of the 2ith semiconductor chip are connected in sequence to form a second data transmission channel; the first data transmission channel is configured to transmit a first data signal; the second data transmission channel is configured to transmit a second data signal; the second data signal is different from the first data signal.

[0035] In some embodiments, the first data selection circuit of the 2i-1th semiconductor chip is configured to: output one of the first data signal and the second data signal to the first data receiving circuit of the 2i-1th semiconductor chip according to the first data selection signal;

[0036] The second data selection circuit of the 2i-1th semiconductor chip is configured to: output the other of the first data signal and the second data signal to the second data receiving circuit of the 2i-1th semiconductor chip according to the first data selection signal;

[0037] The first data selection circuit of the 2i-th semiconductor chip is configured to: output one of the first data signal and the second data signal to the first data receiving circuit of the 2i-th semiconductor chip according to the second data selection signal;

[0038] The second data selection circuit of the 2i-th semiconductor chip is configured to output the other of the first data signal and the second data signal to the second data receiving circuit of the 2i-th semiconductor chip according to the second data selection signal.

[0039] In some embodiments, the central axes of any two adjacent semiconductor chips among the 1st to 2Nth semiconductor chips are aligned; wherein, the first identification transmission path of one of the two adjacent semiconductor chips is aligned with the second identification transmission path of the other of the two adjacent semiconductor chips.

[0040] In some embodiments, the inactive surface of the 2jth semiconductor chip is bonded to the inactive surface of the 2j+1th semiconductor chip, where j is an integer greater than or equal to 1, and 2j+1 is less than 2N.

[0041] In some embodiments, the first identification transmission path includes: a first connection pad located on the inactive surface of the semiconductor chip, a first path located in the substrate, and a first interconnection structure located on the active surface of the semiconductor chip; wherein the first connection pad, the first path, and the first interconnection structure are connected in sequence;

[0042] The second identification transmission path includes: a second connection pad located on the non-active surface of the semiconductor chip, a second path located in the substrate, and a second interconnection structure located on the active surface of the semiconductor chip; wherein the second connection pad, the second path, and the second interconnection structure are connected in sequence

[0043] According to a third aspect of the embodiments of the present disclosure, there is provided a semiconductor device, including:

[0044] substrate;

[0045] The semiconductor chip as described in any embodiment of the first aspect of the embodiments of the present disclosure is located on the substrate, and the semiconductor chip is bonded to the substrate; or the semiconductor structure as described in any embodiment of the second aspect of the embodiments of the present disclosure is located on the substrate, and the semiconductor structure is bonded to the substrate.

[0046] In some embodiments, the semiconductor device includes: a high bandwidth memory.

[0047] In the embodiment of the present disclosure, by setting an identification decoding circuit to be coupled with the first identification transmission path or the second identification transmission path, the identification decoding circuit can generate a data selection signal based on the identification signal transmitted in the first identification transmission path or the second identification transmission path, and the internal receiving circuit can receive the data signal transmitted in one of the multiple data transmission paths based on the data selection signal, thereby ensuring that the data is accurately transmitted to the corresponding internal receiving circuit in the semiconductor chip.

[0048] Moreover, the first identification transmission path and the second identification transmission path are symmetrically distributed based on the central axis of the semiconductor chip. When multiple semiconductor chips are stacked to form a three-dimensional stacking structure, the identification signals transmitted in the first identification transmission path and the second identification transmission path can generate odd flag bits / even flag bits in each semiconductor chip, which is beneficial to reduce the complexity of assigning stacking identification, and at the same time can ensure that data is accurately transmitted to each chip in the three-dimensional stacking structure through the same transmission path. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 is a schematic diagram showing a three-dimensional stacking structure according to an exemplary embodiment;

[0050] Figure 2 is a cross-sectional view of a semiconductor chip according to an embodiment of the present disclosure;

[0051] Figure 3 is a top view of a semiconductor chip according to an embodiment of the present disclosure;

[0052] Figure 4 is a schematic diagram of a semiconductor chip according to an embodiment of the present disclosure;

[0053] Figure 5 is a cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure;

[0054] Figure 6a and Figure 6b FIG. 1 is a top view of a semiconductor chip according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings illustrate exemplary implementations of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0056] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0057] It will be understood that the meanings of “on,” “over,” and “over” throughout this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0058] In the embodiments of the present disclosure, the terms "first," "second," "third," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0059] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0060] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0061] Figure 1 FIG is a schematic diagram showing a three-dimensional stacking structure according to an exemplary embodiment. Figure 1 As shown, the stacked structure includes multiple chips stacked sequentially on a logic chip, for example, chip 0, chip 1, chip 2, and chip 3. Here, four chips are only an example to convey the present disclosure to those skilled in the art. The number of chips in the stacked structure is not limited to four, and can also be 8, 16, or more, and the present disclosure has no special limitations on this.

[0062] By assigning stacking identifiers to multiple chips (such as Figure 1 As shown in , an odd / even flag can be generated in each chip, and the odd / even flag is used as a circuit direction switch to accurately transmit data to each chip. However, this method of assigning stacking identifiers is relatively complicated.

[0063] In view of this, embodiments of the present disclosure provide a semiconductor chip, a semiconductor structure, and a semiconductor device.

[0064] Figure 2 is a cross-sectional schematic diagram of a semiconductor chip 100 according to an embodiment of the present disclosure. Figure 3 is a top view of a semiconductor chip 100 according to an embodiment of the present disclosure. Figure 4This is a schematic diagram of a semiconductor chip 100 according to an embodiment of the present disclosure. Figure 2 、 Figure 3 and Figure 4 The semiconductor chip 100 provided in the embodiment of the present disclosure is described in detail.

[0065] Reference Figures 2 to 4 As shown, the semiconductor chip 100 includes a first identification transmission path 111, a second identification transmission path 112 and an identification decoding circuit 120; the first identification transmission path 111 and the second identification transmission path 112 pass through the substrate in a direction perpendicular to the active surface S1 of the semiconductor chip 100, and are symmetrically distributed based on the central axis L of the semiconductor chip 100; the identification decoding circuit 120 is coupled to the first identification transmission path 111 or the second identification transmission path 112, and the identification decoding circuit 120 is configured to receive an identification signal and decode the identification signal to generate a data selection signal; wherein, the semiconductor chip 100 outputs the data signals transmitted in the multiple data transmission paths to the corresponding internal receiving circuits according to the data selection signal. It should be noted that the central axis is an axis passing through the center of the semiconductor chip and parallel to the active surface S1 (or non-active surface S2), which is represented by a dotted line L in this disclosure, as shown Figure 2 or Figure 3 shown.

[0066] The semiconductor chip 100 includes a front side on which a peripheral circuit and a memory cell array are provided and a back side opposite to the front side. The front side of the semiconductor chip 100 is referred to as an active side S1, and the back side of the semiconductor chip 100 is referred to as an inactive side S2. Figure 2 The semiconductor chip 100 may be a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a NOR flash memory chip, or a NAND flash memory chip. The embodiment of the present disclosure has no particular limitation on the type of the semiconductor chip 100.

[0067] The first identification transmission path 111 and the second identification transmission path 112 are used to transmit identification signals. For example, the first identification transmission path 111 is configured to transmit a first identification signal A1, and the second identification transmission path 112 is configured to transmit a second identification signal A2, which is different from the first identification signal A1.

[0068] It can be understood that when multiple semiconductor chips 100 are three-dimensionally stacked and packaged in a direction perpendicular to the horizontal plane, the identification signals transmitted in the first identification transmission path 111 and the second identification transmission path 112 can generate odd flag bits / even flag bits in each semiconductor chip 100. The odd flag bits or even flag bits can be used as switching markers for the transmission path between data and circuits to ensure that data is accurately transmitted to the corresponding internal receiving circuit in each chip.

[0069] In a specific embodiment, the identification signal can be represented by a binary signal "0" or "1." For example, the identification signal "0" is configured to indicate that the semiconductor chip 100 is an even-numbered chip in the stack structure, and the identification signal "1" is configured to indicate that the semiconductor chip 100 is an odd-numbered chip in the stack structure. For another example, the identification signal "0" is configured to indicate that the semiconductor chip 100 is an odd-numbered chip in the stack structure, and the identification signal "1" is configured to indicate that the semiconductor chip 100 is an even-numbered chip in the stack structure.

[0070] The identification decoding circuit is used to decode the identification signal and generate a data selection signal. For example, the identification decoding circuit 120 is coupled to the first identification transmission path 111. The identification decoding circuit 120 is configured to receive the first identification signal A1 transmitted in the first identification transmission path 111 and decode the first identification signal A1 to generate a data selection signal. For another example, the identification decoding circuit 120 is coupled to the second identification transmission path 112. The identification decoding circuit 120 is configured to receive the second identification signal A2 transmitted in the second identification transmission path 112 and decode the second identification signal A2 to generate a data selection signal.

[0071] It should be noted that because the second identification signal A2 is different from the first identification signal A1, the data selection signal generated by decoding the first identification signal and the data selection signal generated by decoding the second identification signal in this example are different. In other embodiments, when the second identification signal and the first identification signal are the same, the data selection signal generated by decoding the first identification signal and the data selection signal generated by decoding the second identification signal can be the same.

[0072] Semiconductor chip 100 includes multiple data transmission paths and multiple internal receiving circuits. Each internal receiving circuit is coupled to the multiple data transmission paths. Each internal receiving circuit can receive a data signal transmitted from one of the multiple data transmission paths based on a data selection signal. The number of data transmission paths can be two or more, and the number of internal receiving circuits can be two or more, without any particular limitation in the present disclosure.

[0073] In the embodiment of the present disclosure, by setting an identification decoding circuit to be coupled with the first identification transmission path or the second identification transmission path, the identification decoding circuit can generate a data selection signal based on the identification signal transmitted in the first identification transmission path or the second identification transmission path, and the internal receiving circuit can receive the data signal transmitted in one of the multiple data transmission paths based on the data selection signal, thereby ensuring that the data is accurately transmitted to the corresponding internal receiving circuit in the semiconductor chip.

[0074] Moreover, the first identification transmission path and the second identification transmission path are symmetrically distributed based on the central axis of the semiconductor chip. When multiple semiconductor chips are stacked to form a three-dimensional stacking structure, the identification signals transmitted in the first identification transmission path and the second identification transmission path can generate odd flag bits / even flag bits in each semiconductor chip, which is beneficial to reduce the complexity of assigning stacking identification, and at the same time can ensure that data is accurately transmitted to each chip in the three-dimensional stacking structure through the same transmission path.

[0075] In some embodiments, combined Figure 2 and Figure 4 As shown, the internal receiving circuit includes: a first data receiving circuit 131 and a second data receiving circuit 132; wherein the first data receiving circuit 131 is coupled to the first data selecting circuit 141; the second data receiving circuit 132 is coupled to the second data selecting circuit 142;

[0076] Multiple data transmission paths include:

[0077] A first data transmission path 151 passes through the substrate in a direction perpendicular to the active surface S1 of the semiconductor chip 100 ; wherein the first data transmission path 151 is configured to transmit a first data signal B1 ;

[0078] The second data transmission path 152 extends through the substrate in a direction perpendicular to the active surface S1 of the semiconductor chip 100 and is symmetrically arranged with the first data transmission path 151 about the central axis L. The second data transmission path 152 is configured to transmit a second data signal B2, which is different from the first data signal B1.

[0079] The first data selection circuit 141 is coupled to the identification decoding circuit 120, the first data transmission path 151, and the second data transmission path 152, respectively. The first data selection circuit 141 is configured to output one of the first data signal B1 or the second data signal B2 to the first data receiving circuit 131 according to a data selection signal.

[0080] The second data selection circuit 142 is coupled to the identification decoding circuit 120, the first data transmission path 151 and the second data transmission path 152 respectively; wherein the second data selection circuit 142 is configured to output the other of the first data signal B1 or the second data signal B2 to the second data receiving circuit 132 according to the data selection signal.

[0081] The first data selection circuit 141 and the second data selection circuit 142 can output corresponding data signals based on the data selection signal. Taking the first data selection circuit 141 as an example, the first data selection circuit 141 includes a control terminal, multiple input terminals, and an output terminal. The control terminal of the first data selection circuit 141 is configured to receive the data selection signal. The multiple input terminals of the first data selection circuit 141 are respectively coupled to multiple data transmission paths. The output terminal of the first data selection circuit 141 is coupled to the first data receiving circuit 131. Under the control of the data selection signal received at the control terminal, the first data selection circuit 141 can output the first data signal B1 (or the second data signal B2) to the first data receiving circuit 131.

[0082] Similarly, the second data selection circuit 142 includes a control end, multiple input ends and an output end. The control end of the second data selection circuit 142 is configured to receive a data selection signal. The multiple input ends of the second data selection circuit 142 are respectively coupled to multiple data transmission paths. The output end of the second data selection circuit 142 is coupled to the second data receiving circuit 132. The second data selection circuit 142 can output the second data signal B2 (or the first data signal B1) to the second data receiving circuit 132 under the control of the data selection signal received at the control end.

[0083] In some embodiments, the first data signal B1 and the second data signal B2 may be different row address signals (RA). For example, the row address signal RA1 and the row address signal RA2, and the binary values ​​corresponding to the row address signal RA1 and the row address signal RA2 may be the same or different, and this disclosure is not particularly limited in this regard. In other embodiments, the first data signal B1 and the second data signal B2 may also be different types of signals. The first data signal B1 and the second data signal B2 are respectively transmitted to different data receiving circuits within the same semiconductor chip.

[0084] It should be noted that in this example, the first data selection circuit 141 and the second data selection circuit 142 are different data selection circuits. The first data selection circuit 141 and the second data selection circuit 142 can output different types of data signals based on the same data selection signal. For example, the first data selection circuit 141 outputs the row address signal RA1 to the first data receiving circuit 131, and the second data selection circuit 142 outputs the row address signal RA2 to the second data receiving circuit 132.

[0085] The first data transmission path 151 and the second data transmission path 152 may be through silicon via (TSV) structures within the semiconductor chip 100 .

[0086] In the embodiment of the present disclosure, by setting up a first data selection circuit and a second data selection circuit, the first data selection circuit can transmit the first data signal (or the second data signal) to the first data receiving circuit according to the data selection signal, and the second data selection circuit can transmit the second data signal (or the first data signal) to the second data receiving circuit according to the data selection signal, thereby ensuring that the data is accurately transmitted to each data receiving circuit in the semiconductor chip.

[0087] In some embodiments, reference Figure 2 As shown, the first identification transmission path 111 includes: a first connection pad 161 located on the inactive surface S2 of the semiconductor chip 100, a first path 171 located in the substrate, and a first interconnection structure 181 located on the active surface S1 of the semiconductor chip 100; wherein the first connection pad 161, the first path 171 and the first interconnection structure 181 are connected in sequence; the second identification transmission path 112 includes: a second connection pad 162 located on the inactive surface S2 of the semiconductor chip 100, a second path 172 located in the substrate, and a second interconnection structure 182 located on the active surface S1 of the semiconductor chip 100; wherein the second connection pad 162, the second path 172 and the second interconnection structure 182 are connected in sequence.

[0088] In a specific embodiment, the first connection pad 161 and the second connection pad 162 can be microbumps (uBumps) located on the non-active surface S2 of the semiconductor chip 100, the first via 171 and the second via 172 can be TSV structures, and the first interconnection structure 181 and the second interconnection structure 182 can be routing layers located on the active surface S1 of the semiconductor chip 100.

[0089] It should be noted that Figure 2The number of microbumps, the number of through silicon via structures, and the number of wirings shown in the figure are exemplary and are used to convey the present disclosure to those skilled in the art. In actual applications, the number of microbumps, the number of through silicon via structures, and the number of wirings in a semiconductor chip are not limited thereto.

[0090] In some embodiments, the first connection pads 161 and the second connection pads 162 are symmetrically distributed around the central axis L, the first vias 171 and the second vias 172 are symmetrically distributed around the central axis L, and the first interconnection structures 181 and the second interconnection structures 182 are symmetrically distributed around the central axis L.

[0091] In some embodiments, the identification decoding circuit 120 is coupled to the first interconnect structure 181 or the second interconnect structure 182 .

[0092] The materials of first connection pad 161, second connection pad 162, first via 171, second via 172, first interconnect structure 181, and second interconnect structure 182 include conductive materials, such as any one or a combination of polysilicon, doped polysilicon, tantalum, titanium, tungsten, copper, titanium nitride, tantalum nitride, or tungsten nitride. The materials of any two of first connection pad 161, second connection pad 162, first via 171, second via 172, first interconnect structure 181, and second interconnect structure 182 can be the same or different.

[0093] In some embodiments, the first data transmission path 151 includes: a third connection pad located on the inactive surface of the semiconductor chip, a third via located within the substrate, and a third interconnect structure located on the active surface of the semiconductor chip; wherein the third connection pad, the third via, and the third interconnect structure are sequentially connected; and the second data transmission path 152 includes: a fourth connection pad located on the inactive surface of the semiconductor chip, a fourth via located within the substrate, and a fourth interconnect structure located on the active surface of the semiconductor chip; wherein the fourth connection pad, the fourth via, and the fourth interconnect structure are sequentially connected. The structures of the first data transmission path 151 and the second data transmission path 152 can be referred to as the first identification transmission path 111 and the second identification transmission path 112, and will not be further described here.

[0094] In some embodiments, reference Figure 3 As shown, the semiconductor chip 100 further includes a first redundant path 191 and a second redundant path 192, which are symmetrically distributed based on the central axis L of the semiconductor chip. The number of the first redundant path 191 and the second redundant path 192 can be one or more. Figure 3 Three first redundant paths 191 and three second redundant paths 192 are shown.

[0095] Based on the above-mentioned semiconductor chip, an embodiment of the present disclosure further provides a semiconductor structure.

[0096] Figure 5 is a schematic diagram of a semiconductor structure 300 according to an embodiment of the present disclosure. Figure 6a and Figure 6b This is a top view of a semiconductor chip according to an embodiment of the present disclosure. Figure 5 、 Figure 6a and Figure 6b The semiconductor structure 300 provided in the embodiment of the present disclosure is described in detail.

[0097] Reference Figure 5 As shown, the semiconductor structure 300 includes: a logic chip 200 and a stacked structure stacked on the logic chip; the stacked structure includes: the first to the 2Nth semiconductor chips stacked in sequence; wherein the first to the 2Nth semiconductor chips are identical memory chips; the inactive surface of the first semiconductor chip is bonded to the logic chip, and the active surface of the 2ith semiconductor chip is bonded to the active surface of the 2i-1th semiconductor chip; N is a positive integer, and i is a positive integer less than or equal to N;

[0098] The semiconductor chip includes: a first identification transmission path, a second identification transmission path, and an identification decoding circuit; the first identification transmission path and the second identification transmission path penetrate the substrate of the semiconductor chip in a direction perpendicular to the active surface of the semiconductor chip and are symmetrically distributed about the central axis of the semiconductor chip; the identification decoding circuit is coupled to the first identification transmission path or the second identification transmission path, and the identification decoding circuit is configured to receive an identification signal indicating that the semiconductor chip is the 2ith semiconductor chip or the 2i-1th semiconductor chip in the stacked structure;

[0099] Among them, the first identification transmission path of the 2i-1th semiconductor chip and the second identification transmission path of the 2i-th semiconductor chip are connected in sequence to form a first identification transmission channel 301; the second identification transmission path of the 2i-1th semiconductor chip and the first identification transmission path of the 2i-th semiconductor chip are connected in sequence to form a second identification transmission channel 302.

[0100] The semiconductor structure 300 may be a memory including a logic chip and a memory chip, for example, a high bandwidth memory (HBM). The semiconductor structure 300 may also be other memories known in the art.

[0101] The logic chip 200 may be one or more processors that communicate with the memory chip to access data from the memory chip or store data in the memory chip. The logic chip 200 may include a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a central processing unit (CPU), or other known electronic circuits used as processors.

[0102] The stack structure includes a plurality of semiconductor chips stacked in sequence, for example, Figure 5 Four semiconductor chips are shown, which are respectively marked as the first semiconductor chip 100a, the second semiconductor chip 100b, the third semiconductor chip 100c and the fourth semiconductor chip 100d. The first semiconductor chip 100a, the second semiconductor chip 100b, the third semiconductor chip 100c and the fourth semiconductor chip 100d are the same memory chips. Here, the first to fourth semiconductor chips can be referred to as Figure 2 It should be noted that the number of semiconductor chips in the stacked structure is not limited to Figure 5 The 4 shown in , can also be 8, 16 or even more.

[0103] The first semiconductor chip 100a includes a first identification transmission path 111a, a second identification transmission path 112a, and an identification decoding circuit 120a; the second semiconductor chip 100b includes a first identification transmission path 111b, a second identification transmission path 112b, and an identification decoding circuit 120b; the third semiconductor chip 100c includes a first identification transmission path 111c, a second identification transmission path 112c, and an identification decoding circuit 120c; and the fourth semiconductor chip 100d includes a first identification transmission path 111d, a second identification transmission path 112d, and an identification decoding circuit 120d. Here, the first identification transmission paths 111a to 111d, the second identification transmission paths 112a to 112d, and the identification decoding circuits 120a to 120d can be referred to as Figure 2 The first identification transmission path 111, the second identification transmission path 112, and the identification decoding circuit 120 shown in FIG are explained and will not be repeated here.

[0104] Reference Figure 5 As shown, the active surface of the first semiconductor chip 100a and the active surface of the second semiconductor chip 100b are joined to form the first semiconductor chip group 300a; the active surface of the third semiconductor chip 100c and the active surface of the fourth semiconductor chip 100d are joined to form the second semiconductor chip group 300b; 2N semiconductor chips can constitute N semiconductor chip groups.

[0105] It should be noted that the number of semiconductor chip groups in the semiconductor structure can be one or more. The two semiconductor chips in the semiconductor chip group are bonded face to face (active surface to active surface); for example: the first semiconductor chip 100a and the second semiconductor chip 100b, and the third semiconductor chip 100c and the fourth semiconductor chip 100d can be bonded by hybrid bonding, for example, melt bonding, diffusion bonding or eutectic bonding, etc.; two adjacent semiconductor chip groups are bonded back to back (non-active surface to non-active surface); for example: the second semiconductor chip 100b in the first semiconductor chip group 300a and the third semiconductor chip 100c in the second semiconductor chip group 300b can be connected by a microbump (uBump). In other examples, the two semiconductor chips in the semiconductor chip group can also be bonded by other bonding methods known in the art. The following will be combined with Figure 6a and Figure 6b The two semiconductor chips in the first semiconductor chip group will be described.

[0106] Figure 6a 1 and 10 are top views of the first semiconductor chip 100a and the second semiconductor chip 100b, respectively. Figure 6a As shown, the first semiconductor chip 100a includes an upper half located on one side of the central axis L and a lower half located on the other side of the central axis L, and the second semiconductor chip 100b includes an upper half located on one side of the central axis L and a lower half located on the other side of the central axis L. Here, the semiconductor chip can be divided into two equal parts based on the central axis L. The part where the first identification transmission path 111 is located can be defined as the upper half, and the part where the second identification transmission path 112 is located can be defined as the lower half.

[0107] In other embodiments, the semiconductor chip can be divided into two equal parts based on the central axis P. The part where the first identification transmission path 111 is located can be defined as the left half, and the part where the second identification transmission path 112 is located can be defined as the right half. Figure 6b As shown. Those skilled in the art can select according to actual needs. Here, the central axis P passes through the center of the semiconductor chip and is parallel to the active surface, and the central axis P is perpendicular to and intersects the central axis L.

[0108] After the active surface of the first semiconductor chip 100a and the active surface of the second semiconductor chip 100b are bonded, the lower half of the second semiconductor chip 100b is located above the upper half of the first semiconductor chip 100a, and the upper half of the second semiconductor chip 100b is located above the lower half of the first semiconductor chip 100a. Figure 5That is, after the active surface of the first semiconductor chip 100a and the active surface of the second semiconductor chip 100b are bonded, the identification decoding circuit 120a of the first semiconductor chip 100a and the identification decoding circuit 120b of the second semiconductor chip 100b are respectively located on either side of a symmetry plane M of the semiconductor structure 300, and the same data receiving circuit (for example, 131a and 131b) in each semiconductor chip is respectively located on either side of the symmetry plane M. The symmetry plane M is perpendicular to the active surface S1 (or the inactive surface S2), and the central axis L is located in the symmetry plane M.

[0109] When the semiconductor structure 300 includes a first semiconductor chip group, the first identification transmission channel 301 includes the first identification transmission path 111a of the first semiconductor chip 100a and the second identification transmission path 112b of the second semiconductor chip 100b; the second identification transmission channel 302 includes the second identification transmission path 112a of the first semiconductor chip 100a and the first identification transmission path 111b of the second semiconductor chip 100b. Furthermore, when the semiconductor structure 300 includes a second semiconductor chip group, the first identification transmission channel 301 also includes the first identification transmission path 111c of the third semiconductor chip 100c and the second identification transmission path 112d of the fourth semiconductor chip 100d; the second identification transmission channel 302 also includes the second identification transmission path 112c of the third semiconductor chip 100c and the first identification transmission path 111d of the fourth semiconductor chip 100d.

[0110] Here, the identification transmission paths located on one side of the symmetry plane M and connected in sequence constitute the first identification transmission channel 301, and the identification transmission paths located on the other side of the symmetry plane M and connected in sequence constitute the second identification transmission channel 302; the first identification transmission channel 301 and the second identification transmission channel 302 are symmetrically distributed based on the central axis L.

[0111] The first identification transmission channel 301 and the second identification transmission channel 302 are used to transmit identification signals. For example, the first identification transmission channel 301 is configured to transmit a first identification signal, and the second identification transmission channel 302 is configured to transmit a second identification signal, where the first identification signal and the second identification signal are different. The first identification signal can be represented by a binary signal "0", and the second identification signal can be represented by a binary signal "1".

[0112] In some embodiments, when the identification decoding circuit is coupled to the first identification transmission channel, the identification decoding circuit 120a of the first semiconductor chip 100a can assign an odd flag bit to the first semiconductor chip 100a according to the first identification signal "0" transmitted in the first identification transmission channel 301, and the identification decoding circuit 120b of the second semiconductor chip 100b can assign an even flag bit to the second semiconductor chip 100b according to the second identification signal "1" transmitted in the second identification transmission channel 302; further, the identification decoding circuit 120c of the third semiconductor chip 100c can assign an odd flag bit to the third semiconductor chip 100c according to the first identification signal "0" transmitted in the first identification transmission channel 301, and the identification decoding circuit 120d of the fourth semiconductor chip 100d can assign an even flag bit to the fourth semiconductor chip 100d according to the second identification signal "1" transmitted in the second identification transmission channel 302.

[0113] In other embodiments, when the identification decoding circuit is coupled to the second identification transmission channel, the identification decoding circuit 120a of the first semiconductor chip 100a can assign an odd flag bit to the first semiconductor chip 100a according to the second identification signal "1" transmitted in the second identification transmission channel 302, and the identification decoding circuit 120b of the second semiconductor chip 100b can assign an even flag bit to the second semiconductor chip 100b according to the first identification signal "0" transmitted in the first identification transmission channel 301; further, the identification decoding circuit 120c of the third semiconductor chip 100c can assign an odd flag bit to the third semiconductor chip 100c according to the second identification signal "1" transmitted in the second identification transmission channel 302, and the identification decoding circuit 120d of the fourth semiconductor chip 100d can assign an even flag bit to the fourth semiconductor chip 100d according to the first identification signal "0" transmitted in the first identification transmission channel 301.

[0114] It can be understood that in the above two embodiments, different definitions of the identification signal can be given according to the position of the identification decoding circuit. For example, the identification signal "0" indicates that the semiconductor chip is a memory chip of an odd level in the stacking structure, and the identification signal "1" indicates that the semiconductor chip is a memory chip of an even level in the stacking structure; or, the identification signal "0" indicates that the semiconductor chip is a memory chip of an even level in the stacking structure, and the identification signal "1" indicates that the semiconductor chip is a memory chip of an odd level in the stacking structure.

[0115] In other embodiments, the identification signals "0" and "1" can be given fixed definitions, and the identification signals transmitted in the first identification transmission channel 301 and the second identification transmission channel 302 can be exchanged according to the position of the identification decoding circuit to ensure that each semiconductor chip in the stacked structure is assigned an odd flag bit or an even flag bit through the first identification transmission channel 301 and the second identification transmission channel 302.

[0116] It should be noted that since the same data receiving circuit (e.g., 131a and 131b) in the semiconductor chip 100a located at an odd level and the semiconductor chip 100b located at an even level are respectively located on opposite sides of the symmetry plane M, and the data signal transmitted in the data transmission channel is not switched, an odd-even identification signal is required to switch the data signal transmitted to the same data receiving circuit. In the embodiment of the present disclosure, by assigning an odd flag bit or an even flag bit to each semiconductor chip in the stacked structure, the odd flag bit or the even flag bit can be used as a switching identifier for the transmission path between the data and the circuit, thereby accurately transmitting data to the corresponding data receiving circuit in each chip of the stacked structure.

[0117] In an embodiment of the present disclosure, a stacking structure is set on a logic chip; the stacking structure includes the 1st to 2Nth semiconductor chips stacked in sequence, and the 1st to 2Nth semiconductor chips are the same memory chips; and the first identification transmission path of the 2i-1th semiconductor chip and the second identification transmission path of the 2i-th semiconductor chip are connected in sequence to form a first identification transmission channel, and the second identification transmission path of the 2i-1th semiconductor chip and the first identification transmission path of the 2i-th semiconductor chip are connected in sequence to form a second identification transmission channel; through the first identification transmission channel and the second identification transmission channel, each semiconductor chip in the stacking structure can be assigned an odd flag bit or an even flag bit, and the odd flag bit or the even flag bit can be used as a switching identifier for the transmission path between data and the circuit, so that the data can be accurately transmitted to the corresponding data receiving circuit in each chip of the stacking structure.

[0118] In addition, the embodiment of the present disclosure reduces the complexity of assigning stacking identification by setting a first identification transmission path and a second identification transmission path symmetrically distributed based on the central axis in the semiconductor chip, so that more memory chips can be three-dimensionally packaged, which is beneficial to improving the integration of the semiconductor structure and increasing the storage capacity.

[0119] In some embodiments, reference Figure 5As shown, the logic chip 200 is configured to: output a first identification signal to the identification decoding circuit of the 2i-1th semiconductor chip through one of the first identification transmission channel 301 and the second identification transmission channel 302; output a second identification signal to the identification decoding circuit of the 2ith semiconductor chip through the other of the first identification transmission channel and the second identification transmission channel; wherein the second identification signal is different from the first identification signal.

[0120] The logic chip 200 includes an identification signal generation circuit for generating an identification signal. For example, the identification signal generation circuit includes a first sub-identification signal generation circuit and a second sub-identification signal generation circuit. The first sub-identification signal generation circuit is used to generate a first identification signal (or a second identification signal), and the second sub-identification signal generation circuit is used to generate a second identification signal (or a first identification signal). The first sub-identification signal generation circuit can be coupled to the first identification transmission channel 301, and the second sub-identification signal generation circuit can be coupled to the second identification transmission channel 302.

[0121] In some embodiments, when the identification decoding circuit in each chip is coupled to the first identification transmission path, the logic chip 200 transmits the first identification signal "0" to the identification decoding circuit 120a of the first semiconductor chip 100a and the identification decoding circuit 120c of the third semiconductor chip 100c through the first identification transmission channel 301, and the logic chip 200 transmits the second identification signal "1" to the identification decoding circuit 120b of the second semiconductor chip 100b and the identification decoding circuit 120d of the fourth semiconductor chip 100d through the second identification transmission channel 302.

[0122] In other embodiments, when the identification decoding circuit in each chip is coupled to the second identification transmission path, the logic chip 200 transmits the second identification signal "1" to the identification decoding circuit 120a of the first semiconductor chip 100a and the identification decoding circuit 120c of the third semiconductor chip 100c through the second identification transmission channel 302, and the logic chip 200 transmits the first identification signal "0" to the identification decoding circuit 120b of the second semiconductor chip 100b and the identification decoding circuit 120d of the fourth semiconductor chip 100d through the first identification transmission channel 301.

[0123] It can be understood that through the semiconductor structure provided by the embodiment of the present disclosure, different identification signals (for example, "0" and "1") can be transmitted to the identification decoding circuits of storage chips at different levels respectively. The identification decoding circuit decodes the received identification signal to generate a data selection signal, thereby accurately transmitting the data to each chip in the stacked structure.

[0124] In some embodiments, the identification decoding circuit is configured to: decode the first identification signal to generate a first data selection signal, or decode the second identification signal to generate a second data selection signal; wherein the second data selection signal is different from the first data selection signal.

[0125] In one example, the identification decoding circuit in each chip is coupled to the first identification transmission path. Figure 5 As shown, the identification decoding circuit 120a of the first semiconductor chip 100a receives the first identification signal "0" transmitted by the first identification transmission path 111a and decodes it to generate a first data selection signal, for example, a first data selection signal "1"; the identification decoding circuit 120b of the second semiconductor chip 100b receives the second identification signal "1" transmitted by the first identification transmission path 111b and decodes it to generate a second data selection signal, for example, a second data selection signal "0".

[0126] In another example, the identification decoding circuit in each chip is coupled to the second identification transmission path. Figure 5 As shown, the identification decoding circuit 120a of the first semiconductor chip 100a receives the second identification signal "1" transmitted by the second identification transmission path 112a and decodes it to generate a second data selection signal, for example, the second data selection signal "0"; the identification decoding circuit 120b of the second semiconductor chip 100b receives the first identification signal "0" transmitted by the second identification transmission path 112b and decodes it to generate a first data selection signal, for example, the first data selection signal "1".

[0127] In some embodiments, the semiconductor chip further comprises: a first data receiving circuit, a second data receiving circuit, a first data transmission path, a second data transmission path, a first data selection circuit, and a second data selection circuit; wherein the first data transmission path and the second data transmission path penetrate the substrate in a direction perpendicular to the active surface of the semiconductor chip and are symmetrically distributed about the central axis; the first data selection circuit is respectively coupled to the identification decoding circuit, the first data transmission path, the second data transmission path, and the first data receiving circuit; and the second data selection circuit is respectively coupled to the identification decoding circuit, the first data transmission path, the second data transmission path, and the second data receiving circuit;

[0128] Among them, the first data transmission path of the 2i-1th semiconductor chip and the second data transmission path of the 2i-th semiconductor chip are connected in sequence to form a first data transmission channel 311; the second data transmission path of the 2i-1th semiconductor chip and the first data transmission path of the 2i-th semiconductor chip are connected in sequence to form a second data transmission channel 312; the first data transmission channel 311 is configured to transmit a first data signal; the second data transmission channel 312 is configured to transmit a second data signal; the second data signal is different from the first data signal.

[0129] Reference Figure 5 As shown, the first semiconductor chip 100a includes a first data receiving circuit 131a, a second data receiving circuit 132a, a first data transmission path 151a, a second data transmission path 152a, a first data selection circuit 141a and a second data selection circuit 142a; the second semiconductor chip 100b includes a first data receiving circuit 131b, a second data receiving circuit 132b, a first data transmission path 151b, a second data transmission path 152b, a first data selection circuit 141b and a second data selection circuit 142 b; The third semiconductor chip 100c includes a first data receiving circuit 131c, a second data receiving circuit 132c, a first data transmission path 151c, a second data transmission path 152c, a first data selection circuit 141c and a second data selection circuit 142c; the fourth semiconductor chip 100d includes a first data receiving circuit 131d, a second data receiving circuit 132d, a first data transmission path 151d, a second data transmission path 152d, a first data selection circuit 141d and a second data selection circuit 142d.

[0130] Here, the first data receiving circuits 131a to 131d, the second data receiving circuits 132a to 132d, the first data transmission paths 151a to 151d, the second data transmission paths 152a to 152d, the first data selection circuits 141a to 141d, and the second data selection circuits 142a to 142d may be referred to as Figure 2 as well as Figure 4 The first data receiving circuit 131, the second data receiving circuit 132, the first data transmission path 151, the second data transmission path 152, the first data selection circuit 141, and the second data selection circuit 142 shown in FIG are explained and will not be repeated here.

[0131] The first data transmission channel 311 includes the first data transmission path 151a of the first semiconductor chip 100a, the second data transmission path 152b of the second semiconductor chip 100b, the first data transmission path 151c of the third semiconductor chip 100c, and the second data transmission path 152d of the fourth semiconductor chip 100d; the second data transmission channel 312 includes the second data transmission path 152a of the first semiconductor chip 100a, the first data transmission path 151b of the second semiconductor chip 100b, the second data transmission path 152c of the third semiconductor chip 100c, and the first data transmission path 151d of the fourth semiconductor chip 100d.

[0132] It can be understood that the data transmission paths located on one side of the symmetry plane M and connected in sequence constitute the first data transmission channel 311, and the data transmission paths located on the other side of the symmetry plane M and connected in sequence constitute the second data transmission channel 312; the first data transmission channel 311 and the second data transmission channel 312 are symmetrically distributed based on the central axis L.

[0133] The first data transmission channel 311 and the second data transmission channel 312 are used to transmit data signals. For example, the first data transmission channel is configured to transmit a first data signal B1, and the second data transmission channel is configured to transmit a second data signal B2.

[0134] In some embodiments, the first data selection circuit of the 2i-1th semiconductor chip is configured to: output one of the first data signal and the second data signal to the first data receiving circuit of the 2i-1th semiconductor chip according to the first data selection signal;

[0135] The second data selection circuit of the 2i-1th semiconductor chip is configured to: output the other of the first data signal and the second data signal to the second data receiving circuit of the 2i-1th semiconductor chip according to the first data selection signal;

[0136] The first data selection circuit of the 2i-th semiconductor chip is configured to: output one of the first data signal and the second data signal to the first data receiving circuit of the 2i-th semiconductor chip according to the second data selection signal;

[0137] The second data selection circuit of the 2i-th semiconductor chip is configured to output the other of the first data signal and the second data signal to the second data receiving circuit of the 2i-th semiconductor chip according to the second data selection signal.

[0138] The first data selection circuit 141a of the first semiconductor chip 100a can output the first data signal B1 to the first data receiving circuit 131a of the first semiconductor chip 100a according to the first data selection signal; the second data selection circuit 142a of the first semiconductor chip 100a can output the second data signal B2 to the second data receiving circuit 132a of the first semiconductor chip 100a according to the first data selection signal.

[0139] The first data selection circuit 141b of the second semiconductor chip 100b can output the first data signal B1 to the first data receiving circuit 131b of the second semiconductor chip 100b according to the second data selection signal; the second data selection circuit 142b of the second semiconductor chip 100b can output the second data signal B2 to the second data receiving circuit 132b of the second semiconductor chip 100b according to the second data selection signal.

[0140] The first data selection circuit 141c of the third semiconductor chip 100c can output the first data signal B1 to the first data receiving circuit 131c of the third semiconductor chip 100c according to the first data selection signal; the second data selection circuit 142c of the third semiconductor chip 100c can output the second data signal B2 to the second data receiving circuit 132c of the third semiconductor chip 100c according to the first data selection signal.

[0141] The first data selection circuit 141d of the fourth semiconductor chip 100d can output the first data signal B1 to the first data receiving circuit 131d of the fourth semiconductor chip 100d according to the second data selection signal; the second data selection circuit 142d of the fourth semiconductor chip 100d can output the second data signal B2 to the second data receiving circuit 132d of the fourth semiconductor chip 100d according to the second data selection signal.

[0142] It should be pointed out that when the first semiconductor chip 100a, the second semiconductor chip 100b, the third semiconductor chip 100c and the fourth semiconductor chip 100d are not respectively assigned odd flag bits and even flag bits, the first data receiving circuit of the semiconductor chip located at the odd level receives the first data signal B1, and the second data receiving circuit of the semiconductor chip located at the odd level receives the second data signal B2; while the first data receiving circuit of the semiconductor chip located at the even level receives the second data signal B2, and the second data receiving circuit of the semiconductor chip located at the odd level receives the first data signal B1, resulting in the first data signal B1 and the second data signal B2 cannot be accurately transmitted to the corresponding internal receiving circuit.

[0143] The semiconductor structure provided by the embodiment of the present disclosure assigns an odd flag bit or an even flag bit to each semiconductor chip in the stacked structure. The odd flag bit or the even flag bit can be used as a switching identifier for the transmission path between data and the circuit, thereby accurately transmitting data to the internal receiving circuit corresponding to each semiconductor chip in the stacked structure.

[0144] In some embodiments, the central axes of any two adjacent semiconductor chips among the 1st to 2Nth semiconductor chips are aligned; wherein the first identification transmission path of one of the two adjacent semiconductor chips is aligned with the second identification transmission path of the other of the two adjacent semiconductor chips.

[0145] Reference Figure 5 As shown, the central axes L of the first semiconductor chip 100 a , the second semiconductor chip 100 b , the third semiconductor chip 100 c , and the fourth semiconductor chip 100 d are all aligned and coincide with each other.

[0146] The first identification transmission path 111a of the first semiconductor chip 100a is aligned with the second identification transmission path 112b of the second semiconductor chip 100b, and the second identification transmission path 112a of the first semiconductor chip 100a is aligned with the first identification transmission path 111b of the second semiconductor chip 100b. In one embodiment, the first interconnect structure of the first semiconductor chip 100a is aligned with the second interconnect structure of the second semiconductor chip 100b, and the second interconnect structure of the first semiconductor chip 100a is aligned with the first interconnect structure of the second semiconductor chip 100b.

[0147] The second identification transmission path 112b of the second semiconductor chip 100b is aligned with the first identification transmission path 111c of the third semiconductor chip 100c, and the first identification transmission path 111b of the second semiconductor chip 100b is aligned with the second identification transmission path 112c of the third semiconductor chip 100c. In one embodiment, the second connection pad of the second semiconductor chip 100b is aligned with the first connection pad of the third semiconductor chip 100c, and the first connection pad of the second semiconductor chip 100b is aligned with the second connection pad of the third semiconductor chip 100c.

[0148] In some embodiments, the non-active surface of the 2jth semiconductor chip is bonded to the non-active surface of the 2j+1th semiconductor chip, where j is an integer greater than or equal to 1, and 2j+1 is less than 2N. Figure 5 As shown, the inactive surface of the second semiconductor chip 100 b is bonded to the inactive surface of the third semiconductor chip 100 c , for example, via connection pads on the inactive surfaces of the semiconductor chips.

[0149] In some embodiments, a first identification transmission path includes: a first connection pad located on the inactive surface of the semiconductor chip, a first path located in the substrate, and a first interconnection structure located on the active surface of the semiconductor chip; wherein the first connection pad, the first path, and the first interconnection structure are connected in sequence; a second identification transmission path includes: a second connection pad located on the inactive surface of the semiconductor chip, a second path located in the substrate, and a second interconnection structure located on the active surface of the semiconductor chip; wherein the second connection pad, the second path, and the second interconnection structure are connected in sequence. The first identification transmission path and the second identification transmission path can refer to Figure 2 The first identification transmission path 111 and the second identification transmission path 112 are not described in detail here.

[0150] Based on the above semiconductor chip or semiconductor structure, an embodiment of the present disclosure further provides a semiconductor device, including:

[0151] substrate;

[0152] The semiconductor chip 100 in any of the above embodiments is located on a substrate, and the semiconductor chip 100 is bonded to the substrate; or the semiconductor structure 300 in any of the above embodiments is located on a substrate, and the semiconductor structure 300 is bonded to the substrate.

[0153] Substrates include packaging substrates used to carry logic chips and memory chips, such as low-temperature co-fired ceramic substrates or printed circuit boards.

[0154] In some embodiments, a semiconductor device includes: a high bandwidth memory.

[0155] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor chip, characterized in that: include: A first identification transmission path passes through the substrate of the semiconductor chip in a direction perpendicular to the active surface of the semiconductor chip; a second identification transmission path, penetrating the substrate in a direction perpendicular to the active surface of the semiconductor chip and symmetrically distributed with the first identification transmission path based on a central axis of the semiconductor chip, wherein the central axis passes through the center of the semiconductor chip and is parallel to the active surface; an identification decoding circuit coupled to the first identification transmission path or the second identification transmission path, the identification decoding circuit being configured to receive an identification signal and decode the identification signal to generate a data selection signal; The semiconductor chip outputs the data signals transmitted in the plurality of data transmission paths to the corresponding internal receiving circuits according to the data selection signal.

2. The semiconductor chip according to claim 1, wherein The internal receiving circuit includes: a first data receiving circuit and a second data receiving circuit; wherein the first data receiving circuit is coupled to the first data selection circuit; and the second data receiving circuit is coupled to the second data selection circuit; The plurality of data transmission paths include: a first data transmission path, penetrating the substrate in a direction perpendicular to the active surface of the semiconductor chip; wherein the first data transmission path is configured to transmit a first data signal; a second data transmission path extending through the substrate in a direction perpendicular to the active surface of the semiconductor chip and symmetrically distributed with the first data transmission path about the central axis; wherein the second data transmission path is configured to transmit a second data signal; the second data signal is different from the first data signal; The first data selection circuit is coupled to the identification decoding circuit, the first data transmission path, and the second data transmission path, respectively; wherein the first data selection circuit is configured to output one of the first data signal or the second data signal to the first data receiving circuit according to the data selection signal; The second data selection circuit is coupled to the identification decoding circuit, the first data transmission path and the second data transmission path respectively; wherein the second data selection circuit is configured to output the other of the first data signal or the second data signal to the second data receiving circuit according to the data selection signal.

3. The semiconductor chip according to claim 1 or 2, characterized in that The first identification transmission path is configured to transmit a first identification signal; The second identification transmission path is configured to transmit a second identification signal; wherein the second identification signal is different from the first identification signal.

4. The semiconductor chip according to claim 1, wherein The first identification transmission path includes: a first connection pad located on the inactive surface of the semiconductor chip, a first path located in the substrate, and a first interconnection structure located on the active surface of the semiconductor chip; wherein the first connection pad, the first path, and the first interconnection structure are connected in sequence; The second identification transmission path includes: a second connection pad located on the inactive surface of the semiconductor chip, a second path located in the substrate, and a second interconnection structure located on the active surface of the semiconductor chip; wherein the second connection pad, the second path, and the second interconnection structure are connected in sequence.

5. The semiconductor chip according to claim 4, wherein: The identification decoding circuit is coupled to the first interconnect structure or the second interconnect structure.

6. A semiconductor structure, characterized in that include: Logic chips; A stacked structure, stacked on the logic chip, comprising: semiconductor chips No. 1 to No. 2N stacked sequentially; wherein the semiconductor chips No. 1 to No. 2N are identical memory chips; the inactive surface of the No. 1 semiconductor chip is bonded to the logic chip, and the active surface of the No. 2i semiconductor chip is bonded to the active surface of the No. 2i-1 semiconductor chip; N is a positive integer, and i is a positive integer less than or equal to N; The semiconductor chip includes: a first identification transmission path, a second identification transmission path, and an identification decoding circuit; the first identification transmission path and the second identification transmission path penetrate the substrate of the semiconductor chip in a direction perpendicular to the active surface of the semiconductor chip, and are symmetrically distributed based on a central axis of the semiconductor chip, wherein the central axis passes through the center of the semiconductor chip and is parallel to the active surface; the identification decoding circuit is coupled to the first identification transmission path or the second identification transmission path, and the identification decoding circuit is configured to receive an identification signal, wherein the identification signal indicates that the semiconductor chip is the 2ith semiconductor chip or the 2i-1th semiconductor chip in the stacked structure; Among them, the first identification transmission path of the 2i-1th semiconductor chip and the second identification transmission path of the 2i-th semiconductor chip are connected in sequence to form a first identification transmission channel; the second identification transmission path of the 2i-1th semiconductor chip and the first identification transmission path of the 2i-th semiconductor chip are connected in sequence to form a second identification transmission channel.

7. The semiconductor structure according to claim 6, wherein: The logic chip is configured as follows: Outputting the first identification signal to the identification decoding circuit of the 2i-1th semiconductor chip through one of the first identification transmission channel and the second identification transmission channel; A second identification signal is output to the identification decoding circuit of the 2i-th semiconductor chip through the other of the first identification transmission channel and the second identification transmission channel; wherein the second identification signal is different from the first identification signal.

8. The semiconductor structure according to claim 7, wherein: The identification decoding circuit is configured to: decode the first identification signal to generate a first data selection signal, or decode the second identification signal to generate a second data selection signal; The second data selection signal is different from the first data selection signal.

9. The semiconductor structure according to claim 7 or 8, characterized in that: The semiconductor chip further includes: a first data receiving circuit, a second data receiving circuit, a first data transmission path, a second data transmission path, a first data selection circuit, and a second data selection circuit; wherein the first data transmission path and the second data transmission path penetrate the substrate in a direction perpendicular to the active surface of the semiconductor chip and are symmetrically distributed about the central axis; The first data selection circuit is coupled to the identification decoding circuit, the first data transmission path, the second data transmission path and the first data receiving circuit respectively; The second data selection circuit is coupled to the identification decoding circuit, the first data transmission path, the second data transmission path and the second data receiving circuit respectively; Among them, the first data transmission path of the 2i-1th semiconductor chip and the second data transmission path of the 2ith semiconductor chip are connected in sequence to form a first data transmission channel; the second data transmission path of the 2i-1th semiconductor chip and the first data transmission path of the 2ith semiconductor chip are connected in sequence to form a second data transmission channel; the first data transmission channel is configured to transmit a first data signal; the second data transmission channel is configured to transmit a second data signal; the second data signal is different from the first data signal.

10. The semiconductor structure according to claim 9, wherein: The first data selection circuit of the 2i-1th semiconductor chip is configured to: output one of the first data signal and the second data signal to the first data receiving circuit of the 2i-1th semiconductor chip according to the first data selection signal; The second data selection circuit of the 2i-1th semiconductor chip is configured to: output the other of the first data signal and the second data signal to the second data receiving circuit of the 2i-1th semiconductor chip according to the first data selection signal; The first data selection circuit of the 2i-th semiconductor chip is configured to: output one of the first data signal and the second data signal to the first data receiving circuit of the 2i-th semiconductor chip according to the second data selection signal; The second data selection circuit of the 2i-th semiconductor chip is configured to output the other of the first data signal and the second data signal to the second data receiving circuit of the 2i-th semiconductor chip according to the second data selection signal.

11. The semiconductor structure according to claim 6, wherein: The central axes of any two adjacent semiconductor chips among the 1st to 2Nth semiconductor chips are aligned; wherein the first identification transmission path of one of the two adjacent semiconductor chips is aligned with the second identification transmission path of the other of the two adjacent semiconductor chips.

12. The semiconductor structure according to claim 6, wherein: The inactive surface of the 2jth semiconductor chip is bonded to the inactive surface of the 2j+1th semiconductor chip, where j is an integer greater than or equal to 1, and 2j+1 is less than 2N.

13. The semiconductor structure according to claim 6, wherein: The first identification transmission path includes: a first connection pad located on the inactive surface of the semiconductor chip, a first path located in the substrate, and a first interconnection structure located on the active surface of the semiconductor chip; wherein the first connection pad, the first path, and the first interconnection structure are connected in sequence; The second identification transmission path includes: a second connection pad located on the inactive surface of the semiconductor chip, a second path located in the substrate, and a second interconnection structure located on the active surface of the semiconductor chip; wherein the second connection pad, the second path, and the second interconnection structure are connected in sequence.

14. A semiconductor device, characterized in that: include: substrate; The semiconductor chip according to any one of claims 1 to 5, located on the substrate, the semiconductor chip being bonded to the substrate; Or, the semiconductor structure according to any one of claims 6 to 13 is located on the substrate, and the semiconductor structure is bonded to the substrate.

15. The semiconductor device according to claim 14, wherein: The semiconductor device includes a high-bandwidth memory.

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