Semiconductor structure and method of fabricating the same

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a deep trench capacitor, a first etching hole, a second etching hole and a first air gap. The first air gap is located between a first dielectric layer and a second dielectric layer of the deep trench capacitor. The first air gap is recessed from a surface of the second electrode layer of the deep trench capacitor exposed in the first etching hole to the inside of the second electrode layer. The first air gap exposes part of the surface of the first dielectric layer and the second dielectric layer in the first air gap. In the present disclosure, the first air gap is formed in the second electrode layer exposed in the first etching hole, which increases the distance between the edge of the second electrode layer and the edge of the first electrode layer, enhances the barrier between the edge of the first electrode layer and the second electrode layer, and reduces or avoids the generation of leakage current between the edge of the first electrode layer and the second electrode layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for fabricating the same. Background Technology

[0002] With the continuous development of semiconductor technology, semiconductor structures are being widely used in an increasing number of fields. Planar parallel-plate capacitor structures within semiconductor structures can no longer meet capacitance requirements. Currently, deep trench capacitor (DTC) structures are being incorporated into semiconductor structures to improve capacitance density. However, in deep trench capacitor structures, inter-plate leakage current is prone to occur at the edges of adjacent electrode layers, affecting capacitor performance. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] A first aspect of this disclosure provides a semiconductor structure, comprising:

[0005] A substrate, wherein the top surface of the substrate is provided with a trench extending into the interior of the substrate;

[0006] A deep trench capacitor includes a first electrode layer, a first dielectric layer, a second electrode layer, and a second dielectric layer that are sequentially stacked on the inner surface of the trench and the top surface of the substrate.

[0007] A first etched hole and a second etched hole, wherein the first etched hole sequentially penetrates the second dielectric layer, the second electrode layer and the first dielectric layer along the depth direction of the deep trench capacitor; the second etched hole penetrates the second dielectric layer along the depth direction of the deep trench capacitor.

[0008] A first air gap is located between the first dielectric layer and the second dielectric layer. The first air gap is recessed from the surface of the second electrode layer exposed in the first etched hole into the interior of the second electrode layer, and the first air gap exposes a portion of the surfaces of the first dielectric layer and the second dielectric layer within the first air gap.

[0009] In some embodiments, the thickness of the first electrode layer is greater than the thickness of the second electrode layer.

[0010] In some embodiments, the ratio of the depth of the first air gap recess inside the second electrode layer to the height of the first air gap ranges from 0.6 to 7:1.

[0011] In some embodiments, the portion of the second dielectric layer located in the trench forms a second air gap;

[0012] The semiconductor structure further includes a filling layer that covers the second dielectric layer located on the top surface of the substrate and fills the second air gap.

[0013] In some embodiments, the material of the first dielectric layer includes a high dielectric constant material; and / or,

[0014] The material of the second dielectric layer includes polycrystalline silicon; and / or,

[0015] The filling layer is made of oxides.

[0016] In some embodiments, the semiconductor structure further includes an interlayer dielectric layer that covers the deep trench capacitor and fills the first etched via and the second etched via;

[0017] The interlayer dielectric layer is provided with a first contact hole and a second contact hole. The first contact hole penetrates and fills the interlayer dielectric layer in the first etched hole, and the first contact hole exposes a portion of the top surface of the first electrode layer. The second contact hole penetrates and fills the interlayer dielectric layer in the second etched hole, and the second contact hole exposes a portion of the top surface of the second electrode layer.

[0018] A first contact plug is provided in the first contact hole, and the bottom end of the first contact plug is in contact with the first electrode layer;

[0019] A second contact plug is provided in the second contact hole, and the bottom end of the second contact plug is in contact with the second electrode layer.

[0020] In some embodiments, the material of the interlayer dielectric layer includes oxides.

[0021] According to a second aspect of this disclosure, a method for fabricating a semiconductor structure is provided, the method comprising:

[0022] A substrate is provided, wherein the top surface of the substrate has a trench extending into the interior of the substrate;

[0023] A deep trench capacitor is formed, the deep trench capacitor comprising a first electrode layer, a first dielectric layer, a second electrode layer and a second dielectric layer sequentially stacked on the inner surface of the trench and the top surface of the substrate.

[0024] A first etched hole is formed, which sequentially penetrates the second dielectric layer and the second electrode layer along the depth direction of the deep trench capacitor, exposing part of the top surface of the first dielectric layer and the sidewall of the second electrode layer in the first etched hole.

[0025] A first air gap is formed by removing a portion of the sidewall of the second electrode layer exposed within the first etched hole. The first air gap is located between the first dielectric layer and the second dielectric layer, and the first air gap exposes a portion of the surfaces of the first dielectric layer and the second dielectric layer within the first air gap.

[0026] In some embodiments, forming a first etched hole includes:

[0027] The second dielectric layer and the second electrode layer are etched using a first etching gas, wherein the first etching gas includes any one or more of carbon tetrafluoride, hydrogen bromide, and chlorine.

[0028] In some embodiments, removing a portion of the sidewall of the second electrode layer exposed within the first etched hole to form a first air gap includes:

[0029] The second etching gas is used to etch the portion of the sidewall of the second electrode layer exposed within the first etching hole, wherein the second etching gas includes any one or more of carbon tetrafluoride, hydrogen bromide, and chlorine.

[0030] In some embodiments, the flow rate of the second etching gas is greater than the flow rate of the first etching gas.

[0031] In some embodiments, after removing a portion of the sidewall of the second electrode layer exposed within the first etched hole to form a first air gap, the method of fabricating the semiconductor structure further includes:

[0032] The first dielectric layer is etched along the first etching hole, so that a portion of the top surface of the first electrode layer is exposed inside the first etching hole.

[0033] In some embodiments, etching the first dielectric layer along the first etching hole includes:

[0034] The first dielectric layer is etched using a third etching gas, which includes any one or more of boron trichloride, argon, and chlorine.

[0035] In some embodiments, the method for fabricating the semiconductor structure further includes:

[0036] A second etched hole is formed, which penetrates the second dielectric layer along the depth direction of the deep trench capacitor, exposing a portion of the top surface of the second electrode layer within the second etched hole.

[0037] In some embodiments, after forming the second etched hole, the method for fabricating the semiconductor structure further includes:

[0038] An interlayer dielectric layer is formed, which covers the deep trench capacitor and fills the first etched via and the second etched via;

[0039] A first contact hole and a second contact hole are formed in the interlayer dielectric layer. The first contact hole penetrates and fills the interlayer dielectric layer in the first etched hole, exposing a portion of the top surface of the first electrode layer. The second contact hole penetrates and fills the interlayer dielectric layer in the first etched hole, exposing a portion of the top surface of the second electrode layer.

[0040] A first contact plug is formed in the first contact hole to contact the top surface of the first electrode layer, and a second contact plug is formed in the second contact hole to contact the top surface of the second electrode layer.

[0041] In the semiconductor structure and semiconductor structure fabrication method disclosed herein, a first air gap is formed in the second electrode layer exposed in the first etched hole, thereby increasing the distance between the edge of the second electrode layer and the edge of the first electrode layer, strengthening the barrier between the edge of the first electrode layer and the second electrode layer, and reducing or avoiding leakage current between the edge of the first electrode layer and the second electrode layer.

[0042] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0044] Figure 1 This is a schematic diagram of a deep trench capacitor in one of the related embodiments.

[0045] Figure 2 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0046] Figure 3 This is a schematic diagram of a semiconductor structure according to another exemplary embodiment.

[0047] Figure 4 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0048] Figure 5 This is a schematic diagram of a deep trench capacitor according to an exemplary embodiment.

[0049] Figure 6 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0050] Figure 7 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0051] Figure 8 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0052] Figure 9 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0053] Figure 10 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0054] Figure Labels :

[0055] 21', First electrode layer; 22', First dielectric layer; 23', Second electrode layer; 24', Second dielectric layer;

[0056] 100. Semiconductor structure;

[0057] 10. Substrate;

[0058] 20. Deep trench capacitor; 21. First electrode layer; 22. First dielectric layer; 23. Second electrode layer; 24. Second dielectric layer; 25. First contact plug; 26. Second contact plug;

[0059] 30. First etched hole;

[0060] 40. Second etched hole;

[0061] 50. First air gap;

[0062] 60. Third dielectric layer;

[0063] 70. Filler layer;

[0064] 80. Interlayer dielectric layer.

[0065] 91. First photoresist layer; 92. Second photoresist layer. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0067] In deep trench capacitor structures, as the distance between electrode plates gradually decreases, inter-plate leakage current is prone to occur at the edges of adjacent electrode layers, affecting capacitor performance. (Reference) Figure 1 The image shows a partial structure of a deep trench capacitor in the related art. In the related art, the first electrode layer 21' (lower electrode), the first dielectric layer 22', the second electrode layer 23' (upper electrode), and the second dielectric layer 24' are stepped. The distance between the edge of the second electrode layer 23' and the first electrode layer 21' is increased, thereby reducing the current leakage between the first electrode layer 21' and the second electrode layer 23'. However, in the process of fabricating this type of deep trench capacitor, a large number of photomasks are required, resulting in a complicated process and high photomask costs.

[0068] To address the aforementioned issues, this disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure. By forming a first air gap in the second electrode layer exposed in the first etched hole, the distance between the edge of the second electrode layer and the edge of the first electrode layer is increased, thereby strengthening the barrier between the edge of the first electrode layer and the second electrode layer and reducing or avoiding leakage current between the edge of the first electrode layer and the second electrode layer.

[0069] In exemplary embodiments of this disclosure, such as Figure 2 As shown, this disclosure provides a semiconductor structure 100. As... Figure 2 As shown, the semiconductor structure 100 includes a substrate 10, which can be made of monocrystalline silicon, polycrystalline silicon, or amorphous silicon; the substrate 10 can also be made of silicon, germanium, gallium arsenide, or a silicon-germanium compound; the substrate 10 may also have an epitaxial layer or a silicon-on-insulator (SOI); the substrate 10 can also be made of other semiconductor materials. In one example, reference... Figure 2 The substrate 10 can be a silicon interposer, also known as a silicon interposer. It can form an electrical connection with the chip, packaging substrate, etc. through solder bumps (μbumps) to realize information exchange between the upper and lower layers of the chip or between the chip and the packaging substrate.

[0070] like Figure 2 As shown, the semiconductor structure 100 includes a deep trench capacitor 20 (DTC), which is disposed within a trench in the substrate 10, extending from the top surface of the substrate 10 into its interior. The deep trench capacitor 20 effectively improves the impedance and logic voltage drop of the power delivery network (PDN) of the semiconductor structure, as well as reducing leakage current. Experiments have shown that the larger the capacitance of the deep trench capacitor 20, the more significant the effect on reducing leakage current.

[0071] refer to Figure 2 The deep trench capacitor 20 includes a first electrode layer 21, a first dielectric layer 22, a second electrode layer 23, and a second dielectric layer 24 sequentially stacked in a conformal manner on the substrate 10. A portion of the deep trench capacitor 20 is curved and disposed within the trenches, while another portion is flatly disposed on the top surface of the substrate 10. The first electrode layer 21 and the second electrode layer 23 are also the lower and upper electrodes of the deep trench capacitor 20. Both the first electrode layer 21 and the second electrode layer 23 are made of a conductive material, such as titanium nitride (TiN) or a metal. The first dielectric layer 22 is an insulating dielectric layer filling the space between the first electrode layer 21 (lower electrode) and the second electrode layer 23 (upper electrode). The first dielectric layer 22 is made of an insulating material, which can be a high-k (HK) material, such as zirconium oxide (ZrO) or hafnium oxide (HfO2). The first dielectric layer 22, made of a high-k material, can be made thinner, thereby reducing the size of the deep trench capacitor 20. The second dielectric layer 24 covers the second electrode layer 23 and is used to protect the second electrode layer 23. The second dielectric layer 24 can be made of an insulating material, such as polycrystalline silicon or oxide.

[0072] like Figure 2 As shown, the semiconductor structure 100 also includes a first etched hole 30, which is located along the depth direction of the deep trench capacitor 20. Figure 2 Extending in the y-direction shown, and sequentially penetrating the second dielectric layer 24, the second electrode layer 23, and the first dielectric layer 22, the first etched hole 30 exposes a portion of the top surface of the first electrode layer 21 (lower electrode) to facilitate the fabrication of a first contact plug connected to the first electrode layer 21 in subsequent processes. The first contact plug is used to supply power to the first electrode layer 21. (Continue to refer to...) Figure 2The first etched hole 30 also exposes the sidewalls of the second electrode layer 23. The first air gap 50 is located within the sidewalls of the second electrode layer 23 exposed within the first etched hole 30, and the first air gap 50 (described in detail below) communicates with the first etched hole 30. It can be understood that during the formation of the first air gap 50, the sidewalls of the second electrode layer 23 can be exposed through the first etched hole 30 first, and then the portion of the second electrode layer 23 exposed within the first etched hole 30 can be removed by lateral etching, causing the second electrode layer 23 to be recessed inward from the sidewalls to form the first air gap 50.

[0073] Continue to refer to Figure 2 The semiconductor structure 100 also includes a second etched hole 40, which is located along the depth direction of the deep trench capacitor 20. Figure 2 The second etched hole 40 (in the y direction shown) penetrates the second dielectric layer 24 and can expose part of the top surface of the second electrode layer 23 (upper electrode) of the deep trench capacitor 20, so as to facilitate the fabrication of a second contact plug connected to the second electrode layer 23 in subsequent processes. The second contact plug is used to supply power to the second electrode layer 23.

[0074] like Figure 2 As shown, the semiconductor structure 100 also includes a first air gap 50, which is formed by recessing the surface of the second electrode layer 23 exposed in the first etched hole 30 into the interior of the second electrode layer 23. The first air gap 50 exposes a portion of the top surface of the first dielectric layer 22 and the second dielectric layer 24. That is, with Figure 2 Taking the orientation shown as an example, a portion of the top surface of the first dielectric layer 22 forms the bottom wall of the first air gap 50, a portion of the bottom surface of the second dielectric layer 24 forms the top wall of the first air gap 50, the side wall of the second electrode layer 23 forms the side wall of the first air gap 50, and the side of the first air gap 50 facing the first etching hole 30 is connected to the first etching hole 30.

[0075] The first air gap 50 is located at the edge of the second electrode layer 23, which can increase the distance between the edges of the first electrode layer 21 and the second electrode layer 23. The conductivity of air is close to zero, making it difficult for charge to flow in the first air gap 50, thereby reducing or avoiding leakage current between the edges of the first electrode layer 21 and the edges of the second electrode layer 23, and improving the performance of the deep trench capacitor 20.

[0076] In this embodiment of the disclosure, the second electrode layer of the deep trench capacitor is recessed inward to form a first air gap. The first air gap increases the distance between the edge of the second electrode layer and the edge of the first electrode layer, strengthens the barrier between the edge of the first electrode layer and the edge of the second electrode layer, and reduces or avoids leakage current between the edge of the first electrode layer and the edge of the second electrode layer.

[0077] In one exemplary embodiment, such as Figure 2 As shown, in this embodiment, the thickness of the first electrode layer 21 (lower electrode) is ( Figure 2 The thickness of the first electrode layer 21 (in the y-direction shown) is greater than that of the second electrode layer 23 (upper electrode). The thickness of the first electrode layer 21 is set to be greater than that of the second electrode layer 23 to mitigate or prevent structural collapse of the deep trench capacitor 20 caused by a large height of the first air gap 50. The thickness ratio of the first electrode layer 21 to the second electrode layer 23 can be 5:1 to 15:1; in one example, the thickness ratio of the first electrode layer 21 to the second electrode layer 23 is 10:1.

[0078] In some embodiments, such as Figure 2 As shown, the first air gap 50 is recessed to a depth within the second electrode layer 23. Figure 2 (as shown in the opposite direction of the x-direction), the depth of the recess is the width of the first air gap 50. In one example, the width of the first air gap 50 ( Figure 2 The wavelength (in the x-direction shown) is approximately 50 nm to 200 nm. The height of the first air gap 50 ( Figure 2 The thickness (in the y-direction shown) is approximately 30nm to 80nm, where the height of the first air gap 50 is also the thickness of the second electrode layer 23. In one example, refer to... Figure 2 The ratio of the width to the height of the first air gap 50 ranges from 0.6:1 to 7:1.

[0079] In some embodiments, such as Figure 2 As shown, the portion of the second dielectric layer 24 located in the trench forms a second air gap. The semiconductor structure 100 further includes a filling layer 70, which covers the second dielectric layer 24 located on the top surface of the substrate 10 and is capable of filling the second air gap. (Referring to...) Figure 2 The second dielectric layer 24 can be made of polysilicon, and the filling layer 70 can be made of oxide. The oxide material is cheaper than the filling layer 70, thereby reducing the manufacturing cost of the semiconductor structure 100.

[0080] In some alternative embodiments, the second air gap formed by the second dielectric layer 24 may also be filled with the same polycrystalline silicon material as the filling layer 70.

[0081] In one exemplary embodiment, reference Figure 3In this embodiment, the semiconductor structure 100 further includes an interlayer dielectric layer 80, which covers the top surface of the deep trench capacitor 20. The interlayer dielectric layer 80 can be made of an insulating material, such as an oxide, for example, silicon dioxide (SiO2). By providing the interlayer dielectric layer 80 covering the deep trench capacitor 20, the deep trench capacitor 20 can be protected to improve its performance. For example, it can prevent damage caused by physical contact between the deep trench capacitor 20 and external devices, and reduce or avoid signal interference from external devices to the deep trench capacitor 20.

[0082] Continue to refer to Figure 3 The interlayer dielectric layer 80 has a first contact hole and a second contact hole. The first contact hole penetrates the interlayer dielectric layer 80 to expose a portion of the top surface of the first electrode layer 21. A first contact plug 25 is disposed in the first contact hole, and the bottom end of the first contact plug 25 contacts the first electrode layer 21. The second contact hole penetrates the interlayer dielectric layer 80 to expose a portion of the top surface of the second electrode layer 23. A second contact plug 26 is disposed in the second contact hole, and the bottom end of the second contact plug 26 contacts the second electrode layer 23. Power is supplied to the first electrode layer 21 and the second electrode layer 23 through the first contact plug 25 and the second contact plug 26.

[0083] It should be noted that the reference Figure 2 and Figure 3 The sidewall of the first etched hole 30 is connected to the sidewall of the second electrode layer 23 (upper electrode) through the first air gap 50, and the bottom wall of the first etched hole 30 is directly connected to the first electrode layer 21 (lower electrode). In this embodiment, by setting the interlayer dielectric layer 80 to fill the first etched hole 30, and setting the first contact hole 81 in the interlayer dielectric layer 80 to expose only part of the top surface of the first electrode layer 21, since the sidewall of the first contact hole 81 is isolated from the sidewall of the second electrode layer 23 by the interlayer dielectric layer 80, the interlayer dielectric layer 80 can prevent the material of the first contact plug 25 from diffusing to the position of the second electrode layer 23, so as to avoid short circuit between the first contact plug 25 and the second electrode layer 23.

[0084] like Figure 4 As shown, this disclosure also provides a method for fabricating a semiconductor structure. This method can be used to fabricate the semiconductor structures provided in the above embodiments of this disclosure. The method includes the following steps:

[0085] Step S100: A substrate is provided, the top surface of which has a trench extending into the interior of the substrate.

[0086] In this step, refer to Figure 5The substrate 10 can be monocrystalline silicon, polycrystalline silicon, or amorphous silicon; the substrate 10 can also be silicon, germanium, gallium arsenide, or a silicon-germanium compound; the substrate 10 can also have an epitaxial layer or a silicon-on-insulator (SOI); the substrate 10 can also be other semiconductor materials. In this embodiment, the material of the substrate 10 is silicon.

[0087] Continue to refer to Figure 5 The top surface of substrate 10 has trenches extending into the interior of substrate 10 (the trenches are filled by deep trench capacitors 20, which are not shown). The process of forming the trenches may include: forming a patterned mask layer on the surface of substrate 10, the patterned mask layer defining the width, depth, and location of the trenches, and then etching substrate 10 using the patterned mask layer as a mask to form the trenches. In this embodiment, the number of trenches is one; in other possible embodiments, there may be multiple trenches, with shallow trench isolation structures separating adjacent trenches.

[0088] Step S200: Forming a deep trench capacitor, the deep trench capacitor includes a first electrode layer, a first dielectric layer, a second electrode layer and a second dielectric layer sequentially stacked on the inner surface of the trench and on the top surface of the substrate.

[0089] In this step, refer to Figure 5 Alternating multilayer electrode layers and multilayer dielectric layers can be formed by plating, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), or combinations thereof.

[0090] Among them, the electrode layer closest to the substrate 10 is the first electrode layer 21, and from the first electrode layer 21 upwards ( Figure 5 The layers 21 and 23 (in the y-direction shown) are stacked sequentially as a first dielectric layer 22, a second electrode layer 23, and a second dielectric layer 24. The first electrode layer 21 and the second electrode layer 23 are made of conductive materials, such as metal, titanium nitride, or doped polycrystalline silicon. The first dielectric layer 22 and the second dielectric layer 24 are made of insulating materials.

[0091] In some alternative embodiments, before forming the first electrode layer 21 of the deep trench capacitor 20, the method for fabricating the semiconductor structure further includes:

[0092] Step S210: A third dielectric layer is formed, which is stacked conformally on the inner surface of the trench and the top surface of the substrate.

[0093] In this step, refer to Figure 5 A third dielectric layer 60 can be formed on the inner surface of the trench and the top surface of the substrate 10 using processes such as deposition. The third dielectric layer 60 can be made of oxide material. The third dielectric layer 60 is used to separate the first electrode layer 21 and the substrate 10 to prevent the material of the first electrode layer 21 from diffusing into the substrate 10.

[0094] In step S300, a first etched hole is formed. The first etched hole penetrates the second dielectric layer and the second electrode layer sequentially along the depth direction of the deep trench capacitor, exposing part of the top surface of the first dielectric layer and the sidewall of the second electrode layer in the first etched hole.

[0095] In this step, refer to Figure 6 A patterned first photoresist layer 91 can be formed on the surface of the substrate 10. The patterned first photoresist layer 91 defines the size and location of the first etched hole 30 along the thickness direction of the deep trench capacitor 20. Figure 6 The second dielectric layer 24 and the second electrode layer 23 are etched in the y-direction shown in the figure, with the first dielectric layer 22 serving as the etch stop layer, to form a first etched hole 30 in the deep trench capacitor 20. (See reference) Figure 6 It can be determined that the first etch hole 30 can expose the sidewall of the second electrode layer 23 in the first etch hole 30. Thus, in the subsequent process, part of the structure of the first etch hole 30 can be removed by lateral etching to form the first air gap 50.

[0096] Step S400: Remove the portion of the sidewall of the second electrode layer exposed in the first etched hole to form a first air gap. The first air gap is located between the first dielectric layer and the second dielectric layer, and the first air gap exposes a portion of the surface of the first dielectric layer and the second dielectric layer within the first air gap.

[0097] In this step, refer to Figure 2 By adjusting parameters such as the direction and type of the etching gas, the etching gas can be directed horizontally. Figure 2 Etching is performed in the opposite direction of the x-direction shown in the diagram; that is, the etching gas can be emitted from the sidewall of the second electrode layer 23 to the left (in the opposite direction of the x-direction). Figure 2 (In the reverse of the x-direction shown) the internal etching of the second electrode layer 23 removes a portion of the second electrode layer 23 to form a first air gap 50 in the deep trench capacitor 20.

[0098] In the process of forming the first air gap 50 by lateral etching, the type of etching gas can be selected according to the materials of the first dielectric layer 22, the second electrode layer 23, and the second dielectric layer 24. For example, the etching gas has a high etching selectivity for the first electrode layer 21, but the etching selectivity for the first dielectric layer 22 and the second dielectric layer 24 is extremely low. Thus, the etching gas only reacts with the first electrode layer 21 to form the first air gap 50 in the first electrode layer 21. The first air gap 50 is located between the first dielectric layer 22 and the second dielectric layer 24. A portion of the top surface of the first dielectric layer 22 forms the bottom wall of the first air gap 50, and a portion of the bottom surface of the second dielectric layer 24 forms the top wall of the first air gap 50.

[0099] In the semiconductor structure fabrication method provided in this embodiment, a first etch hole 30 is formed in the deep trench capacitor 20, exposing the sidewall of the second electrode layer 23. A lateral etching method is used to etch away part of the structure of the second electrode layer 23 from the sidewall inward, so as to form a first air gap 50 at the edge of the second electrode layer 23. The first air gap 50 strengthens the barrier between the edge of the first electrode layer 21 and the edge of the second electrode layer 23, thereby reducing or avoiding leakage current between the edge of the first electrode layer 21 and the second electrode layer 23.

[0100] In one exemplary embodiment, step S300 may include the following steps:

[0101] Step S310: Use the first etching gas to etch the second dielectric layer and the second electrode layer.

[0102] In this step, refer to Figure 6 A patterned first photoresist layer 91 can be formed on the top surface of the deep trench capacitor 20, and the patterned first photoresist layer 91 defines the size and position of the first etched hole 30.

[0103] The following description uses an example where the second electrode layer 23 is made of titanium nitride (TiN) and the second dielectric layer 24 is made of oxide. The first etching gas includes any one or more of carbon tetrafluoride (CF4), hydrogen bromide (HBr), and chlorine (Cl2). The first etching gas has a high etching selectivity (e.g., greater than 20) for the second dielectric layer 24 and the second electrode layer 23, while having an extremely low etching selectivity for the first dielectric layer 22. As a result, when the first etching gas etches to the first dielectric layer 22, it stops at the top surface of the first dielectric layer 22.

[0104] In one example, under standard temperature (25°C) and pressure (1 atmosphere), the flow rate of carbon tetrafluoride (CF4) can be 100 SCCM (standard milliliters / minute) to 600 SCCM, the flow rate of hydrogen bromide (HBr) can be 100 SCCM to 400 SCCM, and the flow rate of chlorine can be 10 SCCM to 100 SCCM.

[0105] It is understandable that when the material of the second electrode layer 23 changes, the composition of the first etching gas can be adjusted accordingly, as long as the first etching gas has a high selectivity for the second electrode layer 23 and the second dielectric layer 24, while having an extremely low selectivity for the first dielectric layer 22.

[0106] The method for fabricating the semiconductor structure, in which the second dielectric layer 24 and the second electrode layer 23 are etched using the first etching gas, further includes:

[0107] Step S311: Use a first etching protective gas to protect the sidewall of the first etched hole.

[0108] In this step, refer to Figure 6 and Figure 7 The first etching protective gas can be oxygen (O2), and the oxygen flow rate can be 10 SCCM to 100 SCCM under standard temperature and pressure conditions. During the etching of the deep trench capacitor 20 using the first etching gas, after the first etching gas etches away the second electrode layer 23, exposing the sidewalls of the second electrode layer 23, the forming time of the first etched hole 30 is uncontrollable. This may cause the first etching gas to laterally etch away the exposed sidewalls of the second electrode layer 23, forming an air gap of uncertain size. If the air gap is too large, it may cause the deep trench capacitor 20 structure to collapse; if the air gap is too small, it may result in poor leakage isolation capability.

[0109] Therefore, during the process of using the first etching gas to form the first etching hole 30, the first etching protective gas is simultaneously introduced into the sidewall of the first etching hole 30 to prevent the first etching gas from etching away the second electrode layer 23 in the horizontal direction.

[0110] In one example, refer to Figure 2 After the first etched hole 30 is formed, the first photoresist layer 91 can be removed by cleaning and ashing processes to prevent photoresist residue from remaining in the semiconductor structure 100.

[0111] In some embodiments, after forming the first etched hole 30, removing a portion of the sidewall of the second electrode layer 23 exposed within the first etched hole 30 to form a first air gap 50 may include the following steps:

[0112] Step S410: Use a second etching gas to etch a portion of the sidewall of the second electrode layer exposed within the first etched hole.

[0113] In this step, the second etching gas includes any one or more of carbon tetrafluoride (CF4), hydrogen bromide (HBr), and chlorine (Cl2).

[0114] In some embodiments, the flow rates of hydrogen bromide (HBr) and chlorine (Cl2) are increased compared to the first etching gas, so that the second etching gas does not affect the second dielectric layer 24 when etching away the second electrode layer 23.

[0115] The method for fabricating the semiconductor structure, in which the first air gap 50 is formed by etching with a second etching gas, further includes:

[0116] Step S411: Use a second etching protective gas to protect the sidewall of the first etched hole.

[0117] In this step, refer to Figure 7 The second etching protective gas can be oxygen (O2). Compared with the first etching protective gas, the flow rate of oxygen (O2) is reduced. That is to say, the protective ability of the second etching protective gas on the sidewall of the first etching hole 30 is weakened (the blocking ability of the second etching gas is weakened). As a result, the second etching protective gas can etch the sidewall of the second electrode layer 23, so that the second electrode layer 23 is recessed inward from the sidewall to form the first air gap 50.

[0118] The size of the first air gap 50 can be adjusted by controlling the etching time of the second etching gas. For example, the longer the second etching gas is introduced, the larger the first air gap 50 becomes in the horizontal direction. Figure 2 The larger the size of the indentation in the x-direction shown, the greater the size of the indentation.

[0119] In some embodiments, after step S410, that is, after removing the portion of the sidewall of the second electrode layer 23 exposed within the first etched hole 30 to form the first air gap 50, the method for fabricating the semiconductor structure may further include the following steps:

[0120] Step S420: Etch the first dielectric layer along the first etching hole, so that a portion of the top surface of the first electrode layer is exposed in the first etching hole.

[0121] In this step, refer to Figure 7 The first dielectric layer 22 can be etched using a third etching gas. The third etching gas includes boron trichloride (BCl3), argon (Ar), and chlorine (Cl2). Among them, argon (Ar) can etch the first dielectric layer 22 by physical bombardment.

[0122] In one example, the argon flow rate can be from 100 SCCM to 1000 SCCM.

[0123] During the etching of the first dielectric layer 22, nitrogen gas (N2) can be introduced into the sidewall of the first etched hole 30. The nitrogen gas (N2) serves as an etching protection gas during the etching of the first dielectric layer 22 to prevent the second electrode layer 23 and the second dielectric layer 24 from being etched. In one example, the flow rate of nitrogen gas can be 0 to 200 SCCM.

[0124] In one exemplary embodiment, after forming the first air gap, the method for fabricating the semiconductor structure further includes:

[0125] In step S500, a second etched hole is formed. The second etched hole penetrates the second dielectric layer along the depth direction of the deep trench capacitor, exposing part of the top surface of the second electrode layer inside the second etched hole.

[0126] In this step, refer to Figure 8 A patterned second photoresist layer 92 can be formed on the top surface of the deep trench capacitor 20, and the patterned second photoresist layer 92 defines the size and position of the second etched hole 40.

[0127] Photolithography and etching processes can be used to remove part of the structure of the second dielectric layer 24 to form a second etching hole 40 in the second dielectric layer 24. The second etching hole 40 exposes part of the top surface of the second electrode layer 23 located below the second dielectric layer 24.

[0128] In one example, refer to Figure 9 After the second etched hole 40 is formed, the second photoresist layer 92 can be removed by processes such as cleaning and ash to prevent photoresist residue from remaining in the semiconductor structure 100.

[0129] In some embodiments, after forming the second etched hole 40, the method for fabricating the semiconductor structure further includes:

[0130] Step S600: An interlayer dielectric layer is formed, which covers the deep trench capacitor and fills the first and second etched vias.

[0131] In this step, refer to Figure 10An interlayer dielectric layer 80 can be formed using a deposition process. The interlayer dielectric layer 80 is made of an insulating material, such as silicon dioxide (SiO2) or other oxides. The interlayer dielectric layer 80 covers the top surface of the deep trench capacitor 20, protecting it and improving its performance. This includes preventing damage from physical contact with external devices and avoiding signal interference from external devices. The interlayer dielectric layer 80 fills the first etched via 30 and the second etched via 40. In subsequent processes, the shape and position of the first and second contact holes can be defined on the top surface of the interlayer dielectric layer 80 according to usage requirements, ensuring that the first contact plug 25 is far from the edge of the second electrode layer 23.

[0132] In step S700, a first contact hole and a second contact hole are formed in the interlayer dielectric layer. The first contact hole penetrates the interlayer dielectric layer filling the first etched hole, exposing a portion of the top surface of the first electrode layer. The second contact hole penetrates the interlayer dielectric layer filling the first etched hole, exposing a portion of the top surface of the second electrode layer.

[0133] In this step, refer to Figure 3 Photolithography, etching, and other processes can be used to remove part of the structure of the interlayer dielectric layer 80 to form a first contact hole and a second contact hole in the interlayer dielectric layer 80. The first contact hole is along the thickness direction of the substrate 10. Figure 3 The second contact hole penetrates the interlayer dielectric layer 80 along the z-direction shown in the figure until a portion of the top surface of the first electrode layer 21 (lower electrode) is exposed. The second contact hole penetrates the interlayer dielectric layer 80 along the thickness direction of the substrate 10 until a portion of the top surface of the second electrode layer 23 (upper electrode) is exposed.

[0134] In step S800, a first contact plug is formed in the first contact hole to contact the top surface of the first electrode layer, and a second contact plug is formed in the second contact hole to contact the top surface of the second electrode layer.

[0135] In this step, refer to Figure 3 The first contact plug 25 can be formed in the first contact hole using processes such as electroplating or deposition, and the second contact plug 26 can be formed in the second contact hole. The bottom of the first contact plug 25 is connected to the exposed top surface of the first electrode layer 21, and the top surface of the first contact plug 25 can be connected to an external device. The bottom of the second contact plug 26 is connected to the exposed top surface of the second electrode layer 23, and the top surface of the second contact plug 26 can be connected to an external device. It is understood that the external device can supply power to the first electrode layer 21 through the first contact plug 25 and supply power to the second electrode layer 23 through the second contact plug 26, so that the deep trench capacitor 20 can operate.

[0136] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0137] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0138] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0139] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0140] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0141] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0142] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A semiconductor structure, comprising: a substrate having a top surface with a trench extending into the substrate; a deep trench capacitor comprising a first electrode layer, a first dielectric layer, a second electrode layer, and a second dielectric layer sequentially conformally stacked on an inner surface of the trench and the top surface of the substrate; a first etch hole and a second etch hole sequentially penetrating through the second dielectric layer, the second electrode layer, and the first dielectric layer along a depth direction of the deep trench capacitor; the second etch hole penetrating through the second dielectric layer along the depth direction of the deep trench capacitor; an interlayer dielectric layer covering the deep trench capacitor and filling the first etch hole and the second etch hole; a first air gap between the first dielectric layer and the second dielectric layer, and between the second electrode layer and the interlayer dielectric layer, the first air gap being recessed from a surface of the second electrode layer exposed in the first etch hole towards an interior of the second electrode layer, and the first air gap exposing a portion of the first dielectric layer and the second dielectric layer within the first air gap; and wherein a thickness of the first electrode layer is greater than a thickness of the second electrode layer. 2.The semiconductor structure of claim 1, wherein a ratio of a recess depth of the first air gap in the second electrode layer to a height of the first air gap is in a range of 0.6-7:

1. 3.The semiconductor structure of claim 1, wherein a portion of the second dielectric layer in the trench forms a second air gap; and the semiconductor structure further comprises a fill layer covering the second dielectric layer on the top surface of the substrate and filling the second air gap. 4.The semiconductor structure of claim 3, wherein a material of the first dielectric layer comprises a high dielectric constant material; and / or a material of the second dielectric layer comprises polysilicon; and / or a material of the fill layer comprises an oxide. 5.The semiconductor structure of claim 1, wherein a first contact hole and a second contact hole are provided in the interlayer dielectric layer, the first contact hole penetrating through the interlayer dielectric layer filling the first etch hole and exposing a portion of a top surface of the first electrode layer, and the second contact hole penetrating through the interlayer dielectric layer filling the second etch hole and exposing a portion of a top surface of the second electrode layer; a first contact plug is provided in the first contact hole, a bottom end of the first contact plug being in contact with the first electrode layer; and a second contact plug is provided in the second contact hole, a bottom end of the second contact plug being in contact with the second electrode layer. 6.The semiconductor structure of claim 5, wherein a material of the interlayer dielectric layer comprises an oxide. 7.A method for manufacturing the semiconductor structure of claims 1-6, comprising: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ A substrate is provided, a top surface of the substrate is provided with a trench extending to an inside of the substrate; A deep trench capacitor is formed, the deep trench capacitor comprises a first electrode layer, a first dielectric layer, a second electrode layer and a second dielectric layer which are sequentially and conformally stacked on an inner surface of the trench and the top surface of the substrate; A first etching hole is formed, the first etching hole penetrates the second dielectric layer and the second electrode layer in sequence along a depth direction of the deep trench capacitor, so that a part of the top surface of the first dielectric layer and a sidewall of the second electrode layer are exposed in the first etching hole; A part of the sidewall of the second electrode layer exposed in the first etching hole is removed to form a first air gap, the first air gap is located between the first dielectric layer and the second dielectric layer, and the first air gap exposes a part of the surfaces of the first dielectric layer and the second dielectric layer in the first air gap.

8. The method of claim 7, wherein forming the first etching hole comprises: etching the second dielectric layer and the second electrode layer using a first etching gas, the first etching gas comprising any one or more of carbon tetrafluoride, hydrogen bromide, and chlorine.

9. The method of claim 8, wherein removing the part of the sidewall of the second electrode layer exposed in the first etching hole to form the first air gap comprises: etching the part of the sidewall of the second electrode layer exposed in the first etching hole using a second etching gas, the second etching gas comprising any one or more of carbon tetrafluoride, hydrogen bromide, and chlorine.

10. The method of claim 9, wherein a flow rate of the second etching gas is greater than a flow rate of the first etching gas.

11. The method of claim 7, wherein, after removing the part of the sidewall of the second electrode layer exposed in the first etching hole to form the first air gap, the method further comprises: etching the first dielectric layer along the first etching hole to expose a part of the top surface of the first electrode layer in the first etching hole.

12. The method of claim 11, wherein etching the first dielectric layer along the first etching hole comprises: etching the first dielectric layer using a third etching gas, the third etching gas comprising any one or more of boron trichloride, argon, and chlorine.

13. The method of claim 7, wherein the method further comprises: forming a second etching hole, the second etching hole penetrating the second dielectric layer along the depth direction of the deep trench capacitor to expose a part of the top surface of the second electrode layer in the second etching hole.

14. The method of claim 13, wherein, after forming the second etching hole, the method further comprises: forming an interlayer dielectric layer, the interlayer dielectric layer covering the deep trench capacitor and filling the first etching hole and the second etching hole. ​ ​ ​ ​ ​ ​ ​ forming a first contact hole and a second contact hole in the interlayer dielectric layer, the first contact hole penetrating the interlayer dielectric layer filled in the first etching hole to expose a part of the top surface of the first electrode layer, the second contact hole penetrating the interlayer dielectric layer filled in the first etching hole to expose a part of the top surface of the second electrode layer; forming a first contact plug in the first contact hole to contact the top surface of the first electrode layer, and forming a second contact plug in the second contact hole to contact the top surface of the second electrode layer.

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