A metal oxide - field effect transistor power device and its manufacturing method

Abstract

The present invention discloses a metal-oxide field-effect transistor power device and a manufacturing method thereof. Among them, the device includes: a substrate; an epitaxial layer, which is located on one side of the substrate, and a drift region and a body region are provided on the side of the epitaxial layer away from the substrate; a first-polarity crystal epitaxial layer, which includes at least two sub-epitaxial layers, and in the direction perpendicular to the substrate and pointing to the epitaxial layer, the opposite surfaces of two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families; the conductivity type of the first-polarity crystal epitaxial layer is opposite to that of the body region; a gate structure, which is located on the side of the epitaxial layer away from the substrate; a source electrode, which is located on the side of the epitaxial layer away from the substrate and covers part of the first active region; and a drain electrode, which is located on the side of the substrate away from the epitaxial layer. The technical solution provided by the embodiments of the present invention effectively reduces the on-resistance of the metal-oxide field-effect transistor power device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a metal oxide-field effect transistor power device and a preparation method thereof. Background Art

[0002] Compared with silicon-based metal-oxide-semiconductor field effect transistors (MOSFETs), the third-generation semiconductor MOSFET devices have advantages such as high voltage resistance, high temperature resistance, and low power consumption, and have great application potential in industries such as smart grids and new energy vehicles.

[0003] The third-generation semiconductor MOSFET devices are represented by SiC MOSFET devices and GaN field effect transistors (FETs) / GaN high electron mobility transistors (HEMTs). However, the on-resistance of the current third-generation semiconductor MOSFET devices is difficult to meet the requirements. Effectively reducing the on-resistance of the third-generation semiconductor MOSFET devices is the main problem that power device engineers need to consider in the design stage. Summary of the Invention

[0004] The present invention provides a metal oxide-field effect transistor power device and a preparation method thereof to reduce the on-resistance of the MOSFET power device.

[0005] In a first aspect, the present invention provides a metal-oxide field effect transistor power device, wherein the device includes:

[0006] A substrate;

[0007] An epitaxial layer, the epitaxial layer is located on one side of the substrate, and a drift region and a body region are provided on the side of the epitaxial layer away from the substrate;

[0008] A first-polarity crystal epitaxial layer, the first-polarity crystal epitaxial layer is embedded in the body region, and the first-polarity crystal epitaxial layer includes at least two sub-epitaxial layers; in the direction perpendicular to the substrate and pointing to the epitaxial layer, the opposite surfaces of two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families; the conductivity type of the first-polarity crystal epitaxial layer is opposite to that of the body region; the first-polarity crystal epitaxial layer constitutes the first active region of the active region;

[0009] A gate structure, the gate structure is located on the side of the epitaxial layer away from the substrate;

[0010] A source electrode, the source electrode is located on the side of the epitaxial layer away from the substrate and covers a part of the first active region;

[0011] The drain, and the drain is located on the side of the substrate away from the epitaxial layer.

[0012] Optionally, the metal-oxide field-effect transistor power device further includes a second-polarity crystal epitaxial layer, the second-polarity crystal epitaxial layer is embedded in the body region, the second-polarity crystal epitaxial layer and the first-polarity crystal epitaxial layer are arranged adjacent to each other, and the second-polarity crystal epitaxial layer includes at least two sub-epitaxial layers; in the direction perpendicular to the substrate and pointing to the epitaxial layer, the opposite surfaces of two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families; the conductivity type of the second-polarity crystal epitaxial layer is the same as that of the body region; the second-polarity crystal epitaxial layer constitutes the second active region of the active region.

[0013] Optionally, the metal-oxide field-effect transistor power device includes at least one of a planar structure, a single-groove structure, and a double-groove structure.

[0014] Optionally, the metal-oxide field-effect transistor power device includes a planar structure;

[0015] The metal-oxide field-effect transistor power device is provided with a JFET region;

[0016] The metal-oxide field-effect transistor power device further includes a third-polarity crystal epitaxial layer, the third-polarity crystal epitaxial layer is located in the JFET region, and the third-polarity crystal epitaxial layer includes at least two sub-epitaxial layers; in the direction perpendicular to the substrate and pointing to the epitaxial layer, the opposite surfaces of two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families.

[0017] Optionally, the substrate includes a silicon carbide substrate, the epitaxial layer includes a silicon carbide epitaxial layer, and the sub-epitaxial layer includes a silicon carbide sub-epitaxial layer;

[0018] In the direction perpendicular to the substrate and pointing to the epitaxial layer, the opposite surfaces of two adjacent sub-epitaxial layers belong to crystal planes of at least two crystal plane families among the {0001} crystal plane family, the {0338} crystal plane family, the {1010} crystal plane family, and the {1120} crystal plane family.

[0019] Optionally, in the direction perpendicular to the substrate and pointing to the epitaxial layer, the opposite surfaces of two adjacent sub-epitaxial layers respectively belong to crystal planes in the {0001} crystal plane family and the {0338} crystal plane family.

[0020] Optionally, in the direction perpendicular to the substrate and pointing to the epitaxial layer, the opposite surfaces of two adjacent sub-epitaxial layers are respectively the (0001) crystal plane and the (0338) crystal plane.

[0021] Optionally, the silicon carbide epitaxial layer includes a 4H-SiC epitaxial layer.

[0022] Optionally, the substrate comprises a silicon carbide substrate, the epitaxial layer comprises a gallium nitride epitaxial layer, and the sub-epitaxial layer comprises a gallium nitride sub-epitaxial layer.

[0023] Optionally, the substrate is a polar crystal substrate, and the epitaxial layer is a polar crystal epitaxial layer;

[0024] The opposite surfaces of the substrate and the epitaxial layer belong to the crystal planes of the same crystal plane family.

[0025] Optionally, the substrate comprises a silicon carbide substrate, the epitaxial layer comprises a silicon carbide epitaxial layer, and the sub-epitaxial layer comprises a silicon carbide sub-epitaxial layer; the opposite surfaces of the substrate and the epitaxial layer are (0001) crystal planes.

[0026] In a second aspect, the present invention provides a method for manufacturing a metal-oxide field-effect transistor power device, wherein the method comprises:

[0027] Providing a substrate;

[0028] Forming an epitaxial layer on one side of the substrate, wherein a drift region and a body region are provided on the side of the epitaxial layer away from the substrate;

[0029] Forming a first polar crystal epitaxial layer, wherein the first polar crystal epitaxial layer is embedded in the body region, the first polar crystal epitaxial layer comprises at least two sub-epitaxial layers, and in the direction perpendicular to the substrate and pointing to the epitaxial layer, the opposite surfaces of two adjacent sub-epitaxial layers belong to the crystal planes of different crystal plane families; the conduction type of the first polar crystal epitaxial layer is opposite to that of the body region; the first polar crystal epitaxial layer constitutes the first active region of the active region;

[0030] Forming a gate structure on the side of the epitaxial layer away from the substrate;

[0031] Forming a source electrode on the side of the epitaxial layer away from the substrate, wherein the source electrode covers a part of the first active region;

[0032] Forming a drain electrode on the side of the substrate away from the epitaxial layer.

[0033] In the technical solution of the present invention, the first polar crystal epitaxial layer constitutes the first active region of the active region. The first polar crystal epitaxial layer is provided with at least two sub-epitaxial layers, and in the direction perpendicular to the substrate and pointing to the epitaxial layer, the opposite surfaces of two adjacent sub-epitaxial layers belong to the crystal planes of different crystal plane families, that is, the crystal planes corresponding to the opposite surfaces of two adjacent sub-epitaxial layers have different lattice constants, so that local strain exists between the opposite surfaces of two adjacent sub-epitaxial layers, thereby effectively improving the carrier mobility, reducing the on-resistance of the metal-oxide field-effect transistor power device, and increasing the current density of the same chip area.

[0034] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become readily understood from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0036] Figure 1 is a schematic structural diagram of a metal-oxide field-effect transistor power device provided by an embodiment of the present invention;

[0037] Figure 2 is a schematic structural diagram of another metal-oxide field-effect transistor power device provided by an embodiment of the present invention;

[0038] Figure 3 is a schematic structural diagram of yet another metal-oxide field-effect transistor power device provided by an embodiment of the present invention;

[0039] Figure 4 is a schematic structural diagram of yet another metal-oxide field-effect transistor power device provided by an embodiment of the present invention;

[0040] Figure 5 is a schematic structural diagram of yet another metal-oxide field-effect transistor power device provided by an embodiment of the present invention;

[0041] Figure 6 is a schematic structural diagram of yet another metal-oxide field-effect transistor power device provided by an embodiment of the present invention;

[0042] Figure 7 is a schematic structural diagram of yet another metal-oxide field-effect transistor power device provided by an embodiment of the present invention;

[0043] Figure 8 is a schematic structural diagram of yet another metal-oxide field-effect transistor power device provided by an embodiment of the present invention;

[0044] Figure 9 is a schematic structural diagram of yet another metal-oxide field-effect transistor power device provided by an embodiment of the present invention;

[0045] Figure 10 is a schematic structural diagram of yet another metal-oxide field-effect transistor power device provided by an embodiment of the present invention;

[0046] Figure 11 It is a flowchart of a method for manufacturing a metal-oxide field-effect transistor power device provided by an embodiment of the present invention;

[0047] Figures 12 - 16 It is a structural diagram corresponding to each step of a method for manufacturing a metal-oxide field-effect transistor power device provided by an embodiment of the present invention. Detailed implementation manners

[0048] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0049] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0050] Figure 1 It is a schematic structural diagram of a metal-oxide field-effect transistor power device provided by an embodiment of the present invention, Figure 2 It is a schematic structural diagram of another metal-oxide field-effect transistor power device provided by an embodiment of the present invention, Figure 3 It is a schematic structural diagram of yet another metal-oxide field-effect transistor power device provided by an embodiment of the present invention, such as Figures 1 - 3As shown, the metal-oxide field-effect transistor power device includes: a substrate 1; an epitaxial layer 2, which is located on one side of the substrate 1, and a drift region 21 and a body region 22 are provided on the side of the epitaxial layer 2 away from the substrate 1. A first-polarity crystal epitaxial layer 23 is embedded in the body region 22. The first-polarity crystal epitaxial layer 23 includes at least two sub-epitaxial layers; in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, the opposite surfaces of at least two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families. The conductivity type of the first-polarity crystal epitaxial layer 23 is opposite to that of the body region 22. The first-polarity crystal epitaxial layer 23 constitutes the first active region of the active region; a gate structure 3, and the gate structure 3 is located on the side of the epitaxial layer 2 away from the substrate 1. A source electrode 4, and the source electrode 4 is located on the side of the epitaxial layer 2 away from the substrate 1 and covers part of the first active region. A drain electrode 5, and the drain electrode 5 is located on the side of the substrate 1 away from the epitaxial layer 2.

[0051] Specifically, the metal-oxide field-effect transistor power device may include an N-channel metal-oxide field-effect transistor power device or a P-channel metal-oxide field-effect transistor power device. Exemplarily, for an N-channel metal-oxide field-effect transistor power device, the substrate 1 is an N-substrate, the epitaxial layer 2 is an N-epitaxial layer, the drift region 21 is an N-drift region, and the body region 22 is a P-body region; the first-polarity crystal epitaxial layer 23 is an N++ first-polarity crystal epitaxial layer. For a P-channel metal-oxide field-effect transistor power device, the substrate 1 is a P-substrate, the epitaxial layer 2 is a P-epitaxial layer, the drift region 21 is a P-drift region, and the body region 22 is an N-body region; the first-polarity crystal epitaxial layer 23 is a P++ first-polarity crystal epitaxial layer.

[0052] The gate structure 3 includes a gate dielectric layer 31 and a gate conductive layer 32. The gate dielectric layer 31 can be an insulating dielectric layer such as silicon oxide or borophosphosilicate glass. The first-polarity crystal epitaxial layer 23 may include at least two sub-epitaxial layers, and the types and specific numbers of the sub-epitaxial layers in the first-polarity crystal epitaxial layer 23 are not specifically limited herein. As Figures 1 - 3 shown, taking the first-polarity crystal epitaxial layer 23 including two sub-epitaxial layers as an example, the first-polarity crystal epitaxial layer 23 includes a first sub-epitaxial layer 231 and a second sub-epitaxial layer 232. The first sub-epitaxial layer 231 and the second sub-epitaxial layer 232 can be spaced apart in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, and in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, the opposite surfaces of the first sub-epitaxial layer 231 and the second sub-epitaxial layer 232 belong to crystal planes of different crystal plane families. The first-polarity crystal epitaxial layer 23 constitutes the first active region and is in contact with the source electrode 4. In other embodiments, in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, multiple first sub-epitaxial layers 231 can also be continuously arranged, and multiple second sub-epitaxial layers 232 can also be continuously arranged.

[0053] Exemplarily, for an N-channel metal-oxide field-effect transistor power device, the first-polarity crystal epitaxial layer 23 is an N++ first-polarity crystal epitaxial layer, and the first active region is an N++ active region. For a P-channel metal-oxide field-effect transistor power device, the first-polarity crystal epitaxial layer 23 is a P++ first-polarity crystal epitaxial layer, and the first active region is a P++ active region. As Figures 1 - 3 shown, the active region may only include the first active region. As Figures 4 - 6 shown, Figure 4 is a schematic structural diagram of another metal-oxide field-effect transistor power device provided by an embodiment of the present invention, Figure 5 is a schematic structural diagram of another metal-oxide field-effect transistor power device provided by an embodiment of the present invention, Figure 6 is a schematic structural diagram of another metal-oxide field-effect transistor power device provided by an embodiment of the present invention. The active region may further include a first active region and a second active region 26. The conduction types of the first active region and the second active region 26 are different. The conduction types of the second active region 26 and the body region 22 are the same. The doping concentration of the second active region 26 is greater than that of the body region 22.

[0054] In the technical solution of the embodiment of the present invention, the first-polarity crystal epitaxial layer 23 constitutes the first active region of the active region. The first-polarity crystal epitaxial layer 23 is provided to include at least two sub-epitaxial layers. And in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, the opposite surfaces of two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families, that is, the crystal planes corresponding to the opposite surfaces of two adjacent sub-epitaxial layers have different lattice constants. Thus, local strain exists between the opposite surfaces of two adjacent sub-epitaxial layers, thereby effectively improving the carrier mobility, reducing the on-resistance of the metal-oxide field-effect transistor power device, and increasing the current density of the same chip area.

[0055] It should be noted that since the crystal planes corresponding to the opposite surfaces of two adjacent sub-epitaxial layers have a certain included angle, in the drawings of the embodiment of the present invention, there is a certain included angle between the opposite surfaces of two adjacent sub-epitaxial layers and the direction perpendicular to the substrate 1.

[0056] Optionally, on the basis of the above embodiment, Figure 7 is a schematic structural diagram of another metal-oxide field-effect transistor power device provided by an embodiment of the present invention, Figure 8 is a schematic structural diagram of another metal-oxide field-effect transistor power device provided by an embodiment of the present invention, Figure 9 is a schematic structural diagram of another metal-oxide field-effect transistor power device provided by an embodiment of the present invention. As Figures 7 - 9As shown, the metal-oxide field-effect transistor power device further includes a second-polarity crystal epitaxial layer 24. The second-polarity crystal epitaxial layer 24 is embedded in the body region 22. The second-polarity crystal epitaxial layer 24 and the first-polarity crystal epitaxial layer 23 are arranged adjacent to each other. The second-polarity crystal epitaxial layer 24 includes at least two sub-epitaxial layers. In the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, the opposite surfaces of two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families. The conductivity type of the second-polarity crystal epitaxial layer 24 is the same as that of the body region 22. The second-polarity crystal epitaxial layer 24 constitutes the second active region of the active region.

[0057] Exemplarily, for an N-channel metal-oxide field-effect transistor power device, the second-polarity crystal epitaxial layer 24 is a P++ second-polarity crystal epitaxial layer, and the second active region is a P++ second active region. For a P-channel metal-oxide field-effect transistor power device, the second-polarity crystal epitaxial layer 24 is an N++ second-polarity crystal epitaxial layer, and the second active region is an N++ second active region. The conductivity type of the second-polarity crystal epitaxial layer 24 is different from that of the first-polarity crystal epitaxial layer 23. The conductivity type of the second-polarity crystal epitaxial layer 24 is the same as that of the body region 22. The doping concentration of the second-polarity crystal epitaxial layer 24 is greater than that of the body region 22.

[0058] Specifically, the metal-oxide field-effect transistor may further include a second-polarity crystal epitaxial layer 24. The second-polarity crystal epitaxial layer 24 may be disposed inside the body region 22, and the second-polarity crystal epitaxial layer 24 and the first-polarity crystal epitaxial layer 23 are arranged adjacent to each other.

[0059] The second-polarity crystal epitaxial layer 24 may include at least two sub-epitaxial layers. The types and specific numbers of the sub-epitaxial layers in the second-polarity crystal epitaxial layer 24 are not specifically limited herein. As Figures 7 - 9 shown, taking the second-polarity crystal epitaxial layer 24 including two sub-epitaxial layers as an example, the second-polarity crystal epitaxial layer 24 includes a third sub-epitaxial layer 241 and a fourth sub-epitaxial layer 242. The third sub-epitaxial layer 241 and the fourth sub-epitaxial layer 242 may be arranged at intervals in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2. In the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, the opposite surfaces of the third sub-epitaxial layer 241 and the fourth sub-epitaxial layer 242 belong to crystal planes of different crystal plane families. In other embodiments, in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, multiple third sub-epitaxial layers 241 may also be arranged continuously, and multiple fourth sub-epitaxial layers 242 may also be arranged continuously.

[0060] Specifically, the crystal planes corresponding to the opposite surfaces of two adjacent sub-epitaxial layers in the second-polarity crystal epitaxial layer 24 have different lattice constants, so that local strain exists between the opposite surfaces of the two adjacent sub-epitaxial layers, thereby further effectively improving the carrier mobility, further reducing the on-resistance of the metal-oxide field-effect transistor power device, and further increasing the current density of the same chip area.

[0061] Optionally, based on the above embodiments, the metal-oxide field-effect transistor power device includes at least one of a planar structure, a single-groove structure, and a double-groove structure.

[0062] Take Figure 1 as an example. The metal-oxide field-effect transistor includes a planar structure, and at this time, the gate structure 3 is a planar gate structure.

[0063] Take Figure 2 as an example. The metal-oxide field-effect transistor includes a single-groove structure, and at this time, the gate structure 3 is a groove gate structure. Exemplarily, the groove gate structure penetrates through the first-polarity crystal epitaxial layer 23 and the body region 22 and is embedded on the side of the epitaxial layer 2 away from the substrate 1. And the groove gate structure extends from the first-polarity crystal epitaxial layer 23 through the body region 22 to a partial region of the drift region 21. The gate conductive layer 32 is located in the gate dielectric layer 31, and the gate dielectric layer 31 is in contact with the first-polarity crystal epitaxial layer 23, the body region 22, and the drift region 21. Compared with the planar structure, the setting of the groove gate structure has no JFET region with a large resistance, thereby reducing the on-resistance of the metal-oxide field-effect transistor device.

[0064] Take Figure 3 as an example. The metal-oxide field-effect transistor includes a double-groove structure, and at this time, the gate structure 3 is a groove gate structure and the source 4 is a groove source structure. Exemplarily, the groove gate structure penetrates through the first-polarity crystal epitaxial layer 23 and the body region 22 and is embedded on the side of the epitaxial layer 2 away from the substrate 1. And the groove gate structure extends from the first-polarity crystal epitaxial layer 23 through the body region 22 to a partial region of the drift region 21. The gate conductive layer 32 is located in the gate dielectric layer 31, and the gate dielectric layer 31 is in contact with the first-polarity crystal epitaxial layer 23, the body region 22, and the drift region 21. The groove source structure penetrates through the first-polarity crystal epitaxial layer 23 and extends to a partial region of the body region 22. The groove source structure can effectively relieve the electric field distribution under the gate dielectric layer 31 of the groove gate structure close to the epitaxial layer 2.

[0065] Optionally, based on the above embodiments, as Figure 10 shown, Figure 10FIG. 0 is a schematic structural diagram of another metal-oxide field-effect transistor power device provided by an embodiment of the present invention. For a planar metal-oxide field-effect transistor power device, the metal-oxide field-effect transistor power device includes a planar structure. The metal-oxide field-effect transistor power device is provided with a JFET region. The metal-oxide field-effect transistor power device further includes a third-polarity crystal epitaxial layer 25, and the third-polarity crystal epitaxial layer 25 is located in the JFET region. The third-polarity crystal epitaxial layer 25 includes at least two sub-epitaxial layers; in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, the opposite surfaces of two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families.

[0066] Specifically, the JFET region is located on one side of the body region 22 and between the gate structure 3 and the drift region 21. The third-polarity crystal epitaxial layer 25 is disposed in the JFET region. The third-polarity crystal epitaxial layer 25 may include at least two sub-epitaxial layers, and the types and numbers of the sub-epitaxial layers in the third-polarity crystal epitaxial layer 25 are not specifically limited herein. As Figure 10 shown, taking the third-polarity crystal epitaxial layer 25 including two sub-epitaxial layers as an example, the third-polarity crystal epitaxial layer 25 includes a fifth sub-epitaxial layer 251 and a sixth sub-epitaxial layer 252. The fifth sub-epitaxial layer 251 and the sixth sub-epitaxial layer 252 may be arranged at intervals in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, and in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, the opposite surfaces of the fifth sub-epitaxial layer 251 and the sixth sub-epitaxial layer 252 belong to crystal planes of different crystal plane families. In other embodiments, and in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, a plurality of fifth sub-epitaxial layers 251 may also be arranged continuously, and a plurality of sixth sub-epitaxial layers 252 may also be arranged continuously.

[0067] Specifically, at least two sub-epitaxial layers are disposed in the JFET region, and the opposite surfaces of two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families. The two different crystal planes have different lattice constants, so that local strain exists between the opposite surfaces of two adjacent sub-epitaxial layers, thereby further effectively improving the carrier mobility, further reducing the on-resistance of the metal-oxide field-effect transistor power device, and further increasing the current density of the same chip area.

[0068] Optionally, on the basis of the above embodiments, as Figures 1 - 10 shown, the substrate 1 includes a silicon carbide substrate, the epitaxial layer 2 includes a silicon carbide epitaxial layer, and the sub-epitaxial layer includes a silicon carbide sub-epitaxial layer. In the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, the opposite surfaces of two adjacent sub-epitaxial layers belong to crystal planes of at least two crystal plane families among the {0001} crystal plane family, the {0338} crystal plane family, the {1010} crystal plane family, and the {1120} crystal plane family.

[0069] Specifically, asFigures 1 - 3 As shown, the first-polarity crystal epitaxial layer 23 includes a first sub-epitaxial layer 231 and a second sub-epitaxial layer 232. The surface of the first sub-epitaxial layer 231 adjacent to the second sub-epitaxial layer 232 and the surface of the second sub-epitaxial layer 232 adjacent to the first sub-epitaxial layer 231 are set as crystal planes of different crystal plane families. The first sub-epitaxial layer 231 and the second sub-epitaxial layer 232 can be silicon carbide sub-epitaxial layers. In the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, the surface of the first sub-epitaxial layer 231 adjacent to the second sub-epitaxial layer 232 can be a crystal plane of any one of the {0001} crystal plane family, {0338} crystal plane family, {1010} crystal plane family, and {1120} crystal plane family. The surface of the second sub-epitaxial layer 232 adjacent to the first sub-epitaxial layer 231 can be a crystal plane of any one of the {0001} crystal plane family, {0338} crystal plane family, {1010} crystal plane family, and {1120} crystal plane family, but is set as a crystal plane of a different crystal plane family from the surface of the first sub-epitaxial layer 231 adjacent to the second sub-epitaxial layer 232.

[0070] As Figures 7 - 9 As shown, the second-polarity crystal epitaxial layer 24 includes a third sub-epitaxial layer 241 and a fourth sub-epitaxial layer 242. The surface of the third sub-epitaxial layer 241 adjacent to the fourth sub-epitaxial layer 242 and the surface of the fourth sub-epitaxial layer 242 adjacent to the third sub-epitaxial layer 241 are set as crystal planes of different crystal plane families. The third sub-epitaxial layer 241 and the fourth sub-epitaxial layer 242 can be silicon carbide sub-epitaxial layers. In the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, the surface of the third sub-epitaxial layer 241 adjacent to the fourth sub-epitaxial layer 242 can be a crystal plane of any one of the {0001} crystal plane family, {0338} crystal plane family, {1010} crystal plane family, and {1120} crystal plane family. The surface of the fourth sub-epitaxial layer 242 adjacent to the third sub-epitaxial layer 241 can be a crystal plane of any one of the {0001} crystal plane family, {0338} crystal plane family, {1010} crystal plane family, and {1120} crystal plane family, but is set as a crystal plane of a different crystal plane family from the surface of the third sub-epitaxial layer 241 adjacent to the fourth sub-epitaxial layer 242.

[0071] As Figure 10As shown, the third-polarity crystal epitaxial layer 25 includes a fifth sub-epitaxial layer 251 and a sixth sub-epitaxial layer 252. The surface of the fifth sub-epitaxial layer 251 adjacent to the sixth sub-epitaxial layer 252 and the surface of the sixth sub-epitaxial layer 252 adjacent to the fifth sub-epitaxial layer 251 are set as crystal planes of different crystal plane families. The fifth sub-epitaxial layer 251 and the sixth sub-epitaxial layer 252 can be silicon carbide sub-epitaxial layers. In the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, the surface of the fifth sub-epitaxial layer 251 adjacent to the sixth sub-epitaxial layer 252 can be a crystal plane of any one of the {0001} crystal plane family, {0338} crystal plane family, {1010} crystal plane family, and {1120} crystal plane family. The surface of the sixth sub-epitaxial layer 252 adjacent to the fifth sub-epitaxial layer 251 can be a crystal plane of any one of the {0001} crystal plane family, {0338} crystal plane family, {1010} crystal plane family, and {1120} crystal plane family, but is set as a crystal plane of a different crystal plane family from the surface of the fifth sub-epitaxial layer 251 adjacent to the sixth sub-epitaxial layer 252.

[0072] With such a setting, in the first-polarity crystal epitaxial layer 23, the second-polarity crystal epitaxial layer 24, and the third-polarity crystal epitaxial layer 25, the opposite surfaces of two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families. The two different crystal planes have different lattice constants, so that there is local strain between the opposite surfaces of two adjacent sub-epitaxial layers, thereby further effectively improving the carrier mobility, further reducing the on-resistance of the metal-oxide field-effect transistor power device, and further increasing the current density of the same chip area.

[0073] Optionally, on the basis of the above embodiments, as Figures 1 - 10 shown, in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, the opposite surfaces of two adjacent sub-epitaxial layers respectively belong to crystal planes of the {0001} crystal plane family and the {0338} crystal plane family.

[0074] Specifically, as Figures 1 - 3 shown, the surface of the first sub-epitaxial layer 231 adjacent to the second sub-epitaxial layer 232 can be a crystal plane of the {0001} crystal plane family, and the surface of the second sub-epitaxial layer 232 adjacent to the first sub-epitaxial layer 231 can be a crystal plane of the {0338} crystal plane family. Or, the surface of the first sub-epitaxial layer 231 adjacent to the second sub-epitaxial layer 232 can be a crystal plane of the {0338} crystal plane family, and the surface of the second sub-epitaxial layer 232 adjacent to the first sub-epitaxial layer 231 can be a crystal plane of the {0001} crystal plane family.

[0075] As Figures 7 - 9As shown, one surface of the third sub-epitaxial layer 241 adjacent to the fourth sub-epitaxial layer 242 can be a crystal plane in the {0001} crystal plane family, and one surface of the fourth sub-epitaxial layer 242 adjacent to the third sub-epitaxial layer 241 can be a crystal plane in the {0338} crystal plane family. Alternatively, one surface of the third sub-epitaxial layer 241 adjacent to the fourth sub-epitaxial layer 242 can be a crystal plane in the {0338} crystal plane family, and one surface of the fourth sub-epitaxial layer 242 adjacent to the third sub-epitaxial layer 241 can be a crystal plane in the {0001} crystal plane family.

[0076] As Figure 10 shown, one surface of the fifth sub-epitaxial layer 251 adjacent to the sixth sub-epitaxial layer 252 can be a crystal plane in the {0001} crystal plane family, and one surface of the sixth sub-epitaxial layer 252 adjacent to the fifth sub-epitaxial layer 251 can be a crystal plane in the {0338} crystal plane family. Alternatively, one surface of the fifth sub-epitaxial layer 251 adjacent to the sixth sub-epitaxial layer 252 can be a crystal plane in the {0338} crystal plane family, and one surface of the sixth sub-epitaxial layer 252 adjacent to the fifth sub-epitaxial layer 251 can be a crystal plane in the {0001} crystal plane family.

[0077] With such an arrangement, in the first-polarity crystal epitaxial layer 23, the second-polarity crystal epitaxial layer 24, and the third-polarity crystal epitaxial layer 25, the opposite surfaces of two adjacent sub-epitaxial layers respectively belong to crystal planes in the {0001} crystal plane family and the {0338} crystal plane family. The two different crystal planes have different lattice constants, so that there is local strain between the opposite surfaces of two adjacent sub-epitaxial layers, which further effectively improves the carrier mobility, further reduces the on-resistance of the metal-oxide field-effect transistor power device, and further increases the current density of the same chip area. At the same time, the crystal plane in the {0338} crystal plane family has a low interface state density and a high free electron ratio, which improves the electron mobility and the channel mobility, and can further reduce the on-resistance of the metal-oxide field-effect transistor power device.

[0078] Optionally, on the basis of the above embodiments, as Figures 1 - 10 shown, in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, the opposite surfaces of two adjacent sub-epitaxial layers are respectively the (0001) crystal plane and the (0338) crystal plane.

[0079] In the embodiments of the present invention, the {0001} crystal plane family includes the (0001) crystal plane, and the {0338} crystal plane family includes the (0338) crystal plane.

[0080] Specifically, as Figures 1 - 3As shown, one side of the first sub-epitaxial layer 231 close to the second sub-epitaxial layer 232 can be the (0001) crystal plane, and one side of the second sub-epitaxial layer 232 close to the first sub-epitaxial layer 231 can be the (0338) crystal plane. Alternatively, one side of the first sub-epitaxial layer 231 close to the second sub-epitaxial layer 232 can be the (0338) crystal plane, and one side of the second sub-epitaxial layer 232 close to the first sub-epitaxial layer 231 can be the (0001) crystal plane.

[0081] As Figures 7 - 9 shown, one side of the third sub-epitaxial layer 241 close to the fourth sub-epitaxial layer 242 can be the (0001) crystal plane, and one side of the fourth sub-epitaxial layer 242 close to the third sub-epitaxial layer 241 can be the (0338) crystal plane. Alternatively, one side of the third sub-epitaxial layer 241 close to the fourth sub-epitaxial layer 242 can be the (0338) crystal plane, and one side of the fourth sub-epitaxial layer 242 close to the third sub-epitaxial layer 241 can be the (0001) crystal plane.

[0082] As Figure 10 shown, one side of the fifth sub-epitaxial layer 251 close to the sixth sub-epitaxial layer 252 can be the (0001) crystal plane, and one side of the sixth sub-epitaxial layer 252 close to the fifth sub-epitaxial layer 251 can be the (0338) crystal plane. Alternatively, one side of the fifth sub-epitaxial layer 251 close to the sixth sub-epitaxial layer 252 can be the (0338) crystal plane, and one side of the sixth sub-epitaxial layer 252 close to the fifth sub-epitaxial layer 251 can be the (0001) crystal plane.

[0083] With such a setting, in the first polar crystal epitaxial layer 23, the second polar crystal epitaxial layer 24, and the third polar crystal epitaxial layer 25, the opposite surfaces of two adjacent sub-epitaxial layers respectively belong to the (0001) crystal plane and the (0338) crystal plane. The two different crystal planes have different lattice constants, so there is local strain between the opposite surfaces of two adjacent sub-epitaxial layers, which further effectively improves the carrier mobility, thereby further reducing the on-resistance of the metal-oxide field-effect transistor power device and further increasing the current density of the same chip area. At the same time, the (0338) crystal plane has a low interface state density and a high free electron ratio, which improves the electron mobility and the channel mobility, and can further reduce the on-resistance of the metal-oxide field-effect transistor power device.

[0084] Optionally, on the basis of the above embodiments, as Figures 1 - 10 shown, the silicon carbide sub-epitaxial layer includes a 4H-SiC sub-epitaxial layer.

[0085] Specifically, the sub-epitaxial layer includes a silicon carbide sub-epitaxial layer, and the silicon carbide sub-epitaxial layer includes a 4H-SiC sub-epitaxial layer. The 4H-SiC sub-epitaxial layer is a kind of SiC with a hexagonal crystal spacing, and its different crystal planes have a significant impact on the mobilities of electrons and holes, that is, along different directions of the crystal, the mobilities of electrons and holes will be different. The surface of the 4H-SiC sub-epitaxial layer includes crystal planes in the {0001} crystal plane family, {0338} crystal plane family, {1010} crystal plane family, and {1120} crystal plane family. Setting the sub-epitaxial layer as the 4H-SiC sub-epitaxial layer enables the metal-oxide field-effect transistor power device to have advantages such as a large bandgap width, high electron mobility, high thermal conductivity, and good chemical stability.

[0086] Optionally, on the basis of the above embodiments, as Figures 1 - 10 shown, the substrate 1 includes a silicon carbide substrate, the epitaxial layer 2 includes a gallium nitride epitaxial layer, and the sub-epitaxial layer includes a gallium nitride sub-epitaxial layer.

[0087] Specifically, setting the substrate 1 as a silicon carbide substrate, the epitaxial layer 2 as a gallium nitride epitaxial layer, and the sub-epitaxial layer as a gallium nitride sub-epitaxial layer enables the metal-oxide field-effect transistor power device to have high electron mobility, a wide bandgap width, high electron saturation velocity, low resistance, a smaller area, and high-temperature resistance. The adjacent gallium nitride sub-epitaxial layers can be set as crystal planes in different crystal plane families, and the two different crystal planes have different lattice constants, so that there is local strain between the opposite surfaces of the two adjacent sub-epitaxial layers, thereby further effectively improving the carrier mobility, further reducing the on-resistance of the metal-oxide field-effect transistor power device, and further increasing the current density of the same chip area. Optionally, on the basis of the above embodiments, as Figures 1 - 10 shown, the substrate 1 is a polar crystal substrate, and the epitaxial layer 2 is a polar crystal epitaxial layer. The opposite surfaces of the substrate 1 and the epitaxial layer 2 belong to crystal planes in the same crystal plane family.

[0088] Specifically, the substrate 1 can be a polar crystal substrate, and the epitaxial layer 2 can be a polar crystal epitaxial layer. Exemplarily, the substrate 1 can be a silicon carbide polar crystal substrate, and the epitaxial layer 2 can be a silicon carbide polar crystal epitaxial layer. One side of the substrate 1 close to the epitaxial layer 2 can be set as a crystal plane in any one of the {0001} crystal plane family, {0338} crystal plane family, {1010} crystal plane family, and {1120} crystal plane family, and one side of the epitaxial layer 2 close to the substrate 1 can be set as a crystal plane in any one of the {0001} crystal plane family, {0338} crystal plane family, {1010} crystal plane family, and {1120} crystal plane family. The opposite surfaces of the substrate 1 and the epitaxial layer 2 need to be set as crystal planes in the same crystal plane family.

[0089] Optionally, on the basis of the above embodiments, as Figures 1 - 10As shown, the substrate 1 includes a silicon carbide substrate, the epitaxial layer 2 includes a silicon carbide epitaxial layer, and the sub-epitaxial layer includes a silicon carbide sub-epitaxial layer; the opposite surfaces of the substrate 1 and the epitaxial layer 2 are (0001) crystal planes.

[0090] Specifically, one side of the substrate 1 close to the epitaxial layer 2 can be set as the (0001) crystal plane of the {0001} crystal plane family, and one side of the epitaxial layer 2 close to the substrate 1 can also be set as the (0001) crystal plane of the {0001} crystal plane family.

[0091] Figure 11 It is a flowchart of a method for manufacturing a metal-oxide field-effect transistor power device provided by an embodiment of the present invention. As Figure 11 shown, taking a planar metal-oxide field-effect transistor power device as an example, the method includes:

[0092] S100. Provide a substrate.

[0093] Specifically, as Figure 12 shown, first, a substrate 1 is provided. The semiconductor material of the substrate 1 can be silicon carbide. The metal-oxide field-effect transistor power device can include an N-channel metal-oxide field-effect transistor power device or a P-channel metal-oxide field-effect transistor power device. Exemplarily, for an N-channel metal-oxide field-effect transistor power device, the substrate 1 is an N-silicon carbide substrate, and for a P-channel metal-oxide field-effect transistor power device, the substrate 1 is a P-silicon carbide substrate.

[0094] S110. Form an epitaxial layer on one side of the substrate. A drift region and a body region are provided on the side of the epitaxial layer away from the substrate.

[0095] Specifically, as Figure 13 shown, an epitaxial layer 2 is formed on one side of the substrate 1 by an epitaxial process, and then a body region 22 is formed by processes such as ion implantation. After the above steps are completed, a drift region 21 is formed, and the semiconductor material and doping type of the drift region 21 are the same as those of the epitaxial layer 2.

[0096] Exemplarily, for an N-channel metal-oxide field-effect transistor power device, the epitaxial layer 2 is an N-epitaxial layer, the drift region 21 is an N-drift region, and the body region 22 is a P-body region. For a P-channel metal-oxide field-effect transistor power device, the epitaxial layer 2 is a P-epitaxial layer, the drift region 21 is a P-drift region, and the body region 22 is an N-body region.

[0097] S120. Form a first-polarity crystal epitaxial layer, wherein the first-polarity crystal epitaxial layer is embedded in the body region. The first-polarity crystal epitaxial layer includes at least two sub-epitaxial layers. In the direction perpendicular to the substrate and pointing to the epitaxial layer, the opposite surfaces of two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families; the conductivity type of the first-polarity crystal epitaxial layer is opposite to that of the body region; the first-polarity crystal epitaxial layer constitutes the first active region of the active region.

[0098] Specifically, as Figure 14 shown, form the first-polarity crystal epitaxial layer 23. Exemplarily, the first-polarity crystal epitaxial layer 23 includes a first sub-epitaxial layer 231 and a second sub-epitaxial layer 232. The number of sub-epitaxial layers included in the first-polarity epitaxial layer 23 can be greater than two, and the types and specific numbers of sub-epitaxial layers in the first-polarity crystal epitaxial layer 23 are not specifically limited herein. Figure 14 Taking the first-polarity crystal epitaxial layer 23 including two sub-epitaxial layers as an example, the first sub-epitaxial layer 231 and the second sub-epitaxial layer 232 can be arranged at intervals in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, and in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, the opposite surfaces of the first sub-epitaxial layer 231 and the second sub-epitaxial layer 232 belong to crystal planes of different crystal plane families. The first-polarity crystal epitaxial layer 23 constitutes the first active region and is in contact with the source electrode 4. In other embodiments, in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, multiple first sub-epitaxial layers 231 can also be arranged continuously, and multiple second sub-epitaxial layers 232 can also be arranged continuously.

[0099] Exemplarily, for an N-channel metal-oxide field-effect transistor power device, the first-polarity crystal epitaxial layer 23 is an N++ first-polarity crystal epitaxial layer, and the first active region is an N++ active region. For a P-channel metal-oxide field-effect transistor power device, the first-polarity crystal epitaxial layer 23 is a P++ first-polarity crystal epitaxial layer, and the first active region is a P++ active region.

[0100] Exemplarily, sub-epitaxial layers with a preset crystal plane can be formed in the same horizontal direction by at least one of the following methods:

[0101] Obtain sub-epitaxial layers with a preset crystal plane by wafer cutting; wherein, the wafer cutting can be ion beam cutting.

[0102] Obtain sub-epitaxial layers with a preset crystal plane by an etching process; wherein, the etching process can be dry etching or wet etching.

[0103] Obtain sub-epitaxial layers with a preset crystal plane by crystal plane polishing.

[0104] Control the crystal orientation to epitaxially grow an epitaxial layer with a preset crystal plane.

[0105] Specifically, the preparation method of the sub-epitaxial layer identical to the epitaxial layer 2 includes at least one of the following methods: obtaining the sub-epitaxial layer with a preset crystal plane by wafer dicing; wherein, the wafer dicing can be ion beam dicing. Obtaining the sub-epitaxial layer with a preset crystal plane by an etching process; wherein, the etching process can be dry etching or wet etching. Obtaining the sub-epitaxial layer with a preset crystal plane by crystal plane polishing. Growing the epitaxial layer with a preset crystal plane through crystal orientation control.

[0106] The preparation method of the sub-epitaxial layer different from the epitaxial layer 2 includes:

[0107] As Figure 13 shown, a groove 221 is formed in the epitaxial layer 2. Growing the sub-epitaxial layer with different preset crystal planes through crystal orientation control.

[0108] Or, as Figure 13 shown, a groove 221 is formed in the epitaxial layer 2. Growing the epitaxial layer with a preset crystal plane through crystal orientation control. Obtaining the sub-epitaxial layer with different preset crystal planes from the epitaxial layer through wafer dicing, etching process, and crystal plane polishing.

[0109] S130. A gate structure is formed on the side of the epitaxial layer away from the substrate.

[0110] Specifically, as Figure 15 shown, a gate structure 3 is first formed on the side of the epitaxial layer 2 away from the substrate 1. The gate structure 3 includes a gate dielectric layer 31 and a gate conductive layer 32. The gate dielectric layer 31 can be selected from silicon oxide or borophosphosilicate glass. The preparation method of the metal-oxide field-effect transistor power device provided by the embodiment of the present invention is introduced by taking a planar power device as an example.

[0111] S140. A source electrode is formed on the side of the epitaxial layer away from the substrate, wherein the source electrode covers a part of the first active region.

[0112] Specifically, as Figure 16 shown, a source electrode 4 is formed on the side of the epitaxial layer 2 away from the substrate 1 by metal deposition. The source electrode 4 is disposed on both sides of the gate structure 3 in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2. The source electrode 4 is in contact with the first-polarity crystal epitaxial layer 23.

[0113] S150. A drain electrode is formed on the side of the substrate away from the epitaxial layer.

[0114] Specifically, as Figure 1 shown, a drain electrode 5 is formed on the side of the substrate 1 away from the epitaxial layer 2 by processes such as metal deposition.

[0115] In the technical solution of the embodiment of the present invention, the first-polarity crystal epitaxial layer 23 constitutes the first active region of the active region. It is provided that the first-polarity crystal epitaxial layer 23 includes at least two sub-epitaxial layers, and in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, the opposite surfaces of two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families, that is, the crystal planes corresponding to the opposite surfaces of two adjacent sub-epitaxial layers have different lattice constants, so that local strain exists between the opposite surfaces of two adjacent sub-epitaxial layers, thereby effectively improving the carrier mobility, reducing the on-resistance of the metal-oxide field-effect transistor power device, and increasing the current density of the same chip area.

[0116] Optionally, when the active region includes a second active region having the same conductivity type as the body region 22, a second-polarity crystal epitaxial layer 24 can be further formed. Among them, the second-polarity crystal epitaxial layer 24 is embedded in the body region 22, the second-polarity crystal epitaxial layer 24 and the first-polarity crystal epitaxial layer 23 are adjacent to each other, and the second-polarity crystal epitaxial layer 24 includes at least two sub-epitaxial layers; in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, the opposite surfaces of two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families. The conductivity type of the second-polarity crystal epitaxial layer 24 is the same as that of the body region 22; the second-polarity crystal epitaxial layer 24 constitutes the second active region of the active region.

[0117] Among them, the preparation method of the second-polarity crystal epitaxial layer 24 can form sub-epitaxial layers with a preset crystal plane in the same horizontal direction by at least one of the following methods:

[0118] Obtaining sub-epitaxial layers with a preset crystal plane by wafer cutting; among them, the wafer cutting can be ion beam cutting.

[0119] Obtaining sub-epitaxial layers with a preset crystal plane by an etching process; among them, the etching process can be dry etching or wet etching.

[0120] Obtaining sub-epitaxial layers with a preset crystal plane by crystal plane polishing.

[0121] Controlling the crystal orientation to epitaxially grow an epitaxial layer with a preset crystal plane.

[0122] Specifically, the preparation method of the sub-epitaxial layer the same as the epitaxial layer 2 includes at least one of the following methods: obtaining sub-epitaxial layers with a preset crystal plane by wafer cutting; among them, the wafer cutting can be ion beam cutting. Obtaining sub-epitaxial layers with a preset crystal plane by an etching process; among them, the etching process can be dry etching or wet etching. Obtaining sub-epitaxial layers with a preset crystal plane by crystal plane polishing. Controlling the crystal orientation to epitaxially grow an epitaxial layer with a preset crystal plane.

[0123] The preparation method of the sub-epitaxial layer different from the epitaxial layer 2 includes:

[0124] Such asFigure 13 As shown, a groove 221 is formed in the epitaxial layer 2. Sub-epitaxial layers with different preset crystal planes are grown by controlling the crystal orientation during epitaxial growth.

[0125] Alternatively, as Figure 13 shown, a groove 221 is formed in the epitaxial layer 2. The epitaxial layer with a preset crystal plane is grown by controlling the crystal orientation during epitaxial growth. The epitaxial layer is processed through wafer dicing, etching process, and crystal plane polishing to obtain sub-epitaxial layers with different preset crystal planes.

[0126] Specifically, the crystal planes corresponding to the opposite surfaces of two adjacent sub-epitaxial layers in the second-polarity crystal epitaxial layer 24 have different lattice constants, so that local strain exists between the opposite surfaces of two adjacent sub-epitaxial layers, further effectively improving the carrier mobility, further reducing the on-resistance of the metal-oxide field-effect transistor power device, and further increasing the current density of the same chip area.

[0127] Optionally, the metal-oxide field-effect transistor power device includes a planar structure. The metal-oxide field-effect transistor power device is provided with a JFET region. A third-polarity crystal epitaxial layer 25 can also be formed in the metal-oxide field-effect transistor power device. The third-polarity crystal epitaxial layer 25 is located in the JFET region. The third-polarity crystal epitaxial layer 25 includes at least two sub-epitaxial layers; in the direction perpendicular to the substrate 1 and pointing to the epitaxial layer 2, the opposite surfaces of two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families.

[0128] Among them, the preparation method of the third-polarity crystal epitaxial layer 25 can form sub-epitaxial layers with preset crystal planes in the same horizontal direction by at least one of the following methods:

[0129] Obtaining sub-epitaxial layers with preset crystal planes through wafer dicing; among them, the wafer dicing can be ion beam dicing.

[0130] Obtaining sub-epitaxial layers with preset crystal planes through an etching process; among them, the etching process can be dry etching or wet etching.

[0131] Obtaining sub-epitaxial layers with preset crystal planes through crystal plane polishing.

[0132] Growing an epitaxial layer with a preset crystal plane by controlling the crystal orientation during epitaxial growth.

[0133] Specifically, the preparation method of the sub-epitaxial layer the same as the epitaxial layer 2 includes at least one of the following methods: obtaining sub-epitaxial layers with preset crystal planes through wafer dicing; among them, the wafer dicing can be ion beam dicing. Obtaining sub-epitaxial layers with preset crystal planes through an etching process; among them, the etching process can be dry etching or wet etching. Obtaining sub-epitaxial layers with preset crystal planes through crystal plane polishing. Growing an epitaxial layer with a preset crystal plane by controlling the crystal orientation during epitaxial growth.

[0134] The preparation method of a sub-epitaxial layer different from the epitaxial layer 2 includes:

[0135] As Figure 13 shown, a groove 221 is formed in the epitaxial layer 2. Different preset crystal plane sub-epitaxial layers are grown by epitaxy through crystal orientation control.

[0136] Or, as Figure 13 shown, a groove 221 is formed in the epitaxial layer 2. An epitaxial layer of a preset crystal plane is grown by epitaxy through crystal orientation control. The epitaxial layer is processed by wafer dicing, etching process, and crystal plane polishing to obtain sub-epitaxial layers of different preset crystal planes.

[0137] Specifically, at least two sub-epitaxial layers are provided in the JFET region. The opposite surfaces of two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families. The two different crystal planes have different lattice constants, so that local strain exists between the opposite surfaces of two adjacent sub-epitaxial layers. Further, the carrier mobility is effectively improved, and further, the on-resistance of the metal-oxide field-effect transistor power device is reduced, and the current density of the same chip area is further increased.

[0138] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. There is no limitation herein.

[0139] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A metal-oxide field effect transistor power device, characterized in that: include: substrate; An epitaxial layer, wherein the epitaxial layer is located on one side of the substrate, and a drift region and a body region are provided on a side of the epitaxial layer away from the substrate; A first polar crystalline epitaxial layer, the first polar crystalline epitaxial layer is embedded in the body region, the first polar crystalline epitaxial layer includes at least two sub-epitaxial layers; in a direction perpendicular to the substrate and pointing toward the epitaxial layer, the relative surfaces of the two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families; the conductivity type of the first polar crystalline epitaxial layer is opposite to the conductivity type of the body region; the first polar crystalline epitaxial layer constitutes a first active region of the active region; A gate structure, wherein the gate structure is located on a side of the epitaxial layer away from the substrate; A source electrode, the source electrode is located on a side of the epitaxial layer away from the substrate and covers a portion of the first active area; A drain electrode, the drain electrode being located at a side of the substrate away from the epitaxial layer; The metal-oxide field effect transistor power device also includes a second polarity crystalline epitaxial layer, which is embedded in the body region. The second polarity crystalline epitaxial layer and the first polarity crystalline epitaxial layer are arranged adjacent to each other, and the second polarity crystalline epitaxial layer includes at least two sub-epitaxial layers; in a direction perpendicular to the substrate and pointing toward the epitaxial layer, relative surfaces of the two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families; the conductivity type of the second polarity crystalline epitaxial layer is the same as the conductivity type of the body region; the second polarity crystalline epitaxial layer constitutes a second active region of the active region.

2. The metal-oxide field effect transistor power device according to claim 1, characterized in that: The metal-oxide field effect transistor power device includes at least one of a planar structure, a single trench structure and a double trench structure.

3. The metal-oxide field effect transistor power device according to claim 2, characterized in that: The metal-oxide field effect transistor power device comprises a planar structure; The metal-oxide field effect transistor power device is provided with a JFET region; The metal-oxide field effect transistor power device also includes a third polarity crystal epitaxial layer, which is located in the JFET region. The third polarity crystal epitaxial layer includes at least two sub-epitaxial layers; in a direction perpendicular to the substrate and pointing toward the epitaxial layer, relative surfaces of two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families.

4. The metal-oxide field effect transistor power device according to any one of claims 1 to 3, characterized in that: The substrate comprises a silicon carbide substrate, the epitaxial layer comprises a silicon carbide epitaxial layer, and the sub-epitaxial layer comprises a silicon carbide sub-epitaxial layer; In a direction perpendicular to the substrate and pointing toward the epitaxial layer, relative surfaces of two adjacent sub-epitaxial layers belong to crystal planes of at least two of the {0001} crystal plane family, the {0338} crystal plane family, the {1010} crystal plane family, and the {1120} crystal plane family.

5. The metal-oxide field effect transistor power device according to claim 4, characterized in that: In a direction perpendicular to the substrate and pointing toward the epitaxial layer, opposite surfaces of two adjacent sub-epitaxial layers belong to crystal planes in the {0001} crystal plane family and the {0338} crystal plane family, respectively.

6. The metal-oxide field effect transistor power device according to claim 5, characterized in that: In a direction perpendicular to the substrate and pointing toward the epitaxial layer, opposite surfaces of two adjacent sub-epitaxial layers are respectively a (0001) crystal plane and a (0338) crystal plane.

7. The metal-oxide field effect transistor power device according to claim 4, characterized in that: The silicon carbide epitaxial sub-layer includes a 4H-SiC epitaxial sub-layer.

8. The metal-oxide field effect transistor power device according to any one of claims 1 to 3, characterized in that: The substrate comprises a silicon carbide substrate, the epitaxial layer comprises a gallium nitride epitaxial layer, and the sub-epitaxial layer comprises a gallium nitride sub-epitaxial layer.

9. The metal-oxide field effect transistor power device according to any one of claims 1 to 3, characterized in that: The substrate is a polar crystal substrate, and the epitaxial layer is a polar crystal epitaxial layer; Opposing surfaces of the substrate and the epitaxial layer belong to crystal planes of the same crystal plane family.

10. The metal-oxide field effect transistor power device according to claim 9, characterized in that: The substrate comprises a silicon carbide substrate, the epitaxial layer comprises a silicon carbide epitaxial layer, and the sub-epitaxial layer comprises a silicon carbide sub-epitaxial layer; and opposite surfaces of the substrate and the epitaxial layer are (0001) crystal planes.

11. A method for preparing a metal-oxide field effect transistor power device, characterized in that: include: providing a substrate; forming an epitaxial layer on one side of the substrate, wherein a drift region and a body region are provided on a side of the epitaxial layer away from the substrate; A first polarity crystalline epitaxial layer is formed, wherein the first polarity crystalline epitaxial layer is embedded in the body region, the first polarity crystalline epitaxial layer includes at least two sub-epitaxial layers, and in a direction perpendicular to the substrate and pointing toward the epitaxial layer, the relative surfaces of two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families; the conductivity type of the first polarity crystalline epitaxial layer is opposite to the conductivity type of the body region; the first polarity crystalline epitaxial layer constitutes a first active region of the active region; forming a gate structure on a side of the epitaxial layer away from the substrate; forming a source electrode on a side of the epitaxial layer away from the substrate, wherein the source electrode covers a portion of the first active area; forming a drain on a side of the substrate away from the epitaxial layer; A second polarity crystalline epitaxial layer is formed, wherein the second polarity crystalline epitaxial layer is embedded in the body region, the second polarity crystalline epitaxial layer and the first polarity crystalline epitaxial layer are arranged adjacent to each other, and the second polarity crystalline epitaxial layer includes at least two sub-epitaxial layers; in a direction perpendicular to the substrate and pointing to the epitaxial layer, relative surfaces of the two adjacent sub-epitaxial layers belong to crystal planes of different crystal plane families; the conductivity type of the second polarity crystalline epitaxial layer is the same as the conductivity type of the body region; and the second polarity crystalline epitaxial layer constitutes a second active region of the active region.

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