MOS device and method for manufacturing the same

Abstract

The present application discloses a MOS device and a preparation method thereof, comprising at least one cellular structure, wherein the cellular structure comprises: a substrate; a drift layer, located on one side of the substrate; a first source region structure, located on the side of the drift layer away from the substrate; a second source region structure, located on the side of the drift layer away from the substrate, and the surface of the first source region structure on the side away from the substrate is located in the surface of the second source region structure close to the substrate; a shielding region, located between the drift layer and the second source region structure, wherein the shielding region comprises a plurality of first shielding regions, the first shielding regions are spaced apart along a first direction, and the first direction is the direction from the substrate to the drift layer. The plurality of first shielding regions deplete the carriers in the device respectively along the first direction, thereby reducing the built-in electric field in the MOS device, making the device more stable, thereby solving the problem in the related art that the MOS device is easily broken down due to the electric field concentration at the corner.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a MOS device and a method for manufacturing the same. Background Art

[0002] In traditional trench-gate field-effect transistor (MOSFET, Meta-Oxide-SemiconductorField-Effect Transistor, abbreviated as MOS) devices, the electric field concentration at the corners of the gate oxide layer causes the gate dielectric layer to breakdown. In addition, the planar MOS gate dielectric is also prone to breakdown, causing the device to break down at a voltage lower than the rated breakdown voltage, seriously affecting the forward blocking characteristics and long-term reliability of the device. The electric field at the gate trench position of the device is easily concentrated, causing the device to break down, thereby affecting the reliability of the device. Summary of the invention

[0003] The present application provides a MOS device and a method for manufacturing the same, so as to solve the problem in the related art that the MOS device is easily broken down due to the concentrated electric field at the corners.

[0004] According to one aspect of the present application, a MOS device is provided, comprising at least one cellular structure, the cellular structure comprising: a substrate; a drift layer, located on one side of the substrate; a first source region structure, located on a side of the drift layer away from the substrate; a second source region structure, located on a side of the drift layer away from the substrate, and a surface of the first source region structure on a side away from the substrate is located in a surface of the second source region structure close to the substrate; a shielding region, at least partially located between the drift layer and the second source region structure, the shielding region comprising a plurality of first shielding regions, the first shielding regions being spaced apart and distributed along a first direction, the first direction being a direction from the substrate to the drift layer; a gate structure, located on a side of the shielding region away from the drift layer, and in contact with the first source region structure and the second source region structure.

[0005] Optionally, in the first direction, volumes of the plurality of first shielding areas decrease gradually.

[0006] Optionally, the maximum vertical distance between adjacent first shielding areas in the first direction decreases.

[0007] Optionally, the shielding area further includes a plurality of second shielding areas, the second shielding areas are spaced apart along a second direction, the volumes of the plurality of second shielding areas decrease gradually in the second direction, and the second direction is perpendicular to the first direction.

[0008] Optionally, the maximum horizontal distance between adjacent second shielding areas in the second direction decreases.

[0009] Optionally, the cell structure further includes: a current spreading layer located at a side of the drift layer away from the substrate, and the shielding region, the first source region structure and the second source region structure are located in the current spreading layer.

[0010] Optionally, the first source region structure includes a first body region, the first body region is located on both sides of the shielding region in the second direction, a surface of the first body region facing away from the substrate is located on a surface of the current spreading layer facing away from the substrate, and the second direction is perpendicular to the first direction; the second source region structure includes a second body region, the second body region is located on a side of the shielding region facing away from the drift layer.

[0011] According to one aspect of the present application, a method for preparing a MOS device is provided, which is used to prepare a cell structure of the MOS device, and the method comprises: providing a substrate; forming a drift layer on the substrate; forming a shielding region on a side of the drift layer away from the substrate, the shielding region comprising a plurality of first shielding regions, the first shielding regions being spaced apart at least along a first direction, the first direction being a direction in which the substrate points to the drift layer; forming a first source region structure and a second source region structure on a side of the drift layer away from the substrate, the surface of the first source region structure on a side away from the substrate being located in a surface of the second source region structure on a side close to the substrate; forming a gate structure on a side of the shielding region away from the drift layer, the gate structure being in contact with the first source region structure and the second source region structure.

[0012] Optionally, the step of forming a shielding area on the side of the drift layer facing away from the substrate includes: forming a current spreading layer on the side of the drift layer facing away from the substrate; forming a plurality of first shielding areas spaced apart and distributed along the first direction in the current spreading layer, or forming a plurality of second shielding areas spaced apart and distributed along the second direction in the current spreading layer, wherein the second direction is perpendicular to the first direction, and the shielding area includes the first shielding area or the second shielding area.

[0013] Optionally, after the step of forming a shielding region on a side of the drift layer away from the substrate, the preparation method further includes: forming a first body region on one side of the current spreading layer in the second direction; forming a second body region in the current spreading layer on a side of the shielding region away from the drift layer; forming a first doped region in the first body region and the second body region respectively, and forming a second doped region in the first body region and the second body region respectively, wherein, in the first body region, the second doped region is located between the shielding region and the first doped region, in the second body region, a projection of the second doped region on the first surface and a projection of the shielding region on the first surface at least partially overlap, the second doped region is located on a side of the first doped region away from the first body region, the first surface is a side surface of the drift layer away from the substrate, the first body region and the first doped region and the second doped region located in the first body region form a first source region structure, and the second body region and the first doped region and the second doped region located in the second body region form a second source region structure.

[0014] By applying the technical solution of the present application, a MOS device is provided, which includes a substrate, a drift layer, a first source structure, a second source structure, a gate structure and a shielding region, wherein the shielding region is located on a side of the drift layer away from the substrate, and the shielding region includes a plurality of first shielding regions, and the first shielding regions are spaced apart along a direction from the substrate to the drift layer, and the plurality of first shielding regions deplete carriers in the device along a first direction, thereby reducing a built-in electric field in the MOS device, making the device more stable, thereby solving the problem in the related art that the MOS device is easily broken down due to the concentrated electric field at the corner. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 is a schematic cross-sectional structure diagram of a first MOS device according to an embodiment of the present application;

[0017] Figure 2 is a schematic cross-sectional structure diagram of a second MOS device according to an embodiment of the present application;

[0018] Figure 3 is a schematic cross-sectional structure diagram of a third MOS device according to an embodiment of the present application;

[0019] Figure 4 is a schematic cross-sectional structure diagram of a fourth MOS device according to an embodiment of the present application;

[0020] Figure 5 is a schematic cross-sectional structural diagram of a fifth MOS device according to an embodiment of the present application;

[0021] Figure 6 is a schematic cross-sectional structural diagram of a sixth MOS device according to an embodiment of the present application;

[0022] Figure 7 A flow chart of a method for preparing a MOS device provided according to an embodiment of the present application is shown;

[0023] Figure 8 A schematic diagram of the cross-sectional structure of a substrate obtained in each step in a method for preparing a MOS device provided in an embodiment of the present application is shown;

[0024] Fig. 9 A schematic diagram of the cross-sectional structure of a substrate obtained in each step in another method for preparing a MOS device provided in an embodiment of the present application is shown.

[0025] The above drawings include the following reference numerals:

[0026] 10. Substrate; 20. Drift layer; 310. First source region structure; 320. Second source region structure; 30. Shielding region; 31. First shielding region; 32. Second shielding region; 410. Gate structure; 411. Gate oxide layer; 412. Gate; 40. Current spreading layer; 50. First body region; 60. Second body region; 70. First doped region; 80. Second doped region; 90. Insulating layer; 100. Metal contact layer; 110. First electrode; 120. Second electrode. DETAILED DESCRIPTION

[0027] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0028] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] As described in the background technology, in traditional trench-gate MOSFET devices, the electric field concentration at the corners of the gate oxide layer causes the gate dielectric layer to breakdown. In addition, the planar MOS gate dielectric is also prone to breakdown, causing the device to break down at a voltage lower than the rated breakdown voltage, seriously affecting the forward blocking characteristics and long-term reliability of the device. The electric field at the gate trench position of the device is easily concentrated, causing the device to break down, thereby affecting the reliability of the device.

[0031] According to one aspect of the present application, a MOS device is provided, such as Figures 1 to 6 As shown, at least one cellular structure is included, and the cellular structure includes: a substrate 10; a drift layer 20, located on one side of the substrate 10; a first source region structure 310, located on the side of the drift layer 20 away from the substrate 10; a second source region structure 320, located on the side of the drift layer 20 away from the substrate 10, and the surface of the first source region structure 310 away from the substrate 10 is located in the surface of the second source region structure 320 close to the substrate 10; a shielding region 30, at least partially located between the drift layer 20 and the second source region structure 320, the shielding region 30 includes a plurality of first shielding regions 31, and the first shielding regions 31 are spaced apart along a first direction X, and the first direction X is the direction from the substrate 10 to the drift layer 20; a gate structure 410, located on the side of the shielding region 30 away from the drift layer 20, and in contact with the first source region structure 310 and the second source region structure 320.

[0032] By adding multiple first shielding regions in the device, the multiple first shielding regions form depletion regions in sequence from bottom to top, the carriers in the device are depleted, the protection of the corners of the device gate oxide layer is enhanced, the surface electric field of the device gate structure is reduced, and the built-in electric field in the MOS device is reduced, making the device more stable.

[0033] Specifically, the substrate may be N +The resistivity of the SIC substrate is 0.02±20%Ωcm. An epitaxial layer (EPI, epilayer) is grown on the substrate as a drift layer, which serves as the main breakdown layer, and its doping concentration is 1E +15 ~1E +16 cm -3 The thickness can be reasonably adjusted according to product requirements, such as the thickness of the outer drift layer of a 1200V MOS device is 9-11μm, and the thickness of the drift layer of a 650V MOS tube is 5-7μm. A portion of the shielding area is located between the drift layer and the second source region structure, and another portion can also be located in the area outside the drift layer and the second source region structure.

[0034] In some optional embodiments, Figure 1 and Figure 2 As shown, the cell structure further includes: a current spreading layer 40 (CSL) located at a side of the drift layer 20 away from the substrate 10 , and the shielding region 30 is located in the current spreading layer 40 .

[0035] Specifically, the doping type of the current spreading layer is N-type, with a thickness of 0.5~2.0μm and a greater concentration than the drift layer, and its doping concentration is 1E +16 ~1E 17 cm -3 , due to the implantation of the shielding area at the back, the on-resistance of MOS between the source and the drain increases; the doping concentration of CSL is about 100~1000 times that of the ordinary drift layer. Under the same level of other conditions, its carrier mobility can be increased by more than 100 times, and the corresponding JFET region electronic resistance in the MOS device can be reduced to more than 1 / 100 of it, thereby reducing the on-resistance.

[0036] Specifically, Figure 1 and Figure 2 As shown, the shielding region 30 and the current spreading layer 40 have different doping types to form a PN junction structure. When the MOS device is turned on, a depletion layer is formed at the junction of the shielding region 30 and the current spreading layer 40, which prevents the free movement of external charges into the PN junction, thereby preventing the flow of current, shielding the electric field on the gate oxide surface, reducing the surface electric field strength, and improving device reliability.

[0037] In some optional embodiments, such as Figure 1 As shown, in the first direction X, the volumes of the plurality of first shielding areas 31 decrease gradually.

[0038] Specifically, Figure 1As shown, the volume of the first shielding area 31 closest to the drift layer 20 is the largest, that is, the contact area between the first shielding area 31 closest to the drift layer 20 and the current expansion layer 40 is the largest, and the depletion effect on carriers is the largest. The volume of the first shielding area 31 closest to the drift layer 20 and away from the drift layer 20 is slightly smaller, and the depletion effect on carriers is also smaller. At this time, the carriers are relatively less. The first shielding area 31 with the smallest volume can deplete the carriers that have not been depleted for the first two times. The carriers are progressively depleted layer by layer through the shielding area 30 in the first direction X, which can effectively protect the gate oxide corners, reduce the surface electric field strength, and improve the device reliability.

[0039] In some optional embodiments, such as Figure 1 As shown, the maximum vertical distance between adjacent first shielding areas 31 in the first direction X decreases.

[0040] Specifically, Figure 1 As shown, there are vertical distances d1 and d2 between adjacent first shielding areas 31 in the first direction X, wherein d1 is smaller than d2, from the surface of the current spreading layer 40 close to the drift layer 20 to the surface of the current spreading layer 40 away from the drift layer 20, which reduces the crosstalk effect and leakage current in the device, and improves the response speed and anti-interference ability of the device. In addition, reducing the gap can also reduce the size of the device, improve the integration and density of the device, thereby reducing the volume and power consumption of the device, and improving the performance and reliability of the device.

[0041] In some optional embodiments, such as Figure 2 As shown, the shielding area 30 further includes a plurality of second shielding areas 32 , which are spaced apart along a second direction Y. In the second direction Y, the volumes of the plurality of second shielding areas 32 decrease gradually. The second direction Y is perpendicular to the first direction X.

[0042] Specifically, Figure 2 As shown, the shielding region 30 may further include a plurality of second shielding regions 32, and the second shielding regions 32 are arranged at intervals along a second direction Y perpendicular to the first direction X. The volumes of the plurality of second shielding regions 32 along the second direction Y are in a decreasing trend. The shielding regions 30 are used to progressively deplete carriers layer by layer in the second direction Y, which can effectively protect the gate oxide corners, reduce the surface electric field strength, and improve the device reliability.

[0043] In some optional embodiments, such as Figure 2 As shown, the maximum horizontal distance between adjacent second shielding areas 32 in the second direction Y decreases.

[0044] Specifically, Figure 2 As shown, the adjacent second shielding areas 32 in the second direction Y have horizontal distances D1, D2 and D3, respectively, wherein D1 is smaller than D2, and D2 is smaller than D3. By decreasing the horizontal distances between the plurality of second shielding areas 32, the crosstalk effect and leakage current in the device are reduced, and the response speed and anti-interference capability of the device are improved. In addition, reducing the gap can also reduce the size of the device, improve the integration and density of the device, thereby reducing the volume and power consumption of the device, and improving the performance and reliability of the device.

[0045] In some optional embodiments, such as Figure 1 and Figure 2 As shown, the cell structure further includes: a current spreading layer 40 located on a side of the drift layer 20 away from the substrate 10 , and the shielding region 30 , the first source region structure 310 and the second source region structure 320 are located in the current spreading layer 40 .

[0046] Specifically, the element injected into the current spreading layer is Al element (P type), and its injection dose is 1E +19 ±50% cm -3 The injection depth is 0.5~1.8μm and the width is about 0.4~1.0μm to form a shielding area. The length and width ratio of the P+ shielding layer is 1:1~1:3. The shielding area and the CSL current extension layer form depletion under the channel under the reverse voltage, reducing the electric field strength near the channel surface, thereby improving the withstand voltage level and enhancing reliability.

[0047] In some optional embodiments, such as Figure 1 and Figure 2 As shown, the first source region structure 310 includes a first body region 50, which is located on both sides of the shielding region 30 in the second direction Y, and a surface of the first body region 50 facing away from the substrate 10 is located in a surface of the current spreading layer 40 facing away from the substrate 10, and the second direction Y is perpendicular to the first direction X; the second source region structure 320 includes a second body region 60, which is located on a side of the shielding region 30 facing away from the drift layer 20.

[0048] Specifically, Figure 3 and Figure 4 As shown, the element implanted in both sides of the current spreading layer 40 in the second direction Y is Al element, and its implantation dose is 1E +17 ±50% cm -3 The implantation depth is 0.7-0.8 μm to form a first body region 50 ; similarly, the implantation is performed on a side of the current spreading layer 40 away from the drift layer 20 to form a second body region 60 .

[0049] Specifically, Figure 3 and Figure 4 As shown, N element is implanted into the first body region 50 and the second body region 60, and the implantation dose is 1E +19 ~1E +20 cm -3 The implantation depth is 0.2-0.3 μm, forming the first doped region 70; the element implanted into the first body region 50 and the second body region 60 is Al element, and the implantation dose is 1E +19 ±50% cm -3 The injection depth is 0.2~0.3μm to form the second doping region 80. The lateral width ratio of the first doping region 70 and the second doping region 80 is 1:1.5~1:1, and the longitudinal ratio is 1:1~1:3. This ensures that the second doping region 80 prevents the carriers of the first doping region 70 from moving in other directions in the horizontal and longitudinal directions, so that they can only move on the specified path, so that the MOS device has low power consumption and leakage, and completes the injection layer activation and the active area layer film formation and etching.

[0050] Specifically, Figure 5 and Figure 6 As shown, the MOS device further includes a gate structure 410 and an insulating layer 90. The gate structure 410 includes a gate oxide layer 411 and a gate 412. Part of the gate oxide layer 411 is located on both sides of the second body region 60 in the second direction Y, and part of the gate oxide layer 411 is located on the side of the first body region 50 away from the drift layer 20. The gate oxide layer 411 is also in contact with the second doping region in the first body region 50 and the first doping region in the second body region 60. The gate 412 is located on the side of the gate oxide layer 411 away from the second body region 60, and the insulating layer 90 is in contact with the gate 412, the gate oxide layer 411, the first doping region in the second body region 60, and the second doping region in the first body region 50. The insulating layer 90 has a thickness of 400-800Å and may be made of SiO2. The gate 412 may be made of polysilicon. The gate oxide layer 411 has a thickness of 400-800Å and may be made of SiO2. The dry oxygen or wet oxygen process is used and the preparation temperature is 1000-1500°C. If the dry oxygen process is used, Ar and O2 gases are used, and N2 and NO gases are used to improve the interface state between the gate oxide layer 411 and the first body region 50 and the interface state between the gate oxide layer 411 and the second body region 60. A portion of the shielding region is located between the drift layer 20 and the second body region 60, and another portion may also be located between the drift layer 20 and the gate oxide layer 411.

[0051] Specifically, Figure 5 and Figure 6As shown, the cell structure further includes a metal contact layer 100, a first electrode 110 and a second electrode 120, wherein a portion of the metal contact layer 100 is located on a side of the first body region 50 away from the drift layer 20, and is in contact with the first doping region and the second doping region in the first body region 50, and another portion of the metal contact layer 100 is located on a side of the second body region 60 away from the drift layer 20, and is in contact with the first doping region and the second doping region in the second body region 60; the first electrode 110 is located on a side of the metal contact layer 100 away from the drift layer 20, and covers the metal contact layer 100, the insulating layer 90, the first doping region and the second doping region; the second electrode 120 is located on a side of the substrate 10 away from the drift layer 20. The contact surface between the metal contact layer 100 and the first doping region and the contact surface between the second doping region both form ohmic contacts. The metal contact layer 100 can be Ni, Ti or other materials. If Ni metal is used, NiSi is generally formed at 600-800°C with a thickness of about 200-400nm, and then the unreacted Ni is stripped off by Ni etching solution, and high-temperature annealing is performed at 900-1000°C. The first electrode 110 can be made of AlCu material with a thickness of 2-6μm. The second electrode 120 can be made of Ni, Ti or other materials. If Ni metal is used, NiSi is generally formed by laser annealing at about 1000°C with a thickness of about 200-400nm. The second electrode 120 can also be an alloy of materials such as Ti, Ni and Ag.

[0052] According to another aspect of the present application, a method for preparing a MOS device is provided, such as Figure 7 As shown, the method is used to prepare the cell structure of the above-mentioned MOS device, comprising the following steps:

[0053] S101: providing a substrate;

[0054] S102: forming a drift layer on a substrate;

[0055] S103: forming a shielding region on a side of the drift layer away from the substrate, the shielding region comprising a plurality of first shielding regions, the first shielding regions being spaced apart at least along a first direction, the first direction being a direction from the substrate to the drift layer;

[0056] S104: forming a first source region structure and a second source region structure on a side of the drift layer away from the substrate, wherein a surface of the first source region structure away from the substrate is located within a surface of the second source region structure close to the substrate;

[0057] S105: forming a gate structure on a side of the shielding region away from the drift layer, wherein the gate structure is in contact with the first source region structure and the second source region structure.

[0058] By adopting the above-mentioned preparation method of the embodiment of the present application, a plurality of first shielding regions are formed in the MOS device, and the plurality of first shielding regions sequentially form depletion regions from bottom to top, so that the carriers in the device are depleted, the protection of the corners of the gate oxide layer of the device is enhanced, the surface electric field of the gate structure of the device is reduced, and the built-in electric field in the MOS device is reduced, thereby making the device more stable.

[0059] The following will describe in more detail the exemplary embodiments of the method for preparing the MOS device provided by the present application in conjunction with the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0060] First, proceed to step S101: Figure 8 (a) and Fig. 9 As shown in (a), a substrate 10 is provided;

[0061] Specifically, the material of the substrate may include silicon carbide material, or may include silicon, quartz, silicon nitride, gallium nitride, gallium oxide, aluminum oxide, aluminum nitride and other materials. Personnel in this field may make reasonable selections based on actual needs, and no specific limitation is made without application.

[0062] After the step of providing the substrate, step S102 is performed: Figure 8 (a) and Fig. 9 As shown in (a), a drift layer 20 is formed on a substrate 10;

[0063] Specifically, the resistivity of the drift layer 20 is 0.02±20%Ωcm, which bears the main breakdown voltage, and its doping concentration is 1E +15 ~1E +16 cm -3 The thickness can be reasonably adjusted according to product requirements. For example, the drift layer thickness of a 1200V MOS device is 9~11μm, and the epitaxial layer thickness of a 650V MOS device is 5~7μm.

[0064] After forming the drift layer, step S103 is performed, such as Figure 8 As shown in (b), a shielding region 30 is formed on a side of the drift layer 20 away from the substrate 10 , and the shielding region 30 includes a plurality of first shielding regions 31 , and the first shielding regions 31 are spaced apart at least along a first direction, and the first direction is a direction from the substrate 10 to the drift layer 20 .

[0065] Specifically, the doping type of the first shielding region may be N-type. The implanted ions are Al ions, and the implantation dose is 1E+19 ±50% cm -3 The injection depth is 0.5~1.8μm, the width is about 0.4~1.0μm, the length and width ratio of the first shielding area is 1:1~1:3, and the first shielding area and the current expansion layer form depletion under the channel under the reverse voltage, reducing the electric field strength near the channel surface, thereby improving the withstand voltage level and enhancing reliability.

[0066] In some optional embodiments, such as Figure 8 (a), 8(b), 9(a) and Fig. 9 As shown in (b), the step of forming the shielding region 30 includes: forming a current spreading layer 40 on the side of the drift layer 20 away from the substrate 10; forming a plurality of the first shielding regions 31 spaced apart along the first direction in the current spreading layer 40, or forming a plurality of the second shielding regions 32 spaced apart along the second direction in the current spreading layer 40, wherein the second direction is perpendicular to the first direction, and the shielding region 30 includes the first shielding region 31 or the second shielding region 32.

[0067] Specifically, Figure 8 As shown in (b), a plurality of the first shielding regions 31 are formed in the current spreading layer 40 along the first direction and are spaced apart from each other; or as shown in Fig. 9 As shown in (b), a plurality of second shielding regions 32 are formed in the current spreading layer 40 and are distributed at intervals along the second direction.

[0068] After the step of forming the above-mentioned shielding area, Figure 8 (c) to Figure 8 (f) and Fig. 9 (c) to Fig. 9 As shown in (f), step S104 is performed: a first source region structure 310 and a second source region structure 320 are formed on a side of the drift layer 20 away from the substrate 10, and a surface of the first source region structure 310 away from the substrate 10 is located in a surface of the second source region structure 320 close to the substrate 10.

[0069] In some optional embodiments, such as Figure 8 (c) and Fig. 9As shown in (c), after the step of forming the shielding region 30, the preparation method further includes: forming a first body region 50 on one side of the current spreading layer 40 in the second direction Y; forming a second body region 60 in the current spreading layer 40 on the side of the shielding region 30 away from the drift layer 20; forming a first doping region 70 and a second doping region 80 in the first body region 50 and the second body region 60, respectively, wherein, in the first body region 50, the second doping region 80 is located between the shielding region 30 and the first doping region 70, and in the second body region 60, the second doping region 80 is located between the shielding region 30 and the first doping region 70, and in the second body region 60, the second doping region 80 is located between the shielding region 30 and the first doping region 70. The projection on the first surface at least partially overlaps with the projection of the shielding region 30 on the first surface, the second doping region 80 is located on the side of the first doping region 70 away from the first body region 50, the first surface is a surface of the drift layer 20 away from the substrate 10, the first body region 50 and the first doping region 70 and the second doping region 80 located in the first body region 50 form a first source region structure 310, and the second body region 60 and the first doping region 70 and the second doping region 80 located in the second body region 60 form the second source region structure 320.

[0070] Specifically, the first body region and the second body region may be of P type, and the implanted element is Al element, and the implanted dose is 1E +17 ±50% cm -3 The implantation depth is 0.7~0.8μm; the first doping region can be P-type, the implantation element is Al element, and the implantation dose is 1E +19 ±50% cm -3 The implantation depth is 0.2~0.3μm, the second doping region can be N-type, and the implantation dose is 1E +19 ~1E +20 cm -3 The injection depth is 0.2~0.3μm, the lateral width ratio of the first doping region and the second doping region is 1:1.5~1:1, and the longitudinal ratio is 1:1~1:3. This ensures that the second doping region prevents the carriers in the second doping region from moving in other directions in the horizontal and longitudinal directions, so that they can only move on the specified path, with low power consumption and low leakage.

[0071] Specifically, Figure 8 (d) and Fig. 9As shown in (d), after forming the first body region 50 and the second body region 60, the preparation method further comprises: forming a portion of the gate oxide layer 411 on the side of the first body region 50 away from the drift layer 20, and forming another portion of the gate oxide layer 411 on the side of the second body region 60 close to the first body region 50; forming a gate 412 on the side of the gate oxide layer 411 away from the drift layer 20 and the side away from the second body region 60; forming an insulating layer 90 covering the gate 412, the gate oxide layer 411 and the portion of the second doped region 80 located in the first body region 50, and covering the portion of the first doped region 70 located in the second body region 60; as shown in (d). Figure 8 (e) and Fig. 9 As shown in (e), a metal contact layer 100 is formed on the side of the first doping region 70 and a portion of the second doping region 80 away from the drift layer 20; Figure 8 (f) and Fig. 9 As shown in (f), a first electrode 110 is formed to cover the metal contact layer 100 , the insulating layer 90 , the first doping region 70 and the second doping region 80 , and a second electrode 120 is formed on a side of the substrate 10 away from the drift layer 20 .

[0072] Specifically, the thickness of the insulating layer can be 400-800Å, the material can be silicon dioxide, the material of the gate can be polysilicon, the thickness of the gate oxide layer can be 400-800Å, and a dry oxygen or wet oxygen process can be used, and the preparation temperature is 1000-1500°C. If dry oxygen is used, Ar and O2 are used, and N2 and NO are used to improve the interface state between the first body region and the second body region and the gate oxide layer. The material of the first electrode and the second electrode can be Ni, Ti or other materials. If Ni metal is used, NiSi is generally formed at 600-800°C with a thickness of about 200-400nm, and then the unreacted Ni is stripped off by Ni etching solution, and high-temperature annealing is performed at 900-1000°C.

[0073] The MOS device formed by the MOS device preparation method of the present application will be described below in conjunction with an embodiment.

[0074] Example 1

[0075] like Figure 5 As shown, the MOS device provided in this embodiment includes:

[0076] Substrate 10, made of silicon carbide, with a thickness of 1 μm and a doping type of N;

[0077] The drift layer 20 is located on one side of the substrate 10 and is made of silicon carbide, has a thickness of 1 μm, and is doped with N.

[0078] The current spreading layer 40 is located on the side of the drift layer 20 away from the substrate 10, and is made of indium tin oxide, has a thickness of 2 μm, and is doped with N;

[0079] A plurality of second shielding regions 32 are located in the current spreading layer 40 and are arranged at intervals along the second direction Y. The widths of the plurality of second shielding regions 32 along the second direction Y are 1 μm, 0.7 μm and 0.5 μm, respectively. The injection depths of the plurality of second shielding regions 32 along the second direction Y are 1.1 μm. The first direction is the direction from the substrate 10 to the drift layer 20. The second direction Y is perpendicular to the first direction.

[0080] The first body region 50 is located in the current spreading layer 40 and on both sides of the second shielding region 32 in the second direction Y. The thickness of the first body region 50 is 0.8 μm and the doping type is P type.

[0081] The second body region 60 is located in the current spreading layer 40 and on the side of the second shielding region 32 away from the drift layer 20 , has a thickness of 0.8 μm, and is doped with a P type;

[0082] The first doping region 70 is located in the first body region 50 and the second body region 60 , and the doping type is P type, and the implantation depth is 0.3 μm;

[0083] The second doping region 80 is located in the first body region 50 and the second body region 60. In the first body region 50, it is located on the side of the first doping region 70 close to the second shielding region 32, and in the second body region 60, it is located on the side of the first doping region 70 away from the first body region 50, the doping type is N-type, and the implantation depth is 0.3 μm;

[0084] The gate oxide layer 411 is located on the side of the first body region 50 away from the drift layer 20 and on the side of the second body region 60 close to the first body region 50, and is made of silicon dioxide with a thickness of 500Å;

[0085] The gate 412 is located on the side of the gate oxide layer 411 away from the drift layer 20 and is made of polysilicon with a thickness of 1 μm;

[0086] An insulating layer 90, covering the gate 412, the gate oxide layer 411, the first doped region 70 located in the second body region 60 and the second doped region 80 located in the first body region 50, made of silicon oxide with a thickness of 500Å;

[0087] The metal contact layer 100 is located on the side of the first doping region 70 and the second doping region 80 away from the drift layer 20, and is made of Ti with a thickness of 400 nm;

[0088] The first electrode 110 covers the metal contact layer 100, the insulating layer 90, the first doping region 70 and the second doping region 80, and is made of Ag with a thickness of 6 μm;

[0089] The second electrode 120 is located on a side of the substrate 10 away from the drift layer 20 , and is made of Ag with a thickness of 6 μm.

[0090] Example 2

[0091] like Figure 6 As shown, the MOS device provided in this embodiment includes:

[0092] Substrate 10, made of silicon carbide, with a thickness of 1 μm and a doping type of N;

[0093] The drift layer 20 is located on one side of the substrate 10 and is made of silicon carbide, has a thickness of 1 μm, and is doped with N.

[0094] The current spreading layer 40 is located on the side of the drift layer 20 away from the substrate 10, and is made of indium tin oxide, has a thickness of 2 μm, and is doped with N;

[0095] A plurality of first shielding regions 31 are located in the current spreading layer 40 and are arranged at intervals along the first direction X. The widths of the plurality of first shielding regions 31 along the first direction X are 1 μm, 0.7 μm and 0.5 μm, respectively. The injection depths of the plurality of first shielding regions 31 along the first direction X are 1.8 μm, 1.1 μm and 0.8 μm, respectively. The first direction is the direction from the substrate 10 to the drift layer 20.

[0096] The first body region 50 is located in the current spreading layer 40 and on both sides of the first shielding region 31 in the second direction Y, the second direction Y is perpendicular to the first direction X, the thickness of the first body region 50 is 0.8 μm, and the doping type is P type;

[0097] The second body region 60 is located in the current spreading layer 40 and on the side of the first shielding region 31 away from the drift layer 20 , has a thickness of 0.8 μm, and is doped with a P type;

[0098] The first doping region 70 is located in the first body region 50 and the second body region 60 , and the doping type is P type, and the implantation depth is 0.3 μm;

[0099] The second doping region 80 is located in the first body region 50 and the second body region 60. In the first body region 50, it is located on the side of the first doping region 70 close to the first shielding region 31, and in the second body region 60, it is located on the side of the first doping region 70 away from the first body region 50, the doping type is N-type, and the implantation depth is 0.3 μm;

[0100] The gate oxide layer 411 is located on the side of the first body region 50 away from the drift layer 20 and on the side of the second body region 60 close to the first body region 50, and is made of silicon dioxide with a thickness of 500Å;

[0101] The gate 412 is located on the side of the gate oxide layer 411 away from the drift layer 20 and is made of polysilicon with a thickness of 1 μm;

[0102] An insulating layer 90, covering the gate 412, the gate oxide layer 411, the first doped region 70 located in the second body region 60 and the second doped region 80 located in the first body region 50, made of silicon oxide with a thickness of 500Å;

[0103] The metal contact layer 100 is located on the side of the first doping region 70 and the second doping region 80 away from the drift layer 20, and is made of Ti with a thickness of 400 nm;

[0104] The first electrode 110 covers the metal contact layer 100, the insulating layer 90, the first doping region 70 and the second doping region 80, and is made of Ag with a thickness of 6 μm;

[0105] The second electrode 120 is located on a side of the substrate 10 away from the drift layer 20 , and is made of Ag with a thickness of 6 μm.

[0106] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0107] 1) The introduction of the current extension layer in the MOS device of the present application increases the carrier mobility of the device by more than 100 times, and the electronic resistance of the JFET region of the corresponding device can be reduced to more than 1 / 100, thereby improving the on-resistance of the device.

[0108] 2) The MOS device of the present application introduces spaced shielding areas, and the contact area of ​​the shielding areas with the current expansion layer in a certain direction decreases, and the distance between adjacent shielding areas tends to decrease. Under the reverse voltage of the device, the current expansion layer is gradually depleted under the channel, and the electric field strength near the channel surface is gradually reduced, thereby improving the withstand voltage level and enhancing the reliability of the device.

[0109] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0110] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A MOS device, characterized in that: The invention comprises at least one cellular structure, wherein the cellular structure comprises: substrate; A drift layer, located on one side of the substrate; A first source region structure, located on a side of the drift layer away from the substrate; A second source region structure is located on a side of the drift layer away from the substrate, and a surface of the first source region structure on a side away from the substrate is located in a surface of the second source region structure on a side close to the substrate; a shielding region, at least partially located between the drift layer and the second source region structure, the shielding region comprising a plurality of first shielding regions, the first shielding regions being spaced apart and distributed along a first direction, the volumes of the plurality of first shielding regions decreasing in the first direction, the maximum vertical distances between adjacent first shielding regions decreasing in the first direction, the first direction being a direction from the substrate to the drift layer; The gate structure is located at a side of the shielding region away from the drift layer and is in contact with the first source region structure and the second source region structure.

2. The MOS device according to claim 1, characterized in that: The shielding area further includes a plurality of second shielding areas, which are spaced apart and distributed along a second direction. In the second direction, the volumes of the plurality of second shielding areas decrease gradually, and the second direction is perpendicular to the first direction.

3. The MOS device according to claim 2, characterized in that: The maximum horizontal distances between adjacent second shielding areas decrease in the second direction.

4. The MOS device according to claim 1, characterized in that: The cellular structure also includes: A current spreading layer is located at a side of the drift layer away from the substrate, and the shielding region, the first source region structure and the second source region structure are located in the current spreading layer.

5. The MOS device according to claim 4, characterized in that: The first source region structure includes a first body region, the first body region is located on both sides of the shielding region in the second direction, a surface of the first body region facing away from the substrate is located on a surface of the current spreading layer facing away from the substrate, and the second direction is perpendicular to the first direction; the second source region structure includes a second body region, the second body region is located on a side of the shielding region facing away from the drift layer.

6. A method for preparing a MOS device, characterized in that: Used to prepare the MOS device according to any one of claims 1 to 5, wherein the MOS device comprises at least one cellular structure, and the preparation method of the cellular structure comprises: providing a substrate; forming a drift layer on the substrate; A shielding region is formed on a side of the drift layer facing away from the substrate, the shielding region includes a plurality of first shielding regions, the first shielding regions are spaced apart at least along a first direction, the volumes of the plurality of first shielding regions decrease in the first direction, and the maximum vertical distances between adjacent first shielding regions decrease in the first direction, and the first direction is a direction from the substrate to the drift layer; A first source region structure and a second source region structure are formed on a side of the drift layer away from the substrate, wherein a surface of the first source region structure on a side away from the substrate is located in a surface of the second source region structure on a side close to the substrate; A gate structure is formed on a side of the shielding region away from the drift layer, and the gate structure is in contact with the first source region structure and the second source region structure.

7. The preparation method according to claim 6, characterized in that: The step of forming a shielding region on a side of the drift layer facing away from the substrate comprises: forming a current spreading layer on a side of the drift layer facing away from the substrate; forming a plurality of first shielding areas spaced apart and distributed along the first direction in the current spreading layer, or A plurality of second shielding regions are formed in the current spreading layer along a second direction and are spaced apart from each other. The second direction is perpendicular to the first direction. The shielding regions include the first shielding regions or the second shielding regions.

8. The preparation method according to claim 7, characterized in that: After the step of forming a shielding region on a side of the drift layer facing away from the substrate, the preparation method further comprises: forming a first body region on one side of the current spreading layer in the second direction; forming a second body region in the current spreading layer on a side of the shielding region away from the drift layer; A first doped region is formed in the first body region and the second body region, respectively, and a second doped region is formed in the first body region and the second body region, respectively, wherein, in the first body region, the second doped region is located between the shielding region and the first doped region, in the second body region, a projection of the second doped region on the first surface and a projection of the shielding region on the first surface at least partially overlap, the second doped region is located on a side of the first doped region facing away from the first body region, the first surface is a side surface of the drift layer facing away from the substrate, the first body region and the first doped region and the second doped region located in the first body region form a first source region structure, and the second body region and the first doped region and the second doped region located in the second body region form a second source region structure.

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