Light emitting diode and method of manufacturing the same

Abstract

The embodiment of the present disclosure provides a light emitting diode and a preparation method thereof, and belongs to the technical field of semiconductors. The light emitting diode comprises a first semiconductor layer, an insertion layer, a light emitting layer and a second semiconductor layer which are stacked in sequence, the insertion layer comprises a plurality of protrusions and a filling layer, the plurality of protrusions are located between the first semiconductor layer and the light emitting layer, the protrusions comprise a stress control layer, the stress control layer is formed by decomposing through an annealing process, and the filling layer is filled between the plurality of protrusions. The embodiment of the present disclosure can improve the light emitting efficiency and quality of the LED.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and particularly relates to a light emitting diode and a preparation method thereof. BACKGROUND

[0002] Light emitting diodes (LEDs) have been widely applied in various light source fields such as backlight, illumination and landscape, due to their small size, long service life, rich color, low energy consumption and other characteristics.

[0003] In the related art, an LED includes a substrate and a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked on the substrate.

[0004] However, there is a large lattice mismatch between the substrate and the semiconductor material, and the stress generated by the lattice mismatch accumulates to the first semiconductor layer and upwardly to the light emitting layer. The lattice mismatch stress accumulated to the light emitting layer generates a high dislocation density in the light emitting layer, which affects the quality of the light emitting layer, and generates a polarization effect in the light emitting layer, thereby reducing the radiative recombination efficiency of the electrons and holes in the light emitting layer and affecting the light emitting efficiency of the LED. SUMMARY

[0005] Embodiments of the present disclosure provide a light emitting diode and a preparation method thereof, which can improve the light emitting efficiency and quality of the LED. The technical solutions are as follows:

[0006] In one aspect, a light emitting diode is provided, which includes a first semiconductor layer, an insertion layer, a light emitting layer and a second semiconductor layer which are sequentially stacked, the insertion layer includes a plurality of protrusions and a filling layer, the plurality of protrusions are located between the first semiconductor layer and the light emitting layer, the protrusions include a stress control layer, the stress control layer is formed by decomposition using an annealing process, and the filling layer is filled between the plurality of protrusions.

[0007] Optionally, the stress control layer is an InN layer or an InSb layer.

[0008] Optionally, the thickness of the stress control layer is 50 nm to 100 nm.

[0009] Optionally, the protrusion further includes a metal mask layer, the stress control layer and the metal mask layer are sequentially stacked in a direction away from the first semiconductor layer, and the metal mask layer is formed by shrinkage using an annealing process.

[0010] Optionally, the metal mask layer is an Al layer, an Ag layer, a Sn layer or a Zn layer.

[0011] Optionally, the thickness of the metal mask layer is 1 nm to 5 nm.

[0012] Optionally, the insertion layer further includes an isolation layer, and the isolation layer is located between the first semiconductor layer and the plurality of protrusions.

[0013] Optionally, the isolation layer is an AlN layer or an AlGaN layer.

[0014] Optionally, the filling layer is an InGaN layer.

[0015] On the other hand, a method for preparing a light-emitting diode is provided, comprising: forming an insertion layer on a first semiconductor layer, the insertion layer comprising a plurality of protrusions and a filling layer, the plurality of protrusions being located between the first semiconductor layer and the light-emitting layer, the protrusions comprising a stress regulation layer, the stress regulation layer being formed by decomposition through an annealing process, and the filling layer being filled between the plurality of protrusions; forming a light-emitting layer on the insertion layer; and forming a second semiconductor layer on the light-emitting layer.

[0016] The technical solutions provided by the embodiments of the present disclosure have the following beneficial effects:

[0017] In the disclosed embodiments, an insertion layer is provided between the first semiconductor layer and the light-emitting layer. The insertion layer includes a plurality of protrusions and a leveling layer. The plurality of protrusions are located between the first semiconductor layer and the light-emitting layer. The protrusions include a stress regulation layer. The stress regulation layer can release stress accumulated in the first semiconductor layer due to the lattice mismatch between the substrate and the semiconductor material, and guide the dislocations generated by the lattice mismatch stress to be transferred to the sidewalls of the plurality of protrusions, thereby reducing the probability of dislocations extending upward into the light-emitting layer, improving the quality of the light-emitting layer, reducing the polarization effect of the light-emitting layer, thereby increasing the radiative recombination efficiency of electrons and holes in the light-emitting layer, and improving the luminous efficiency of the LED. The leveling layer is filled between the plurality of protrusions and can fill the gaps between the plurality of protrusions, ensuring good growth quality of the insertion layer and the light-emitting layer, thereby improving the quality of the LED.

[0018] Furthermore, the stress regulating layer is formed by decomposing it through an annealing process, which can reduce the probability of etching damage introduced when the stress regulating layer is formed through an etching process and thus affect the quality of the LED, thereby further improving the quality of the LED. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 This is a schematic structural diagram of an LED provided by an embodiment of the present disclosure;

[0021] Figure 2 This is a flow chart of a method for preparing an LED provided by an embodiment of the present disclosure;

[0022] Figure 3 This is a flow chart of another method for preparing an LED provided by an embodiment of the present disclosure;

[0023] Figure 4 This is a structural diagram of an LED manufacturing process provided by an embodiment of the present disclosure;

[0024] Figure 5 This is a structural diagram of an LED manufacturing process provided by an embodiment of the present disclosure;

[0025] Figure 6 This is a structural diagram of an LED manufacturing process provided by an embodiment of the present disclosure;

[0026] Figure 7 This is a structural schematic diagram of an LED manufacturing process provided by an embodiment of the present disclosure.

[0027] Reference numerals:

[0028] 10: substrate; 20: first semiconductor layer; 30: insertion layer; 31: isolation layer; 32: protrusion; 321: stress regulation layer; 321a: initial InN layer; 322: metal mask layer; 322a: initial metal layer; 33: filling layer; 40: light-emitting layer; 50: second semiconductor layer; 60: first buffer layer; 61: second buffer layer; 70: electron blocking layer; 80: contact layer. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0030] Unless otherwise defined, the technical or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second", "third" and similar terms used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "a" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" and similar terms mean that the elements or objects appearing before "include" cover the elements or objects listed after "include" and their equivalents, and do not exclude other elements or objects. "Up", "down", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0031] Figure 1: is a schematic diagram of the structure of an LED provided by an embodiment of the present disclosure. The LED can be a mini light emitting diode (Mini-LED) or a micro light emitting diode (Micro-LED) of various sizes or types. Figure 1 As shown, the LED includes a first semiconductor layer 20, an insertion layer 30, a light emitting layer 40 and a second semiconductor layer 50 stacked in sequence.

[0032] The insertion layer 30 includes a plurality of protrusions 32 and a fill layer 33. The protrusions 32 are located between the first semiconductor layer 20 and the light-emitting layer 40. The protrusions 32 include a stress-regulating layer 321 formed by decomposition using an annealing process. The fill layer 33 is filled between the protrusions 32.

[0033] In the disclosed embodiment, an insertion layer 30 is provided between the first semiconductor layer 20 and the light-emitting layer 40. The insertion layer 30 includes a plurality of protrusions 32 and a leveling layer 33. The plurality of protrusions 32 are located between the first semiconductor layer 20 and the light-emitting layer 40. The protrusions 32 include a stress-regulating layer 321. The stress-regulating layer 321 can release stress accumulated in the first semiconductor layer 20 due to the lattice mismatch between the substrate and the semiconductor material, and guide dislocations generated by the lattice mismatch stress to the sidewalls of the plurality of protrusions 32, thereby reducing the probability of dislocations extending upward into the light-emitting layer 40, improving the quality of the light-emitting layer 40, and reducing the polarization effect of the light-emitting layer 40. This thereby increases the radiative recombination efficiency of electrons and holes in the light-emitting layer 40, thereby improving the luminous efficiency of the LED. The leveling layer 33 is filled between the plurality of protrusions 32 to fill the gaps between the plurality of protrusions 32, ensuring good growth quality of the insertion layer 30 and the light-emitting layer 40, thereby improving the quality of the LED.

[0034] Furthermore, the stress regulation layer 321 is formed by decomposing it through an annealing process, which can reduce the probability of the quality of the LED being affected by etching damage introduced when forming the stress regulation layer 321 through an etching process, thereby further improving the quality of the LED.

[0035] Optionally, the stress-regulating layer 321 is an InN layer. The InN material is a heterogeneous material with the semiconductor materials in the first semiconductor layer 20 and the light-emitting layer 40 of the LED. This effectively relieves stress accumulated in the first semiconductor layer 20 due to the lattice mismatch between the substrate and the semiconductor material, thereby improving the quality of the light-emitting layer 40. Furthermore, because the InN material has a low dissociation temperature, it decomposes when annealed at a higher temperature, thereby facilitating the formation of the protruding stress-regulating layer 321 through decomposition during the annealing process.

[0036] In other embodiments, the stress regulating layer 321 may also be an InSb layer. InSb material can also play a role in relieving stress, and the decomposition temperature of InSb material is relatively low, and it can also be formed by decomposition through an annealing process.

[0037] Optionally, the thickness of the stress-regulating layer 321 is 50 nm to 100 nm. If the thickness of the stress-regulating layer 321 is too thin, the stress-regulating layer 321 is less effective in releasing lattice mismatch stress and preventing dislocations from extending upward. If the thickness of the stress-regulating layer 321 is too thick, the effectiveness of releasing lattice mismatch stress and preventing dislocations from extending upward is limited, resulting in increased production costs and possibly affecting the quality of the stress-regulating layer 321. Within this thickness range, the stress-regulating layer 321 can effectively release lattice mismatch stress and prevent dislocations from extending upward, thereby effectively improving the quality of the light-emitting layer 40 and ensuring good quality of the stress-regulating layer 321.

[0038] Exemplarily, the thickness of the stress regulation layer 321 may be 70 nm to 80 nm. For example, the thickness of the stress regulation layer 321 may be 70 nm, 75 nm, or 80 nm.

[0039] Optionally, the In component content of the stress regulation layer 321 is 0.8 to 1.

[0040] For example, the In component content of the stress regulation layer 321 may be 0.8, 0.9, or 1.

[0041] Optionally, the protrusion 32 further includes a metal mask layer 322 . The stress regulation layer 321 and the metal mask layer 322 are sequentially stacked in a direction away from the first semiconductor layer 20 . The metal mask layer 322 is formed by shrinking through an annealing process.

[0042] Thus, a metal mask layer 322 is provided on the stress-regulating layer 321. During annealing and decomposition at a relatively high temperature, the metal mask layer 322 protects the InN material beneath it, thereby preventing the decomposition of the InN material beneath the metal mask layer 322. However, the InN material not protected by the metal mask layer 322 is decomposed, thereby acting as a mask. The metal mask layer 322 is formed by shrinking during the annealing process, which facilitates the formation of multiple protrusions 32 including the stress-regulating layer 321 during the annealing process. This eliminates the need for etching to form multiple protrusions 32, thereby reducing the likelihood of etching damage introduced during the etching process affecting the quality of the LED. Furthermore, since the etching process requires interrupting the epitaxial growth process before performing secondary epitaxy, this not only increases the number of process steps but also easily introduces impurity particles that contaminate the film layer. Therefore, forming multiple protrusions 32 including the stress-regulating layer 321 through the annealing process also simplifies the process steps, reduces the likelihood of impurities contaminating the film layer during the etching process, and ensures high-quality protrusions 32.

[0043] Optionally, the metal mask layer 322 is an Al layer. Since the Al material layer becomes unstable during annealing at relatively high temperatures, surface tension on the Al material layer can cause it to break and shrink into multiple, spaced-apart nanometer-sized Al droplets, thereby facilitating a patterned masking effect on the underlying stress-regulating layer 321. Furthermore, Al has a high reflectivity, and the multiple protrusions 32 thus provided facilitate multiple reflections of light emitted from the light-emitting layer 40 between the multiple protrusions 32, making it easier for the light to be emitted outward, thereby improving the light extraction efficiency of the LED.

[0044] In other embodiments, the metal mask layer 322 may also be an Ag layer, a Sn layer, or a Zn layer, etc., which is not limited in the present disclosure.

[0045] Optionally, the thickness of the metal mask layer 322 is 1 nm to 5 nm. In this way, the metal mask layer 322 can effectively protect the InN material thereunder during annealing at a relatively high temperature, and the metal mask layer 322 will not significantly affect the quality of the insertion layer 30 .

[0046] For example, the thickness of the metal mask layer 322 may be 1 nm, 3 nm, or 5 nm.

[0047] like Figure 1 As shown, the insertion layer 30 further includes an isolation layer 31, which is located between the first semiconductor layer 20 and the plurality of protrusions 32. The isolation layer 31 can isolate the plurality of protrusions 32 from the first semiconductor layer 20, thereby reducing the impact of annealing on the quality of the first semiconductor layer 20 when forming the plurality of protrusions 32, thereby ensuring good quality of the first semiconductor layer 20.

[0048] Optionally, the isolation layer 31 is an AlN layer or an AlGaN layer. Thus, the isolation layer 31 can isolate the plurality of protrusions 32 from the first semiconductor layer 20, thereby reducing the probability of high-temperature decomposition of the first semiconductor layer 20 when annealing at a higher temperature to form the plurality of protrusions 32, thereby ensuring the good quality of the first semiconductor layer 20. The AlN layer can also relieve stress accumulated in the first semiconductor layer 20 due to the lattice mismatch between the substrate and the semiconductor material, thereby further improving the luminous efficiency of the LED.

[0049] Exemplarily, the thickness of the isolation layer 31 is 1 nm to 10 nm.

[0050] Optionally, the filler layer 33 is an InGaN layer. Filling the gaps between the protrusions 32 with the InGaN layer ensures a relatively flat surface of the insertion layer 30 away from the first semiconductor layer 20, thereby improving the quality of the LED. Furthermore, the lattice mismatch between the InGaN material and the semiconductor material in the light-emitting layer 40 is small, and the InGaN layer helps reduce stress during the growth of the light-emitting layer 40, ensuring good growth quality of the light-emitting layer 40.

[0051] Illustratively, the In composition content of the leveling layer 33 is 0.1 to 0.4.

[0052] For example, the thickness of the leveling layer 33 is greater than or equal to the height of the protrusions 32. That is, the leveling layer 33 may not only fill the spaces between the protrusions 32, but also be located on the surfaces of the protrusions 32 away from the first semiconductor layer 20. This helps to make the surface for growing the light-emitting layer 40 smoother, thereby improving the quality of the light-emitting layer 40.

[0053] Optionally, the thickness of the leveling layer 33 is 100 nm to 200 nm. For example, the thickness of the leveling layer 33 may be 140 nm to 160 nm.

[0054] like Figure 1 As shown, the LED further includes a substrate 10 , which is located on a surface of the first semiconductor layer 20 away from the insertion layer 30 .

[0055] Optionally, the substrate 10 may be a sapphire substrate, a silicon substrate, or a silicon carbide substrate.

[0056] Optionally, the first semiconductor layer 20 may be an N-type GaN layer, and the second semiconductor layer 50 may be a P-type GaN layer.

[0057] Exemplarily, the first semiconductor layer 20 is a Si-doped GaN layer.

[0058] For example, the Si doping concentration of the first semiconductor layer 20 is 1*10 19 cm -3 to 1*10 21 cm -3 .

[0059] Illustratively, the thickness of the first semiconductor layer 20 is 1 μm to 3 μm.

[0060] Exemplarily, the second semiconductor layer 50 is a Mg-doped GaN layer.

[0061] For example, the Mg doping concentration of the second semiconductor layer 50 is 1*10 19 cm -3 Up to 5*10 21 cm -3 .

[0062] Illustratively, the thickness of the second semiconductor layer 50 is 30 nm to 100 nm.

[0063] Optionally, the light-emitting layer 40 is a multi-quantum well layer comprising multiple pairs of alternating InGaN and GaN layers. Depending on the wavelength range of the LED, the light-emitting layer 40 may be made of different materials. For example, the light-emitting layer 40 of a blue-green LED may comprise multiple pairs of alternating InGaN and GaN layers, while the light-emitting layer 40 of a red LED may comprise multiple pairs of alternating InGaAs and GaAs layers.

[0064] Exemplarily, the light emitting layer 40 includes 5 to 12 pairs of alternately stacked InGaN layers and GaN layers, for example, 8 pairs of alternately stacked InGaN layers and GaN layers, and other numbers of pairs are also possible, which is not limited in the present disclosure.

[0065] Illustratively, the thickness of the InGaN layer in the light emitting layer 40 is 2 nm to 4 nm.

[0066] Illustratively, the In composition content of the InGaN layer in the light emitting layer 40 is 0.1 to 0.4.

[0067] Illustratively, the thickness of the GaN layer in the light emitting layer 40 is 8 nm to 20 nm.

[0068] It should be noted that the materials of the first semiconductor layer 20, the light-emitting layer 40 and the second semiconductor layer 50 are only used as an example. In other embodiments, the materials of the first semiconductor layer 20, the light-emitting layer 40 and the second semiconductor layer 50 can be selected according to actual needs, and the present disclosure does not impose any restrictions on this.

[0069] like Figure 1 As shown, the LED further includes a first buffer layer 60 , which is located between the substrate 10 and the first semiconductor layer 20 .

[0070] Alternatively, the first buffer layer 60 may be an AlN buffer layer. The AlN buffer layer can reduce the lattice mismatch between the substrate 10 and the semiconductor material, thereby reducing lattice defects in the LED. Because the AlN buffer layer is grown at a relatively low temperature, the first buffer layer 60 may also be referred to as a low-temperature buffer layer.

[0071] Illustratively, the thickness of the first buffer layer 60 is 15 nm to 30 nm.

[0072] Optionally, the LED further includes a second buffer layer 61 , which is located between the first buffer layer 60 and the first semiconductor layer 20 .

[0073] Alternatively, the second buffer layer 61 may be an undoped GaN buffer layer. This undoped GaN buffer layer can reduce the thermal mismatch stress between the substrate 10 and the semiconductor material, thereby ensuring better LED quality. Because this undoped GaN buffer layer is grown at a relatively high temperature, the second buffer layer 61 may also be referred to as a high-temperature buffer layer.

[0074] Illustratively, the thickness of the second buffer layer 61 is 1 μm to 3 μm.

[0075] like Figure 1 As shown, the LED chip further includes an electron blocking layer 70, which is located between the light-emitting layer 40 and the second semiconductor layer 50. The electron blocking layer 70 can block electrons, reducing the probability of electrons escaping from the light-emitting layer 40 to the second semiconductor layer 50, thereby improving the radiative recombination efficiency of electrons and holes.

[0076] Alternatively, the electron blocking layer 70 may be an AlGaN layer. Exemplarily, the Al component content of the electron blocking layer 70 is 0.1 to 0.5.

[0077] Optionally, the thickness of the electron blocking layer 70 is 50 nm to 100 nm. For example, the thickness of the electron blocking layer 70 is 70 nm to 80 nm.

[0078] Optionally, the LED chip further includes a contact layer 80 , which is located on a surface of the second semiconductor layer 50 away from the light-emitting layer 40 .

[0079] Optionally, the contact layer 80 may be a P-type GaN contact layer, which can be used to provide holes and is beneficial for reducing contact resistance.

[0080] Exemplarily, the contact layer 80 is a Mg-doped GaN contact layer.

[0081] For example, the Mg doping concentration of the contact layer 80 is 1*10 19 cm -3 Up to 5*10 21 cm -3 .

[0082] Illustratively, the thickness of the contact layer 80 is 10 nm to 30 nm.

[0083] It should be noted that the above film layer structure is only an example. In other embodiments, the LED may further include more or fewer film layer structures, and the present disclosure does not impose any limitation on this.

[0084] Figure 2 This is a flow chart of a method for preparing an LED provided by an embodiment of the present disclosure. Figure 2 As shown, the preparation method comprises:

[0085] In step S101 , an insertion layer is formed on a first semiconductor layer.

[0086] Among them, the insertion layer includes multiple protrusions and a filling layer. The multiple protrusions are located between the first semiconductor layer and the light-emitting layer. The protrusions include a stress regulation layer, which is formed by decomposition using an annealing process. The filling layer is filled between the multiple protrusions.

[0087] In step S102 , a light emitting layer is formed on the insertion layer.

[0088] In step S103 , a second semiconductor layer is formed on the light emitting layer.

[0089] In the disclosed embodiments, an insertion layer is provided between the first semiconductor layer and the light-emitting layer. The insertion layer includes a plurality of protrusions and a leveling layer. The plurality of protrusions are located between the first semiconductor layer and the light-emitting layer. The protrusions include a stress regulation layer. The stress regulation layer can release stress accumulated in the first semiconductor layer due to the lattice mismatch between the substrate and the semiconductor material, and guide the dislocations generated by the lattice mismatch stress to be transferred to the sidewalls of the plurality of protrusions, thereby reducing the probability of dislocations extending upward into the light-emitting layer, improving the quality of the light-emitting layer, reducing the polarization effect of the light-emitting layer, thereby increasing the radiative recombination efficiency of electrons and holes in the light-emitting layer, and improving the luminous efficiency of the LED. The leveling layer is filled between the plurality of protrusions and can fill the gaps between the plurality of protrusions, ensuring good growth quality of the insertion layer and the light-emitting layer, thereby improving the quality of the LED.

[0090] Furthermore, the stress regulating layer is formed by decomposing it through an annealing process, which can reduce the probability of etching damage introduced when the stress regulating layer is formed through an etching process and thus affect the quality of the LED, thereby further improving the quality of the LED.

[0091] Figure 3 This is a flow chart of another method for preparing LEDs provided by the embodiment of the present disclosure. Figure 3 As shown, the preparation method comprises:

[0092] In step S201 , a first buffer layer is formed on a substrate.

[0093] Optionally, the substrate may be a sapphire substrate.

[0094] For example, the substrate may be placed in a physical vapor deposition (PVD) device, and the temperature may be controlled to be 500° C. to 650° C. and the pressure may be controlled to be 1 torr to 10 torr to form an AlN buffer layer on the substrate to obtain the first buffer layer.

[0095] Exemplarily, the sputtering power of the PVD equipment is 2500W to 4000W.

[0096] Optionally, before performing step S201 , the preparation method may further include: decomposing oxides on the surface of the substrate using hydrogen at high temperature to remove the oxides on the surface of the substrate and obtain a clean substrate.

[0097] Optionally, after completing step S201, the preparation method may further include: placing the product having the first buffer layer formed on the substrate into a metal-organic chemical vapor deposition (MOCVD) reaction chamber, controlling the temperature of the reaction chamber to 1000° C. to 1200° C. and the pressure to 150 torr to 500 torr, and performing annealing treatment in a hydrogen atmosphere for a duration of 5 min to 10 min.

[0098] In step S202 , a second buffer layer is formed on the first buffer layer.

[0099] Optionally, in step S202 , the temperature of the reaction chamber can be controlled to be 1050° C. to 1200° C., and the pressure can be controlled to be 100 torr to 300 torr, and NH 3 and TMGa can be introduced to form an undoped GaN buffer layer on the first buffer layer to obtain a second buffer layer.

[0100] In step S203 , a first semiconductor layer is formed on the second buffer layer.

[0101] Optionally, in step S203, the temperature of the reaction chamber can be controlled to 1100° C. to 1200° C. and the pressure can be controlled to 100 torr to 300 torr, and NH 3 , TMGa and SiH 4 can be introduced to form a Si-doped GaN layer on the second buffer layer to obtain a first semiconductor layer.

[0102] In step S204 , an initial InN layer is formed on the first semiconductor layer.

[0103] Figure 4 This is a schematic diagram of the structure of an LED manufacturing process provided by an embodiment of the present disclosure. Figure 4 As shown, in step S204 , the temperature of the reaction chamber can be controlled to be 500° C. to 600° C., the pressure can be controlled to be 50 torr to 100 torr, and NH 3 and TMIn can be introduced to form an initial InN layer 321 a on the first semiconductor layer 20 .

[0104] Optionally, before performing step S204, the temperature of the reaction chamber can be controlled to 1000° C. to 1100° C. and the pressure to 30 torr to 50 torr, and NH3 and TMAl can be introduced to form an AlN layer on the first semiconductor layer 20 to obtain the isolation layer 31. When the isolation layer 31 is formed, step S204 is to form an initial InN layer 321a on the isolation layer 31.

[0105] In step S205 , a plurality of metal mask layers in a convex shape are formed on the initial InN layer.

[0106] Optionally, step S205 may include the following steps:

[0107] In the first step, an initial metal layer is formed on the initial InN layer.

[0108] like Figure 4 As shown, the temperature of the reaction chamber can be controlled to be 700° C. to 800° C. and the pressure can be controlled to be 30 torr to 50 torr, and TMAl can be introduced to form an Al material layer on the initial InN layer 321 a to obtain the initial metal layer 322 a .

[0109] In the second step, the initial metal layer is annealed to form a plurality of metal mask layers in a convex shape.

[0110] Figure 5 This is a schematic diagram of the structure of an LED manufacturing process provided by an embodiment of the present disclosure. Figure 5 As shown, the temperature of the reaction chamber can be controlled to be 1000℃ to 1100℃, the pressure to be 50torr to 100torr, and hydrogen gas can be introduced as a carrier gas to Figure 4 The initial metal layer 322a is annealed to form Figure 5 A plurality of metal mask layers 322 are formed in a convex shape.

[0111] Optionally, the duration of annealing the initial metal layer may be 10s to 100s.

[0112] When annealed at a high temperature, the Al material layer will be in an unstable state. There is tension on the surface of the Al material layer, which will cause the Al material layer to break and shrink into multiple nano-scale Al droplets arranged at intervals, forming Figure 5 The metal mask layer 322 is formed in a convex shape. The metal mask layer 322 is beneficial for protecting the InN material thereunder in the subsequent annealing step and acts as a mask.

[0113] Through the above two steps, a plurality of protruding metal mask layers 322 can be formed on the initial InN layer 321 a.

[0114] In step S206 , the initial InN layer is annealed under the cover of the plurality of protrusion-shaped metal mask layers to form a plurality of protrusions.

[0115] Figure 6 This is a schematic diagram of the structure of an LED manufacturing process provided by an embodiment of the present disclosure. Figure 6 As shown, the temperature of the reaction chamber can be controlled to be 900°C to 1000°C, the pressure to be 50 torr to 100 torr, hydrogen gas is introduced as a carrier gas, and the convex multiple metal mask layers 322 are covered to form a plurality of metal mask layers 322. Figure 5 The initial InN layer 321a in the embodiment is annealed to form Figure 6 A plurality of protrusions 32 are shown.

[0116] Optionally, the duration of annealing the initial InN layer may be 1 min to 5 min.

[0117] Since the metal mask layer 322 can protect the InN material thereunder and act as a mask, the InN material protected by the metal mask layer 322 will not decompose during annealing, while the InN material not protected by the metal mask layer 322 will be decomposed, thereby forming a plurality of protrusions 32 .

[0118] In step S207 , a filling layer is formed between the plurality of protrusions to obtain an insertion layer.

[0119] Figure 7 This is a schematic diagram of the structure of an LED manufacturing process provided by an embodiment of the present disclosure. Figure 7 As shown, the temperature of the reaction chamber can be controlled to be 700°C to 900°C, the pressure to be 50 torr to 100 torr, NH3, TMGa and TMIn to be introduced, and a filling layer 33 is filled between the multiple protrusions 32, and the filling layer 33 is an InGaN layer to obtain an insertion layer 30.

[0120] Through the above steps S204 to S207 , the insertion layer 30 can be formed on the first semiconductor layer 20 .

[0121] In step S208 , a light emitting layer is formed on the insertion layer.

[0122] Optionally, NH 3 , TEGa and TMIn may be introduced in step S208 to form a plurality of pairs of alternately stacked InGaN layers and GaN layers on the insertion layer to obtain a light-emitting layer.

[0123] Optionally, the growth temperature of the InGaN layer is 800° C. to 900° C., and the growth pressure is 100 torr to 300 torr.

[0124] Optionally, the growth temperature of the GaN layer is 900° C. to 1000° C., and the growth pressure is 100 torr to 300 torr.

[0125] In step S209 , an electron blocking layer is formed on the light emitting layer.

[0126] Optionally, in step S209 , the temperature of the reaction chamber can be controlled to be 950° C. to 1050° C. and the pressure can be controlled to be 50 torr to 100 torr, and NH 3 , TEGa and TMAl can be introduced to form an AlGaN layer on the light-emitting layer to obtain an electron blocking layer.

[0127] In step S210 , a second semiconductor layer is formed on the electron blocking layer.

[0128] Optionally, in step S210, the temperature of the reaction chamber can be controlled to 950° C. to 1050° C. and the pressure can be controlled to 100 torr to 600 torr, and NH 3 , TEGa and Cp 2 Mg can be introduced to form a Mg-doped GaN layer on the electron blocking layer to obtain a second semiconductor layer.

[0129] In step S211 , a contact layer is formed on the second semiconductor layer.

[0130] Optionally, in step S211, the temperature of the reaction chamber can be controlled to be 1000° C. to 1100° C. and the pressure can be controlled to be 100 torr to 300 torr, and NH 3 , TEGa and Cp 2 Mg can be introduced to form a Mg-doped GaN contact layer on the second semiconductor layer to obtain a contact layer.

[0131] Optionally, after completing step S211, the preparation method may include: controlling the temperature of the reaction chamber to be 650° C. to 850° C., and performing an annealing treatment on the LED in a nitrogen atmosphere for a duration of 5 min to 15 min.

[0132] Optionally, the material, doping concentration, thickness, component content and number of cycles of each layer can be found in Figure 1 Detailed description of the related embodiments is omitted here.

[0133] The above description does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not intended to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments with equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure are still within the scope of the technical solution of the present disclosure.

Claims

1. A light emitting diode, characterized in that: It comprises a first semiconductor layer (20), an insertion layer (30), a light-emitting layer (40) and a second semiconductor layer (50) stacked in sequence, The insertion layer (30) comprises a plurality of protrusions (32) and a filling layer (33), the plurality of protrusions (32) are located between the first semiconductor layer (20) and the light-emitting layer (40), the protrusions (32) comprise a stress regulating layer (321), and the stress regulating layer (321) is formed by decomposition using an annealing process; The filling layer (33) is filled between the plurality of protrusions (32); The protrusion (32) further includes a metal mask layer (322), and the stress regulation layer (321) and the metal mask layer (322) are stacked in sequence along a direction away from the first semiconductor layer (20).

2. The light emitting diode according to claim 1, characterized in that The stress regulating layer (321) is an InN layer or an InSb layer.

3. The light emitting diode according to claim 2, characterized in that The thickness of the stress regulating layer (321) is 50 nm to 100 nm.

4. The light emitting diode according to any one of claims 1 to 3, characterized in that: The metal mask layer (322) is formed by shrinking through an annealing process.

5. The light emitting diode according to claim 4, characterized in that The metal mask layer (322) is an Al layer, an Ag layer, a Sn layer or a Zn layer.

6. The light emitting diode according to claim 5, characterized in that The thickness of the metal mask layer (322) is 1 nm to 5 nm.

7. The light emitting diode according to any one of claims 1 to 3 and claims 5 to 6, characterized in that: The insertion layer (30) further includes an isolation layer (31), wherein the isolation layer (31) is located between the first semiconductor layer (20) and the plurality of protrusions (32).

8. The light emitting diode according to claim 7, characterized in that The isolation layer (31) is an AlN layer or an AlGaN layer.

9. The light emitting diode according to any one of claims 1 to 3, claims 5 to 6 and claim 8, characterized in that The filling layer (33) is an InGaN layer.

10. A method for preparing a light emitting diode, characterized in that: include: An insertion layer (30) is formed on the first semiconductor layer (20), the insertion layer (30) comprising a plurality of protrusions (32) and a filling layer (33), the plurality of protrusions (32) being located between the first semiconductor layer (20) and the light-emitting layer (40), the protrusions (32) comprising a stress regulating layer (321), the stress regulating layer (321) being formed by decomposition through an annealing process, and the filling layer (33) being filled between the plurality of protrusions (32); the protrusions (32) further comprising a metal mask layer (322), the stress regulating layer (321) and the metal mask layer (322) being stacked in sequence in a direction away from the first semiconductor layer (20); forming a light-emitting layer (40) on the insertion layer (30); A second semiconductor layer (50) is formed on the light emitting layer (40).

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