UPS parallel operation system synchronous and buffer starting control method

Abstract

The application discloses a UPS parallel system synchronous slow start control method, the UPS parallel system comprises a plurality of parallel UPSs; the method comprises the following steps: a plurality of UPSs simultaneously upload output state information of the UPSs to a first bus; the plurality of UPSs simultaneously acquire bus transmission information from the first bus; in the case that the output state information of any UPS indicates that the UPS is in an output state, the bus transmission information indicates that the UPS parallel system is in the output state; the UPS acquires an inverter target voltage; the inverter target voltage is determined according to the bus transmission information; in the output state, each UPS simultaneously slowly increases the inverter given voltage to the inverter target voltage based on the synchronous time sequence of the first bus at a preset slow start rate.

Description

Technical Field

[0001] This application relates to, but is not limited to, the power grid field, and in particular to a synchronous soft start control method for a UPS parallel system. Background Technology

[0002] When there are impulsive loads such as transformers at the power output, a soft start-up of the inverter output voltage can reduce the current surge during startup, thus decreasing the probability of damage to fuses, switching transistors, and user loads. However, when a parallel uninterruptible power supply (UPS) operates in impulsive load mode, the different soft start-up timings of each UPS will lead to voltage differences among the UPSs during the soft start-up process. This can create circulating currents between UPSs, increasing the probability of damage to the UPS and even the user load. Summary of the Invention

[0003] This application provides a synchronous soft-start control method for a parallel UPS system, which can achieve voltage soft-start under impact load mode, reduce circulating current between parallel UPSs, and reduce the probability of damage to the UPS and even the user load.

[0004] The technical solution of this application is implemented as follows:

[0005] This application provides a synchronous soft-start control method for a UPS parallel system, wherein the UPS parallel system includes multiple UPSs connected in parallel; the method includes:

[0006] Multiple UPS units simultaneously upload their output status information to the first bus;

[0007] Multiple UPSs simultaneously acquire bus transmission information from the first bus; when the output status information of any one of the UPSs indicates that the UPS is in the output state, the bus transmission information indicates that the UPS parallel system is in the output state;

[0008] The UPS acquires the inverter target voltage; the inverter target voltage is determined based on the bus transmission information; in the output state, each UPS simultaneously raises the inverter given voltage to the inverter target voltage according to a preset soft-start rate and based on the synchronization timing of the first bus.

[0009] The embodiment of the present application provides a UPS parallel system synchronous slow start control method, since each UPS in the UPS parallel system can upload the transmission state of the UPS on the first bus in time sequence synchronization, and then the transmission state of the UPS parallel system is determined; and the transmission state of the UPS parallel system is used for determining the inverter target voltage; in this way, each UPS is based on the synchronous time sequence of the first bus, and simultaneously slowly starts from the inverter given voltage to the inverter target voltage according to the preset slow start rate. Therefore, the voltage consistency of each UPS at any moment in the slow start process can be improved, the circulating current is reduced, and the safety of the UPS and the user load is improved. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 A structure schematic diagram of a parallel UPS in a related art is provided for the embodiment of the present application.

[0011] Figure 2 A flowchart of a UPS parallel system synchronous slow start control method is provided for the embodiment of the present application.

[0012] Figure 3 A structure schematic diagram of an optional UPS parallel system is provided for the embodiment of the present application.

[0013] Figure 4 A structure schematic diagram of another optional UPS parallel system is provided for the embodiment of the present application.

[0014] Figure 5 A voltage slow start process schematic diagram of an optional UPS parallel system is provided for the embodiment of the present application.

[0015] Figure 6 A voltage and current change process schematic diagram in an optional slow start process is provided for the embodiment of the present application. Figure 1

[0016] Figure 7 A voltage and current change process schematic diagram in an optional slow start process is provided for the embodiment of the present application. Figure 2

[0017] Figure 8 A voltage and current change process schematic diagram in an optional slow start process is provided for the embodiment of the present application. Figure 3

[0018] Figure 9 A voltage and current change process schematic diagram in an optional slow start process is provided for the embodiment of the present application. Figure 4

[0019] Figure 10 A voltage and current change process schematic diagram in an optional slow start process is provided for the embodiment of the present application. Figure 5 ​​​​​

[0020] Figure 11 An optional voltage and current change process in a slow start process provided for an embodiment of the present application Figure 6 ;

[0021] Figure 12 An optional voltage and current change process in a slow start process provided for an embodiment of the present application Figure 7 . DETAILED DESCRIPTION

[0022] In order to make the purposes, technical solutions and advantages of the present application clearer, the following will further describe the present application in conjunction with the accompanying drawings, and the described embodiments should not be regarded as limiting the present application, and all other embodiments obtained by those skilled in the art without making creative efforts fall within the scope of protection of the present application.

[0023] In the following description, "some embodiments" are referred to, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0024] In the following description, the terms "first\second\third" are only to distinguish similar objects, and do not represent a specific order of the objects, and it can be understood that "first\second\third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application, and are not intended to limit the present application.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the present application, and are not intended to limit the present application.

[0027] For the purpose of understanding the present application, before the embodiments of the present application are described, the application background in the embodiments of the present application is described.

[0028] Figure 1 The structure of a related technology parallel UPS (the parallel UPS is also called a UPS parallel system, a parallel UPS system, etc.) is shown, as shown in Figure 1As shown in the figure, the parallel UPS includes a plurality of UPSs (exemplarily shown as UPS1 and UPS2), UPSj (j is 1 or 2) is powered by a battery pack Pj, and under the joint action of a static switch Kj2 and a bypass switch Kj1, the user load L is powered through a main path j or a bypass j. The parallel UPS can supply power to the user load through at least one UPS, and in the case of at least one including a plurality of cases, a plurality of UPSs are required to maintain voltage synchronization during the common soft start process, that is, the consistency of the voltage at any time point. At any time point, a circulating current will be generated between two UPSs with different voltages, causing a current impact, and further causing damage to the UPS and even the user load.

[0029] To solve the above problems, the embodiment of the application provides a UPS parallel system synchronous soft start control method, which can simultaneously perform soft start, improve the voltage synchronization of the parallel UPS during the soft start process, reduce the circulating current between the parallel UPSs, and further reduce the damage probability of the UPS and even the user load.

[0030] Figure 2 A flowchart of a UPS parallel system synchronous soft start control method provided by the embodiment of the application is shown in the figure, Figure 3 Exemplarily shown in the figure are three UPSs: UPS21, UPS22 and UPS23. In the embodiment of the application, the number of UPSs is N, N is an integer greater than 1, each UPS is denoted as UPS2i, N≥i≥1, i is a positive integer, and in the embodiment of the application, the number of UPSs is three. Figure 3 In the example of the figure, N=3.

[0031] As shown in the figure, Figure 2 The method can include:

[0032] S101: A plurality of UPSs simultaneously upload output state information of the UPSs to a first bus;

[0033] S102: A plurality of UPSs simultaneously obtain bus transmission information from the first bus; in the case that the output state information of any one UPS indicates that the UPS is in an output state, the bus transmission information indicates that the UPS parallel system is in an output state;

[0034] S103: The UPS obtains an inverter target voltage; the inverter target voltage is determined according to the bus transmission information; in the output state, each UPS according to a preset soft start rate, based on the synchronization timing of the first bus, soft starts the inverter given voltage to the inverter target voltage.

[0035] Here, the inverter given voltage is a given value of inverter closed-loop control, and the inverter given voltage can be set according to actual needs, which is not limited in the embodiment of the application.

[0036] As shown in the figure, Figure 3As shown, in the embodiment of the present application, the plurality of UPSs in the UPS parallel system are connected in parallel, and each UPS is a communication node in the first bus CAN1. The first bus CAN1 is a time-synchronous bus, and each node simultaneously transmits or receives data to or from the first bus CAN1 under the same time control. In some embodiments, the UPS 2i can transmit data to the first bus CAN1 when a clock edge arrives, and receive data from the first bus CAN1 when a clock edge arrives.

[0037] In the embodiment of the present application, the topology of the first bus CAN1 can be a linear topology, a star topology, a tree topology, a ring topology, or the like. The topology can be set as needed, and the embodiment of the present application does not limit the topology.

[0038] In some embodiments, the first bus is a Controller Area Network (CAN) bus. For the discrete CAN bus, all nodes on the bus are time-synchronously transmitted or received to or from the bus at the same time, and have a high communication rate. It should be noted that, in order to ensure that the start time of the inverter buffer of all UPSs in the UPS parallel system is synchronized, the time-synchronous nature of the discrete CAN bus can be used to achieve the synchronization, but the discrete CAN bus is only one means to achieve the first bus, and other means can also be used, which are not limited herein.

[0039] In the embodiment of the present application, the UPS 2i can simultaneously upload the output state information of itself to the first bus CAN1. The output state information indicates whether the transmission state of the UPS 2i is an output state or a non-output state. In some embodiments, the method further includes: in the case that the output condition is met, the UPS 2i determines that the output state of itself is in the output state. The output condition includes at least one of the following: the UPS 2i is in the inverter output (main circuit output), self-aging, bypass output, economic operation (ECO) mode, or WECO (i.e., intelligent ECO) state, in any of the above cases, the UPS 2i is in the output state; otherwise, the UPS 2i is in the non-output state.

[0040] In the embodiment of the present application, after the UPS 2i uploads the output state information of itself to the first bus CAN1, the first bus CAN1 transmits the bus transmission information. In the case that the output state information of at least one of the plurality of UPSs indicates that the output state of itself is in the output state, the bus transmission information on the first bus CAN1 is in the output state. That is, if any UPS 2i is in the output state and supplies power to the load, it indicates that the UPS parallel system supplies power to the load, and the UPS parallel system is in the output state.

[0041] In the embodiments of the present application, the uploaded output state information is a dominant level when the UPS 2i is in the output state; and the uploaded output state information is a recessive level when the UPS 2i is in the non-output state. When any one of the UPS 2i uploads the dominant level, the bus transmission information transmitted by the first bus CAN1 is a dominant level.

[0042] In some embodiments, the dominant level is a high level and the recessive level is a low level (only as an example, and the opposite can also be possible). When any one of the UPS 2i is in the output state and uploads the output state information as a high level, the bus transmission information of the first bus CAN1 is a high level. In this way, each UPS 2i can obtain the bus transmission information as a high level, and then determine that the UPS parallel system is in the output state and supplies power to the load. It can be understood that, in this case, the UPS parallel system as a whole is in the output state and supplies power to the load together, and each UPS in the UPS parallel system performs the soft start according to the same preset soft start rate and the same time sequence, but only the UPS in the output state supplies power to the load, and the remaining UPSs perform the soft start but are not in the output state and do not supply power to the load; since multiple UPSs perform the soft start together, the problem of circulating current is effectively improved.

[0043] In the embodiments of the present application, each UPS 2i can obtain the inverter target voltage. In some embodiments, each UPS 2i can determine the inverter target voltage according to the bus transmission information. In some embodiments, multiple parallel UPSs 2i can determine the inverter target voltage by one UPS, and then share the inverter target voltage with other slaves. In some embodiments, the UPS that determines the inverter target voltage can be a master, and the other UPSs can be slaves. In some embodiments, the master is the UPS with the highest priority of transmission information, and the other UPSs are slaves. In some embodiments, the master and the slave communicate through the second bus CAN2.

[0044] In some embodiments, the second bus CAN2 can be a standard CAN bus, for which the nodes on the bus need to follow the priority principle when sending information to the bus, and the node with a high priority can successfully send information to the bus. Alternatively, the second bus CAN2 can also be a Local Interconnect Network (LIN) bus, a Serial Peripheral Interface (SPI) bus, a Universal Asynchronous Receiver / Transmitter (UART) bus, or the like, and the corresponding functions can still be implemented; for this, the actual needs can be set, and the embodiments of the present application do not make any limitation.

[0045] In this embodiment, when each node on the second bus CAN2 uploads data to the second bus CAN2, the data from the node with the highest transmission priority can be successfully uploaded to the second bus CAN2. Thus, in a UPS parallel system where multiple UPSs are in output mode, the UPS with the highest transmission priority can act as the master.

[0046] based on Figure 3 , Figure 4 A schematic diagram of a UPS parallel system is shown. Figure 2 ,like Figure 4 As shown, UPS2i can also communicate via the second bus CAN2. Multiple UPS units include one master unit and at least one slave unit, and the master unit and slave unit communicate with each other via the second bus CAN2. The UPS can obtain the inverter target voltage, which may include:

[0047] The host determines the inverter target voltage based on the bus transmission information and transmits the inverter target voltage to at least one slave device via the second bus CAN2.

[0048] In this embodiment, different bus transmission information represents different transmission states of the UPS parallel system. A high bus transmission level indicates the parallel UPS is in an output state; a low bus transmission level indicates the parallel UPS is in a non-output state (this is just an example; the opposite representation is also possible). Different output states of the parallel UPS result in different inverter target voltages. After the master unit shares the inverter target voltage with each slave unit via the second bus CAN2, each UPS2i, when in an output state, can gradually transition from the given inverter voltage to the inverter target voltage. The given inverter voltage for each UPS2i is the same, and its magnitude can be set as needed; this embodiment does not impose any limitations. When a UPS2i is in a non-output state, the given inverter voltage and the inverter target voltage can be the same, so that when the UPS2i transitions to an output state, it can still gradually transition from the given inverter voltage.

[0049] Understandably, the slave device can obtain the inverter target voltage from the master device through the second bus CAN2, instead of each UPS2i determining the same inverter target voltage in the same way. This can reduce the computing resource consumption of the UPS2i.

[0050] In some embodiments, the UPS 2i can determine the transmission flag according to its own transmission state, and output state information to the first bus according to the transmission flag. For example, when the transmission state is an output state, the UPS 2i can set the transmission flag to "1". At this time, the UPS 2i transmits a high level to the first bus, so that the bus transmission information on the first bus CAN1 is a high level. When the transmission state is a non-output state, the UPS 2i can set the transmission flag to "0". At this time, the UPS 2i transmits a low level to the first bus CAN1, and when all the UPS 2i in the UPS parallel system transmit a low level to the first bus CAN1, the bus transmission information on the first bus CAN1 is a low level. That is, when the output state information from any one UPS is a high level, the signal received by the first bus is a high level, which indicates that the parallel UPS is in an output state.

[0051] In some embodiments of the present application, the method can further include:

[0052] When the bus transmission information indicates that the UPS parallel system is in an output state, the host determines that the inverter target voltage is a rated voltage.

[0053] In the embodiments of the present application, when the bus transmission information on the first bus is a high level, it indicates that at least one UPS 2i in the UPS parallel system is in an output state, and the UPS parallel system is in an output state. At this time, the host can determine that the inverter target voltage is a rated voltage. After the host shares the rated voltage to each slave through the second bus CAN2, all the UPS 2i can obtain the rated voltage as the inverter target voltage. Then, the UPS 2i can gradually increase the inverter given voltage to the rated voltage when the UPS parallel system is in an output state. Here, the rated voltage is greater than or equal to the inverter given voltage. The value of the rated voltage can be set according to the needs, and the embodiments of the present application do not make any limitation.

[0054] It can be understood that multiple UPSs can simultaneously increase the inverter given voltage, and the target value is the rated voltage. In this way, the consistency of the voltage between the UPSs during the voltage increasing process can be improved, and the circulating current can be reduced.

[0055] In some embodiments of the present application, the method can further include:

[0056] When the bus transmission information indicates that the parallel UPS is in a non-output state, the host determines that the inverter target voltage is a starting voltage.

[0057] In the embodiment of the present application, the bus transmission information on the first bus CAN1 is low, indicating that all the UPSs 2i are in the non-output state, and the UPS parallel system is in the non-output state. At this time, the host computer can determine that the inverter target voltage is the starting voltage. That is, the UPS 2i can start to gradually increase the inverter given voltage from the starting voltage. Here, the starting voltage is smaller than the inverter given voltage, and the starting voltage is small enough so that the current peak of the UPS during the gradual increase is smaller than the current threshold. The starting voltage and the current threshold can be set as needed, and the embodiment of the present application does not limit them.

[0058] It can be understood that, by setting the starting voltage to be smaller than the inverter given voltage, the UPS 2i can start to gradually increase from the starting voltage. In this way, the current peak of the UPS during the gradual increase under the impact load can be reduced.

[0059] In some embodiments of the present application, the method further comprises:

[0060] In the case where the bus transmission information indicates that the UPS parallel system is in the non-output state, the UPS 2i determines that the inverter given voltage is the starting voltage.

[0061] In the embodiment of the present application, the bus transmission information on the first bus CAN1 is low, indicating that all the UPSs 2i are in the non-output state, and the UPS parallel system is in the non-output state. At this time, the UPS 2i can also determine that the inverter given voltage is the starting voltage. That is, in the case where none of the UPSs 2i is supplying power to the load, both the inverter given voltage and the inverter target voltage are the starting voltage. In this way, after the UPS 2i changes to the output state, the UPS 2i can start to gradually increase from the starting voltage under the impact load mode, reducing the current peak of the UPS 2i during the gradual increase.

[0062] In some embodiments, during the gradual increase of the UPS parallel system, if new output state information of a UPS indicates that the UPS is in the output state, the new UPS in the output state and the UPSs already in the output state share the current together.

[0063] It should be noted that, as described above, for the UPS parallel system, if at least one of the UPSs is in the output state, all the UPSs gradually increase according to the same time sequence, but the UPSs in the non-output state do not supply power to the load, and only the UPSs in the output state supply power to the load. If a UPS changes from the non-output state to the output state during the gradual increase of the UPS parallel system, the new UPS in the output state also starts to supply power to the load and shares the current with the UPSs already in the output state, thereby reducing the current pressure borne by each UPS.

[0064] Thus, since all the UPSs are synchronously started, the voltage of the new UPS in the output state is the same as that of the UPS already in the output state, and no circulating current problem occurs due to the voltage difference, effectively improving the stability and safety of the UPS parallel system.

[0065] In some embodiments, the method can further include:

[0066] If the UPS in the non-output state receives the start-up instruction, the state information of the UPS changes to the output state.

[0067] It should be noted that in the embodiments of the present application, if the UPS in the non-output state receives the start-up instruction, the UPS changes to the output state, so that in the start-up process of the parallel UPS system, if a UPS in the non-output state receives the start-up instruction, the UPS also supplies power to the load, sharing the current pressure.

[0068] Figure 5 A detailed flowchart of the start-up process of a UPS parallel system is shown, as shown in Figure 5 The process can include:

[0069] S11, the UPS 2i uploads the output state information to the first bus.

[0070] S12, the UPS 2i reads the bus transmission information on the first bus.

[0071] S13, it is judged whether the bus is without output, or the bypass output is out of synchronization, or the ECO output is out of synchronization. If yes, S15 is executed; otherwise, S14 is executed.

[0072] It should be noted that it is judged whether the bus is without output, that is, according to the bus transmission information, the transmission state of the UPS parallel system is judged, if the UPS parallel system is in the non-output state, it is determined that the bus is without output, if the UPS parallel system is in the output state, it is determined that the bus has output. The bypass output out of synchronization refers to the problem that the UPS fails to keep the frequency, phase and amplitude synchronized in the process of trying to keep its inverter output synchronized with the bypass power supply. The ECO output out of synchronization is temporarily disabled or out of synchronization due to the priority of other important functions under certain conditions.

[0073] In addition, the bypass output out of synchronization or the ECO output out of synchronization can also be considered as a manifestation of the bus without output, and the bypass output not out of synchronization or the ECO output not out of synchronization can also be considered as a manifestation of the bus with output.

[0074] It should be further explained that in the embodiments of the present application, the "bus has output" flag bit can be used to indicate whether one or more UPSs on the output bus are in the output state. The working principle is that when any one of the bypass or inverter of any one of the UPSs is in the output state, the UPS will set its own "bus has output" flag bit to 1 and send a dominant level on the discrete CAN bus through the field programmable logic gate array (FPGA), and then all the UPSs on the bus read back the bit as 1.

[0075] In the embodiments of the present application, if the host determines that the bus transmission information is high level, i.e. the transmission flag bit is 1, it indicates that at least one of the multiple UPSs 2i in parallel is in the output state. If the host determines that the bus transmission information is low level, i.e. the transmission flag bit is 0, it indicates that all the multiple UPSs 2i in parallel are in the non-output state.

[0076] Here, the host can perform out-of-sync detection through a software phase-locked loop to obtain a detection result to determine whether there is bypass output out-of-sync or ECO output out-of-sync. Among them, the first level phase-locked loop out-of-sync means that the phase of the software lock is different from the actual phase of the bypass. The second level phase-locked loop out-of-sync means that the inverter phase is different from the phase of the first level phase-locked loop.

[0077] S14, the host determines that the inverter target voltage is the rated voltage.

[0078] S15, the host determines that the inverter target voltage is the starting voltage.

[0079] S16, the host transmits the inverter target voltage to the slave through the second bus.

[0080] S17, it is determined whether the bus has no output. If the determination result is yes, S19 is executed; otherwise, S18 is executed.

[0081] S18, the UPS 2i increases the inverter given voltage to the inverter target voltage.

[0082] S19, the UPS 2i determines that the inverter given voltage is the starting voltage.

[0083] It should be noted that in the embodiment of the present application, the "inverter target voltage" of the slave machine follows the "inverter target voltage" of the current-sharing host machine (i.e. the aforementioned host machine), and the current-sharing host machine shares the "inverter target voltage" through the standard CAN (i.e. the second bus). In the impact load mode, when the current-sharing host machine detects that the "bus has output" flag bit is 0, or the bypass output state is out of synchronization, or the ECO output state is out of synchronization, the "inverter target voltage" is returned to the starting voltage. Otherwise, when the current-sharing host machine detects that the "bus has output" flag bit is 1, the "inverter target voltage" is set to the rated voltage.

[0084] When the bus has output (i.e. the UPS parallel system is in the output state), the "inverter given voltage" values of all the UPSs gradually approach the "inverter target voltage" at a set rate. Otherwise, the "inverter given voltage" values of all the UPSs are equal to the starting voltage.

[0085] In the parallel machine gradual start-up scheme described above, when one or more of the parallel machines receives a start-up instruction and performs inverter output, the "bus has output" flag bit of all the UPSs changes from 0 to 1, so that the current-sharing host machine changes the "inverter target voltage" value of the bus from the starting voltage to the rated voltage; then the "inverter given voltage" of all the UPSs on the bus gradually approaches the "inverter target voltage" together, so as to realize the synchronization of the parallel machine UPS gradual start-up voltage values.

[0086] In the embodiment of the present application, in the case that at least one of the UPSs 2i supplies power to the user load, each UPS 2i needs to gradually start up from the inverter given voltage to the rated voltage. In the case that none of the UPSs 2i supplies power to the user load, the UPS 2i can determine that the inverter target voltage and the inverter given voltage are the starting voltage; thus, in the case that the UPS 2i supplies power to the user load, the gradual start-up can be started from the starting voltage.

[0087] For example, the UPS 21 and the UPS 22 are in the output state, and the UPS 23 is in the non-output state, and all of them upload the output state information to the first bus, the UPS 21 and the UPS 22 upload high-level signals, and the UPS 23 uploads a low-level signal. Thus, the bus transmission information on the first bus CAN1 is high. If the output priority of the UPS 21 is higher than the priority of the UPS 22, and the priority of the UPS 22 is higher than the priority of the UPS 23, the transmission priority of the UPS 21 is the highest, and the UPS 21 is the host machine. The UPS 21 can determine that the inverter target voltage is the rated voltage when the bus transmission information is high, and share the rated voltage to the UPS 22 and the UPS 23 through the second bus CAN2. Thus, the UPS 21 and the UPS 22 can gradually start up from the inverter given voltage to the rated voltage, and the inverter given voltage and the inverter target voltage of the UPS 23 are both the starting voltage, and the gradual start-up can be started from the starting voltage when the UPS 23 turns to the output state.

[0088] In the user load is transformer, that is, the impact load mode, if two UPSs are started at the same time, and the starting voltage is 0V, the starting current peak value is high during the starting stage of the soft starting. In the case of the current exceeding the peak threshold, the inverter output short circuit alarm may be generated. Figures 5-11 The voltage and current changes of different starting voltage soft starting are shown. As shown in Figures 5-11 , the current scanning frequency is 100k / s. Among them, Iin and Iout are the inverter inductance currents of two UPSs, and the display upper limit is 200A; Vout is the parallel output voltage of two UPSs, and the display upper limit is 100V. In Figure 5 , the starting voltage is 0V, and the current peak value of two UPSs is high, which can exceed 200A, and even reach 600A. Figures 6-11 The starting voltage of the two UPSs is 10V, 20V, 30V, 40V, 50V and 60V, and the current peak value of the two UPSs is less than 200A. Therefore, the starting voltage can be greater than 10V.

[0089] In some embodiments of the present application, the starting voltage is greater than or equal to 10V and less than or equal to 60V.

[0090] It can be seen from Figures 5-11 that when the starting voltage is between 10V and 60V, the current peak value is less than 200A. Here, the setting of the starting voltage is not limited in the embodiments of the present application. In order to reserve a certain margin, the starting voltage can be set to 20V.

[0091] In the embodiments of the present application, when the UPS2i performs voltage soft starting, it can be started according to the preset soft starting rate. The preset soft starting rate can be set as needed, and the embodiments of the present application are not limited. For example, the preset soft starting rate can be 1V / working frequency period. In this way, the starting value of the voltage soft starting of the UPS2i is the inverter given voltage, and the termination value is the inverter target voltage. In the case that the soft starting rate is the preset soft starting rate, at any moment during the soft starting process, the voltage of the UPS2i is the same. It can further improve the voltage synchronization and reduce the circulating current.

[0092] In summary, to be compatible with the impact load mode in the parallel operation condition, the parallel operation buffer start function is added in the parallel operation UPS system (for example, 480V high voltage UPS product) in the embodiments of the present application. In the parallel operation condition of multiple UPSs, the parallel operation buffer start function in the embodiments of the present application uses the high-speed same-line characteristic of the discrete CAN to ensure that the buffer start time of all the UPSs in the parallel operation system is almost synchronous, so that the given voltage of the inverter of each parallel operation can have a small difference, thereby realizing the buffer start of any one UPS alone or the buffer start of multiple UPSs together. Meanwhile, during the buffer start, the UPS inputting the start instruction can join the buffer start in the middle, share the starting current, and reduce the current stress of each UPS.

[0093] The parallel operation inverter voltage buffer start control scheme is shown in Figure 5 The "inverter given voltage" is used as the given value of the inverter closed-loop control. The timing synchronization is realized by the parallel operation discrete CAN communication, and the information synchronization is realized by the parallel operation standard CAN communication. Whether each parallel operation UPS is in the inverter output state or not, the "inverter given voltage" can be simultaneously buffered.

[0094] It should be noted that the above description of the various embodiments is inclined to emphasize the differences between the various embodiments, and the same or similar parts can be referred to each other. In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be realized by other ways. The above-described device embodiments are only schematic, for example, the division of the modules is only a logical function division, and in actual implementation, other division manners can be used, for example, multiple modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the various components shown or discussed can be indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0095] The above description is only for the embodiments of the present application, and is not used to limit the protection scope of the present application. Any modification, equivalent replacement and improvement made within the spirit and scope of the present application shall be included in the protection scope of the present application.

Claims

1. A method for controlling synchronization and soft start of a UPS parallel operation system, characterized in that, The UPS parallel system comprises a plurality of UPSs in parallel; the method comprises: The plurality of UPSs simultaneously upload output state information of the UPSs to a first bus; The plurality of UPSs simultaneously acquire bus transmission information from the first bus; in the case that the output state information of any one of the UPSs represents that the UPS is in an output state, the bus transmission information represents that the UPS parallel system is in the output state; The UPS acquires an inverter target voltage; the inverter target voltage is determined according to the bus transmission information; in the output state, each of the UPSs simultaneously ramps up an inverter given voltage to the inverter target voltage based on synchronous timing of the first bus at a preset ramp-up rate; The plurality of UPSs comprises a master and at least one slave, and the master and the slave communicate through a second bus; the UPS acquires an inverter target voltage, which comprises: The master determines the inverter target voltage according to the bus transmission information, and transmits the inverter target voltage to the at least one slave through the second bus; The method further comprises: in the case that the bus transmission information represents that the UPS parallel system is in the output state, the master determines the inverter target voltage as a rated voltage; The method further comprises: in the case that the bus transmission information represents that the UPS parallel system is in a non-output state, the master determines the inverter target voltage as a starting voltage.

2. The method of claim 1, wherein, In the case that the output state information from any one of the UPSs is a high level, a signal received by the first bus is the high level; the high level represents that the UPS parallel system is in the output state.

3. The method of claim 1, wherein, The method further comprises: In the case that the bus transmission information represents that the UPS parallel system is in a non-output state, the UPS determines the inverter given voltage as a starting voltage.

4. The method of claim 3, wherein, The starting voltage is greater than 10V and less than or equal to 60V.

5. The method according to any one of claims 1 to 4, characterized in that, In the process of ramping up of the UPS parallel system, if there is a new UPS in the output state, the new UPS in the output state and the UPSs already in the output state share the current together.

6. The method of claim 5, wherein, The method further comprises: If the UPS in the non-output state receives a start-up instruction, the state information of the UPS changes to the output state.

7. The method of claim 1, wherein, The method further comprises: In the case that an output condition is met, the UPS determines that it is in the output state; the output condition comprises at least one of the following: bypass output; inverter output.

8. The method of claim 1, wherein, The first bus is a discrete local area network controller CAN bus; and the second bus is a standard CAN bus.

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