A circuit for suppressing ripple of an amplitude detector and a method of suppressing ripple thereof

Abstract

The application discloses a circuit for suppressing ripple of an amplitude detector and a suppression method thereof. The circuit comprises an amplitude detection loop and a ripple elimination loop. The amplitude detection loop comprises a peak value detector, a valley value detector and a subtractor. The ripple elimination loop comprises a first inverter, a second inverter, a time difference generator, an integrator and a half-peak value detector. The suppression method comprises: obtaining a differential input signal and performing amplitude detection to obtain a peak-to-peak value of the differential input signal; and performing a capacitance charging and discharging rate adjustment process according to the peak-to-peak value of the differential input signal to eliminate ripple information of the differential input signal. The embodiment of the application can match the charging and discharging speed of the capacitance with the input signal frequency to eliminate the ripple, and the input signal amplitude has no influence. The application can be widely applied in the technical field of analog integrated circuits.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog integrated circuits, and in particular to a circuit for suppressing ripple of an amplitude detector and a method for suppressing ripple of an amplitude detector. BACKGROUND

[0002] In an analog circuit, an automatic gain control system is a common circuit that automatically adjusts the gain size according to the amplitude of a signal. Stable output signal amplitude helps to improve the dynamic range and linearity of the circuit. The amplitude of the signal is usually realized by an amplitude detector. The amplitude detector includes a peak detector and a valley detector, which are used to monitor the positive peak value and the negative peak value of the signal, respectively. The signal faced by the amplitude detector in the automatic gain control system often changes randomly in frequency and amplitude, which is a great challenge to the amplitude detector. Due to the change in frequency, it is inevitable to produce ripple when detecting the amplitude, and the ripple is an adverse AC interference that will cause the positive and negative peak values detected by the amplitude detector to be not fixed DC voltages. The AC component in the ripple will cause the generated peak values to be unstable, thereby causing the linearity of the subsequent circuit to deteriorate sharply. In the related art, only one low-pass filter is usually used to reduce the ripple. Although the low-pass filter can effectively reduce the high-frequency ripple, it may also affect the high-frequency components of the signal, causing signal distortion. This effect is more pronounced when the signal frequency is close to the filter cutoff frequency. At the same time, the low-pass filter will slow down the response of the system to sudden signals, and may miss some rapidly changing information.

[0003] In summary, the technical problems existing in the related art need to be improved. SUMMARY

[0004] The main purpose of the embodiments of the present application is to provide a circuit for suppressing ripple of an amplitude detector and a method for suppressing ripple of an amplitude detector, which can eliminate the ripple by adjusting the charging and discharging speed of the capacitor to match the input signal frequency, and is not affected by the amplitude of the input signal.

[0005] ​To achieve the above object, one aspect of the embodiment of the present application provides a circuit for suppressing ripple of an amplitude detector, which comprises an amplitude detection loop and a ripple elimination loop, the amplitude detection loop comprising a peak detector, a valley detector and a subtractor, the ripple elimination loop comprising a first inverter, a second inverter, a time difference generator, an integrator and a half-peak detector, a first output terminal of the peak detector being connected with a first input terminal of the subtractor, a first output terminal of the valley detector being connected with a second input terminal of the subtractor, a second output terminal of the peak detector being connected with an input terminal of the first inverter, a second output terminal of the valley detector being connected with an input terminal of the second inverter, an output terminal of the second inverter and an output terminal of the first inverter both being connected with an input terminal of the time difference generator, an output terminal of the time difference generator being connected with an input terminal of the integrator, an output terminal of the integrator being connected with a first input terminal of the half-peak detector, and an output terminal of the subtractor being connected with a second input terminal of the half-peak detector, wherein:

[0006] The amplitude detection loop is configured to perform amplitude detection on a differential input signal to obtain a peak-to-peak value of the differential input signal.

[0007] The ripple elimination loop is configured to perform a capacitance charging and discharging rate adjustment process according to the peak-to-peak value of the differential input signal to eliminate ripple information of the differential input signal.

[0008] In some embodiments, further comprising:

[0009] The peak detector is configured to obtain positive peak value signal data of the differential input signal.

[0010] The valley detector is configured to obtain negative peak value signal data of the differential input signal.

[0011] The subtractor is configured to perform a subtraction calculation on the positive peak value signal data and the negative peak value signal data to obtain the peak-to-peak value of the differential input signal.

[0012] In some embodiments, further comprising:

[0013] The first inverter is configured to perform frequency signal node detection on the positive peak value signal data to obtain square wave information of the positive peak value signal data.

[0014] The second inverter is configured to perform frequency signal node detection on the negative peak value signal data to obtain square wave information of the negative peak value signal data.

[0015] The time difference generator is configured to compare the square wave information of the negative peak value signal data with the square wave information of the positive peak value signal data to obtain a pulse signal.

[0016] The integrator is configured to perform waveform conversion processing on the pulse signal to obtain a control voltage value.

[0017] The half-peak detector is configured to perform a capacitance charging and discharging rate adjustment processing according to the control voltage value to eliminate ripple information of the differential input signal.

[0018] In some embodiments, the peak detector and the first inverter include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first current meter, a second capacitor, a first inverter unit, wherein a source of the first transistor, a source of the second transistor, a source of the third transistor, a source of the fourth transistor, a source of the fifth transistor, a source of the sixth transistor, a source of the seventh transistor, and a source of the eighth transistor are connected, a gate of the first transistor, a gate of the second transistor, a drain of the second transistor, and a drain of the tenth transistor are connected, a drain of the first transistor, a drain of the ninth transistor, a drain of the third transistor, a gate of the third transistor, and a gate of the fourth transistor are connected, a source of the ninth transistor, a source of the tenth transistor, and a drain of the thirteenth transistor are connected, a source of the thirteenth transistor, a second end of the first current meter, a second end of the second capacitor, and a source of the fourteenth transistor are connected, a drain of the fourth transistor, a gate of the tenth transistor, a first end of the first current meter, a drain of the fifth transistor, a first end of the second capacitor, and a gate of the eleventh transistor are connected, a gate of the fifth transistor, a gate of the sixth transistor, a drain of the sixth transistor, a drain of the eighth transistor, an input end of the first inverter unit, and a drain of the twelfth transistor are connected, a gate of the seventh transistor, a drain of the seventh transistor, a gate of the eighth transistor, and a drain of the eleventh transistor are connected, a source of the eleventh transistor, a source of the twelfth transistor, and a drain of the fourteenth transistor are connected.

[0019] In some embodiments, the valley detector and the second inverter include a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a third capacitor, a second current meter, and a second inverter unit, wherein a source of the fifteenth transistor, a source of the sixteenth transistor, a first terminal of the third capacitor, and a first terminal of the second current meter are connected, a drain of the fifteenth transistor, a source of the seventeenth transistor and a source of the eighteenth transistor are connected, a drain of the seventeenth transistor, a drain of the twenty-first transistor, a drain of the twenty-third transistor, a gate of the twenty-third transistor and a gate of the twenty-fourth transistor are connected, a drain of the eighteenth transistor, a drain of the twenty-second transistor, a gate of the twenty-first transistor and a gate of the twenty-second transistor are connected, a gate of the eighteenth transistor, a second terminal of the third capacitor, a second terminal of the second current meter, a drain of the twenty-fourth transistor, a drain of the twenty-fifth transistor, and a gate of the nineteenth transistor are connected, a drain of the nineteenth transistor, a drain of the twenty-seventh transistor, a gate of the twenty-seventh transistor and a gate of the twenty-eighth transistor are connected, a drain of the twenty-sixth transistor, a source of the nineteenth transistor and a source of the twentieth transistor are connected, a drain of the twentieth transistor, a drain of the twenty-eighth transistor, a drain of the twenty-sixth transistor, a gate of the twenty-fifth transistor, a gate of the twenty-sixth transistor and an input terminal of the second inverter unit are connected, and a source of the twenty-first transistor, a source of the twenty-second transistor, a source of the twenty-third transistor, a source of the twenty-fourth transistor, a source of the twenty-fifth transistor, a source of the twenty-sixth transistor, a source of the twenty-seventh transistor, and a source of the twenty-eighth transistor are connected.

[0020] In some embodiments, the time difference generator comprises a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate, a ninth NAND gate, a tenth NAND gate, an eleventh NAND gate, and a first XOR gate, wherein a first input terminal of the first NAND gate is connected with an output terminal of the seventh NAND gate, an output terminal of the first NAND gate, a first input terminal of the third NAND gate, a first input terminal of the seventh NAND gate, a second input terminal of the eighth NAND gate, and a second input terminal of the ninth NAND gate are connected, a second input terminal of the second NAND gate is connected with an output terminal of the eleventh NAND gate, an output terminal of the second NAND gate, a second input terminal of the sixth NAND gate, a third input terminal of the eleventh NAND gate, a first input terminal of the tenth NAND gate, and a third input terminal of the ninth NAND gate are connected, a second input terminal of the third NAND gate is connected with an output terminal of the fourth NAND gate, an output terminal of the third NAND gate, a first input terminal of the fourth NAND gate, a third input terminal of the seventh NAND gate, a first input terminal of the eighth NAND gate, and a first input terminal of the ninth NAND gate are connected, a second input terminal of the fourth NAND gate, a first input terminal of the fifth NAND gate, a second input terminal of the seventh NAND gate, an output terminal of the ninth NAND gate, and a second input terminal of the eleventh NAND gate are connected, a second input terminal of the fifth NAND gate, an output terminal of the sixth NAND gate, a fourth input terminal of the ninth NAND gate, a second input terminal of the tenth NAND gate, and a first input terminal of the eleventh NAND gate are connected, an output terminal of the fifth NAND gate is connected with a first input terminal of the sixth NAND gate, an output terminal of the eighth NAND gate is connected with a first input terminal of the first XOR gate, and an output terminal of the tenth NAND gate is connected with a second input terminal of the first XOR gate.

[0021] In some embodiments, the integrator comprises a second resistor, a third resistor, a fourth capacitor, and an operational amplifier, a second terminal of the second resistor, a first terminal of the third resistor, a first terminal of the fourth capacitor, and a negative input terminal of the operational amplifier are connected, a second terminal of the third resistor and a second terminal of the fourth capacitor are connected with an output terminal of the operational amplifier.

[0022] In some embodiments, the half-peak detector comprises a twenty-ninth transistor, a thirtieth transistor, a thirty-first transistor, a thirty-second transistor, a thirty-third transistor, a thirty-fourth transistor, a thirty-fifth transistor, a thirty-sixth transistor and a fifth capacitor, wherein the source of the twenty-ninth transistor, the source of the thirtieth transistor and the source of the thirty-first transistor are connected, the gate of the twenty-ninth transistor, the gate of the thirtieth transistor, the drain of the thirtieth transistor and the drain of the thirty-fourth transistor are connected, the drain of the twenty-ninth transistor, the drain of the thirty-third transistor, the drain of the thirty-first transistor, the gate of the thirty-first transistor and the gate of the thirty-second transistor are connected, the drain of the thirty-second transistor, the gate of the thirty-fourth transistor, the first end of the fifth capacitor and the drain of the thirty-sixth transistor are connected, the source of the thirty-third transistor, the source of the thirty-fourth transistor and the drain of the thirty-fifth transistor are connected, and the source of the thirty-fifth transistor, the second end of the fifth capacitor and the source of the thirty-sixth transistor are connected.

[0023] To achieve the above object, another aspect of the embodiments of the present application provides a method for suppressing the ripple of an amplitude detector circuit, comprising the following steps:

[0024] obtaining a differential input signal and performing amplitude detection to obtain a peak-to-peak value of the differential input signal;

[0025] performing a capacitor charging and discharging rate adjustment process according to the peak-to-peak value of the differential input signal to eliminate the ripple information of the differential input signal.

[0026] In some embodiments, the capacitor charging and discharging rate adjustment process according to the peak-to-peak value of the differential input signal to eliminate the ripple information of the differential input signal comprises:

[0027] performing frequency signal node detection on the positive peak value signal data to obtain square wave information of the positive peak value signal data;

[0028] performing frequency signal node detection on the negative peak value signal data to obtain square wave information of the negative peak value signal data;

[0029] comparing the square wave information of the negative peak value signal data with the square wave information of the positive peak value signal data to obtain a pulse signal;

[0030] performing waveform conversion processing on the pulse signal to obtain a control voltage value;

[0031] performing a capacitor charging and discharging rate adjustment process according to the control voltage value to eliminate the ripple information of the differential input signal.

[0032] The embodiments of the present application at least have the following beneficial effects: the present application provides a circuit for suppressing ripple of an amplitude detector and a suppression method thereof, the scheme monitors the output with frequency information in the amplitude detector by using an inverter, compares the peak detector and the valley detector by a time difference generator to obtain a pulse signal, inputs the pulse signal with frequency information to an integrator after passing through a capacitor, thereby obtaining a control voltage value related to the input frequency, and connects the control voltage value to a current source in the half-peak detector to control and regulate the charging and discharging speed of the capacitor in the parallel branch, so that the charging and discharging speed of the capacitor in the half-peak detector matches the input signal frequency to eliminate the ripple, can match the frequency of the input signal and is not affected by the amplitude of the input signal, and greatly suppresses the ripple generated due to the mismatch between the charging and discharging speed and the input signal frequency. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a structural schematic diagram of a circuit for suppressing ripple of an amplitude detector provided by the embodiments of the present application;

[0034] Figure 2 is a step flowchart of a suppression method of a circuit for suppressing ripple of an amplitude detector provided by the embodiments of the present application;

[0035] Figure 3 is a schematic diagram of the basic principle of the existing peak detector;

[0036] Figure 4 is a structural schematic diagram of a peak detector and a first inverter provided by the embodiments of the present application;

[0037] Figure 5 is a structural schematic diagram of a valley detector and a second inverter provided by the embodiments of the present application;

[0038] Figure 6 is a logic principle schematic diagram of a time difference generator provided by the embodiments of the present application;

[0039] Figure 7 is a waveform schematic diagram of a time difference generator provided by the embodiments of the present application;

[0040] Figure 8 is a structural schematic diagram of an integrator provided by the embodiments of the present application;

[0041] Figure 9 is a structural schematic diagram of a half-peak detector provided by the embodiments of the present application;

[0042] Figure 10 is a waveform schematic diagram of a differential input signal provided by the embodiments of the present application;

[0043] Figure 11is a waveform diagram of a peak-to-peak value of a differential input signal provided by an embodiment of the present application.

[0044] Figure 12 is a waveform diagram of an output signal of a half-peak detector provided by an embodiment of the present application.

[0045] BRIEF DESCRIPTION OF DRAWINGS: 1, amplitude detection loop; 101, peak detector; 102, valley detector; 103, subtractor; 2, ripple elimination loop; 201, first inverter; 202, second inverter; 203, time difference generator; 204, integrator; 205, half-peak detector. DETAILED DESCRIPTION

[0046] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application. When the following description refers to the accompanying drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementation described in the following exemplary embodiments does not represent all the implementations consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0047] It can be understood that the terms "first", "second", and the like used herein can be used to describe various concepts in this document, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "when" or "in response to determining".

[0048] The terms "at least one", "multiple", "each", "any" and the like used in the present application include one, two or more than two, multiple includes two or more than two, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as understood by those skilled in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0050] Before providing a detailed description of the embodiments of this application, some terms used in the embodiments of this application will be explained first. The amplitude of a signal is typically determined by an amplitude detector. An amplitude detector includes a peak detector and a valley detector, which are used to monitor the positive and negative peak values ​​of the signal, respectively. The basic principle of the simplest peak detector is as follows: Figure 3 As shown, the peak detector consists of a diode switch. Holding capacitor and discharge resistor Composition. A diode switch controls charging and discharging, essentially functioning as a half-wave rectifier. Based on the principle of forward conduction and reverse cutoff, when the input signal exceeds the voltage drop across the diode plus the peak voltage, the diode conducts in the forward direction. Forward current flows from the input terminal to the output terminal through the capacitor. As it charges, the peak output voltage increases.

[0051] Conversely, when the input signal is less than the voltage drop across the diode plus the peak voltage, the diode is reverse-biased and cut off. No reverse current flows from the output to the input, and the capacitor maintains the current peak voltage.

[0052] The left side is the excitation terminal, and the right side is the passive terminal. The peak voltage can never exceed the input signal. Therefore, the output voltage is at most the maximum value of the input signal, meaning that the peak value of the input signal is always being detected.

[0053] The circuit difference between a valley detector and a peak detector is the diode. The directions are opposite, and the control conditions for the valley detector and the peak detector are completely opposite. The principle is similar to the peak detection circuit described above. Therefore, the voltage at the output of the valley detector is at most the minimum value of the input signal, and it always detects the valley value of the input signal.

[0054] Voltage drop is a phenomenon caused by the slow discharge of capacitors through leakage and downstream loads, flowing through the diode. The current will affect the capacitor The expression for charging is as follows:

[0055]

[0056] The discharge of a charge through a capacitor is expressed as follows:

[0057]

[0058] capacitance Charge on It is constantly changing, if the capacitance If the voltage cannot change at the corresponding rate, then the voltage across the capacitor will... The peak output voltage will change. It cannot remain constant, but the capacitance Once determined, it cannot be changed. Due to the mismatch in charging and discharging speeds, ripple will inevitably be generated in the amplitude detection circuit.

[0059] The causes of ripple are analyzed in detail below.

[0060] When an input signal is received At that time, the output voltage of the peak detector will immediately rise to However, when no input signal is received... or At this time, the charge on the capacitor will leak due to parasitic effects, leading to... It decreases at a fixed slope. When the next input peak signal arrives, the capacitor... It will be recharged to its peak charge, at which point... This will result in a periodic slow decline followed by a rise, exhibiting a sawtooth shape, thus forming circuit ripples.

[0061] Circuit ripple and slew rate It is a compromise. For large-signal parameters, defined as the ratio of discharge current to charging capacitance. The ratio, expressed as:

[0062]

[0063] The capacitor can be adjusted capacitance and discharge current Adjust the size . The larger the value, the faster the speed, and the better it can track signals with drastic amplitude changes, but the drawback is that it also produces larger ripples.

[0064] It is worth noting that, regardless of Ripple will be generated whether the drop is sudden or gradual from the highest point. The traditional method of discharge is through a load resistor. Discharge, discharge rate from time constant Decide. The smaller the value, the faster the discharge speed. follow The changes are more frequent. But within the same time period... The faster the rise / fall, the narrower the ripple spacing and the denser the ripples.

[0065] Clearly, ripple is a detrimental form of AC interference, causing the peak-to-peak values ​​detected by the amplitude detector to be non-fixed DC voltages. The AC component in the ripple results in peak values ​​that are not constant. Unstable, thus causing the linearity of the next stage circuit to deteriorate sharply. Therefore, in order to improve the linearity of the circuit, the ripple must be eliminated.

[0066] In related technologies, some of the deficiencies exist, which usually only use a low-pass filter to reduce the ripple, although the low-pass filter can effectively reduce the high-frequency ripple, but it may also affect the high-frequency components of the signal, leading to signal distortion. Especially when the signal frequency is close to the filter cutoff frequency, this effect is more obvious. At the same time, the low-pass filter will make the system response to the sudden signal slow, and may miss some rapidly changing information.

[0067] Therefore, in the embodiments of the present application, a circuit for suppressing the ripple of the amplitude detector is provided, which includes a peak detector module, a valley detector module, a subtractor, an inverter, a time difference generator, an integrator and a half-peak detector. The inverter is used to monitor the signal node related to the input frequency in the peak detector and the valley detector, and the obtained square wave information is sent to the time difference generator to generate a frequency-related pulse waveform. The duty cycle of the pulse waveform is positively related to the input frequency. The pulse waveform is converted into a direct current voltage by the capacitor and the integrator, which is used as a control signal to adjust the charging and discharging speed of the current source in the half-peak detector. That is, the half-peak detector is controlled by the input signal frequency, which can automatically adjust the charging and discharging speed to follow the signal frequency and will not be disturbed by the signal amplitude.

[0068] When the frequency of the input signal is very low, the voltage on the capacitor cannot be maintained for a long time due to parasitic effects, so the control voltage will decrease with the signal frequency to slow down the discharging speed of the capacitor in the half-peak detector. Similarly, as the frequency of the input signal increases, the control voltage gradually increases to speed up the discharging of the capacitor to follow the change of the peak signal. Therefore, the charging and discharging speed of the capacitor in the detector matches the input signal frequency, thereby effectively avoiding the generation of ripple.

[0069] Reference Figure 1 , Figure 1 The structure diagram of the circuit for suppressing the ripple of the amplitude detector provided by the embodiments of the present application is shown in FIG. 1. Figure 1The circuit comprises an amplitude detection loop 1 and a ripple elimination loop 2, the amplitude detection loop comprises a peak detector 101, a valley detector 102 and a subtractor 103, the ripple elimination loop comprises a first inverter 201, a second inverter 202, a time difference generator 203, an integrator 204 and a half-peak detector 205, the first output end of the peak detector is connected with the first input end of the subtractor, the first output end of the valley detector is connected with the second input end of the subtractor, the second output end of the peak detector is connected with the input end of the first inverter, the second output end of the valley detector is connected with the input end of the second inverter, the output end of the second inverter and the output end of the first inverter are both connected with the input end of the time difference generator, the output end of the time difference generator is connected with the input end of the integrator, the output end of the integrator is connected with the first input end of the half-peak detector, and the output end of the subtractor is connected with the second input end of the half-peak detector, wherein:

[0070] The amplitude detection loop is used for amplitude detection on the differential input signal to obtain a peak-to-peak value of the differential input signal.

[0071] Specifically, the peak detector is used for obtaining positive peak value signal data of the differential input signal, the valley detector is used for obtaining negative peak value signal data of the differential input signal, and the subtractor is used for subtracting calculation on the positive peak value signal data and the negative peak value signal data to obtain the peak-to-peak value of the differential input signal.

[0072] The ripple elimination loop is used for capacitor charging and discharging rate adjustment processing according to the peak-to-peak value of the differential input signal to eliminate ripple information of the differential input signal.

[0073] Specifically, the first inverter is used for frequency signal node detection on the positive peak value signal data to obtain square wave information of the positive peak value signal data, the second inverter is used for frequency signal node detection on the negative peak value signal data to obtain square wave information of the negative peak value signal data, the time difference generator is used for comparison on the square wave information of the negative peak value signal data and the square wave information of the positive peak value signal data to obtain a pulse signal, the integrator is used for waveform conversion processing on the pulse signal to obtain a control voltage value, and the half-peak detector is used for capacitor charging and discharging rate adjustment processing according to the control voltage value to eliminate the ripple information of the differential input signal.

[0074] Further, it needs to be explained that, as shown in Figure 4 , the peak detector and the first inverter comprise a first transistor , a second transistor , a third transistor , a fourth transistor , a fifth transistor , a sixth transistor , a seventh transistor , an eighth transistor • ninth transistor • tenth transistor • eleventh transistor • twelfth transistor • thirteenth transistor • fourteenth transistor • first current meter • second capacitor • first inverter unit wherein the source of the first transistor, the source of the second transistor, the source of the third transistor, the source of the fourth transistor, the source of the fifth transistor, the source of the sixth transistor, the source of the seventh transistor, and the source of the eighth transistor are connected, the gate of the first transistor, the gate of the second transistor, and the drain of the second transistor are connected with the drain of the tenth transistor, the drain of the first transistor, the drain of the ninth transistor, the drain of the third transistor, and the gate of the fourth transistor are connected, the source of the ninth transistor, the source of the tenth transistor, and the drain of the thirteenth transistor are connected, the source of the thirteenth transistor, the second terminal of the first current meter, the second terminal of the second capacitor, and the source of the fourteenth transistor are connected, the drain of the fourth transistor, the gate of the tenth transistor, the first terminal of the first current meter, the drain of the fifth transistor, the first terminal of the second capacitor, and the gate of the eleventh transistor are connected, the gate of the fifth transistor, the gate of the sixth transistor, the drain of the sixth transistor, the drain of the eighth transistor, the input terminal of the first inverter unit, and the drain of the twelfth transistor are connected, the gate of the seventh transistor, the drain of the seventh transistor, the gate of the eighth transistor, and the drain of the eleventh transistor are connected, the source of the eleventh transistor, the source of the twelfth transistor, and the drain of the fourteenth transistor are connected.

[0075] Further, it is to be noted that, as shown in Figure 5 , the valley detector and the second inverter include a fifteenth transistor • sixteenth transistor • seventeenth transistor • eighteenth transistor • nineteenth transistor • twentieth transistor • twenty-first transistor • twenty-second transistor • twenty-third transistor • twenty-fourth transistor • twenty-fifth transistor • twenty-sixth transistor • twenty-seventh transistor • twenty-eighth transistor • third capacitor • second current meter and a second inverter unit wherein the source of the fifteenth transistor, the source of the sixteenth transistor, the first terminal of the third capacitor and the first terminal of the second current meter are connected, the drain of the fifteenth transistor is connected with the source of the seventeenth transistor and the source of the eighteenth transistor, the drain of the seventeenth transistor is connected with the drain of the twenty-first transistor, the drain of the twenty-third transistor, the gate of the twenty-third transistor and the gate of the twenty-fourth transistor, the drain of the eighteenth transistor is connected with the drain of the twenty-second transistor, the gate of the twenty-first transistor and the gate of the twenty-second transistor, the gate of the eighteenth transistor is connected with the second terminal of the third capacitor, the second terminal of the second current meter, the drain of the twenty-fourth transistor, the drain of the twenty-fifth transistor and the gate of the nineteenth transistor, the drain of the nineteenth transistor is connected with the drain of the twenty-seventh transistor, the gate of the twenty-seventh transistor and the gate of the twenty-eighth transistor, the drain of the twenty-sixth transistor is connected with the source of the nineteenth transistor and the source of the twentieth transistor, the drain of the twentieth transistor is connected with the drain of the twenty-eighth transistor, the drain of the twenty-sixth transistor, the gate of the twenty-fifth transistor, the gate of the twenty-sixth transistor and the input terminal of the second inverter unit, the source of the twenty-first transistor is connected with the source of the twenty-second transistor, the source of the twenty-third transistor, the source of the twenty-fourth transistor, the source of the twenty-fifth transistor, the source of the twenty-sixth transistor, the source of the twenty-seventh transistor and the source of the twenty-eighth transistor.

[0076] Further, it needs to be explained that, as shown in Figure 6 the time difference generator comprises a first NAND gate , a second NAND gate , a third NAND gate , a fourth NAND gate , a fifth NAND gate , a sixth NAND gate , a seventh NAND gate , an eighth NAND gate , a ninth NAND gate , a tenth NAND gate , an eleventh NAND gate and a first XOR gate The first input terminal of the first NAND gate is connected with the output terminal of the seventh NAND gate, the output terminal of the first NAND gate, the first input terminal of the third NAND gate, the first input terminal of the seventh NAND gate, the second input terminal of the eighth NAND gate and the second input terminal of the ninth NAND gate are connected, the second input terminal of the second NAND gate is connected with the output terminal of the eleventh NAND gate, the output terminal of the second NAND gate, the second input terminal of the sixth NAND gate, the third input terminal of the eleventh NAND gate, the first input terminal of the tenth NAND gate and the third input terminal of the ninth NAND gate are connected, the second input terminal of the third NAND gate is connected with the output terminal of the fourth NAND gate, the output terminal of the third NAND gate, the first input terminal of the fourth NAND gate, the third input terminal of the seventh NAND gate, the first input terminal of the eighth NAND gate and the first input terminal of the ninth NAND gate are connected, the second input terminal of the fourth NAND gate, the first input terminal of the fifth NAND gate, the second input terminal of the seventh NAND gate, the output terminal of the ninth NAND gate and the second input terminal of the eleventh NAND gate are connected, the second input terminal of the fifth NAND gate, the output terminal of the sixth NAND gate, the fourth input terminal of the ninth NAND gate, the second input terminal of the tenth NAND gate and the first input terminal of the eleventh NAND gate are connected, the output terminal of the fifth NAND gate is connected with the first input terminal of the sixth NAND gate, the output terminal of the eighth NAND gate is connected with the first input terminal of the first XOR gate, and the output terminal of the tenth NAND gate is connected with the second input terminal of the first XOR gate.

[0077] Further, it needs to be explained that, as shown in Figure 8 , the integrator comprises a second resistor , a third resistor , a fourth capacitor and an operational amplifier , the second terminal of the second resistor, the first terminal of the third resistor and the first terminal of the fourth capacitor are connected with the negative input terminal of the operational amplifier, the second terminal of the third resistor and the second terminal of the fourth capacitor are connected with the output terminal of the operational amplifier.

[0078] Further, it needs to be explained that, as shown in Figure 9 , the half-peak detector comprises a twenty-ninth transistor , a thirtieth transistor , a thirty-first transistor , a thirty-second transistor , a thirty-third transistor , a thirty-fourth transistor , a thirty-fifth transistor , a thirty-sixth transistor and a fifth capacitor The source of the twenty-ninth transistor, the source of the thirtieth transistor, the source of the thirty-first transistor and the source of the thirty-second transistor are connected, the gate of the twenty-ninth transistor, the gate of the thirtieth transistor, the drain of the thirtieth transistor and the drain of the thirty-fourth transistor are connected, the drain of the twenty-ninth transistor, the drain of the thirty-third transistor, the drain of the thirty-first transistor, the gate of the thirty-first transistor and the gate of the thirty-second transistor are connected, the drain of the thirty-second transistor, the gate of the thirty-fourth transistor, the first end of the fifth capacitor and the drain of the thirty-sixth transistor are connected, the source of the thirty-third transistor, the source of the thirty-fourth transistor and the drain of the thirty-fifth transistor are connected, the source of the thirty-fifth transistor, the second end of the fifth capacitor and the source of the thirty-sixth transistor are connected.

[0079] Referring to Figure 2 The application also provides a suppression method of the circuit for suppressing amplitude detector ripples, which can realize the circuit for suppressing amplitude detector ripples.

[0080] S100, acquiring a differential input signal and performing amplitude detection to obtain a peak-to-peak value of the differential input signal;

[0081] Firstly, it should be noted that the automatic gain control structure is essentially a subsystem, and the function of the automatic gain control is realized by the cooperation of multiple sub-modules. The functional modules can be adjusted according to actual needs.

[0082] Generally, the detected amplitude is subjected to a series of mathematical operations to obtain a control voltage or a control current , which contains output amplitude information, meaning that the gain control loop adjusts the gain according to the output amplitude. If the output is too large, the gain is reduced, and if the output is too small, the gain is increased. Finally, the output signal of the system is stabilized at a fixed amplitude.

[0083] In some specific embodiments, the amplitude detection loop part includes a peak detector, a valley detector and a subtractor. The peak detector is used to obtain the positive peak value data of the input signal, the valley detector is used to obtain the negative peak value data of the input signal, and the subtractor is used to obtain the peak-to-peak value data of the input signal. The output of the peak detector is the positive peak value of the input signal, the output of the valley detector is the negative peak value of the input signal, and the output of the subtractor obtained by subtracting the positive peak value from the negative peak value is the differential input signal and The amplitude of the output signal is detected by the peak detector and the valley detector. The peak detector is a differential input single-ended output structure.

[0084] The peak detector and the valley detector are used to detect the peak value of the output signal as the amplitude detector. The peak detector is a differential input single-ended output structure.

[0085] The first transistor , the second transistor , the ninth transistor , the tenth transistor , the thirteenth transistor , and the seventh transistor , the eighth transistor , the eleventh transistor , the twelfth transistor , and the fourteenth transistor are feedback op-amps, the third transistor , the fourth transistor , and the fifth transistor , the sixth transistor are current mirrors, are holding capacitors, are discharge current sources. The inverter is connected to the output of the feedback op-amp. The peak detector is mirrored on both sides, the left side is used to detect the peak value of the in-phase output signal, and the right side is used to detect the peak value of the reverse output signal. The output outputs the peak voltage, and both sides charge the capacitor every half cycle.

[0086] The basic principle is as follows: taking the right side as an example, the seventh transistor , the eighth transistor , the eleventh transistor , the twelfth transistor , and the fourteenth transistor are classic 5-tube op-amps, used to compare the difference between the input signal and the peak voltage of the current output. The output of the feedback op-amp is at the drain of the twelfth transistor and the eighth transistor , and the current flows from the feedback op-amp to the fifth transistor and the sixth transistor in the current mirror. At the same time, this output serves as the input of the inverter to monitor the frequency value of the input signal . When the input signal Rising, inverter output Conversely, falling.

[0087] For peak detection: when current mirror is on, equivalent to diode forward conducting, current is copied to the fifth transistor branch, charging the capacitor. Feedback op-amp behaves as a buffer stage, isolating input and speeding up the output. When current mirror is off, equivalent to diode reverse conducting, the fifth transistor branch has no current, the capacitor holds the peak voltage.

[0088] Specifically, when input signal rises, the gate voltage of the twelfth transistor is higher than the peak voltage output by the output terminal , the small signal current of the twelfth transistor will increase. At the same time, the falling of the inverter input voltage leads to rising. Due to the clamping effect of the seventh transistor and the eighth transistor on the branch current, the current of the seventh transistor remains unchanged. According to the KCL equation of the drain junction of the seventh transistor and the twelfth transistor , the increased small signal current can only be extracted from the sixth transistor , and the increased current of the sixth transistor is copied to the output branch by the fifth transistor and the sixth transistor in the current mirror. This current will charge the capacitor , and the output voltage rises.

[0089] Conversely, when the input signal falls, the gate voltage of the twelfth transistor is lower than the peak voltage output by the output terminal Vo+, the small signal current of the twelfth transistor will decrease. At the same time, the rising of the inverter input voltage leads to falling. The gate voltage of the eleventh transistor rises, the current of the eleventh transistor increases, and the current copied to the input branch by the seventh transistor and the eighth transistor in the current mirror increases, so that the drain junction of the eighth transistor and the twelfth transistor no longer needs to extract current from the sixth transistor , and the sixth transistor The eighth transistor will only provide current and not consume current , the twelfth transistor The drain node potential of the fifth transistor will be pulled up to VDD The sixth transistor is off The circuit enters a brief equilibrium state, and the output is the peak value of the current signal.

[0090] Similarly, the valley detector is always detecting the minimum value of the signal, and the function of the valley detector is opposite to that of the peak detector, and the circuit structure is upside down. The inverter connected with the valley detector is used to detect the frequency of the input signal When the input signal Rises, the inverter output Follows. The principle of detecting the negative peak value by the valley detector is the same as that of detecting the positive peak value by the peak detector, which will not be described here.

[0091] S200, according to the peak-to-peak value of the differential input signal, the rate of the capacitor charging and discharging is adjusted, and the ripple information of the differential input signal is eliminated;

[0092] It should be noted that in some embodiments, step S200 can include steps S210 to S250.

[0093] S210, frequency signal node detection is performed on the positive peak value signal data to obtain square wave information of the positive peak value signal data;

[0094] S220, frequency signal node detection is performed on the negative peak value signal data to obtain square wave information of the negative peak value signal data;

[0095] In this embodiment, the output ends of the two inverters obtain voltage values And Related to the frequency of the input signal. Both are pulse signals, and the difference between their rising edges represents the period of the input signal.

[0096] S230, comparing the square wave information of the negative peak value signal data with the square wave information of the positive peak value signal data to obtain a pulse signal;

[0097] In this embodiment, the time difference generator is used to calculate the rising edge time difference between And Two signals. The time difference generator is realized by using a classic three-state phase frequency detector based on NOR gate and XOR gate.

[0098] The time difference generator circuit detects the time difference between the positive edges of its two inputs, and generates an output digital pulse with a width equal to the input time difference.

[0099] The analysis of the input of point :

[0100] Node ① is the input of SR latch, node ② is the output of SR latch, the state of node ② is opposite to the input node ①, the input of nodes ① and ② generates the output node X, due to the characteristic of NAND gate, when the input is all high, the output is low.

[0101] Suppose node ⑦ is high, when the input of point is low, the output node ① is low, one PMOS is turned on, which causes node ② to be high, the output node X is high, the output node ⑨ is high, the output node ⑤ is low, the output node ⑦ is high, the supposition is true, and the circuit keeps stable.

[0102] When the input of point suddenly jumps to high, the node ① becomes high, the node ② maintains high due to the low node ⑤, the output node X is low, the four-input NAND gate input is all high, which causes the node ⑨ to be low, leading to the output of node ⑤ to be high, the nodes ① and ⑤ are both high, which causes the node ② to jump from high to low, the falling edge of node ② causes the rising edge of node X, so that the output node X jumps from low to high in a very short time. It can be seen that the falling edge of the output node X detects the rising edge of the input end .

[0103] The analysis of the input of point :

[0104] Similarly, suppose node ⑧ is high, when the input of point is low, the output node ③ is low, which causes the node ④ to be high, the output node Y is high, the output node ⑨ is high, the output node ⑥ is low, the output node ⑧ is high, the supposition is true, and the circuit keeps stable. Similarly, the falling edge of the output node Y detects the rising edge of the input end .

[0105] When the nodes ①, ②, ③, ④ are all high, the node ⑨ outputs low, when any low level appears in the nodes ① to ④, the node ⑨ outputs high, which causes the nodes ⑤ and ⑥ to be low, which controls the nodes ② and ④ to output low, which causes the nodes X and Y to rise from low level to high. It can be seen that the rising edges of the output nodes X and Y are controlled by the rising edge of the node ⑨.

[0106] After the nodes X and Y pass through an XOR gate circuit, the output is obtained, which detects the time difference of the falling edges of the output nodes X and Y, that is, the time difference of the rising edges of the input ends and . The waveform of the time difference generator in the application is shown in Figure 7 .

[0107] S240. Perform waveform conversion processing on the pulse signal to obtain the control voltage value;

[0108] In this embodiment, the pulse waveform carries frequency information For a fixed capacitor By performing charging and discharging, the pulse signal can be converted into a right-angle wave signal, and the voltage of this right-angle wave is high. We obtain it from the following formula:

[0109]

[0110] in, It is for fixed capacitors The current source for charging, Pulse waveform The high-level time. This shows that the higher the frequency of the input signal, the higher the voltage. and The faster the change, the more pronounced the waveform. The smaller the duty cycle, the lower the voltage value of the right-angle wave. That is, the smaller it will be. In other words, the voltage value The value represents the frequency of the input signal.

[0111] This invention inputs the right-angle wave to the integrator and the reference voltage. The controlled DC voltage is obtained after comparison. .

[0112] In this invention, the operational amplifier A of the integrator can be implemented by a general-purpose five-transistor amplifier, with its inverting input connected to the right-angle wave voltage of the preceding stage. The non-inverting input is connected to the reference voltage. Output terminal Connect the voltage control terminal of the subsequent half-peak detector. Add a resistor and capacitor between the input and output terminals of the operational amplifier to form a closed-loop feedback, thus realizing the function of the integrator. The integrator first converts the input... With the preset reference voltage After comparison, the difference between the two inputs is integrated. Based on virtual short and virtual open circuits, current flows through the integrating capacitor. The current is:

[0113]

[0114] The output voltage of the integrator can be obtained as follows:

[0115]

[0116] And because of the input of the integrator and reference voltage They don't change with time. The changing DC voltage can be simplified to:

[0117]

[0118] Among them, in the capacitor of the integrator A feedback resistor is connected in parallel. This implements a low-pass pathper to filter out the high-frequency components of right-angle waves. Therefore, the integrator's output voltage... It is a DC voltage with frequency information, which can be used as a control voltage to automatically adjust the charging and discharging rate of the capacitor in the subsequent half-peak detector.

[0119] S250: Adjust the capacitor charging and discharging rate according to the control voltage value to eliminate the ripple information of the differential input signal.

[0120] In some specific embodiments, the half-peak detector is half of the circuit of the peak detector, and the circuit structure is simple and easy to implement. The twenty-ninth transistor is mentioned. 30th transistor 33rd transistor 34th transistor The 35th transistor This is a classic 5-transistor op-amp used to compare the output signal of a subtractor. With the current peak voltage at the output terminal The difference. Thirty-first transistor. The 35th transistor For current mirror, To maintain the capacitance, the thirty-sixth transistor As a discharge current source, the DC voltage carries the input signal frequency information. As the control voltage for its gate.

[0121] When the input voltage During the rise, the input tube The small-signal current increases, and the increased small-signal current flows from... Extraction, The increased current is reflected by the current mirror. , Copying to the output branch, this increased current will affect the capacitor. Charging is performed because of the discharge current source. It operates in the saturation region and discharges with a stable current, so the output voltage is... It will rise accordingly. Thus, the output of the half-peak detector achieves peak-to-peak tracking of the subtractor's amplitude.

[0122] When the frequency of the input signal decreases, the pulse waveform An increase in duty cycle leads to an increase in the output voltage of the integrator. The smaller size makes the originally stable discharge current source The gate-source voltage decreases while the on-current decreases, which can effectively reduce the holding capacitance. The discharge rate. This is achieved by finely adjusting the discharge current source. The transistor size is adjusted to match the reduced frequency of the input signal, which effectively eliminates the ripple generated during the operation of the amplitude detector.

[0123] In summary, the embodiments of the present invention can effectively eliminate ripple regardless of the input signal frequency. The principle is to use the frequency information extracted from the amplitude detector to generate a control voltage to adjust the charging and discharging speed of the capacitor in the peak detector. Specifically, an inverter monitors the frequency-information output of the amplitude detector. A pulse signal is obtained by comparing the peak and valley detectors using a time difference generator. This pulse signal, carrying frequency information, is passed through a capacitor and input to an integrator, thereby obtaining a control voltage value related to the input frequency. This voltage value controls the current source connected to the half-peak detector, regulating the charging and discharging speed of the capacitor in the parallel branch. This ensures that the charging and discharging speed of the capacitor in the half-peak detector matches the input signal frequency, thus eliminating ripple.

[0124] This invention provides a method for automatically eliminating ripple by following the frequency of an input signal, effectively solving the problem of signal distortion caused by frequency changes. The half-peak detector circuit has a simple structure and an automatically adjustable charging / discharging current source, which can match the frequency of the input signal and is unaffected by the amplitude of the input signal.

[0125] This invention utilizes the frequency information in the detector's output, thus enabling frequency extraction without the need for complex detection circuits. Accurate amplitude readings in automatic gain control systems can be achieved by adjusting the amplitude of the half-peak detector based on the input signal frequency.

[0126] Compared with existing technologies, this invention can greatly suppress ripple caused by the mismatch between charging and discharging speed and input signal frequency, and will not limit system bandwidth or affect overall performance.

[0127] Compared to the fixed charging and discharging rates of the previous peak and amplitude detectors, this half-peak detector features an automatically adjustable charging and discharging current source. While effectively detecting peak values, it automatically adjusts the charging and discharging current based on the frequency of the input signal. This invention, through precise design of the discharge current source dimensions, can almost perfectly match the input frequency to eliminate the ripple of the amplitude detector.

[0128] Figure 10 The effects of the present invention are demonstrated. Figure 10 Input signal and is a set of differential signals, the amplitude is 0.32V and the frequency is 10Hz within 0.05-0.25s; the amplitude is 0.65V and the frequency is 20Hz within 0.25-0.35s; the amplitude is 1V and the frequency is 40Hz within 0.35-0.55s; then, the amplitude gradually decreases at the frequency of 80Hz.

[0129] Figure 11 The output results without using the application are shown, it can be seen that the output voltage Although the amplitude can be detected, there is serious ripple interference. Especially, obvious ripples are caused by the mismatch of the discharging speed when the frequency is relatively low, and the superposition of these AC components can cause the gain of the automatic gain control system to be unstable and the linearity to be deteriorated.

[0130] Figure 12 The output results after using the application are shown, thanks to the control of the charging and discharging currents, the output ripples at different frequencies are greatly eliminated, and the amplitude of the input differential signal can be clearly distinguished. The method of the application effectively eliminates the ripples in the amplitude detector.

[0131] It can be understood that the contents in the above method embodiments are all applicable to the system embodiments, the system embodiments specifically realize the same functions as the above method embodiments, and achieve the same beneficial effects as the above method embodiments.

[0132] The preferred embodiments of the application are described above with reference to the accompanying drawings, and the scope of the right of the application embodiments is not limited by this. Any modification, equivalent replacement and improvement made by the person skilled in the art without departing from the scope and essence of the application embodiments should be within the scope of the right of the application embodiments.

Claims

1. A circuit for suppressing ripple in an amplitude detector, characterized in that, The circuit includes an amplitude detection loop and a ripple elimination loop. The amplitude detection loop includes a peak detector, a valley detector, and a subtractor. The ripple elimination loop includes a first inverter, a second inverter, a time difference generator, an integrator, and a half-peak detector. The first output of the peak detector is connected to the first input of the subtractor. The first output of the valley detector is connected to the second input of the subtractor. The second output of the peak detector is connected to the input of the first inverter. The second output of the valley detector is connected to the input of the second inverter. The outputs of the second inverter and the first inverter are both connected to the input of the time difference generator. The output of the time difference generator is connected to the input of the integrator. The output of the integrator is connected to the first input of the half-peak detector. The output of the subtractor is connected to the second input of the half-peak detector. The half-peak detector includes a 29th transistor, a 30th transistor, a 31st transistor, a 32nd transistor, a 33rd transistor, a 34th transistor, a 35th transistor, a 36th transistor, and a fifth capacitor. The sources of the 29th transistor, the 30th transistor, the 31st transistor, and the 32nd transistor are connected. The gates of the 29th transistor, the 30th transistor, and the 30th transistor are connected to the drain of the 34th transistor. The drains of the 29th transistor, the 33rd transistor, and the 31st transistor are connected. The drain of the body transistor, the gate of the thirty-first transistor, and the gate of the thirty-second transistor are connected; the drain of the thirty-second transistor, the gate of the thirty-fourth transistor, and the first terminal of the fifth capacitor are connected to the drain of the thirty-sixth transistor; the source of the thirty-third transistor, the source of the thirty-fourth transistor, and the drain of the thirty-fifth transistor are connected; the source of the thirty-fifth transistor, the second terminal of the fifth capacitor, and the source of the thirty-sixth transistor are connected; the gate of the thirty-third transistor is connected to the output terminal of the subtractor; the gate of the thirty-sixth transistor is connected to the output terminal of the integrator; wherein: The peak detector is used to acquire the positive peak signal data of the differential input signal; The valley detector is used to acquire the negative peak signal data of the differential input signal; The amplitude detection loop is used to detect the amplitude of the differential input signal to obtain the peak-to-peak value of the differential input signal; The ripple elimination loop is used to adjust the charging and discharging rate of the fifth capacitor based on the peak-to-peak value of the differential input signal, thereby eliminating the ripple information of the differential input signal.

2. The circuit according to claim 1, characterized in that, Also includes: The subtractor is used to subtract the positive peak signal data from the negative peak signal data to obtain the peak-to-peak value of the differential input signal.

3. The circuit according to claim 1, characterized in that, Also includes: The first inverter is used to perform frequency signal node detection on the positive peak signal data to obtain the square wave information of the positive peak signal data; The second inverter is used to perform frequency signal node detection on the negative peak signal data to obtain the square wave information of the negative peak signal data; The time difference generator is used to compare the square wave information of the negative peak signal data with the square wave information of the positive peak signal data to obtain a pulse signal; The integrator is used to perform waveform conversion processing on the pulse signal to obtain a control voltage value; The half-peak detector is used to adjust the capacitor charging and discharging rate according to the control voltage value, thereby eliminating the ripple information of the differential input signal.

4. The circuit according to claim 1, characterized in that, The peak detector and the first inverter include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first galvanometer, a second capacitor, and a first inverter unit. The sources of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are connected. The gates of the first transistor, the second transistor, and the second transistor are connected to the drain of the tenth transistor. The drains of the first transistor, the ninth transistor, the third transistor, and the third transistor are connected to the gate of the fourth transistor. The sources of the ninth transistor, the tenth transistor, and the thirteenth transistor are connected. The source of the thirteenth transistor, the second terminal of the first galvanometer, the second terminal of the second capacitor, and the source of the fourteenth transistor are connected. The drain of the fourth transistor, the gate of the tenth transistor, the first terminal of the first galvanometer, the drain of the fifth transistor, the first terminal of the second capacitor, and the gate of the eleventh transistor are connected. The gate of the fifth transistor, the gate of the sixth transistor, the drain of the sixth transistor, the drain of the eighth transistor, the input terminal of the first inverter unit, and the drain of the twelfth transistor are connected. The gate of the seventh transistor, the drain of the seventh transistor, the gate of the eighth transistor, and the drain of the eleventh transistor are connected. The sources of the eleventh transistor and the twelfth transistor are connected to the drain of the fourteenth transistor.

5. The circuit according to claim 1, characterized in that, The valley detector and the second inverter include a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a third capacitor, a second galvanometer, and a second inverter unit. The source of the fifteenth transistor, the source of the sixteenth transistor, the first terminal of the third capacitor, and the first terminal of the second galvanometer are connected. The drain of the fifteenth transistor, the source of the seventeenth transistor, and the source of the eighteenth transistor are connected. The drain of the seventeenth transistor, the drain of the twenty-first transistor, the drain of the twenty-third transistor, and the gate of the twenty-third transistor are connected to the gate of the twenty-fourth transistor. The drain of the eighteenth transistor, the drain of the twenty-second transistor, and the gate of the twenty-first transistor are connected to the gate of the twenty-second transistor. The gate of the eighteenth transistor, the second terminal of the third capacitor, the second terminal of the second galvanometer, the drain of the twenty-fourth transistor, the drain of the twenty-fifth transistor, and the gate of the nineteenth transistor are connected. The drain of the nineteenth transistor, the drain of the twenty-seventh transistor, and the gate of the twenty-seventh transistor are connected to the gate of the twenty-eighth transistor. The drain of the twenty-sixth transistor, the source of the nineteenth transistor, and the source of the twentieth transistor are connected. The drain of the twentieth transistor, the drain of the twenty-eighth transistor, the drain of the twenty-sixth transistor, the gate of the twenty-fifth transistor, and the gate of the twenty-sixth transistor are connected to the input terminal of the second inverter unit. The sources of the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fourth transistor, the twenty-fifth transistor, the twenty-sixth transistor, the twenty-seventh transistor, and the twenty-eighth transistor are connected.

6. The circuit according to claim 1, characterized in that, The time difference generator includes a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate, a ninth NAND gate, a tenth NAND gate, an eleventh NAND gate, and a first XOR gate. The first input of the first NAND gate is connected to the output of the seventh NAND gate. The output of the first NAND gate, the first input of the third NAND gate, the first input of the seventh NAND gate, and the second input of the eighth NAND gate are connected to the second input of the ninth NAND gate. The second input of the second NAND gate is connected to the output of the eleventh NAND gate. The output of the second NAND gate, the second input of the sixth NAND gate, the third input of the eleventh NAND gate, the first input of the tenth NAND gate, and the third input of the ninth NAND gate are connected. The second input of the third NAND gate is connected to the first NAND gate. The output terminals of the gates are connected as follows: the output terminal of the third NAND gate, the first input terminal of the fourth NAND gate, the third input terminal of the seventh NAND gate, the first input terminal of the eighth NAND gate, and the first input terminal of the ninth NAND gate are connected; the second input terminal of the fourth NAND gate, the first input terminal of the fifth NAND gate, the second input terminal of the seventh NAND gate, and the output terminal of the ninth NAND gate are connected to the second input terminal of the eleventh NAND gate; the second input terminal of the fifth NAND gate, the output terminal of the sixth NAND gate, the fourth input terminal of the ninth NAND gate, and the second input terminal of the tenth NAND gate are connected to the first input terminal of the eleventh NAND gate; the output terminal of the fifth NAND gate is connected to the first input terminal of the sixth NAND gate; the output terminal of the eighth NAND gate is connected to the first input terminal of the first XOR gate; and the output terminal of the tenth NAND gate is connected to the second input terminal of the first XOR gate.

7. The circuit according to claim 1, characterized in that, The integrator includes a second resistor, a third resistor, a fourth capacitor, and an operational amplifier. The second end of the second resistor, the first end of the third resistor, and the first end of the fourth capacitor are connected to the negative input terminal of the operational amplifier, and the second end of the third resistor and the second end of the fourth capacitor are connected to the output terminal of the operational amplifier.

8. A method for suppressing ripple in an amplitude detector circuit, characterized in that, The suppression method is applied to the circuit according to any one of claims 1-7, and the suppression method includes the following steps: Acquire the differential input signal and perform amplitude detection to obtain the peak-to-peak value of the differential input signal; The capacitor charging and discharging rate is adjusted based on the peak-to-peak value of the differential input signal to eliminate the ripple information of the differential input signal.

9. The method according to claim 8, characterized in that, The step of adjusting the capacitor charging and discharging rate based on the peak-to-peak value of the differential input signal to eliminate the ripple information of the differential input signal includes: Frequency signal node detection is performed on the positive peak signal data to obtain the square wave information of the positive peak signal data; Frequency signal node detection is performed on the negative peak signal data to obtain the square wave information of the negative peak signal data; The square wave information of the negative peak signal data is compared with the square wave information of the positive peak signal data to obtain a pulse signal; The pulse signal is subjected to waveform conversion processing to obtain the control voltage value; The capacitor charging and discharging rate is adjusted according to the control voltage value to eliminate the ripple information of the differential input signal.

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