A method for detecting zero line loss in three-phase electric energy meter

Abstract

The present invention discloses a method for detecting a dropped zero line of a three-phase electric energy meter. The dropped zero line is judged by the frequency of an unbalanced voltage signal. The judgment criterion of this method is stable and reliable, and can be implemented by using a software algorithm synthesis method and a hardware sampling resistance method respectively. The two methods can also be applied simultaneously for double detection to increase reliability. The software algorithm synthesis method does not require any additional circuit, has higher detection sensitivity, and is more suitable for occasions with high detection accuracy requirements. The hardware sampling resistance method only needs to add a sampling resistor RN1, and the circuit is simple, reliable and low-cost, and is more suitable for occasions with low detection accuracy requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of intelligent electric meter detection, and in particular to a method for detecting a zero line drop of a three-phase electric energy meter. Background Art

[0002] An electric energy meter is an instrument used to measure electric energy. It is also called an electric meter, a fire meter, or a kilowatt-hour meter. It refers to an instrument that measures various electrical quantities. The neutral line is the line that leads from the neutral point on the secondary side of the transformer, and it forms a loop with the phase line to supply power to electrical equipment.

[0003] In a low-voltage three-phase four-wire system, if the neutral line is broken or the neutral line is artificially unplugged to steal electricity, the voltage of each phase will be unequal due to the imbalance of the three-phase load. Specifically, the voltage of the phase with a large load is low; the voltage of the phase with a small load is high. If the phase voltage is too high, the electrical equipment will be burned, and if the phase voltage is too low, the equipment will not operate normally.

[0004] According to data, at present, the power company needs to detect whether the neutral line is broken or whether it has been artificially unplugged by going to the site manually and using test equipment to detect the neutral line current or phase voltage. This detection method is time-consuming, labor-intensive, and inefficient, and it is necessary to improve it.

[0005] Chinese patent document CN106291089A discloses a "neutral line drop detection method for smart electric energy meters". First, the electric energy meter is powered on and initialized, and it is determined whether the neutral line drop flag is set. If not, voltage caches of phases A, B, and C are opened, three for each phase, to store the voltage value per second. Then the electric energy meter is powered on and operates normally, and the neutral line drop event is detected every second to determine the neutral line drop status flag. If it is currently in the neutral line drop state, it is determined that the neutral line drop event has ended; if it is currently in the non-neutral line drop state, it is determined that the neutral line drop event has started. The above technical solution cannot improve the adaptability of neutral line drop detection for different working occasions. Summary of the invention

[0006] The present invention mainly solves the technical problem that the original technical solution cannot improve the adaptability of zero line drop detection for different working occasions, and provides a zero line drop detection method for a three-phase electric energy meter. The zero line drop is judged by the frequency of the unbalanced voltage signal. The judgment criterion of this method is stable and reliable, and can be implemented using a software algorithm synthesis method and a hardware sampling resistor method respectively. The two methods can also be used simultaneously for double detection to increase reliability; the software algorithm synthesis method does not require any additional circuits, has higher detection sensitivity, and is more suitable for occasions with high detection accuracy requirements; the hardware sampling resistor method only needs to add a sampling resistor RN1, the circuit is simple, reliable and low-cost, and is more suitable for occasions with low detection accuracy requirements.

[0007] The above technical problems of the present invention are mainly solved by the following technical solutions: The present invention includes the following steps:

[0008] S1 According to the detection accuracy requirements, transform by software algorithm synthesis method and hardware sampling resistance method;

[0009] S2 Obtain the effective values UA, UB, and UC of three-phase voltages, and the frequencies fUA, fUB, and fUC of three-phase voltages;

[0010] S3 Conduct a primary judgment on the frequency detection signal to detect whether there is an effective waveform; if not, return to step S2 for the next cycle of waveform sampling;

[0011] S4 If there is, conduct a secondary judgment on the three-phase voltage frequencies to judge whether UA, UB, and UC are all greater than the threshold UL; if not, return to step S2 for the next cycle of waveform sampling;

[0012] S5 If UA, UB, and UC are all greater than the threshold UL, calculate the multiple relationship m between the sum of fUA, fU, and fUC and the frequency value fU0 of the frequency detection signal; calculate the multiple relationship between fU0 and fUA, fUB, fUC, m = fU0 / (fUA + fUB + fUC).

[0013] S6 Conduct a third judgment. If 0.9 < m < 1.1, output a zero-crossing signal; otherwise, return to step S1 for the next cycle of waveform sampling.

[0014] Preferably, the specific steps of obtaining waveform information by the software algorithm synthesis method in step S2 include: at a sampling rate of N points per cycle, collect the waveform values of three-phase voltages and record them in the sampling waveform arrays UAi[0...n - 1], UBi[0...n - 1], and UCi[0...n - 1]; according to the sampling waveform arrays UAi[0...n - 1], UBi[0...n - 1], and UCi[0...n - 1], calculate the corresponding effective values UA, UB, and UC of three-phase voltages and the frequencies fUA, fUB, and fUC of three-phase voltages.

[0015] Preferably, define U0 as the sum of three-phase voltage vectors, calculate U0i = UAi + UBi + UCi, record it in the sampling waveform array U0i[0...n - 1], and calculate the corresponding effective voltage value U0 and voltage frequency fU0 according to the sampling waveform array U0i[0...n - 1].

[0016] Preferably, the specific steps of conducting a primary judgment on the frequency detection signal by the software algorithm synthesis method in step S3 include: set the minimum voltage signal UL for accurate measurement of the electric energy meter for U0, judge whether U0 is greater than UL. If it is greater, proceed to step S4; if not, return to step S2 for the next cycle of waveform sampling.

[0017] Preferably, the step S2 of obtaining waveform information by hardware sampling resistance method specifically includes: reading three-phase voltage effective values ​​UA, UB and UC and three-phase voltage frequencies fUA, fUB and fUC respectively according to the data update cycle of the A, B and C phase metering chips.

[0018] Preferably, the step S3 of the hardware sampling resistor method for performing a frequency detection signal judgment specifically includes: judging whether a valid waveform is detected on the frequency detection signal F0-OUT, and if there is a waveform signal, proceeding to step S4, otherwise returning to step S2 and waiting for the next data update. A valid waveform refers to a continuous square wave signal with a frequency between 45Hz and 165Hz.

[0019] Preferably, the number of calculation cycles of the sampling data of the software algorithm synthesis method is M, and the number of sampling points required for each calculation cycle is n=M*N. For the convenience of subsequent calculations, N is usually selected as 64 / 128 / 256 / 512 points per cycle, and the number of sampling points depends on the design accuracy of the meter, the computing power of the MCU, etc. M is usually an integer multiple of the power grid frequency cycle, the minimum can be 1, and the maximum does not exceed 0.5 seconds.

[0020] As a preferred option, when the three-phase voltages of UA, UB, and UC are balanced and the neutral line is normally connected, , then UAi+UBi+UCi=0, that is, U0i=0, at this time the amplitude of U0 is 0 and there is no frequency value.

[0021] As a preferred option, when the three-phase voltages of UA, UB, and UC are unbalanced and the neutral line is normally connected, , U0i sequence is a sine wave, and U0 amplitude is , the frequency value is the same as the phase voltage UA, UB, and UC.

[0022] As a preferred embodiment, when the neutral line UN is not connected, the three-phase electric vector relationship is is no longer true. At this time, the AGND in the three-phase energy meter is determined by the dynamic balance of the input voltage through the resistor divider network, the varistor and the power supply circuit. When UA, UB and UC exist at the same time, the waveform obtained by the U0i sequence is an AC waveform with a frequency three times that of the input voltage signal.

[0023] The beneficial effects of the present invention are as follows: the zero line drop judgment is performed through the frequency of the unbalanced voltage signal, the judgment criterion of this method is stable and reliable, and can be implemented using the software algorithm synthesis method and the hardware sampling resistance method respectively, and the two methods can also be applied simultaneously for double detection to increase reliability; the software algorithm synthesis method does not require any additional circuit, has higher detection sensitivity, and is more suitable for occasions with high detection accuracy requirements; the hardware sampling resistance method only needs to add a sampling resistor RN1, the circuit is simple, reliable and low-cost, and is more suitable for occasions with low detection accuracy requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a flow chart of a software algorithm synthesis method of the present invention.

[0025] Figure 2 It is a flow chart of a hardware sampling resistance method of the present invention.

[0026] Figure 3 It is a circuit diagram of a first embodiment of the present invention.

[0027] Figure 4 This is a sampling waveform diagram of an embodiment 1 of the present invention when it is normally connected to a three-phase power grid.

[0028] Figure 5 This is a U0i waveform diagram when an embodiment 1 of the present invention is normally connected to a three-phase power grid.

[0029] Figure 6 This is a waveform diagram of a zero line sampling when an embodiment 1 of the present invention is normally connected to a three-phase power grid.

[0030] Figure 7 This is a waveform diagram of the neutral line U0i dropped when the first embodiment of the present invention is normally connected to the three-phase power grid.

[0031] Figure 8 This is a zero line drop harmonic analysis result diagram of the present invention.

[0032] Fig. 9 The present invention is an example of a sampling waveform diagram when the grid voltage is unbalanced.

[0033] Fig.10 This is a waveform diagram of U0i when the grid voltage is unbalanced, according to an embodiment of the present invention.

[0034] Fig.11 This is a waveform diagram of a zero line sampling when the grid voltage is unbalanced according to an embodiment of the present invention.

[0035] Fig.12 This is a waveform diagram of the neutral line U0i dropped when the grid voltage is unbalanced according to an embodiment of the present invention.

[0036] Fig.13 It is a circuit diagram of a second embodiment of the present invention.

[0037] Fig.14 This is a sampling waveform diagram of Embodiment 2 of the present invention when normally connected to a three-phase power grid.

[0038] Fig.15 This is a U0i waveform diagram when a second embodiment of the present invention is normally connected to a three-phase power grid.

[0039] Fig.16This is a waveform diagram of the sampling of the neutral line when the second embodiment of the present invention is normally connected to the three-phase power grid.

[0040] Fig.17 This is a waveform diagram of the neutral line U0i dropped when the second embodiment of the present invention is normally connected to the three-phase power grid.

[0041] Fig.18 This is a sampling waveform diagram when the grid voltage is unbalanced according to embodiment 2 of the present invention.

[0042] Fig.19 This is a waveform diagram of U0i when the grid voltage is unbalanced according to a second embodiment of the present invention.

[0043] Fig. 20 This is a waveform diagram of zero line sampling when the grid voltage is unbalanced according to embodiment 2 of the present invention.

[0044] Fig.21 This is a waveform diagram of the neutral line U0i dropped when the grid voltage is unbalanced according to the second embodiment of the present invention.

[0045] Fig. 22 The invention discloses a circuit schematic diagram of a software algorithm synthesis method.

[0046] Fig.23 The present invention is a circuit schematic diagram of a hardware sampling resistance method.

[0047] Fig.24 This is a sampling principle diagram of a hardware sampling resistor method of the present invention.

[0048] Fig.25 This is a circuit diagram of a third embodiment of the present invention.

[0049] Fig.26 This is a waveform diagram of Embodiment 3 of the present invention when normally connected to a three-phase power grid.

[0050] Fig. 27 This is a waveform diagram of a neutral line drop when a third embodiment of the present invention is normally connected to a three-phase power grid.

[0051] Fig.28 This is a waveform diagram of an embodiment 3 of the present invention when the grid voltage is unbalanced.

[0052] Fig.29 This is a waveform diagram of a zero line drop when the grid voltage is unbalanced in Embodiment 3 of the present invention.

[0053] Fig.30 This is a circuit diagram of a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the technical solution of the present invention is further described in detail below through embodiments and in combination with the accompanying drawings. It should be understood that the specific implementation method described here is only an optimal embodiment of the present invention, which is only used to explain the present invention and does not limit the scope of protection of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0055] The invention discloses a method for detecting a dropped neutral line (N line) of a three-phase electric energy meter, which is used for giving an alarm signal when the neutral line of the three-phase electric energy meter is disconnected, so as to facilitate on-site maintenance.

[0056] An implementation of the detection method mainly involves a signal input front-end circuit, a voltage signal sampling circuit, an ADC conversion circuit, a digital communication interface and a detection algorithm.

[0057] Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the operations (or steps) as sequential processes, many of the operations (or steps) therein can be implemented in parallel, concurrently, or simultaneously. In addition, the order of the operations can be rearranged. The process can be terminated when its operation is completed, but can also have additional steps not included in the drawings; the process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0058] The technical solution of the present invention is further specifically described below through embodiments and in conjunction with the accompanying drawings.

[0059] Embodiment: A method for detecting a zero line drop of a three-phase electric energy meter in this embodiment includes a method for detecting a zero line drop of a three-phase electric energy meter, characterized in that it includes the following steps:

[0060] S1 performs software algorithm synthesis method and hardware sampling resistance method transformation according to the detection accuracy requirements;

[0061] S2 obtains the three-phase voltage effective values ​​UA, UB and UC, and the three-phase voltage frequencies fUA, fUB and fUC.

[0062] The software algorithm synthesis method for obtaining waveform information specifically includes: collecting the three-phase voltage waveform values ​​at a sampling rate of N points per cycle and recording them in the sampling waveform arrays UAi[0...n-1], UBi[0...n-1] and UCi[0...n-1]; according to the sampling waveform arrays UAi[0...n-1], UBi[0...n-1] and UCi[0...n-1], calculating the corresponding three-phase voltage effective values ​​UA, UB and UC and the three-phase voltage frequencies fUA, fUB and fUC.

[0063] Define U0 as the three-phase voltage vector sum, calculate U0i=UAi+UBi+UCi, record it in the sampling waveform array U0i[0…n-1], and calculate the corresponding voltage effective value U0 and voltage frequency fU0 based on the sampling waveform array U0i[0…n-1].

[0064] The number of calculation cycles for the software algorithm synthesis method to sample data is M, and the number of sampling points required for each calculation cycle is n=M*N. To facilitate subsequent calculations, N is usually selected as 64 / 128 / 256 / 512 points per cycle. The number of sampling points depends on the design accuracy of the meter, the computing power of the MCU, etc. M is usually an integer multiple of the grid frequency cycle, the minimum can be 1, and the maximum does not exceed 0.5 seconds.

[0065] When the three-phase voltages of UA, UB, and UC are balanced and the neutral line is connected normally, , then UAi+UBi+UCi=0, that is, U0i=0, at this time the amplitude of U0 is 0 and there is no frequency value.

[0066] When the three-phase voltages of UA, UB, and UC are unbalanced and the neutral line is connected normally, , U0i sequence is a sine wave, and U0 amplitude is , the frequency value is the same as the phase voltage UA, UB, and UC.

[0067] When the neutral line UN is not connected, the three-phase electric vector relationship is no longer true. At this time, the AGND in the three-phase energy meter is determined by the dynamic balance of the input voltage through the resistor divider network, the varistor and the power supply circuit. When UA, UB and UC exist at the same time, the waveform obtained by the U0i sequence is an AC waveform with a frequency three times that of the input voltage signal.

[0068] The hardware sampling resistance method for obtaining waveform information specifically includes: reading the three-phase voltage effective values ​​UA, UB and UC and the three-phase voltage frequencies fUA, fUB and fUC respectively according to the data update cycle of the A, B and C phase metering chips.

[0069] S3 performs a frequency detection signal judgment to detect whether there is a valid waveform; if not, returns to step S2 to perform waveform sampling for the next cycle;

[0070] The minimum voltage signal of U0 accurately measured by the electric energy meter is set to UL, and it is determined whether U0 is greater than UL. If so, step S4 is performed; if not, step S2 is returned to perform waveform sampling for the next cycle.

[0071] The hardware sampling resistor method performs a frequency detection signal judgment specifically including: judging whether a valid waveform is detected on the frequency detection signal F0-OUT, if there is a waveform signal, proceeding to step S4, otherwise returning to step S2 and waiting for the next data update.

[0072] If S4 exists, perform a secondary judgment on the three-phase voltage frequency to determine whether UA, UB, and UC are all greater than the threshold UL; if not, return to step S2 for the next cycle of waveform sampling.

[0073] If UA, UB, and UC are all greater than the threshold UL, calculate the multiple relationship m between the sum of fUA, fU, and fUC and the frequency value fU0 of the frequency detection signal, and calculate the multiple relationship between fU0 and fUA, fUB, fUC, m = fU0 / (fUA + fUB + fUC).

[0074] Perform three judgments. If 0.9 < m < 1.1, perform zero-crossing signal output; otherwise, return to step S1 for the next cycle of waveform sampling.

[0075] Embodiment 1

[0076] As Fig. 22 shown, the external input voltage signals UA, UB, UC, and UN represent the A-phase voltage, B-phase voltage, C-phase voltage, and neutral line (N line) respectively. The A-phase voltage signal passes through voltage-dividing resistors RA1~RA8 and obtains a mV-level voltage sampling signal VS-UA on the sampling resistor RA9. After being conditioned, this signal is sent to the ADC for analog-to-digital conversion, and the waveform sampling value UAi of the A-phase voltage can be obtained at the MCU end. After the B-phase and C-phase voltage signals are processed in the same way, the waveform sampling values UBi and UCi are obtained respectively. At the same time, the external voltage input signals pass through varistor protection resistors RVA, RVB, and RVC respectively and are connected to the power supply circuit to provide the system working power for the entire watt-hour meter.

[0077] Define U0 as the three-phase voltage vector sum, then U0i = UAi + UBi + UCi. According to the three-phase electrical vector relationship, when the three-phase voltages UA, UB, and UC are balanced and the neutral line is normally connected, then UAi + UBi + UCi = 0, that is, U0i = 0. At this time, the amplitude of U0 is 0 and there is no frequency value.

[0078] When the three-phase voltages UA, UB, and UC are unbalanced and the neutral line is normally connected, , the U0i sequence is a sine wave, and the amplitude of U0 is , and the frequency value is the same as the phase voltages UA, UB, and UC.

[0079] When the neutral line UN is not connected, the three-phase electrical vector relationship no longer holds. At this time, the AGND in the meter is determined by the dynamic balance of the input voltage through the resistor voltage-dividing network, varistor, and power supply circuit. When UA, UB, and UC exist simultaneously, the waveform obtained from the U0i sequence is an AC waveform with a frequency three times that of the input voltage signal.

[0080] In a power grid with a rated voltage of 220V, let the voltage judgment start threshold be UL = 3.0V, the U0 frequency be f0, the power grid frequency be f = 50Hz, and the zero-crossing judgment logic is as Figure 1 shown.

[0081] The specific steps are as follows:

[0082] First, according to the project design requirements, confirm that the ADC sampling rate is N points per cycle (for convenience of subsequent calculations, usually 64 / 128 / 256 / 512 points per cycle are selected, and the number of sampling points depends on the design accuracy of the meter, the computing power of the MCU, etc.). Then, according to the real-time requirements, determine the number of calculation cycles M of the sampling data (usually an integer multiple of the power grid frequency cycle, the minimum can be 1, and the maximum does not exceed 0.5 seconds). Then, the number of sampling points n required for each calculation cycle is n = M * N.

[0083] 1) Continuously collect the voltage waveform values at a sampling rate of N points per cycle, and record them into the arrays UAi[0…n-1], UBi[0…n-1], UCi[0…n-1] respectively. At the same time, calculate U0i = UAi + UBi + UCi and record it into the array U0i[0…n-1]. When the number of sampling points reaches n, enter step 2;

[0084] 2) According to the sampling waveform sequences UAi[0…n-1], UBi[0…n-1], UCi[0…n-1], U0i[0…n-1], calculate the corresponding voltage effective values UA, UB, UC, U0 and frequencies fUA, fUB, fUC, fU0;

[0085] 3) Judge whether U0 is greater than UL (this value is the minimum voltage signal of U0 that the electric energy meter can accurately measure. To prevent misjudgment caused by interference signals, usually a value greater than 2.0V is selected). If it is greater, enter step 4; otherwise, return to step 1 for the next cycle of waveform sampling;

[0086] 4) Judge whether UA, UB, and UC are all greater than UL. If they are greater, enter step 5; otherwise, output a missing-phase signal for the phase with a voltage effective value less than UL, and then return to step 1 for the next cycle of waveform sampling;

[0087] 5) Calculate the multiple relationship between fU0 and fUA, fUB, fUC, m = fU0 / (fUA + fUB + fUC);

[0088] 6) Judge the numerical range of m. If 0.9 < m < 1.1, output a zero-crossing signal; otherwise, return to step 1 for the next cycle of waveform sampling;

[0089] 7) This judgment ends, return to step 1, and start the next cycle.

[0090] In the design of a 0.5S-class three-phase mutual inductor watt-hour meter, the circuit connection is as Figure 3 shown. The sampling chip used is HCT5812B. The voltage sampling signal is obtained by dividing the voltage with 8 pieces of 150 kΩ resistors and 1 piece of 360 Ω resistor. When the input voltage is 220 VAC, the sampling signal VS-UA = 220 / (8 * 150k + 360) * 360 = 0.066 VAC. After being amplified 4 times by the on-chip PGA, it enters the 22-bit ADC channel. There are two communication interfaces between HCT5812B and the MCU. Among them, the UART port is used for ADC configuration and reading the on-chip calculation results, and the SPI port is used for reading the real-time sampling waveform values. The sampling rate is set to 128 points per cycle. The MCU uses Huada HC32F460, which is a Ckortex-M4 core with a main frequency of 200 MHz to ensure the computing power required by the system. According to the design accuracy of this watt-hour meter, the minimum voltage detection threshold UL is defined as 3.0 V.

[0091] When the detection meter is normally connected to the three-phase power grid, the sampled waveform is as Figure 4 、 Figure 5 shown. The calculation coefficient between this sampled waveform and the actual voltage effective value is 2803.92 (this coefficient is obtained by comprehensively considering the voltage division ratio of the sampling resistor network, the ADC reference voltage, the ADC output bits, and the system gain). Under the condition of balanced power grid voltage and normal wiring, the calculated U0 value is about 1.41 V. At this time, U0 < UL, that is, U0 is lower than the set threshold of 3.0 V, and the zero-line disconnection judgment is not performed;

[0092] When the zero line of the meter is disconnected while keeping the input voltage unchanged, the sampled waveform becomes as Figure 6 、 Figure 7 shown. It can be seen from the waveforms of UA, UB, and UC that the sampled waveform has changed significantly at this time, and the harmonic analysis result is as Figure 8 shown. It can be seen from the figure that the 3rd harmonic content reaches 9.53%, which seriously affects the accuracy of watt-hour meter measurement, and this also directly illustrates the necessity of zero-line disconnection detection for three-phase watt-hour meters. At this time, the calculated U0 is 62.79 V, that is, U0 > UL. At this time, it can be seen from the waveform that the frequency of U0i is 3 times that of the input voltage signals UAi / Ubi / UCi, and it is judged as zero-line disconnection.

[0093] When the power grid voltage is unbalanced, such as when the voltage of phase C is 215 V, the sampled waveform is as Fig. 9 、 Fig.10As shown. At this time, the calculated U0 is 4.71V, that is, U0>UL, which meets the zero-drop judgment start and conditions. It can be seen from the waveform that the frequency of U0i is the same as that of the input voltage signals UAi / Ubi / UCi, and it is judged that the neutral line is normal;

[0094] When the grid voltage is unbalanced, for example, when the voltage of phase C is 215V, disconnect the neutral line of the meter, and the sampled waveform is as Fig.11 、 Fig.12 shown. It can be seen from the waveforms of UA, UB, and UC that the sampled waveform has also undergone obvious distortion at this time. At this time, the calculated U0 is 61.64V, that is, U0>UL. At this time, it can be seen from the waveform that the frequency of U0i is 3 times that of the input voltage signals UAi / Ubi / UCi, and it is judged as a dropped neutral line.

[0095] Embodiment 2

[0096] In the design of a 0.2S-class three-phase inductive energy meter, the circuit connection is as Fig.13 shown. The sampling chip used is HCT6311. The voltage sampling signal is obtained by voltage division of 8 200kΩ resistors and 1 360Ω resistor. When the input voltage is 240VAC, the sampling signal VS-UA = 240 / (8 * 200k + 360) * 360 = 0.054VAC. After being amplified 8 times by the on-chip PGA, it enters the 32-bit ADC channel. An SPI interface is used between HCT6311 and the MCU, and the sampling rate is set to 512 points per cycle. The MCU uses Huada HC32F4A0, which is a Ckortex-M4 core with a main frequency of 240MHz to ensure the computing power required by the system. According to the design accuracy of this energy meter, the minimum voltage detection threshold UL is defined as 2.0V.

[0097] When the detection meter is normally connected to the three-phase power grid, the sampled waveform is as Fig.14 、 Fig.15 shown. The calculated U0 value is about 0.68V. At this time, U0<UL, that is, U0 is lower than the set threshold of 2.0V, and no zero-drop judgment is made.

[0098] While keeping the input voltage unchanged, disconnect the neutral line of the meter, and the sampled waveform is as Fig.16 、 Fig.17 shown. At this time, the calculated U0 is 63.27V, that is, U0>UL. At this time, it can be seen from the waveform that the frequency of U0i is 3 times that of the input voltage signals UAi / Ubi / UCi, and it is judged as a dropped neutral line.

[0099] When the grid voltage is unbalanced, for example, when the voltage of phase C is 235V, the sampled waveform is as Fig.18 、 Fig.19At this time, the calculated U0 is 4.73V, that is, U0>UL, which meets the zero drop judgment start and conditions. From the waveform, it can be seen that the frequency of U0i is the same as the frequency of the input voltage signal UAi / Ubi / UCi, and it is judged that the zero line is normal.

[0100] When the grid voltage is unbalanced, such as when the C phase voltage is 235V, disconnect the neutral line of the meter, and the waveform sampled is as follows: Fig. 20 , Fig.21 As shown. From the waveforms of UA, UB, and UC, it can be seen that the sampling waveform has also been significantly distorted. At this time, the calculated U0 is 61.81V, that is, U0>UL. At this time, it can be seen from the waveform that the frequency of U0i is 3 times that of the input voltage signal UAi / Ubi / UCi, and it is judged that the zero line is dropped.

[0101] Another implementation of the detection method mainly involves a voltage signal sampling circuit, a zero-sequence voltage sampling circuit, a signal frequency detection circuit and a detection algorithm.

[0102] like Fig.23 As shown, the external input voltage signals UA, UB, UC, and UN represent the A-phase voltage, B-phase voltage, C-phase voltage, and neutral line (N line) respectively. After the A-phase voltage signal passes through the voltage-dividing resistors RA2 to RA9, a mV-level voltage sampling signal VS-UA is obtained on the sampling resistor RA1. After the signal is conditioned and sent to the metering chip for processing, the effective value and frequency of the A-phase voltage can be obtained on the MCU side. After the B and C-phase voltage signals are processed in the same way, the effective values ​​and frequencies of the B and C phase voltages are obtained respectively. The sampling resistor RN1 is connected in series to the UN input end to sample the current from the virtual center point U0' to UN of the resistor voltage-dividing network. The obtained voltage signal is VS-UN. At the same time, the external voltage input signal passes through the varistor protection resistors RVA, RVB, and RVC respectively, and is connected to the power supply circuit to provide the system working power supply for the entire electric energy meter.

[0103] like Fig.24 As shown, the neutral current sampling signal VS-UN is divided by resistors R1 and R2, and then sent to the comparator U1A to be compared with the threshold voltage set by VCC divided by R3 and R4. When the signal amplitude of VS-UN exceeds the set threshold, a square wave signal is output at the output terminal F0-OUT, corresponding to the frequency of the input signal VS-UN.

[0104] Define U0 as the three-phase voltage vector sum, then According to the three-phase electric vector relationship, when the three-phase voltages of UA, UB, and UC are balanced and the neutral line is connected normally, ,Right now , at this time, the amplitude of U0 is 0 and there is no frequency value.

[0105] When the three-phase voltages of UA, UB, and UC are unbalanced and the neutral line is properly connected, , is a sine wave, and the amplitude of U0 is , and the frequency value is the same as that of the phase voltages UA, UB, and UC.

[0106] When the neutral line UN is not connected, the three-phase electrical vector relationship no longer holds. At this time, the AGND in the meter is determined by the dynamic balance of the input voltage through the resistor voltage division network, varistor, and power supply circuit. When UA, UB, and UC exist simultaneously, is an AC waveform with a frequency three times that of the input voltage signal. The zero-drop judgment logic is as Figure 2 shown.

[0107] The specific steps are as follows:

[0108] 1) According to the data update period of the A, B, and C phase metering chips (the data update period of the metering chip used in this application is 80 ms), read the effective voltage values UA, UB, UC and frequencies fUA, fUB, fUC respectively;

[0109] 2) Determine whether there is a valid waveform detected on the frequency detection signal F0-OUT (a valid waveform refers to a continuous square wave signal with a frequency between 45 Hz and 165 Hz). If there is a waveform signal, proceed to step 3; otherwise, return to step 1 and wait for the next data update;

[0110] 3) Determine whether UA, UB, and UC are all greater than UL (in a direct three-phase meter, this value is set to 6.0 V). If greater, proceed to step 4; otherwise, output a missing phase signal for the phase with an effective voltage less than UL, and then return to step 1;

[0111] 4) Calculate the frequency value fU0 of the frequency detection signal F0-OUT (the MCU obtains its period T0 by capturing the rising edge signal of the F0-OUT signal, and fU0 = 1 / T0);

[0112] 5) Calculate the multiple relationship between fU0 and fUA, fUB, fUC, n = fU0 / (fUA + fUB + fUC);

[0113] 6) Determine the numerical range of n. If 0.9 < n < 1.1, output a zero-drop signal; otherwise, return to step 1 and perform waveform sampling for the next cycle;

[0114] 7) End this judgment, return to step 1, and start the next cycle.

[0115] Embodiment 3

[0116] In a 1.0 level direct manganese copper three-phase energy meter, if Fig.25 As shown, the metering chip uses HCT5821B (spare model V9240), and the communication interface between it and the MCU is UART, which can directly read the voltage and current effective value, active and reactive power, grid frequency and other data. The average effective value data update cycle is 1.28S, and the frequency update cycle is 2.56S. The MCU uses Juquan HT6333 (spare model: Fudan Micro FM33A066EV), which is a special chip for electric energy meters with Cortex-M0 core.

[0117] The detection signal sampling resistor RN1 is 1kΩ, and the zero-crossing detection comparator uses LMV331 from SiRuiPu, which is a high-precision, low-zero-drift comparator. The comparison threshold is set to 5mV, and the minimum detection voltage Vmin = 0.005 / 1k * 150k * 8 = 6V.

[0118] When the test meter is normally connected to the three-phase power grid, use an oscilloscope to observe the waveforms of VS-UN (CH1 channel) and F0-OUT (CH2 channel). Fig.26 At this time, the comparator input signal VS-UN is almost zero, the comparator output remains at a low level, no zero-crossing signal is detected, and no zero-drop judgment is performed.

[0119] While keeping the input voltage unchanged, disconnect the zero line of the meter, and the waveform sampled is as follows Fig. 27 At this time, it can be observed that the sampling signal VS-UN is obviously distorted and almost becomes a square wave. The comparator output signal F0-OUT is a 150Hz square wave, which is judged to be zero-dropped.

[0120] When the grid voltage is unbalanced, such as when the C phase voltage is 210V, the sampled waveform is as follows: Fig.28 shown.

[0121] When the grid voltage is unbalanced, such as when the C phase voltage is 210V, disconnect the neutral line of the meter, and the waveform sampled is as follows: Fig.29 At this time, it can be observed that the sampling signal VS-UN is similar to the three-phase voltage balance, and the comparator output signal F0-OUT is a 150Hz square wave, which is judged to be zero drop.

[0122] Embodiment 4

[0123] In a 1.0-level direct manganese-copper three-phase energy meter with neutral current detection function, if Fig.30As shown, the metering chip uses HCT5821B (spare model V9240), and the communication interface between it and the MCU is UART, which can directly read the voltage and current effective value, active and reactive power, grid frequency and other data. The average effective value data update cycle is 1.28S, and the frequency update cycle is 2.56S. The MCU uses Juquan HT6333 (spare model: Fudan Micro FM33A066EV), which is a special chip for electric energy meters with Cortex-M0 core.

[0124] The detection signal sampling resistor RN2 takes a value of 360Ω. The obtained voltage signal VS-UN enters the zero line sampling chip U4 (HCT5821B) after passing through the filter composed of RN2 and CN7. After being amplified by the on-chip 4x PGA, it enters the ADC channel. The voltage value U0 and its frequency fU0 of the detection signal can be directly read in the measurement data through the UART port.

[0125] The test results are as follows:

[0126]

[0127] Table 1 Test results

[0128] It can be seen from the data in the above table that under the four test conditions, fU0 can be used to determine whether the electric energy meter is in a zero-drop state.

[0129] The first technical key point in this method is the acquisition of the unbalanced voltage signal of the neutral line. The two implementation methods use the software algorithm synthesis method and the hardware sampling resistor method respectively. The former does not have any additional circuit, and the latter only adds a sampling resistor RN1. The circuit is simple and reliable. The software algorithm synthesis scheme has higher detection sensitivity and is more suitable for occasions with high detection accuracy. The hardware detection scheme has low cost and simple circuit, which is suitable for low-requirement occasions.

[0130] The second technical key point in this method is to judge whether the unbalanced voltage signal drops to zero based on its frequency, which is the key to this method. The judgment criterion is stable and reliable.

[0131] The specific embodiments described herein are merely examples of the spirit of the present invention. The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that technicians in the technical field to which the present invention belongs can make various modifications or supplements to the described specific embodiments or replace them in a similar manner, but will not deviate from the spirit of the present invention or exceed the scope defined in the attached claims. For ordinary technicians in this field, multiple deformations and improvements can also be made without departing from the concept of the present invention. Therefore, the scope of protection of the patent of the present invention shall be based on the attached claims.

Claims

1. A method for detecting a three-phase electric energy meter with a zero line drop, characterized in that: Including: S1 is transformed by the software algorithm synthesis method and / or the hardware sampling resistor method; In the software algorithm synthesis method, U0 is defined as the sum of three-phase voltage vectors, the effective voltage value U0 and the voltage frequency fU0; In the hardware sampling resistor method, a sampling resistor is connected in series at the input end of the neutral line UN, and the voltage signal VS-UN between the virtual center point U0' of the resistor voltage division network and UN is obtained. After voltage division and comparison, the frequency detection signal fU0 is output at the output end F0-OUT; S2 obtains the effective values UA, UB, and UC of the three-phase voltages, and the three-phase voltage frequencies fUA, fUB, and fUC; S3 makes a first judgment. The minimum voltage signal UL for accurate measurement of the watt-hour meter by the software algorithm synthesis method is set to judge whether U0 is greater than UL; the hardware sampling resistor method judges whether there is a continuous square wave signal with a frequency between 45 Hz and 165 Hz at the output end F0-OUT; S4 If so, a second judgment is made to judge whether UA, UB, and UC are all greater than the threshold UL; S5 If so, calculate the multiple relationship m between the sum of fUA, fUB, and fUC and the frequency value fU0; S6 makes a third judgment. If 0.9 < m < 1.1, then a zero-crossing signal is output.

2. A method for detecting a zero line drop in a three-phase electric energy meter according to claim 1, characterized in that: The specific steps for the software algorithm synthesis method in step S2 to obtain waveform information include: at a sampling rate of N points per cycle, collect the three-phase voltage waveform values and record them in the sampling waveform arrays UAi[0...n-1], UBi[0...n-1], and UCi[0...n-1]; according to the sampling waveform arrays UAi[0...n-1], UBi[0...n-1], and UCi[0...n-1], calculate the corresponding effective values UA, UB, and UC of the three-phase voltages and the three-phase voltage frequencies fUA, fUB, and fUC.

3. A method for detecting zero line loss in a three-phase electric energy meter according to claim 2, characterized in that: Define U0 as the sum of three-phase voltage vectors, calculate U0i = UAi + UBi + UCi, record it in the sampling waveform array U0i[0...n-1], and calculate the corresponding effective voltage value U0 and voltage frequency fU0 according to the sampling waveform array U0i[0...n-1].

4. A method for detecting a zero line drop in a three-phase electric energy meter according to claim 3, characterized in that: The specific steps for the software algorithm synthesis method in step S3 to make a first judgment on the frequency detection signal include: set the minimum voltage signal UL for accurate measurement of the watt-hour meter by U0, judge whether U0 is greater than UL. If it is greater, go to step S4; if not, return to step S2 for the next cycle of waveform sampling.

5. A method for detecting a zero line drop in a three-phase electric energy meter according to claim 1, characterized in that: The specific steps for the hardware sampling resistor method in step S2 to obtain waveform information include: respectively read the effective values UA, UB, and UC of the three-phase voltages and the three-phase voltage frequencies fUA, fUB, and fUC according to the data update period of the A, B, and C phase metering chips.

6. A method for detecting a zero line drop in a three-phase electric energy meter according to claim 5, characterized in that: The specific steps for the hardware sampling resistor method in step S3 to make a first judgment on the frequency detection signal include: judge whether there is an effective waveform detected on the frequency detection signal F0-OUT. If there is a waveform signal, go to step S4; otherwise, return to step S2 and wait for the next data update.

7. A method for detecting zero line loss in a three-phase electric energy meter according to claim 2, 3 or 4, characterized in that: The number of calculation cycles for sampling data by the software algorithm synthesis method is M, and the number of sampling points n required for each calculation cycle is n = M * N.

8. A method for detecting zero line loss in a three-phase electric energy meter according to claim 2, 3 or 4, characterized in that: When the three-phase voltages of UA, UB and UC are balanced and the neutral line is connected normally, Then UAi+UBi+UCi=0, that is, U0i=0. At this time, the amplitude of U0 is 0 and there is no frequency value.

9. A method for detecting zero line loss in a three-phase electric energy meter according to claim 2, 3 or 4, characterized in that: When the three-phase voltages of UA, UB and UC are unbalanced and the neutral line is connected normally, The U0i sequence is a sine wave, and the U0 amplitude is The frequency value is the same as the phase voltages UA, UB and UC.

10. A method for detecting zero line loss in a three-phase electric energy meter according to claim 2, 3 or 4, characterized in that: When the neutral line UN is not connected, the three-phase electric vector relationship is no longer true. At this time, the AGND in the three-phase energy meter is determined by the dynamic balance of the input voltage through the resistor divider network, the varistor and the power supply circuit. When UA, UB and UC exist at the same time, the waveform obtained by the U0i sequence is an AC waveform with a frequency three times that of the input voltage signal.

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