Memory and storage systems

Abstract

The application discloses a memory and a storage system, wherein the memory comprises: a first operation decoding module configured to perform first analysis processing on a read-write instruction signal in a bus signal to output a read-write preprocessing signal; a read-write preprocessing module configured to start a read-write preprocessing operation according to the read-write preprocessing signal to output a read-write operation signal to a storage array; and at least one correlation decoding module configured to perform second analysis processing on a correlation instruction signal in the bus signal to output a correlation operation signal to the storage array. The memory, the working method thereof and the storage system can simplify the decoding logic of the bus signal and shorten the time for finally reading or writing data to the storage array.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a memory and a storage system. BACKGROUND

[0002] Memory is used to store information in various electronic devices (such as computers, wireless communication devices, and cameras, etc.), and the information is stored by regulating different states of the memory. With the rapid development of artificial intelligence technology, higher requirements are put forward for the computing performance, reading performance, writing performance, reliability, data retention capability, etc. of electronic devices.

[0003] In existing memory, multi-cycle instruction memory can complete the reading operation of instructions within one or more clock cycles, can improve the performance of the processor, and can increase the parallelism of instruction acquisition, reduce the waiting time, and thus improve the throughput of the entire system. 3D XPoint phase-change memory (PCM) is a kind of multi-cycle instruction memory.

[0004] In multi-cycle instruction memory, the acquisition process of instructions can be divided into multiple stages, such as address stage, reading stage, and execution stage, etc. In this way, various modules of the processor can work at the same time in different stages, without having to wait for each stage to be completed sequentially as in single-cycle memory. This design allows the processor to start the next instruction within one clock cycle, even if the previous instruction has not been completely read.

[0005] However, the read-write instruction response time of the existing multi-cycle instruction memory still needs to be shortened. SUMMARY

[0006] The main purpose of the present application is to provide a memory and a storage system, which aims to shorten the read-write instruction response time of the memory.

[0007] To achieve the above purpose, the technical scheme of the present application provides a memory, comprising: a first operation decoding module configured to receive a bus signal and perform first analysis processing on a read-write instruction signal in the bus signal to output a read-write preprocessing signal; a read-write preprocessing module configured to be coupled with the first operation decoding module, start a read-write preprocessing operation according to the read-write preprocessing signal, and output a read-write operation signal to a storage array; and at least one correlation decoding module configured to receive the bus signal and perform second analysis processing on a correlation instruction signal in the bus signal to output a correlation operation signal to the storage array.

[0008] In some embodiments, the time of the first analysis processing is less than the time of the second analysis processing.

[0009] In some embodiments, the read-write instruction signal comprises a read-write flag signal and a read-write distinguishing signal; and the read-write preprocessing signal comprises a read instruction signal or a write instruction signal.

[0010] In some embodiments, the first operation decoding module is configured to perform first parsing processing on the read-write instruction signal, specifically comprising: judging whether to perform a read-write operation according to the read-write flag signal; and when confirming to perform the read-write operation, outputting the read instruction signal or the write instruction signal according to the read-write distinguishing signal.

[0011] In some embodiments, further comprising: at least one second operation decoding module, coupled with the first operation decoding module, and configured to, when confirming not to perform the read-write operation, perform third parsing processing on other instruction signals in the bus signal to output other operation signals to the storage array.

[0012] In some embodiments, the first operation decoding module comprises: a first gate circuit, one input end of the first gate circuit being used for inputting the read-write flag signal, and the other input end being used for inputting the read-write command signal; a second gate circuit, one input end of the second gate circuit being used for inputting the read-write distinguishing signal, and the other input end being used for inputting the read-write command signal; and a third gate circuit, two input ends of the third gate circuit being connected with the output ends of the first gate circuit and the second gate circuit respectively, and the output end of the third gate circuit being used for outputting the read-write operation signal.

[0013] In some embodiments, the read-write operation signal comprises a read operation signal and a write operation signal; and the read-write preprocessing module is configured to start a read-write preprocessing operation according to the read-write preprocessing signal, specifically comprising: starting a read preprocessing operation according to the read instruction signal to output the read operation signal; and starting a write preprocessing operation according to the write instruction signal to output the write operation signal.

[0014] In some embodiments, the related decoding module is configured to, when starting the read-write preprocessing operation or before starting the read-write preprocessing operation, perform second parsing processing on related instruction signals in the bus signal to output related operation signals to the storage array.

[0015] In some embodiments, further comprising: a read-write operation core processing module, coupled with the read-write preprocessing module and the related decoding module respectively, and configured to perform data read-write operations on the storage array according to the read-write operation signal and the related operation signal.

[0016] In some embodiments, further comprising: an N-bus, an i-th control line and a j-th control line in the N-bus are used to output the read-write instruction signal, and a relevant control line other than the i-th control line and the j-th control line in the N-bus is used to output a relevant instruction signal, wherein N, i and j are natural numbers, N≥3, i≠j, i≤N, and j≤N.

[0017] Correspondingly, the present application also provides a storage system, comprising: a controller, configured to output a bus signal, wherein the bus signal in a first period comprises a read-write instruction signal and a relevant instruction signal; and the memory according to any one of the preceding embodiments, coupled to the controller.

[0018] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0019] In the memory of the present application, the read-write instruction signal in the bus signal is subjected to first analysis processing by the first operation decoder and a read-write pre-processing signal is outputted. Since the read-write instruction signal is part of the instruction signal in the bus signal, the first analysis processing of the read-write instruction signal is simple, the time of the first analysis processing is short, and the outputted read-write pre-processing signal is simple and difficult to cause backend signal delay. Moreover, the read-write pre-processing module can start read-write pre-processing operation based on the read-write pre-processing signal. Since the time of the first analysis processing is short, that is, the time from the start of analysis of the bus signal to the output of the read-write operation signal to the storage array is short, that is, the response time of the storage array to the bus signal is short. At the same time, the relevant decoding module can perform second analysis processing of the relevant instruction signal in the bus signal at the same time as the first analysis processing and the read-write pre-processing operation, so that the time of the second analysis processing does not prolong the response time of the read-write instruction signal. In summary, the memory can simplify the decoding logic of the bus signal and shorten the time of finally reading or writing data to the storage array.

[0020] In some embodiments, the time of the first analysis processing is shorter than the time of the second analysis processing. On the one hand, the analysis time of the read-write instruction is shorter than the analysis time of the relevant instruction, so that the read-write pre-processing module can start the read-write pre-processing operation before the relevant instruction is completed, thereby shortening the time from the start of analysis of the read-write instruction signal to the output of the read-write operation signal. On the other hand, the relevant instruction signal can continue to be analyzed during the read-write pre-processing operation, so that the second analysis processing does not prolong the time of the storage array responding to the read-write instruction.

[0021] In the working method of the memory of the technical solution of the present application, since the read-write instruction signal is part of the instruction signal in the bus signal, the first analysis processing of the read-write instruction signal is simple, the first analysis processing time is short, and the output read-write pre-processing signal is simple, and the backend signal delay is difficult to occur. Moreover, since the first analysis processing time is short, that is, the response time of the memory array responding to the bus signal is short. At the same time, the second analysis processing of the related instruction signal in the bus signal is performed while the first analysis processing and the read-write pre-processing operation are performed, and the second analysis processing time will not prolong the response time of the read-write instruction signal. In summary, the working method of the memory can simplify the decoding logic of the bus signal and shorten the time of finally reading data or writing data to the memory array.

[0022] In the storage system of the technical solution of the present application, the decoding logic of the bus signal is simplified, and the time of reading data or writing data to the memory array is shortened. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor based on the drawings shown.

[0024] Figure 1 It is a structural schematic diagram of a multi-cycle instruction type memory embodiment;

[0025] Figure 2 For Figure 1 The circuit structure diagram of each decoding module 100 in the embodiment is shown in the figure;

[0026] Figure 3 It is a structural schematic diagram of a memory of the embodiment of the present application;

[0027] Figure 4 It is a circuit structure diagram of a first operation decoding module 200 of the embodiment of the present application;

[0028] Figure 5 It is a circuit structure diagram of another first operation decoding module 200 embodiment of the present application;

[0029] Figure 6 It is a structural schematic diagram of a read-write operation core processing module of the embodiment;

[0030] Figure 7 It is a flowchart of the working method of the memory of the embodiment of the present application;

[0031] Figure 8 is a flowchart of a first analysis process and a read-write preprocessing operation process;

[0032] Figure 9 is Figure 1 The memory embodiment shown in Figures 3 to 6 The timing diagram of the read operation or the write operation of the memory embodiment shown in

[0033] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0034] As described in the background, the read-write instruction response time of the existing multi-cycle instruction memory still needs to be shortened. The following will be described in detail in conjunction with the accompanying drawings.

[0035] Figure 1 is a structural schematic diagram of a multi-cycle instruction memory embodiment, comprising: a plurality of decoding modules 100, the first input end of each decoding module 100 is connected to an N-way bus CA, the second input end of each decoding module is connected to an N-bit command signal end B, and the output end of each decoding module 100 outputs operation instructions to a storage array 101 respectively. Wherein, N is a natural number.

[0036] In the multi-cycle instruction memory, the instruction information of the N-way bus CA is contained in multiple cycles. Specifically, in the first cycle, the instruction information of the N-way bus CA contains all operation information, such as read operation information and write operation information; in the remaining cycles, the instruction information of the N-way bus CA contains address information, etc. However, the analysis time of the multi-cycle instruction memory for each read operation information and write operation information is relatively long, please refer to Figure 2 for a detailed description.

[0037] Figure 2 is Figure 1 is a circuit structure diagram of each decoding module 100 in the multi-cycle instruction memory, comprising: N exclusive OR gates 110, the first input end of each exclusive OR gate 110 is connected to a control line in the N-way bus CA, and the second input end of each exclusive OR gate 110 is connected to one end of the N-bit command code signal end B; a multi-stage combinational logic module 120, the N input ends of the multi-stage combinational logic module 120 are connected to the output ends of the N exclusive OR gates 110, and the output end of the multi-stage combinational logic module 120 is used to output read operation instructions or write operation instructions CMD to the storage array 101.

[0038] Since the read operation information or the write operation information is encoded into the multi-way control lines of the N-way bus CA in the multi-cycle instruction memory, each read operation information or write operation information needs a corresponding decoding module 100 to parse, resulting in a relatively long time for parsing each read operation information and write operation information.

[0039] Moreover, the multi-cycle instruction memory includes multiple different types of read operation types and write operation types, and thus needs multiple decoding modules 100 to parse the different types of read operation information and write operation information. Figure 2 The decoding module 100 shown is controlled by the N-bit command code signal end B to implement parallel operation to parse the different types of read operation information and write operation information. When the parsed multiple read operation instructions or write operation instructions converge at the output ends of the multiple decoding modules 100, additional signal time delay is easily introduced. Ultimately, the multi-cycle instruction memory still has a relatively long response time to read and write instructions.

[0040] To solve the above problems, an embodiment of the present application provides a memory, including: a first operation decoding module configured to perform first parsing processing on read and write instruction signals in bus signals to output read and write preprocessing signals; a read and write preprocessing module configured to start read and write preprocessing operations according to the read and write preprocessing signals to output read and write operation signals to a storage array; and at least one related decoding module configured to perform second parsing processing on related instruction signals in the bus signals to output related operation signals to the storage array.

[0041] The first operation decoder performs first parsing processing on read and write instruction signals in bus signals and outputs read and write preprocessing signals. Since the read and write instruction signals are part of the instruction signals in the bus signals, the first parsing processing on the read and write instruction signals is simple, the first parsing processing time is short, and the output read and write preprocessing signals are simple and difficult to have backend signal delay. Moreover, the read and write preprocessing module can start read and write preprocessing operations based on the read and write preprocessing signals. Since the first parsing processing time is short, the time from starting to parse the bus signals to outputting read and write operation signals to the storage array is short, that is, the response time of the storage array to the bus signals is short. At the same time, the related decoding module can perform second parsing processing on related instruction signals in the bus signals while performing the first parsing processing and the read and write preprocessing operations, and thus the second parsing processing time does not prolong the response time of the read and write instruction signals. In summary, the memory can simplify the decoding logic of the bus signals and shorten the time for finally reading or writing data to the storage array.

[0042] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0043] In addition, the descriptions such as "first", "second" and the like in the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the fact that a person of ordinary skill in the art can realize it. When the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist, and is not within the protection scope of the present application.

[0044] Figure 3 is a structural schematic diagram of a memory according to an embodiment of the present application, comprising: a first operation decoding module 200 configured to receive a bus signal and perform first analysis processing on a read-write instruction signal in the bus signal to output a read-write preprocessing signal; a read-write preprocessing module 210 coupled with the first operation decoding module 200 and configured to start a read-write preprocessing operation according to the read-write preprocessing signal to output a read-write operation signal to a memory array 220; and at least one correlation decoding module 230 configured to receive the bus signal and perform second analysis processing on a correlation instruction signal in the bus signal to output a correlation operation signal to the memory array 220.

[0045] The following will be described in detail with reference to the accompanying drawings.

[0046] The memory is a multi-cycle instruction memory, and the memory is coupled with a controller through a bus CA_n. The controller obtains a bus signal through the bus CA_n. In a first cycle of the bus signal, all operation instruction information is included. In other cycles after the first cycle, the bus signal includes address information, data information, etc. In the embodiment, the bus signal in the first cycle includes a read-write instruction signal, which is used to control the memory array 220 to perform a read operation or a write operation.

[0047] The bus CA_n includes N control lines, where N is a natural number greater than or equal to 3. In the embodiment, in the N control lines, an i-th control line and a j-th control line CA[i; j] are used to output a read-write instruction signal for distinguishing whether a read operation, a write operation or other operation is performed on the memory array 220, where i and j are natural numbers, i≠j, i≤N, and j≤N.

[0048] In the N control lines, an i-th control line and a j-th control line CA The read / write instruction signal includes a read / write flag signal and a read / write distinguishing signal. The read / write flag signal is used to distinguish the read / write operation from other operations. The read / write distinguishing signal is used to distinguish the read operation from the write operation.

[0049] In this embodiment, the read / write instruction signal includes a read / write flag signal and a read / write distinguishing signal. The read / write flag signal is used to distinguish the read / write operation from other operations. The read / write distinguishing signal is used to distinguish the read operation from the write operation.

[0050] The first operation decoding module 200 is configured to perform a first parsing process on the read / write instruction signal. The method includes: judging whether to perform the read / write operation according to the read / write flag signal; and outputting the read instruction signal or the write instruction signal according to the read / write distinguishing signal after confirming to perform the read / write operation.

[0051] In this embodiment, the time of the first parsing process is less than the time of the second parsing process. On one hand, the parsing time of the read / write instruction is shorter than the parsing time of the related instruction. The read / write pre-processing module 210 can start the read / write pre-processing operation before the related instruction is parsed, thereby shortening the time from the start of the parsing of the read / write instruction signal to the output of the read / write operation signal. On the other hand, the related instruction signal can continue to be parsed during the read / write pre-processing operation, thereby making the second parsing process not prolong the time of the storage array responding to the read / write instruction.

[0052] In this embodiment, the i-th control line CA for outputting the read / write flag signal to the first operation decoding module 200, the jth control line CA <j>The read-write distinguishing signal is output to the first operation decoding module 200. In addition, the first operation decoding module 200 is also used for inputting a 2-bit (2-bit) read-write command signal B1 for controlling the operation of the first operation decoding module 200.

[0053] In the embodiment, please refer to Figure 4 , Figure 4 is a circuit structure diagram of a first operation decoding module 200 in the embodiment of the application, which comprises a first gate circuit 201, one input end of the first gate circuit 201 is connected with the i-th control line CA a connection for inputting the read / write flag signal; a second gate circuit 202, one input terminal of the second gate circuit 202 being connected to the jth control line CA <j>a third gate circuit 203, two input ends of the third gate circuit 203 are connected with an output end of the first gate circuit 201 and an output end of the second gate circuit 202 respectively, and an output end of the third gate circuit 203 is used for outputting the read-write operation signal CMD; another input end of the first gate circuit 201 and another input end of the second gate circuit 202 are used for inputting the 2-bit read-write command signal B1.

[0054] In the embodiment, the first gate circuit 201 and the second gate circuit 202 are XOR gates, and the third gate circuit is an AND gate.

[0055] Please refer to Table 1, which is an encoding table of the first operation decoding module 200 for the first analysis processing of the read-write instruction signal.

[0056] Table 1

[0057]

[0058]

[0059] As shown in Table 1, when the ith control line CAi is high, the first gate circuit 201 outputs the read-write instruction signal, and the second gate circuit 202 outputs the read-write instruction signal. The read-write flag signal is output to the first operation decoding module 200 as high level 1, and it is determined to perform read-write operation on the memory array; when the i-th control line CA When a low level 0 is output to the first operation decode module 200, other operations are performed on the memory array. At the ith control line CA On the basis of outputting a high level 1 to the first operation decode module 200, when the jth control line CA <j>When a high level 1 is output to the first operation decode module 200, it is determined that a write operation is performed on the memory array; when the jth control line CA <j>When the low level 0 is output to the first operation decoding module 200, it is determined to perform the read operation on the storage array.

[0060] In another embodiment, referring to Figure 5 , Figure 5 is the circuit structure diagram of another embodiment of the first operation decoding module 200 of the present application, which comprises:

[0061] The first gate circuit 301 has one input end connected with the i-th control line CA a connection, another input terminal of the first gate circuit 301 is used for inputting one bit signal in the 2-bit read-write command signal B1;

[0062] a second gate circuit 302, one input terminal of the second gate circuit 302 is connected with the i-th control line CA The connection, one of the two read-write command signals B1 is input to the other input terminal of the second gate circuit 302 through the second inverter 306.

[0063] The third gate circuit 303, one input terminal of the third gate circuit 303 is connected with the i control line CA <j>a connection, another input terminal of the third gate circuit 303 is used for inputting one bit signal in the 2-bit read-write command signal B1;

[0064] a fourth gate circuit 304, one input terminal of the fourth gate circuit 304 is connected with the i-th control line CA <j>The one signal in the 2-bit read-write command signal B1 is input to another input terminal of the fourth gate circuit 304 through a second inverter 311;

[0065] The fifth gate circuit 307 has two input terminals connected to the output terminals of the first gate circuit 301 and the second gate circuit 302 respectively;

[0066] The sixth gate circuit 308 has two input terminals connected to the output terminals of the third gate circuit 303 and the fourth gate circuit 304 respectively;

[0067] The seventh gate circuit 309 has two input terminals connected to the output terminals of the fifth gate circuit 307 and the sixth gate circuit 308 respectively, and is configured to output the read-write operation signal CMD.

[0068] The first gate circuit 301, the second gate circuit 302, the third gate circuit 303, the fourth gate circuit 304 and the seventh gate circuit 309 are AND gates, and the fifth gate circuit 307 and the sixth gate circuit 308 are OR gates.

[0069] In some embodiments, the memory further comprises at least one second operation decoding module (not shown) coupled to the first operation decoding module 200, and the second operation decoding module is configured to perform a third parsing process on other instruction signals in the bus signals to output other operation signals to the memory array 220 when it is confirmed that the read-write operation is not to be performed. Specifically, when the i-th control line CA When the output low level is 0, the second operation decoding module performs third analysis processing on the other instruction signals, so that the storage array 220 performs other operations. When the number of the second operation decoding modules is multiple, the operation signals output by different second operation decoding modules are different, and the storage array performs corresponding operations based on the different operation signals. Each second operation decoder controls the working mode by using the input multi-bit command signal.

[0070] The read-write preprocessing module is configured to start a read-write state machine based on the read-write preprocessing signal, and to prepare for the read-write operation of the storage array 220. In the embodiment, the read-write preprocessing signal includes a read instruction signal or a write instruction signal; and the read-write operation signal includes a read operation signal and a write operation signal. The method for starting the read-write preprocessing operation according to the read-write preprocessing signal includes: starting a read preprocessing operation according to the read instruction signal to output the read operation signal; and starting a write preprocessing operation according to the write instruction signal to output the write operation signal.

[0071] The correlation decoding module 230 outputs a correlation operation signal including detailed information related to the read-write operation, such as whether it is a regular read-write or a burst read-write, and the correlation operation signal and the read-write operation signal are both output to the read-write operation core processing module 240, so that the read-write operation core processing module 240 can perform corresponding operations on the storage array 220 based on the correlation operation signal and the read-write operation signal.

[0072] When the number of the correlation decoding modules 230 is multiple, the correlation operation signals output by different correlation decoding modules 230 are different, and are used to control different operations of the storage array 220. Each correlation decoding module 230 controls the operation according to different multi-bit command signals B2-Bn, so as to control the corresponding correlation decoding module 230 to output the corresponding correlation operation signal.

[0073] In the embodiment, the correlation decoding module 230 is configured to perform second analysis processing on the correlation instruction signal in the bus signal to output the correlation operation signal to the storage array when starting the read-write preprocessing operation or before starting the read-write preprocessing operation. In other embodiments, the correlation decoding module 230 is configured to perform second analysis processing on the correlation instruction signal in the bus signal before starting the read-write preprocessing operation.

[0074] The read-write operation core processing module is coupled with the read-write preprocessing module and the correlation decoding module, and is configured to perform data read-write operation on the storage array 220 according to the read-write operation signal and the correlation operation signal.

[0075] In the embodiment, refer to Figure 6 , Figure 6 is a structural schematic diagram of a read-write operation core processing module of the embodiment, comprising:

[0076] a logic control module, configured to output row-column decoding signals and row-column processing signals according to the read-write operation signal CMD_1 and the related operation signal CMD_2[x;0];

[0077] a row-column decoder, configured to output the row-column operation signal according to the row-column decoding signals;

[0078] a row-column processing module, configured to output bit line driving signals and word line driving signals according to the row-column operation signal and the row-column processing signals;

[0079] a bit line driver, configured to output bit line operation signals according to the bit line driving signals;

[0080] a word line driver, configured to output word line operation signals according to the word line driving signals;

[0081] the storage array 220 performs read operation or write operation according to the bit line operation signals and the word line operation signals.

[0082] In summary, the read-write instruction signal in the bus signal is subjected to first analysis processing by the first operation decoder and read-write preprocessing signals are outputted, since the read-write instruction signal is part of the instruction signal in the bus signal, the first analysis processing of the read-write instruction signal is simple, the first analysis processing time is short, and the outputted read-write preprocessing signal is simple, and it is difficult to cause backend signal delay. Moreover, the read-write preprocessing module can start read-write preprocessing operation based on the read-write preprocessing signal, since the first analysis processing time is short, that is, the time from starting to analyze the bus signal to outputting read-write operation signal to the storage array is short, that is, the response time of the storage array to the bus signal is short. At the same time, the related decoding module can perform second analysis processing of the related instruction signal in the bus signal at the same time of performing first analysis processing and read-write preprocessing operation, and the second analysis processing time will not extend the response time of the read-write instruction signal. In summary, the memory can simplify the decoding logic of the bus signal and shorten the time of finally reading data or writing data to the storage array.

[0083] Correspondingly, the embodiment of the application further provides a working method of the above memory, refer to Figure 7 , Figure 7 is a flowchart of a working method of the memory of the embodiment of the application, comprising:

[0084] Step S10, obtaining bus signals;

[0085] Step S11, performing first analysis processing on read-write instruction signals in the bus signals to output read-write preprocessing signals;

[0086] Step S12, starting read-write preprocessing operation according to the read-write preprocessing signals to output read-write operation signals to the storage array;

[0087] Step S13, performing second analysis processing on related instruction signals in the bus signals to output related operation signals to the storage array.

[0088] The following will be described in detail with reference to the accompanying drawings.

[0089] Please refer to Figure 7 Step S10 is performed to obtain bus signals.

[0090] The memory is a multi-cycle instruction memory. In the first cycle of the bus signals, all operation instruction information is included; in other cycles after the first cycle, the bus signals include address information, data information, etc. In this embodiment, the bus signals in the first cycle include read-write instruction signals, which are used to control the storage array 220 to perform read operation or write operation.

[0091] Please continue to refer to Figure 7 Step S11 is performed to perform first analysis processing on read-write instruction signals in the bus signals to output read-write preprocessing signals.

[0092] In this embodiment, the read-write instruction signals include read-write flag signals and read-write distinguishing signals, the read-write flag signals are used to distinguish read-write operation and other operations, and the read-write distinguishing signals are used to distinguish read operation and write operation. The read-write preprocessing signals include read instruction signals or write instruction signals.

[0093] In the following, the first analysis processing of this embodiment will be described with reference to Figure 8 , Figure 8 is a flowchart of the first analysis processing and the starting of read-write preprocessing operation processing.

[0094] The method of performing first analysis processing on the read-write instruction signals includes:

[0095] Step S100, judging whether to perform read-write operation according to the read-write flag signals;

[0096] Step S101, when confirming to perform the read-write operation, outputting the read instruction signals or the write instruction signals according to the read-write distinguishing signals.

[0097] Step S102, when confirming that the read-write operation is not performed, performing third parsing processing on other instruction signals in the bus signals to output other operation signals to the storage array.

[0098] Please continue to refer to Figure 7 Step S12 is performed, and a read-write preprocessing operation is started according to the read-write preprocessing signal to output a read-write operation signal to the storage array.

[0099] The read-write preprocessing signal is used to start a read-write state machine and to prepare for a read-write operation on the storage array. In this embodiment, the read-write preprocessing signal includes a read instruction signal or a write instruction signal; and the read-write operation signal includes a read operation signal and a write operation signal.

[0100] Please continue to refer to Figure 8 The method for starting the read-write preprocessing operation according to the read-write preprocessing signal includes:

[0101] Step S103, a read preprocessing operation is started according to the read instruction signal to output a read operation signal;

[0102] Step S104, a write preprocessing operation is started according to the write instruction signal to output a write operation signal.

[0103] Please continue to refer to Figure 7 Step S13 is performed, and second parsing processing is performed on related instruction signals in the bus signals to output related operation signals to the storage array.

[0104] The related operation signals include detailed information related to the read-write operation, such as whether it is a regular read-write or a burst read-write, and the related operation signals and the read-write operation signal are both output to the read-write operation core processing module 240, so that the read-write operation core processing module 240 can perform corresponding operations on the storage array 220 based on the related operation signals and the read-write operation signal.

[0105] The second parsing processing includes various different parsing processing modes for outputting different related operation signals to perform different operation controls on the storage array 220.

[0106] In this embodiment, the time of the first parsing processing is less than the time of the second parsing processing. On the one hand, the parsing time of the read-write instruction is shorter than the parsing time of the related instruction, and then the read-write preprocessing module 210 can start the read-write preprocessing operation before the related instruction is completed, thereby shortening the time from the start of the parsing of the read-write instruction signal to the output of the read-write operation signal. On the other hand, the related instruction signal can continue to be parsed during the read-write preprocessing operation, so that the second parsing processing does not prolong the time of the storage array responding to the read-write instruction.

[0107] In the embodiment, the second parsing process is performed on the relevant instruction signal in the bus signal to output the relevant operation signal to the storage array when the read-write preprocessing operation is started. In other embodiments, the second parsing process is performed on the relevant instruction signal in the bus signal before the read-write preprocessing operation is started.

[0108] After step S13, the storage array performs the data read-write operation according to the read-write operation signal and the relevant operation signal.

[0109] Please refer to Figure 9 , Figure 9 is Figure 1 the timing diagram of the read operation or the write operation of the memory embodiment shown in Figures 3 to 6 .

[0110] Specifically, Figure 1 in the memory shown in, the decoding signals output by each decoding module 100 are input to the read-write preprocessing module, and the read-write preprocessing module controls the read-write operation of the storage array. In Figure 9 , T0 is the time when the memory acquires the read-write instruction signal; CMD_pre0 is Figure 1 in the memory embodiment shown in, the working state signal of the read-write preprocessing module, when the working state signal is inverted from low level to high level, that is, each decoding module 100 completes the decoding work, the read-write preprocessing module starts to work; CMD_pre1 is Figures 3 to 6 in the memory embodiment shown in, the working state signal of the read-write preprocessing module 210, when the working state signal is inverted from low level to high level, that is, the read-write preprocessing module 210 acquires the read-write preprocessing signal and starts the read-write preprocessing operation.

[0111] As can be seen from Figure 9 , Figure 1 in the memory shown in, the time from when the memory acquires the read-write instruction signal to when the read-write preprocessing module starts to work is a, and the time from when the read-write preprocessing module runs to when the storage array starts to perform the read-write operation is b, that is, the time from when the memory acquires the read-write instruction signal to when the storage array starts to perform the read-write operation is a+b.

[0112] And Figures 3 to 6 in the memory shown in, the time from when the memory acquires the read-write instruction signal to when the read-write preprocessing module starts to work is a1, and the time from when the read-write preprocessing module runs to when the storage array starts to perform the read-write operation is b, that is, the time from when the memory acquires the read-write instruction signal to when the storage array starts to perform the read-write operation is a1+b.

[0113] And the a1 < a, the time of the memory of the embodiment shortens from obtaining the read-write instruction signal to starting the read-write operation of the memory array, thus the response time of the memory array to the bus signal is shorter.

[0114] In summary, since the read-write instruction signal is part of the bus signal, the first analysis processing of the read-write instruction signal is simple, the time of the first analysis processing is shorter, and the output read-write preprocessing signal is simple, and the backend signal delay is difficult to occur. Moreover, since the time of the first analysis processing is shorter, that is, the response time of the memory array to the bus signal is shorter. At the same time, the second analysis processing of the related instruction signal in the bus signal is performed at the same time of the first analysis processing and the read-write preprocessing operation, and the time of the second analysis processing does not prolong the response time of the read-write instruction signal. In summary, the working method of the memory can simplify the decoding logic of the bus signal and shorten the time of reading data or writing data to the memory array.

[0115] Correspondingly, the embodiment of the application also provides a storage system, comprising: a controller, configured to output bus signals, wherein the read-write instruction signal and the related instruction signal are included in the bus signal of the first period; and Figures 3 to 6 The memory is coupled with the controller. In the storage system, the decoding logic of the bus signal is simplified, and the time of reading data or writing data to the memory array is shortened.

[0116] The above description is only optional embodiments of the application, and does not limit the patent scope of the application, and any equivalent structural transformation, direct / indirect application in other related technical fields under the inventive concept of the application, and the contents of the specification and drawings are included in the patent protection scope of the application. < / j> < / j> < / j> < / j> < / j> < / j>

Claims

1. A memory, comprising: Comprising: a first operation decoding module configured to receive bus signals and perform a first parsing process on read-write instruction signals in the bus signals to output read-write pre-processing signals; a read-write pre-processing module coupled with the first operation decoding module and configured to start a read-write pre-processing operation according to the read-write pre-processing signals to output read-write operation signals to a storage array; at least one correlation decoding module configured to receive the bus signals and perform a second parsing process on correlation instruction signals in the bus signals to output correlation operation signals to the storage array.

2. The memory of claim 1, wherein, The first parsing process takes less time than the second parsing process.

3. The memory of claim 1, wherein, The read-write instruction signals include read-write flag signals and read-write distinguishing signals; and the read-write pre-processing signals include read instruction signals or write instruction signals.

4. The memory of claim 3, wherein, The first operation decoding module is configured to perform the first parsing process on the read-write instruction signals, specifically including: determining whether to perform a read-write operation according to the read-write flag signals; after confirming to perform the read-write operation, outputting the read instruction signals or the write instruction signals according to the read-write distinguishing signals.

5. The memory of claim 4, wherein, Further comprising: at least one second operation decoding module coupled with the first operation decoding module and configured to perform a third parsing process on other instruction signals in the bus signals to output other operation signals to the storage array when it is determined not to perform the read-write operation.

6. The memory of claim 4, wherein, The first operation decoding module includes: a first gate circuit, one input end of the first gate circuit being used to input the read-write flag signals and the other input end being used to input read-write command signals; a second gate circuit, one input end of the second gate circuit being used to input the read-write distinguishing signals and the other input end being used to input the read-write command signals; a third gate circuit, two input ends of the third gate circuit being connected to output ends of the first gate circuit and the second gate circuit respectively, and an output end of the third gate circuit being used to output the read-write operation signals.

7. The memory of claim 3, wherein, The read-write operation signals include read operation signals and write operation signals; The read-write pre-processing module is configured to start the read-write pre-processing operation according to the read-write pre-processing signals, specifically including: starting a read pre-processing operation according to the read instruction signals to output the read operation signals; starting a write pre-processing operation according to the write instruction signals to output the write operation signals.

8. The memory of claim 1, wherein, The correlation decoding module is configured to perform the second parsing process on the correlation instruction signals to output the correlation operation signals to the storage array when or before the read-write pre-processing operation is started.

9. The memory of claim 1, wherein, Further comprising: a read-write operation core processing module coupled with the read-write pre-processing module and the correlation decoding module respectively and configured to perform data read-write operations on the storage array according to the read-write operation signals and the correlation operation signals.

10. The memory of claim 1, wherein, Further comprising: An N-bus, an i-th control line and a j-th control line in the N-bus being used for outputting the read-write instruction signal, and a relevant control line other than the i-th control line and the j-th control line in the N-bus being used for outputting a relevant instruction signal, N, i and j being natural numbers, N≥3, i≠j, i≤N and j≤N.

11. A storage system, characterized by Comprising: a controller for outputting bus signals, the bus signals in a first period including a read-write instruction signal and a relevant instruction signal; The memory of any one of claims 1 to 10, coupled with the controller.

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