A fast configuration method for programmable logic device

Abstract

The present invention provides a method for quickly configuring a programmable logic device, comprising the following steps: Step 1: using an EDA tool to generate an Octal SPI configuration file, the EDA tool loads the Octal SPI configuration file into a Flash chip; Step 2: setting the SPI controller of the programmable logic device to the SPI Master mode, and configuring the programmable logic device in the Octal SPI mode; Step 3: the programmable logic device reads part of the files in the configuration file in the Octal SPI mode, and determines whether the part of the files is correct. If the part of the files is correct, the configuration is successful, and if the part of the files is wrong, the configuration fails, and the programmable logic device reloads the data stream from the Flash. The beneficial effect of the technical solution is that the configuration file is stored in the Flash, the Flash interface signal is small, and the FPGA can be quickly configured.

Description

Technical Field

[0001] The invention belongs to the technical field of programmable logic device design, and in particular relates to a method for quickly configuring a programmable logic device. Background Art

[0002] Programmable logic devices (PLDs) are a type of integrated circuit whose internal logic functions can be defined by users through software tools without modifying the hardware design.

[0003] Field Programmable Gate Array (FPGA), as a type of programmable logic device, is a large-scale programmable device. Users can design the required functions through hardware description languages ​​(such as Verilog or VHDL) and compile them into data flow files to program the FPGA. FPGA provides system programmability and reconfiguration capabilities, is highly customizable and scalable, and has a short development cycle. These advantages have made FPGAs widely used in various fields, and have also promoted the continuous increase in the scale of FPGAs. The FPGA configuration file is automatically generated by the FPGA design software. It contains all the information of the FPGA design. As the scale of the FPGA increases, the configuration file also increases. Therefore, it is also very important to speed up the configuration of the FPGA. If the FPGA can quickly transmit the configuration file through fewer communication signal lines, it will greatly simplify user use while improving configuration efficiency.

[0004] A complex programmable logic device (CPLD) is a digital integrated circuit that can be configured and programmed by the user according to their needs. CPLD allows designers to create custom logic functions without the need to use discrete logic gate circuits or other fixed-function logic chips.

[0005] In the prior art, the conventional FPGA and CPLD parallel configuration methods include: 1. QSPI configuration method, using quadspi nor flash, but only a maximum of 4-bit data line configuration is possible. When two flashes are used, only 8-bit data line configuration can be achieved; 2. BPI configuration method (schematic diagram as shown in Figure 2 ) Using bpi flash requires addressing (address line), which is inconvenient to use; 3. Select map (active parallel / passive parallel) configuration method (diagram as shown Figure 3 ) The interface has many control signals and generally requires larger peripheral configurations such as prom or MCU, making it more complicated to use.

[0006] In order to solve the problems of slow configuration speed and inconvenient use of FPGA and CPLD configuration in the prior art, it is necessary to design a new programmable logic device configuration method, which can effectively improve the efficiency of programmable logic device configuration. Summary of the invention

[0007] The invention provides a method for fast configuration of a programmable logic device, which utilizes Octal SPI NOR Flash to store configuration files, an Octal SPI parallel interface, and can select a single transmission rate or a double transmission rate mode to transmit the configuration files, thereby realizing fast active configuration of the programmable logic device.

[0008] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0009] To achieve one or part or all of the above purposes or other purposes, a technical solution of the present invention provides a method for quickly configuring a programmable logic device, comprising the following steps: Step 1: Using an EDA tool to generate an Octal SPI configuration file, the EDA tool loads the Octal SPI configuration file into an Octal SPI NOR Flash chip; Step 2: Setting the SPI controller of the programmable logic device to SPI Master mode, the programmable logic device is powered on or a PROGAM_B instruction is sent, the programmable logic device sends a clock signal to the Octal SPI NOR Flash, and the programmable logic device is configured in Octal SPI mode; Step 3: The programmable logic device reads part of the files in the configuration file in Octal SPI mode, and determines whether the part of the files is correct. If the part of the files is correct, the configuration is successful; if the part of the files is wrong, the configuration fails, and the programmable logic device reloads the data stream from the Octal SPI NOR Flash. The beneficial effect of the technical solution is that the present invention stores configuration files through Octal SPI NOR Flash. The Octal SPI NOR Flash has few interface signals but can achieve a configuration rate of up to 16 times that of SPI, and has a large storage capacity, which is convenient for users to use. While being able to quickly configure, the user's data can also be placed in the Octal SPI NOR Flash, thereby realizing functions such as multiple startup and storage of a large amount of user data, and improving the flexibility of FPGA configuration.

[0010] The configuration file generated in step 1 includes setting the data bit width for transmitting configuration data between the programmable logic device and the Octal SPI NORFlash, where the bit width can be configured as X1 or X8; and setting the data transmission rate to a single transmission rate or a double transmission rate.

[0011] The configuration file generated in step 1 includes a combination of data bit width and transmission rate transmitted between the programmable logic device and the Octal SPI NOR Flash.

[0012] The configuration file generated in step 1 is used to represent the configuration parameters transmitted in the Octal SPI mode by setting the value of the register configuring the Octal SPI mode in the data stream.

[0013] The method for loading the Octal SPI configuration file into the Octal SPI NOR Flash chip by the EDA tool includes offline burning or loading through JTAG; the JTAG loading includes that the jtag interface on the programmable logic device receives the configuration file and sends the configuration file to the configuration controller of the programmable logic device, the configuration controller converts the received data into SPI commands, and loads the configuration file into the Octal SPI NOR Flash through the SPI interface.

[0014] In the step 2, the programmable logic device is configured in the Octal SPI mode in the following manner: the programmable logic device first sends a clock signal to the Octal SPI NOR Flash, and sets the initial Octal SPI configuration mode to the data bit width X1, and reads the data in the Octal SPI NOR Flash at a single transmission rate to configure the programmable logic device; after the programmable logic device recognizes the Octal SPI configuration information in the data stream, the Octal SPI configuration mode is selected to configure the programmable logic device.

[0015] The programmable logic device identifying the Octal SPI configuration information in the data stream means that when the programmable logic device parses the configuration file data stream, it selects the corresponding Octal SPI configuration mode according to the value of the register for configuring the Octal SPI mode obtained through the parsing.

[0016] The Octal SPI configuration mode is selected to configure the programmable logic device in such a manner that the programmable logic device identifies the Octal SPI configuration mode according to the parsed register value, and the configuration controller inside the programmable logic device automatically arbitrates and switches the Octal SPI configuration mode according to the identified Octal SPI configuration mode, and reads data from the Octal SPI NOR Flash in the adjusted Octal SPI configuration mode.

[0017] In step 3, the programmable logic device reads the header file in the configuration file in the Octal SPI mode, and when the parsed data stream is correct, the programmable logic device is configured successfully.

[0018] In step 3, when the PLD configuration fails, the multi-boot function is enabled, and the device falls back to the golden address to reload the data stream from the Octal SPI NOR Flash.

[0019] The programmable logic device is FPGA or CPLD.

[0020] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. The present invention stores configuration files through Octal SPI NOR Flash. The Octal SPI NOR Flash has few interface signals, but can achieve a configuration rate of up to 16 times the SPI, and has a large storage capacity, which is convenient for users to use. While being able to quickly configure, the user's data can also be placed in the Octal SPINOR Flash to achieve functions such as multiple startup, thereby improving the flexibility of FPGA configuration;

[0021] 2. The present invention stores configuration files through Octal SPI NOR Flash, and can select single transmission rate or double transmission rate to transmit configuration files, thereby improving the efficiency of traditional configuration of programmable logic devices using SPI mode. When powered on or reconfiguration is required, the programmable logic device reads the data stream from the flash through Octal SPI x1, and automatically arbitrates the data bit width and switches to Octal SPI x8 for configuration file according to the configuration information in the data stream. No external control switch is required, and the programmable logic device configuration method is quickly started.

[0022] 3. The configuration method of the present invention is not only applicable to FPGA but also to other programmable logic chips, such as CPLD.

[0023] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 This is a flow chart of the Octal SPI configuration of the programmable logic device of the present invention.

[0026] Figure 2 It is a schematic diagram of the Octal SPI configuration method of the programmable logic device of the present invention.

[0027] Figure 3 Schematic diagram of the method for loading data into flash using JTAG in the present invention. DETAILED DESCRIPTION

[0028] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0029] Example 1 takes the programmable fast configuration method of the present invention to realize the fast configuration of FPGA as an example to explain the fast configuration method of the programmable logic device of the present invention. It should be noted that the fast configuration method of the programmable logic device of the present invention is not only applicable to FPGA but also to other programmable logic devices such as complex programmable logic devices (CPLD).

[0030] See also Figure 1 , the FPGA configuration of embodiment 1 includes the following steps:

[0031] Step 1: Set Octal SPI (OSPI is a high-speed serial peripheral interface that extends the traditional SPI protocol. Compared with the traditional SPI interface, in addition to the basic clock and chip select signals, it also provides multiple data lines, usually 8 data lines (DQ0-DQ7). For the connection method of the data lines and the direction of signal transmission, please refer to Figure 2 ,visible Figure 2There are 8 data interfaces and data lines for signal transmission between the FPGA and the Octal SPI NOR Flash. OSPI can transmit multiple bits of data in parallel within one clock cycle, which improves the data transmission speed and configuration parameters, and uses EDA tools (Electronic Design Automation, EDA tools are a series of software used to assist in the design, simulation, verification and manufacture of electronic systems) to generate an Octal SPI configuration file. The Octal SPI configuration file generated here is a file that has set and defined the Octal SPI interface parameters and is used to store in the Octal SPINOR Flash to configure the programmable device. This embodiment 1 defines the optional configuration of Octal SPI including data transmission bit width: X1 mode with 1 data line for data transmission between Octal SPI NOR Flash and FPGA, and X8 mode with 8 data lines; and data transmission rate: single transmission rate STR (data is transmitted only on the rising edge of the clock), double transmission rate DTR (data is transmitted on both the rising and falling edges of the clock signal, which is twice the transmission speed of the single transmission rate). At the same time, the data transmission bit width and the data transmission rate are combined to obtain the configuration method parameters in the Octal SPI mode.

[0032] The configuration file adds the register value for configuring the Octal SPI mode in the data stream file. When the FPGA parses the data stream, it obtains the register value for configuring the Octal SPI mode, and can switch the configuration parameters of the Octal SPI mode, thereby controlling the FPGA to fetch data from flsah in the switched Octal SPI mode. The register value represents the configuration parameters of the Octal SPI mode, see Table 1 below.

[0033] Table 1 Correspondence between register values ​​and configuration parameters of Octal SPI mode

[0034]

[0035] The X1 transmission mode means that one data line transmits the configuration file, and the X8 transmission mode means that eight data lines transmit the configuration file. When the Octal SPI X1 STR mode is used for transmission, it means that only a 1-bit configuration file is transmitted in one clock cycle; when the Octal SPI X1 DTR mode is used for transmission, it means that a 2-bit configuration file is transmitted in one clock cycle; when the Octal SPI X8STR mode is used for transmission, it means that only an 8-bit configuration file is transmitted in one clock cycle; when the Octal SPI X8 DTR mode is used for transmission, it means that a 16-bit configuration file is transmitted in one clock cycle. The configuration speed of the Octal SPI X8 DTR mode is 16 times that of the traditional SPI X1 mode.

[0036] The EDA tool loads the Octal SPI configuration file into the Octal SPI NOR Flash chip. The OctalSPI configuration file can be loaded by offline burning or by using jtag to burn the configuration file. If you use the offline burning method, you can use the FPGA dedicated tool or the factory test machine to directly burn the configuration file. If you use the jtag method to burn, refer to Figure 3 , import the configuration file data through the FPGA's JTAG interface and send the input data to the configuration controller in the FPGA. The configuration controller converts the received data into SPI commands and loads the data into the Octal SPI NORFlash through the SPI interface.

[0037] Step 2: Set the FPGA's SPI controller to SPI Master mode. Here, the FPGA is set to SPI Master mode. The configuration mode is determined by the input of the FPGA's mode PIN (M2M1M0). For example, M2M1M0=000 indicates active serial mode, and M2M1M0=001 indicates SPI_Master mode.

[0038] At the same time, the FPGA is configured in Octal SPI mode. When the FPGA is powered on or the PROGAM_B instruction is sent, the FPGA sends a clock signal to the Octal SPI NOR Flash. The clock signal sent can be found in Figure 2 The signal cclk in the FPGA is a bidirectional signal, which can be an output signal or an input signal, used to transmit data. When in active mode, cclk is output, and the FPGA configuration controller will output a clock. When in passive mode, cclk is input, which is input from the outside. The FPGA is configured in Octal SPI mode, and the FPGA will read data from the Octal SPI NOR Flash for loading.

[0039] When reading the FPGA configuration file in Octal SPI mode, the initial loading mode can be set to OctalSPI X1 STR. When the FPGA loads the configuration file in the flash in the initial loading mode, the value of the register that configures the Octal SPI transmission mode can be read from the parsed data stream. The configuration controller in the FPGA will adjust the Octal SPI mode according to the register value, first adjust the bit width of the transmitted data, and then decide whether to adjust the data transmission rate. After the Octal SPI mode is adjusted, the FPGA will read data from the Octal SPI NOR Flash according to the adjusted Octal SPI mode to configure the FPGA.

[0040] Step 3: FPGA reads some files in the configuration file. Some files here are usually located at the beginning of the configuration file and will be parsed out first during parsing. FPGA verifies the parsed files to determine whether the files are correct. If some files are correct, FPGA DONE=1, then the configuration is successful; if some files are wrong, FPGA DONE=0, then the configuration fails, and FPGA reloads the data stream from Octal SPI NOR Flash. When the programmable logic device configuration fails, enable the multi-boot function (Multboot), fall back to the golden address, and reload the data stream from Octal SPINOR Flash. Enabling the multi-boot function and falling back to the golden address to reload the data stream is a conventional solution in the prior art, and this application does not elaborate on this solution here.

[0041] The above mainly describes how to use the method of the present invention to configure FPGA. When the method of the present invention is used to configure CPLD, except for the chip to be configured, the remaining steps and methods are the same as the FPGA configuration method.

[0042] The above is a detailed introduction to a method for rapid configuration of a programmable logic device provided by the present invention. This article uses specific examples to illustrate the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for rapid configuration of a programmable logic device, characterized in that: The steps include: Step 1: Use the EDA tool to generate an Octal SPI configuration file, and the EDA tool loads the Octal SPI configuration file into the Octal SPI NOR Flash chip; The generated configuration file includes setting the data bit width for transmitting configuration data between the programmable logic device and the Octal SPI NOR Flash, and the bit width can be configured as X1 or X8; and setting the data transmission rate to single transmission rate or double transmission rate; The generated configuration file sets the value of the register that configures the Octal SPI mode in the data stream to represent the configuration parameters transmitted in the Octal SPI mode. Step 2: Set the SPI controller of the PLD to SPI Master mode, power on the PLD or send the PROGAM_B instruction, the PLD sends a clock signal to the Octal SPI NOR Flash, and configures the PLD in OctalSPI mode; Step 3: The programmable logic device reads some files in the configuration file in Octal SPI mode, and determines whether the some files are correct. If the some files are correct, the configuration is successful; if the some files are wrong, the configuration fails, and the programmable logic device reloads the data stream from the Octal SPI NOR Flash.

2. A method for rapid configuration of a programmable logic device according to claim 1, characterized in that: The configuration file generated in step 1 includes a combination of data bit width and transmission rate transmitted between the programmable logic device and the Octal SPI NOR Flash.

3. A method for rapid configuration of a programmable logic device according to claim 1, characterized in that: The method of loading the Octal SPI configuration file into the Octal SPI NOR Flash chip by the EDA tool includes offline burning or loading through JTAG; The JTAG loading method includes: the JTAG interface on the programmable logic device receives the configuration file and sends the configuration file to the configuration controller of the programmable logic device. The configuration controller converts the received data into SPI commands and loads the configuration file into Octal SPI NOR Flash through the SPI interface.

4. A method for rapid configuration of a programmable logic device according to claim 1, characterized in that: In the step 2, the programmable logic device is configured in the Octal SPI mode in such a way that the programmable logic device first sends a clock signal to the Octal SPI NOR Flash, and sets the initial Octal SPI configuration mode to a data bit width of X1, and reads data in the Octal SPI NOR Flash at a single transmission rate to configure the programmable logic device; After the programmable logic device recognizes the Octal SPI configuration information in the data stream, the Octal SPI configuration mode is selected to configure the programmable logic device.

5. A method for rapid configuration of a programmable logic device according to claim 4, characterized in that: The programmable logic device identifying the Octal SPI configuration information in the data stream means that when the programmable logic device parses the configuration file data stream, it selects the corresponding Octal SPI configuration mode according to the value of the register for configuring the Octal SPI mode obtained through the parsing.

6. A method for rapid configuration of a programmable logic device according to claim 5, characterized in that: The OctalSPI configuration mode is selected to configure the programmable logic device in such a manner that the programmable logic device identifies the Octal SPI configuration mode according to the parsed register value, and the configuration controller inside the programmable logic device automatically arbitrates and switches the Octal SPI configuration mode according to the identified Octal SPI configuration mode, and reads data from the Octal SPI NOR Flash in the adjusted Octal SPI configuration mode.

7. A method for rapid configuration of a programmable logic device according to claim 5, characterized in that: In step 3, the programmable logic device reads the header file in the configuration file in the Octal SPI mode, and when the parsed data stream is correct, the programmable logic device is configured successfully.

8. A method for rapid configuration of a programmable logic device according to claim 1, characterized in that: In step 3, when the PLD configuration fails, the multi-boot function is enabled, and the device falls back to the golden address to reload the data stream from the Octal SPINOR Flash.

9. A method for rapid configuration of a programmable logic device according to any one of claims 1 to 8, characterized in that: The programmable logic device is FPGA or CPLD.

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