Method for verifying function of electronic migration inspection module, computer device, medium and program product

Abstract

The present application relates to the technical field of electron migration function verification, and particularly relates to a method for verifying the function of an electron migration checking module, a computer device, a medium and a program product.The method provided by the present application comprises the following steps: providing feature layout and combining at least two different feature layouts to obtain a first number of initial use cases; screening the initial use cases to obtain a second number of test cases, wherein the first number is greater than the second number; providing electron migration rules, generating a plurality of test condition parameters based on the electron migration rules; combining the test cases with each test condition parameter respectively to obtain a plurality of test case sets; providing standard output results, running the test case sets based on the electron migration checking module and obtaining running results; comparing the running results with the standard output results to verify the accuracy of the function of the electron migration checking module. The present application solves the problem of low efficiency of testing and verifying the electron migration checking.

Description

[Technical Field]

[0002] This invention relates to the field of electronic migration function verification technology, and in particular to an electronic migration check module function verification method, computer equipment, media, and program products. [Background Technology]

[0004] Electromigration (EM) refers to the migration of metal atoms in a metal conductor under high-density current, leading to problems such as conductor deformation and increased heat generation. This phenomenon becomes increasingly pronounced with advanced manufacturing processes, significantly negatively impacting the performance, reliability, and lifespan of integrated circuits. Therefore, Electronic Design Automation (EDA) software needs to include EM detection capabilities.

[0005] Electromigration rules refer to specified constraints under variable factors, such as the effects of current or temperature. Circuit designs provided by designers typically need to meet electromigration rules, therefore, electromigration rule checking tests are usually performed on the designed circuits. Electromigration rule checking is part of the physical verification of integrated circuit designs. It mainly uses an electromigration rule checking module to check the designed circuit, and its main purpose is to ensure that the drawn layout is completely consistent with the designed circuit. Before using the function of the electromigration rule checking module, its accuracy must be verified. Design layouts are composed of individual circuit units. A small-scale design layout can contain tens of thousands of circuit units. Taking a small-scale design with 400,000 units as an example, in current technology, verifying the function of the electromigration rule checking module using a small-scale design layout takes about 30 minutes, and the complex layout and routing in the layout during result analysis can interfere with the determination of the cause of problems, which is very inconvenient. Therefore, using existing verification techniques to test and verify the EM (Electromigration Rule Check) function is very inefficient. [Summary of the Invention]

[0007] To address the problem of low efficiency in testing and verifying the EM (Electronic Migration Inspection) function using existing verification technologies, this invention provides a method, computer equipment, media, and program product for verifying the function of an electronic migration inspection module.

[0008] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a method for verifying the function of an electron migration inspection module, comprising the following steps:

[0009] Provide a design layout, select some circuit units to form a feature layout, and combine at least two different feature layouts to obtain a first number of initial use cases;

[0010] The initial test cases are filtered to obtain a second number of test cases, where the first number is greater than the second number;

[0011] Provides e-migration rules, and generates multiple test condition parameters based on these rules;

[0012] The test cases are combined with each test condition parameter to obtain multiple test case sets;

[0013] It provides standard output results, runs test case sets based on the e-migration check module, and obtains the results.

[0014] The results were compared with the standard output to verify the accuracy of the electronic migration check module.

[0015] Preferably, the feature layout includes normal layout and abnormal layout; normal layout includes layout with multiple lines connected and vias, layout with multiple lines connected and interrupted, layout with multiple lines connected in T-shapes, layout with line connection ports, layout with pins in the line connection base unit, and layout with variable width lines; abnormal layout includes empty layout, layout with cells but lacking routing information, and layout with open and closed lines.

[0016] Preferably, combining the feature maps includes:

[0017] Each feature map is combined with other feature maps to construct a factor table;

[0018] Initial use cases that remove combinations with outliers from the factor table are generated, and a first number of initial use cases are generated.

[0019] Among them, the combination of abnormal situations is the initial use case composed of the combination of normal layout and abnormal layout.

[0020] Preferably, the initial use case screening includes:

[0021] The initial test cases are filtered using an orthogonal array method to obtain a second number of test cases;

[0022] The orthogonal array method is as follows:

[0023] ;

[0024] In the formula, n represents the minimum number of test cases, and s represents the number of feature maps. This represents the number of level factors under the i-th influencing factor, where =2.

[0025] Preferably, the generation of multiple test condition parameters based on electron migration rules includes:

[0026] Electromigration rules include the maximum effective current rule, the maximum average current rule, and the maximum peak current rule;

[0027] The maximum current RMS value rule generates the first test condition parameters based on the equivalence class partitioning method;

[0028] The maximum average current rule generates the second test condition parameters based on the equivalence class partitioning method;

[0029] The maximum peak current rule generates the third test condition parameters based on the equivalence class partitioning method;

[0030] The number of parameters in the first test condition is less than the number of parameters in the second test condition, which in turn is less than the number of parameters in the third test condition.

[0031] Preferably, combining test cases with each test condition parameter includes:

[0032] The test cases are combined with the first test condition parameters and filtered using a preset method to form the first test case set;

[0033] The test cases are combined with the second test condition parameters and filtered using a preset method to form the second test case set;

[0034] The test cases are combined with the third test condition parameters and filtered using a preset method to form a third test case set.

[0035] The test case set includes a first test case set, a second test case set, and a third test case set, and the contents of the first test case set, the second test case set, and the third test case set are all different.

[0036] Preferably, comparing the running results with the standard output results to verify the accuracy of the electronic migration check module's function includes:

[0037] The running results are compared with the standard output results, and the error value of the comparison is obtained;

[0038] Determine whether the error value meets the preset range;

[0039] If so, it indicates that the electronic migration check module is functioning correctly;

[0040] If not, it indicates that the sub-migration check function is inaccurate.

[0041] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a computer program product, including a computer program / instruction, which, when executed by a processor, implements the above-described electronic migration check module function verification method.

[0042] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, the computer instructions being used to cause the computer to execute the above-mentioned electronic migration check module function verification method.

[0043] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a computer device applied to the above-mentioned electronic migration check module function verification method, including a memory, a processor and a computer program stored in the memory, wherein the processor executes the above-mentioned computer program to implement the electronic migration check module function verification method.

[0044] Compared with the prior art, the electronic migration inspection module functional verification method, computer equipment, medium, and program product provided by the present invention have the following beneficial effects:

[0045] 1. In the method for verifying the function of an e-migration checking module provided in this embodiment of the invention, a design layout is first provided, and some circuit units are selected to form a feature layout. A first number of initial test cases are obtained from different feature layouts, and then the initial test cases are filtered to obtain a smaller number of test cases. This filtering process can significantly reduce the verification time required to verify the accuracy of the e-migration rule checking module function. Furthermore, multiple test condition parameters are generated based on e-migration rules, resulting in a wider coverage of test conditions. Then, the test cases are combined with each test condition parameter to obtain multiple test case sets. These test case sets can be directly input into the e-migration rule checking module for execution, and the execution results are output. Finally, the execution results are directly compared with the standard output results to determine whether the e-migration rule checking module function is accurate, which is simple and convenient.

[0046] 2. The feature layouts in this embodiment include normal layouts and abnormal layouts. Normal layouts include layouts with multiple lines connected and vias, layouts with multiple lines connected and interrupted, layouts with multiple lines connected in T-shapes, layouts with line connections at ports, layouts with pins within line connection base units, and layouts with lines of varying widths. Abnormal layouts include empty layouts, layouts with cells but lacking routing information, and layouts with open and closed lines. The feature layouts in this embodiment are diverse, covering most physical shape patterns that are prone to errors when the electron migration rule checking module functions.

[0047] 3. The combination of feature maps in embodiments of the present invention includes:

[0048] Each feature map is combined with other feature maps to construct a factor table;

[0049] Initial use cases that remove combinations with outliers from the factor table are generated, and a first number of initial use cases are generated.

[0050] The combination of abnormal cases is the initial use case formed by combining normal and abnormal layouts. The factor table can quickly remove combinations containing abnormal cases, and the operation is intuitive and simple.

[0051] 4. The initial use case screening in this embodiment of the invention includes:

[0052] The initial test cases are filtered using an orthogonal array method to obtain a second number of test cases;

[0053] The orthogonal array method is as follows:

[0054] ;

[0055] In the formula, n represents the minimum number of test cases, and s represents the number of feature maps. This represents the number of level factors under the i-th influencing factor, where =2. The orthogonal array method significantly reduces the verification time required to verify the accuracy of the electronic migration rule checking module.

[0056] 5. The embodiments of the present invention generate multiple test condition parameters based on electron migration rules, including:

[0057] Electromigration rules include the maximum effective current rule, the maximum average current rule, and the maximum peak current rule;

[0058] The maximum current RMS value rule generates the first test condition parameters based on the equivalence class partitioning method;

[0059] The maximum average current rule generates the second test condition parameters based on the equivalence class partitioning method;

[0060] The maximum peak current rule generates the third test condition parameters based on the equivalence class partitioning method;

[0061] The number of first test condition parameters < the number of second test condition parameters < the number of third test condition parameters. Different numbers of test condition parameters are generated based on different electronic migration rules, and different test condition parameters can improve the reliability of verifying the accuracy of electronic migration rule checks.

[0062] 6. In this embodiment of the invention, the test cases are combined with each test condition parameter, including:

[0063] The test cases are combined with the first test condition parameters and filtered using a preset method to form the first test case set;

[0064] The test cases are combined with the second test condition parameters and filtered using a preset method to form the second test case set;

[0065] The test cases are combined with the third test condition parameters and filtered using a preset method to form a third test case set.

[0066] The test case sets include a first test case set, a second test case set, and a third test case set, and the content of each of these three test case sets is different. When verifying the accuracy of the e-migration rule check, the three test case sets effectively cover various error scenarios that may occur in the e-migration rule check module, achieving comprehensive coverage.

[0067] 7. In this embodiment of the invention, the running results are compared with the standard output results to verify the accuracy of the electronic migration check module's function, including:

[0068] The running results are compared with the standard output results, and the error value of the comparison is obtained;

[0069] Determine whether the error value meets the preset range;

[0070] If so, it indicates that the electronic migration check module is functioning correctly;

[0071] If not, it indicates that the sub-migration check function is inaccurate. The verification is highly efficient and simple to operate.

[0072] 8. The present invention also provides a computer program product that has the same beneficial effects as the above-described method for verifying the function of an electronic migration check module, and will not be described in detail here.

[0073] 9. The present invention also provides a computer-readable storage medium, which has the same beneficial effects as the above-described method for verifying the function of an electronic migration check module, and will not be described in detail here.

[0074] 10. This invention also provides a computer device that has the same beneficial effects as the above-described method for verifying the function of an electronic migration inspection module, and will not be described in detail here. [Attached Image Description]

[0076] Figure 1 This is a flowchart illustrating the electronic migration check module function verification method provided in the first embodiment of the present invention.

[0077] Figure 2a This is a schematic diagram of the structure of the initial use case formed by combining the feature layouts provided by the present invention. Figure 1 .

[0078] Figure 2b This is a schematic diagram of the structure of the initial use case formed by combining the feature layouts provided by the present invention.

[0079] Figure 2c This is a schematic diagram of the structure of the initial use case formed by combining the feature layouts provided by the present invention.

[0080] Figure 3a This invention provides a layout design for the VVS threshold current scenario. Figure 1 .

[0081] Figure 3b This is the second layout design diagram for the VVS threshold current scenario provided by the present invention.

[0082] Figure 4a This is a schematic diagram of via stacking under the superimposed via shape provided by the present invention. Figure 1 .

[0083] Figure 4b This is a schematic diagram of the via stacking under the superimposed via shape provided by the present invention.

[0084] Figure 4c This is a schematic diagram of via stacking under the superimposed via shape provided by the present invention.

[0085] Figure 5 This is a schematic diagram illustrating the process of combining test cases with each test condition parameter in the first embodiment of the present invention.

[0086] Figure 6 This is a schematic diagram of the structure of the computer program product provided in the second embodiment of the present invention.

[0087] Figure 7 This is a schematic diagram of the structure of a computer-readable storage medium provided in the third embodiment of the present invention.

[0088] Figure 8 This is a schematic diagram of the structure of the computer device provided in the fourth embodiment of the present invention.

Detailed Implementation Methods

[0090] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0091] In the embodiments provided by this invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0092] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also recognize that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to the invention.

[0093] In various embodiments of the present invention, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0094] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It is particularly important to note that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0095] Electromigration (EM) refers to the migration of metal atoms in a metal conductor under high-density current, leading to problems such as conductor deformation and increased heat generation. This phenomenon becomes increasingly pronounced with advanced manufacturing processes, significantly negatively impacting the performance, reliability, and lifespan of integrated circuits. Therefore, Electronic Design Automation (EDA) software needs to include EM detection capabilities.

[0096] Electromigration rules refer to specified constraints under variable factors, such as the effects of current or temperature. Circuit designs provided by designers typically need to meet electromigration rules, therefore, electromigration rule checking tests are usually performed on the designed circuits. Electromigration rule checking is part of the physical verification of integrated circuit designs. It mainly uses an electromigration rule checking module to check the designed circuit, and its main purpose is to ensure that the drawn layout is completely consistent with the designed circuit. Before using the function of the electromigration rule checking module, its accuracy must be verified. Design layouts are composed of individual circuit units. A small-scale design layout can contain tens of thousands of circuit units. Taking a small-scale design with 400,000 units as an example, in current technology, verifying the function of the electromigration rule checking module using a small-scale design layout takes about 30 minutes, and the complex layout and routing in the layout during result analysis can interfere with the determination of the cause of problems, which is very inconvenient. Therefore, using existing verification techniques to test and verify the EM (Electromigration Rule Check) function is very inefficient.

[0097] Please see Figure 1 The first embodiment of the present invention provides a method for verifying the function of an electronic migration check module, used to verify the accuracy of the function of the electronic migration check module, including the following steps:

[0098] S1 provides a design layout, selects some circuit units to form a feature layout, and combines at least two different feature layouts to obtain a first number of initial use cases;

[0099] S2, filter the initial test cases to obtain a second number of test cases, where the first number is greater than the second number;

[0100] S3 provides e-migration rules and generates multiple test condition parameters based on these rules.

[0101] S4 combines the test cases with each test condition parameter to obtain multiple test case sets;

[0102] S5 provides standard output results, runs test case sets based on the electronic migration check module, and obtains the results.

[0103] S6 compares the running results with the standard output results to verify the accuracy of the electronic migration check module's function.

[0104] Understandably, existing methods require a significant amount of time to verify the accuracy of the e-migration rule checking module. In this embodiment, a design layout is first provided, and a subset of circuit units are selected to form a feature layout. The feature layout refers to a layout selected by the designer based on experience from the design layout, characterized by its simple structure. The e-migration rule checking module primarily checks the design layout, which may contain a vast number of circuit structures. These circuit structures are composed of small circuit units, referred to as physical shapes. During e-migration rule checking, smaller circuit units in the design layout are often more prone to errors. Therefore, designers use experience to design these smaller circuit units into feature layouts. Feature layouts inherently possess a characteristic: when the e-migration rule checking module runs on a feature layout, errors are more likely to occur. In other words, a feature layout is a layout composed of small circuit units on the design layout that are more prone to errors during the e-migration rule checking process. For example, the number of circuit units in a feature layout does not exceed 100.

[0105] Furthermore, at least two different feature layouts can be combined to obtain a first number of initial test cases. It should be understood that errors occurring during the e-migration rule checking process are random. Therefore, after providing a well-designed feature layout, at least two different feature layouts are combined. This combination is random. The combined initial test cases represent the presence of at least two different feature layouts internally. Further, the initial test cases are filtered to obtain a second number of test cases, reducing the number of initial test cases from a large number. For example, assuming *a* feature layouts are provided, combining these *a* feature layouts to generate initial test cases will produce fewer than *a*^a* initial test cases, which is excessively large. Although the initial test cases represent multiple small physical shapes combined together, directly using the initial test cases to verify the accuracy of the e-migration rule checking module's function will require less verification time than using a small-scale design to verify the accuracy of the e-migration rule checking module's function. In this embodiment, the initial test cases are filtered to obtain a second number of test cases. The number of test cases obtained after filtering *a*^a* initial test cases will be drastically reduced. Therefore, the verification time required to verify the accuracy of the electronic migration rule checking module will be significantly reduced.

[0106] Specifically, in step S4 above, it should be understood that the test cases and initial test cases are the same, both referring to a set of at least two different feature layouts, that is, the content within a test case is a set of physical shapes of multiple designs. However, the test condition parameters differ from the test cases. For example, test condition parameters can be considered as parameters such as ambient temperature or current density on small circuit units within a test case. Therefore, by combining each test case with each test condition parameter, multiple test case sets can be obtained.

[0107] Furthermore, in steps S5 and S6 above, it should be understood that the test case set can be considered as a collection of test conditions paired with physical shapes. When it is necessary to verify the accuracy of the e-migration rule checking module's function, the test case set can be used as input values. Inputting these input values ​​into the module responsible for e-migration rule checking will yield a result. To determine whether the e-migration rule checking module's function is accurate based on the result, simply compare the result with the standard output. If the comparison result matches expectations, the e-migration rule checking module's function is considered accurate. The judgment process is simple and convenient.

[0108] It should be understood that this invention differs from the traditional method of providing a small-scale design layout to verify the accuracy of the e-migration rule checking module. In this embodiment, a design layout is first provided, and a portion of the circuit units are selected to form a feature layout. The feature layout represents the physical shape of the specific circuit design that is prone to errors during e-migration rule checking. Furthermore, a first number of initial test cases are obtained from different feature layouts, and these initial test cases are then filtered to obtain a smaller number of test cases. This filtering process significantly reduces the verification time required to verify the accuracy of the e-migration rule checking module. Further, multiple test condition parameters are generated based on e-migration rules, resulting in a broad coverage of test conditions. The test cases are then combined with each test condition parameter to obtain multiple test case sets. These test case sets can be directly input into the e-migration rule checking module for execution, and the execution results are output. Finally, the accuracy of the e-migration rule checking module's function can be determined by directly comparing the execution results with the standard output results, which is simple and convenient.

[0109] Specifically, the feature layout includes normal layout and abnormal layout; normal layout includes layout with multiple lines connected and vias, layout with multiple lines connected and interrupted, layout with multiple lines connected in T-shapes, layout with lines connected to ports, layout with lines connected to pins within basic cells, and layout with lines of varying widths; abnormal layout includes empty layout, layout with cells but lacking routing information, and layout with lines that are open or closed.

[0110] Please combine them together Figures 2a-2c , Figures 2a-2cThis represents a structural diagram illustrating the combination of several feature layouts to form an initial use case. Understandably, the style of the feature layouts is derived from the designer's practical experience. For example, a via-containing layout refers to a layout containing vias; its specific style can be found in [reference needed]. Figure 2a The via 2h1 in the diagram. A multi-line connection with breakpoints refers to a layout where multiple lines are connected and there are breakpoints between the lines. For specific examples, please refer to [reference needed]. Figure 2b The breakpoint is 2d1. A multi-line T-connection layout refers to a layout where two lines are connected to form a T-connection structure. For specific examples, please refer to [reference needed]. Figure 2a The T-type connection structure 2a1 in the diagram. A line connection port layout refers to a layout where lines and ports on cells are connected; this type of feature... Figure 1 In general, if lines and cells exist in a layout, there must be ports on those lines and cells for connection. For specific examples, please refer to [reference needed]. Figure 2a The line in the diagram connects to port 2p1 on the cell. A line-connected pin layout within a basic cell refers to a layout where a line connects to a pin in the cell. Typically, in this type of layout, there is no port on the cell; instead, the line directly connects to the cell pin. The specific style is not shown in the attached diagram. A variable-width line layout refers to a layout where a line suddenly changes from narrow to wide. The specific style can be seen in Figure c, specifically in the structure 2b1 where the line suddenly changes from narrow to wide.

[0111] Furthermore, the aforementioned feature layouts are all normal layouts, while the following three types of feature layouts are abnormal layouts. That is, the eMigration rule checking module function must accurately detect both normal and abnormal layouts. The three types of abnormal layouts are: empty layouts, layouts containing cells but lacking routing information, and layouts with open / closed lines. An empty layout refers to a layout lacking any physical shape, i.e., a missing structure. A layout containing cells but lacking routing information refers to a layout containing cells, but lacking connections between cells. A layout with open / closed lines refers to a layout containing cells and their routing information, but the actual data read by the eMigration rule checking module function does not display the routing information present in the layout.

[0112] Understandably, the feature layouts in this implementation are diverse, covering most of the physical shape patterns that are prone to errors when the e-migration rule checking module functions. Therefore, combining at least two different feature layouts can completely cover the error-prone situations when the e-migration rule checking module functions. Furthermore, providing feature layouts for verification testing is more targeted. Traditional testing methods often perform numerous repetitive tests on single test points, while covering less common layout shapes in some backend designs, making it difficult to expose program defects immediately. For example, layouts with vias in the middle of multiple lines are very common, leading to frequent test execution of such test points; while layouts with variable-width lines are usually less common in traditional testing, making them easy to miss during testing.

[0113] Specifically, in step S4 above, combining the feature maps includes:

[0114] Each feature map is combined with other feature maps to construct a factor table;

[0115] Initial use cases that remove combinations with outliers from the factor table are generated, and a first number of initial use cases are generated.

[0116] Among them, the combination of abnormal situations is the initial use case composed of the combination of normal layout and abnormal layout.

[0117] It should be understood that when generating initial use cases, assuming nine feature layouts are provided, combining these nine feature layouts to generate initial use cases will produce 2^9 = 512 initial use cases, which is an excessively large number. However, some layouts with abnormal conditions may exist in the initial use cases. Abnormal layouts refer to initial use cases formed by combining normal layouts and abnormal layouts. For example, an initial use case may consist of an empty layout and a layout with multiple lines connected and vias. Since this initial use case already contains an incorrect empty layout, combining other normal layouts with the empty layout is meaningless. Therefore, when generating the first number of initial use cases, it is often necessary to remove combinations with abnormal conditions like the one described above to obtain the first number of initial use cases. That is, theoretically, 2^9 = 512 initial use cases will be generated, but after removing combinations with abnormal conditions, there will still be approximately 100 or more initial use cases.

[0118] Table 1 Initial Use Case Factors Table:

[0119]

[0120] It should be understood that Table 1 is a factor table constructed by combining each feature layout with other feature layouts. A '1' in the table indicates that the initial use case contains that layout feature, and a '0' indicates that the initial use case does not contain that layout feature. Table 1 clearly shows which feature layouts are used to combine each initial use case. Table 1 will generate 2^9 = 512 initial use cases. The factor table also allows for faster removal of combinations with abnormal conditions. For example, in the column for initial use case 512, there is an initial use case combining a line connection port layout and an empty layout. Since this combination is abnormal, it can be quickly removed using the factor table when generating the first number of initial use cases, making the operation intuitive and simple.

[0121] Furthermore, in step S2 above, the initial use case screening includes:

[0122] The initial test cases are filtered using an orthogonal array method to obtain a second number of test cases;

[0123] The orthogonal array method is as follows:

[0124] ;

[0125] In the formula, n represents the minimum number of test cases, and s represents the number of influencing factors. Specifically, s represents the number of feature maps. This represents the number of level factors under the i-th influencing factor, where in this embodiment... =2.

[0126] It should be understood that, in order to further reduce the number of test cases that need to be built and increase the value of a single test case, this embodiment uses the orthogonal array method to filter the first number of initial test cases into a second number of test cases. Specifically, the orthogonal array method has been widely used in the fields of software testing and quality control and has achieved good results. This method has the following advantages: it can improve the efficiency of test case execution, significantly reduce the number of test cases, and cover various combinations of factors during e-migration rule checks; it provides a systematic and structured method for generating test cases, avoiding duplication and omissions among test cases; it can perform balanced testing, as the test cases generated by the orthogonal array can be evenly distributed across all possible factor combinations, reducing result bias; and it simplifies the test case result analysis process, making it easy to identify key factors affecting the results through statistical analysis.

[0127] Understandably, this embodiment, while ensuring that the test cases can cover errors that are prone to occur during e-migration rule checks, significantly reduces the verification time required to verify the accuracy of the e-migration rule check module by screening the initial test cases.

[0128] For example, if nine feature maps are provided, and the orthogonal array method is used for filtering, the value of s is 9. =2. Therefore, n=10. That is, the minimum number of test cases is 10.

[0129] Furthermore, after obtaining the second number of test cases, the number of test cases can be increased based on experience to obtain a third number of test cases, where the third number is greater than the second number. It should be understood that if the designer needs to increase the number of test cases based on experience, they can do so directly according to their own choice, offering a high degree of flexibility.

[0130] Table 2 Test Case Factor Table:

[0131]

[0132] It should be understood that Table 2 shows the 10 test cases obtained after screening using the orthogonal array method. Test cases 11-13 are the number of test cases added by the designer based on experience. In the table, 1 indicates that the test case contains the layout feature, and 0 indicates that the test case does not contain the layout feature. It can be seen that the initial number of test cases is approximately 100. After screening using the orthogonal array method, 10 test cases are obtained. Three more can be added based on the designer's experience, ultimately forming 13 test cases. These 13 test cases can cover various combinations of factors during e-migration rule checking, thus significantly reducing the verification time required to verify the accuracy of the e-migration rule checking module in subsequent verification processes.

[0133] Furthermore, please combine Figure 1 and Figure 5 Multiple test condition parameters are generated based on electronic migration rules, including:

[0134] Electromigration rules include the maximum effective current rule, the maximum average current rule, and the maximum peak current rule;

[0135] The maximum current RMS value rule generates the first test condition parameters based on the equivalence class partitioning method;

[0136] The maximum average current rule generates the second test condition parameters based on the equivalence class partitioning method;

[0137] The maximum peak current rule generates the third test condition parameters based on the equivalence class partitioning method;

[0138] The number of parameters in the first test condition is less than the number of parameters in the second test condition, which in turn is less than the number of parameters in the third test condition.

[0139] Understandably, electromigration is a crucial consideration in integrated circuit design, especially with the continuous shrinking of feature sizes. Electromigration primarily occurs on metal interconnects, where metal atoms migrate due to factors such as current density and temperature gradients, potentially leading to circuit performance degradation or failure. Therefore, the purpose of establishing electromigration rules is to prevent and mitigate the impact of electromigration on integrated circuit performance. In integrated circuit design, electromigration rules specifically refer to a method for analyzing electromigration in integrated circuits, aiming to ensure the performance and reliability of integrated circuits.

[0140] In the first implementation method, the first test condition parameters are generated based on the maximum current RMS value rule, which needs to consider the ambient temperature configuration, metal trace density, and VVS (Via-Via spacing) threshold current. For example, the ambient temperature is a continuous variable, and the temperature input can be divided into four types of parameters using the equivalence class partitioning method. For instance, a continuous temperature variable can be divided into four inputs: a temperature equal to 110℃ as one parameter, a temperature less than 110℃ but greater than or equal to 85℃ as another parameter, a temperature greater than 110℃ but less than 150℃ as another parameter, and a temperature greater than 150℃ as yet another parameter. The metal trace density is determined by looking up the corresponding coefficient in a table based on the number of metal lines surrounding the metal layer trace to be analyzed. Similar to the temperature condition parameters, it can also be divided into four types of parameters. VVS includes the following two cases. Please refer to [link / reference]. Figure 3a One type is a concave layout design, where the lines have vias 3h1 and 3h2 at both ends. Please refer to [link / reference]. Figure 3b Another approach is a T-shaped layout design, where the outer ends of the T-shape have vias 3h3, 3h4, and 3h5. Since VVS and metal trace density are correlated, and neither is correlated with temperature, the number of first test condition parameters obtained from the combination of VVS and metal trace density is 2 × 4 = 8. Ambient temperature is configured as 4 first test condition parameters. Finally, there will be a set of overlapping test conditions related to ambient temperature and metal density. Therefore, the number of first test condition parameters generated based on the maximum current effective value rule will be 4 + 4 * 2 - 1 = 11.

[0141] In the second implementation method, the second test condition parameters are generated based on the maximum average current rule. This requires considering ambient temperature configuration, metal trace density, VVS (Via-Via spacing) threshold current, and stacked via shape current threshold. In this embodiment, the number of second test condition parameters generated from the ambient temperature configuration, metal trace density, and VVS threshold current, which are related to the maximum current effective value rule, is the same as the number of first test condition parameters generated in the first implementation method: 4 + 4 * 2 - 1 = 11. This will not be elaborated further. In the maximum average current rule, stacked via shape refers to vias in two adjacent layers being exactly in the same position, causing the two vias to overlap in the top view direction. This situation can be further subdivided into three characteristic test conditions. Please participate. Figure 4a , Figure 4a This demonstrates the case where adjacent vias 4h1 and 4h2 do not overlap. Please participate as well. Figure 4b , Figure 4b This demonstrates a partial overlap between two adjacent vias, 4h1 and 4h2. Please participate as well. Figure 4c , Figure 4c The example demonstrates the case where two adjacent vias, 4h1 and 4h2, completely overlap. This means that the number of second test condition parameters obtained by superimposing the via shape current threshold is 3. However, there will be a set of overlapping test conditions related to ambient temperature and those related to the superimposed via shape current threshold. Therefore, the number of second test condition parameters generated based on the maximum average current rule will be 11 + 3 - 1 = 13.

[0142] As a third implementation method, generating third test condition parameters based on the maximum peak current rule requires considering ambient temperature configuration, metal trace density, VVS (Via-Via spacing) threshold current, current duty cycle, and period. The number of third test condition parameters generated from the ambient temperature configuration, metal trace density, and VVS threshold current, which are related to the maximum current effective value rule, is the same as the number of first test condition parameters generated in the first implementation method: 4 + 4 * 2 - 1 = 11. This will not be elaborated further. The current duty cycle and period, like the ambient temperature configuration, are continuous variables. Therefore, they also require the use of the equivalent value classification method to generate the corresponding third test condition parameters. Specifically, according to existing process manuals and the equivalent value classification method, each metal layer can be given 7 combinations of current duty cycle and period. Since the current duty cycle and period are independent of the factors in the test case, the duty cycle-period combinations between different metal layers no longer need to be combined. That is, 7 third test condition parameters can ultimately be generated. However, the test conditions related to ambient temperature, current duty cycle, and cycle will also have a set of repeated test conditions. The number of third test condition parameters generated based on the maximum peak current rule is 11 + 7 - 1 = 17.

[0143] It should be understood that in this embodiment, the number of first test condition parameters is less than the number of second test condition parameters, which is less than the number of third test condition parameters. Different numbers of test condition parameters are generated based on different electronic migration rules, and different test condition parameters can improve the reliability of the functional accuracy of verifying electronic migration rule checks.

[0144] Furthermore, combining test cases with each test condition parameter includes:

[0145] The test cases are combined with the first test condition parameters and filtered using a preset method to form the first test case set;

[0146] The test cases are combined with the second test condition parameters and filtered using a preset method to form the second test case set;

[0147] The test cases are combined with the third test condition parameters and filtered using a preset method to form a third test case set.

[0148] The test case set includes a first test case set, a second test case set, and a third test case set, and the contents of the first test case set, the second test case set, and the third test case set are all different.

[0149] Understandably, the default method is the Boundary Value Combination (BC) method. BC is a test case design method in software testing, primarily used to test boundary value cases within the input domain. The general steps of BC are: First, understand the input domain and boundary values: Determine the input parameters to be tested and their value ranges. Determine the boundary values ​​for each input parameter, including the minimum, maximum, and intermediate values ​​close to the boundary. Second, divide into equivalence classes: For each input parameter, divide into equivalence classes based on its value range. An equivalence class is a set of input values ​​that have the same test result. Typically, this is divided into valid equivalence classes (valid values), invalid equivalence classes (invalid values), and boundary values. Then, generate boundary value test cases: For each input parameter, select its boundary values ​​for testing. Boundary values ​​are values ​​that fall on the boundaries of equivalence classes. Finally, combine boundary values: For multiple input parameters, use the boundary value combination method to generate test cases. Select boundary values ​​of different input parameters to combine to cover multiple boundary cases.

[0150] For example, suppose there are two input parameters, x (test case) and y (test condition parameter), with the following values: x is 1 to 10; y is 20 to 30. First, determine the boundary values ​​of the test cases to be 1 and 10. The boundary values ​​of the test condition parameter are 20 and 30. Therefore, generate boundary value test cases: x is 1 and 10, y is 20 and 30. Finally, combining these, we can obtain four test case sets: (x=1, y=20); (x=1, y=30); (x=10, y=20); and (x=10, y=30).

[0151] In one implementation, if there are 13 test cases, the number of first test condition parameters will be 11. Then, the test cases and the first test condition parameters, after being combined and filtered using the BC combination method, will form a first test case set of 60-70. In another implementation, if there are 13 test cases, the number of second test condition parameters will be 13. Then, the test cases and the second test condition parameters, after being combined and filtered using the BC combination method, will form a second test case set of 70-90. In yet another implementation, if there are 13 test cases, the number of third test condition parameters will be 13. Then, the test cases and the third test condition parameters, after being combined and filtered using the BC combination method, will form a third test case set of 100-120.

[0152] Understandably, the three test case sets contain different test conditions, meaning that the results obtained when the e-migration rule checking module is used to run the three test case sets will be different. When verifying the accuracy of the e-migration rule checking, the three test case sets effectively cover various error scenarios that the e-migration rule checking module may encounter, achieving comprehensive coverage and improving the reliability of verifying the functional accuracy of the e-migration rule checking.

[0153] Furthermore, in step S5 above, the running results are compared with the standard output results to verify the accuracy of the electronic migration check module's function, including:

[0154] S51 compares the running results with the standard output results and obtains the comparison error value;

[0155] S52, determine whether the error value meets the preset range;

[0156] S53, if yes, it indicates that the electronic migration check module is functioning correctly;

[0157] S54. If not, it indicates that the sub-migration check function is inaccurate.

[0158] It should be understood that the standard output result refers to a standard output result stored in text after calculation based on expert experience or benchmarks for a test case set. In essence, the standard output result is a standard answer for running the test case set using the e-migration rule checking module. In practice, users need to verify the accuracy of the e-migration rule checking module each time they use it before using it to test design layouts. Therefore, to determine the accuracy of the e-migration rule checking module, simply run the test case set based on it and obtain the results. If the error value obtained after comparing the running result with the standard output result falls within the preset range, it indicates that the e-migration rule checking module is accurate, meaning users can directly use it to test other design layouts. Conversely, if the error value falls outside the preset range (e.g., -1 to 1), it indicates that the e-migration rule checking module is accurate, has high verification efficiency, and is easy to operate. It should be noted that the preset range in this embodiment is set according to the designer's actual needs, and the specific setting value is not specifically limited.

[0159] It should be understood that the electronic migration check module functional verification method provided in this embodiment has a faster testing speed. Traditional testing methods often involve complex back-end designs, with the number of circuits and pins ranging from hundreds of thousands to millions, or even higher, resulting in lengthy processes such as test condition setting and test execution. In contrast, the number of test cases in this invention is very small, and the physical size of the test case set is also very small. The number of lines is far less than the number of wirings in the small-scale design layout of traditional testing methods, thereby significantly shortening the verification time required to verify the accuracy of the electronic migration rule check module function.

[0160] Please see Figure 6 The second embodiment of the present invention also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the above-described electronic migration check module function verification method.

[0161] Please see Figure 7 The computer program product provided by this invention has the same beneficial effects as the above-mentioned method for verifying the function of an electronic migration inspection module, and will not be elaborated here.

[0162] The third embodiment of the present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, the computer instructions being used to cause the computer to execute the above-described electronic migration check module function verification method.

[0163] It should be noted that a computer-readable storage medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium can be a machine-readable signal medium or a machine-readable storage medium. A computer-readable storage medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of computer-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0164] The computer-readable storage medium provided by this invention has the same beneficial effects as the above-described method for verifying the functionality of an electronic migration check module, and will not be elaborated here.

[0165] Please see Figure 8 The fourth embodiment of the present invention also provides a computer device applied to the above-described electronic migration check module function verification method, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the above-described computer program to implement the electronic migration check module function verification method.

[0166] The computer device provided by this invention has the same beneficial effects as the above-described method for verifying the function of an electronic migration inspection module, and will not be elaborated upon here.

[0167] The foregoing has provided a detailed description of an electronic migration inspection module functional verification method, computer equipment, medium, and program product disclosed in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention. Any modifications, equivalent substitutions, and improvements made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for verifying the functionality of an electronic migration check module, used to verify the accuracy of the electronic migration check module's functionality, characterized in that: Includes the following steps: Provide a design layout, which is composed of multiple circuit units. Select some circuit units to form a feature layout. Combine at least two different feature layouts to obtain a first number of initial use cases. The initial test cases are filtered to obtain a second number of test cases, where the first number is greater than the second number; Electromigration rules are provided, including maximum current RMS rules, maximum average current rules, and maximum peak current rules. Based on the electron migration rules, multiple test condition parameters are generated using the equivalence class partitioning method. The test cases are combined with each test condition parameter to obtain multiple test case sets; It provides standard output results, runs test case sets based on the e-migration check module, and obtains the results. The results were compared with the standard output to verify the accuracy of the electronic migration check module.

2. The method for verifying the functionality of the electronic migration check module as described in claim 1, characterized in that: The feature map includes normal maps and abnormal maps; Normal layouts include multi-line connections with vias, multi-line connections with breakpoints, multi-line T-connections, line-connected port layouts, pin layouts within line-connected base cells, and variable-width line layouts. Abnormal layouts include empty layouts, layouts with cells but lacking routing information, and layouts with open and closed lines.

3. The method for verifying the functionality of the electronic migration check module as described in claim 2, characterized in that: Combining feature maps includes: Each feature map is combined with other feature maps to construct a factor table; Initial use cases that remove combinations with outliers from the factor table are generated, and a first number of initial use cases are generated. Among them, the combination of abnormal situations is the initial use case composed of the combination of normal layout and abnormal layout.

4. The method for verifying the functionality of the electronic migration check module as described in claim 3, characterized in that: The initial use case screening includes: The initial test cases are filtered using an orthogonal array method to obtain a second number of test cases; The orthogonal array method is as follows: ； In the formula, n represents the minimum number of test cases, and s represents the number of feature maps. This represents the number of level factors under the i-th influencing factor, where =2.

5. The method for verifying the functionality of the electronic migration check module as described in claim 4, characterized in that: Multiple test condition parameters are generated based on electronic migration rules, including: Electromigration rules include the maximum effective current rule, the maximum average current rule, and the maximum peak current rule; The maximum current RMS value rule generates the first test condition parameters based on the equivalence class partitioning method; The maximum average current rule generates the second test condition parameters based on the equivalence class partitioning method; The maximum peak current rule generates the third test condition parameters based on the equivalence class partitioning method; The number of parameters in the first test condition is less than the number of parameters in the second test condition, which in turn is less than the number of parameters in the third test condition.

6. The method for verifying the functionality of the electronic migration check module as described in claim 5, characterized in that: Combining test cases with each test condition parameter includes: The test cases are combined with the first test condition parameters and filtered using a preset method to form the first test case set; The test cases are combined with the second test condition parameters and filtered using a preset method to form the second test case set; The test cases are combined with the third test condition parameters and filtered using a preset method to form a third test case set. The test case set includes a first test case set, a second test case set, and a third test case set, and the contents of the first test case set, the second test case set, and the third test case set are all different.

7. The method for verifying the functionality of the electronic migration check module as described in claim 1, characterized in that: The results of the operation are compared with the standard output to verify the accuracy of the electronic migration check module's function, including: The running results are compared with the standard output results, and the error value of the comparison is obtained; Determine whether the error value meets the preset range; If so, it indicates that the electronic migration check module is functioning correctly; If not, it indicates that the sub-migration check function is inaccurate.

8. A computer program product comprising a computer program / instructions, characterized in that: When the computer program / instruction is executed by the processor, it implements the electronic migration check module functional verification method as described in any one of claims 1 to 7.

9. A computer-readable storage medium, wherein, The computer-readable storage medium stores computer instructions for causing the computer to execute the electronic migration check module function verification method according to any one of claims 1 to 7.

10. A computer device, applied to the electronic migration check module functional verification method as described in any one of claims 1 to 7, characterized in that: The system includes a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the electronic migration check module functional verification method.

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