A memory read method

Abstract

The application discloses a reading method of a novel memory and belongs to the technical field of semiconductor and CMOS hybrid integrated circuits. The novel memory is a nonvolatile memory, which comprises a CMOS transistor and a resistive random access memory (RRAM). The bottom electrode of the RRAM is connected with the drain end of the CMOS transistor. The RRAM is a four-terminal operating device. The reading operation of the novel memory specifically comprises the following steps: 1) performing the device electrical initialization (FORMING) and setting (SET) steps at the drain end (BL) of the transistor, and performing the resetting (RESET) operation at the source end (SL) of the transistor; and 2) controlling the gate of the transistor to apply an opening voltage, applying a reading voltage Vread at the SL end, and reading the current at the BL end. The application adopts the reading scheme in the same direction as the RESET, improves the current difference window on the premise of adopting a large reading voltage, and effectively suppresses the reading interference.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor and CMOS hybrid integrated circuit technology, and specifically relates to a method for reading memory. Background Technology

[0002] With the advent of the intelligent era, the volume of data has surged, highlighting the limitations of the traditional von Neumann computing architecture, especially its inherent separation of access and computation, and the speed mismatch of traditional structures. Faced with these challenges, industry has been forced to explore innovative solutions, including developing high-efficiency embedded storage and non-volatile devices that integrate storage and computation, aiming to improve storage efficiency and significantly reduce the latency required for data transmission. Against this backdrop, memristor technology, particularly in embedded storage applications and deep neural network construction, has become a research focus due to its compatibility with current CMOS processes, simplified manufacturing processes, potential for high-density integration, and low-power, high-efficiency performance in performing complex neural network tasks.

[0003] Resistive random access memory (RRAM) has gained widespread industry favor among various memristor technologies due to its advantages such as simple structure, high efficiency, fast read / write speeds, and multi-bit storage capabilities. Oxygen-vacancy RRAM (OxRRAM), in particular, facilitates the orderly migration of oxygen vacancies through low operating voltage, thereby achieving a change in resistance state. It supports multi-bit storage and ensures the device is in the correct resistance state through precise current control. Changes in the device's resistance value are primarily achieved through SET and RESET operations.

[0004] To achieve high-density integration while reducing the impact of crosstalk current, RRAM devices commonly employ a cross-array structure. However, passive cross-arrays are susceptible to crosstalk current, potentially leading to read / write errors and performance degradation. To address this issue, researchers have proposed introducing selector elements into the array, such as 1T1R, 1D1R, and 1S1R structures. The 1T1R structure is widely adopted due to its mature transistor design and manufacturing process. Through transistor control, specific RRAM cells can be precisely selected and operated, and precise current control can be achieved using the transistor's transfer characteristics, ensuring that the RRAM cells reach the correct resistance state. This method not only improves operational accuracy but also optimizes the overall performance and reliability of the device.

[0005] For applications, whether embedded storage or in-memory computing, devices require high current difference / high switching ratio and the ability to perform multiple (>1E9) reads. For a 1T1R structure, the traditional read scheme uses the BL terminal for reading. However, the current difference is positively correlated with the read voltage. A high read voltage leads to a high current difference, but it also introduces read interference.

[0006] In recent years, the academic community has attempted various control methods to implement diverse operations on the 1T1R to suppress read interference. These methods include introducing peripheral circuitry to periodically refresh the resistance value, or using higher-precision sensitive amplifiers to reduce the current difference threshold, ultimately lowering the read voltage. While mitigating read interference, these approaches come at a significant cost. These issues pose challenges to the large-scale integration and commercialization of memory devices. Summary of the Invention

[0007] This invention provides a method for reading a memory. By adopting a reading scheme that is in the same direction as Reset, the current difference window is increased by ~3 times while using a large reading voltage, and reading interference is effectively suppressed.

[0008] The technical solution provided by this invention is as follows:

[0009] A method for reading a memory, wherein the memory is a non-volatile memory, the memory includes a CMOS transistor and a resistive random access memory (RRAM), the bottom electrode of the RRAM is connected to the drain terminal of the CMOS transistor, and the RRAM is a four-terminal operating device. The memory reading operation specifically includes the following steps:

[0010] 1) Perform the electrical initialization and set steps at the drain (BL) terminal of the transistor, and perform the reset operation at the source (SL) terminal of the transistor;

[0011] 2) Apply a turn-on voltage to the gate of the control transistor, apply a read voltage Vread to the SL terminal, and read the current at the BL terminal.

[0012] Furthermore, the gate voltage is applied in the range of 0.5 to 3 times the Vdd voltage.

[0013] Furthermore, the range of the applied read voltage is 0.2 to 0.8 times the set voltage (Vset), and the pulse width of the read voltage Vdd is applied from 1 to 10000 ns.

[0014] Furthermore, CMOS transistors are selective transistors, employing either planar transistors or FinFETs.

[0015] Furthermore, the resistive switching memory uses metal, metal nitride, or conductive metal oxide materials as electrode layers, and uses one or more layers of resistive switching materials as resistive switching layers. The single-layer resistive switching materials include AlOx, HfOx, TaOx, ZrOx, SiOx, VOx, MnOx, TiOx, CuOx, ZnOx, WOx, AgOx, SrTiOx, CaTiOx, ferroelectric tunnel junction (FTJ), P(VDF-TrFE) based ferroelectric polymer, HfO2 based materials (hafnium fluoride), PVDF and its copolymers, germanene, tinene and MoS2 single-layer two-dimensional materials, aluminum scandium nitrogen (AlScN) or organic materials, and combinations thereof. Each of the two or more layers of material includes one or a combination of AlOx, HfOx, TaOx, ZrOx, SiOx, VOx, MnOx, TiOx, CuOx, ZnOx, WOx, AgOx, SrTiOx, CaTiOx, or organic materials.

[0016] Compared with the prior art, the method of the present invention has the following beneficial effects:

[0017] In traditional methods, memory operations include: electrical initialization (Forming), set, and read operations all occurring on the same side, for example, all at the drain. The reset operation applies a positive voltage to the drain. Alternatively, an increased positive voltage is applied to the gate of the transistor, while the source and substrate share a common ground potential. In traditional read schemes, with the transistor turned on (positive voltage applied to the gate), a read voltage of 0.1~0.4V is applied to the drain, and current is read from the source. When the resistive switching memory (RSM) is in a high-resistance state, the conductive filament breaks, creating a gap around the top electrode. The positive voltage in the same direction as the set operation increases the local electric field at the gap, causing negatively charged oxygen ions to move towards the top electrode, and oxygen vacancies to cluster at the virtual electrode. The longitudinally growing conductive filament reduces the gap, increasing the electric field and creating positive feedback, ultimately accelerating resistance fluctuations and even state changes.

[0018] The present invention applies a positive voltage to the SL terminal to achieve reading, which has little impact on HRS. In the LRS state, the conductive wire of the device is fully formed, and its breakage is affected by both the electric field and Joule heating. Joule heating has a square relationship with voltage. Therefore, below the voltage threshold of conductive wire breakage, Joule heating will be dissipated through high thermal conductivity materials, thereby dynamically reducing the impact of resistance change. This allows the reading method from the SL terminal to use a higher reading voltage and achieve a high current window. Attached Figure Description

[0019] Figure 1This is a schematic diagram of the 1T1R connection method and reading method used in this invention;

[0020] Figure 2 This is a schematic diagram illustrating the voltage application signal and signal readout method in a specific embodiment of the present invention;

[0021] Figure 3 This invention addresses the effect of resistance changes after multiple reads. Detailed Implementation

[0022] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings.

[0023] This invention, by employing a reading scheme in the same direction as the Reset, increases the current difference window by approximately 3 times while maintaining a large reading voltage, and effectively suppresses read interference. For example... Figure 1 As shown, this invention takes a non-volatile memory 1T1R device as an example. The resistive random access memory uses an inert electrode material as the electrode layer and a tantalum base as the resistive switching layer. The bottom electrode of the resistive random access memory is connected to the drain terminal of the transistor. Forming and setting steps are performed at the drain (BL) terminal of the transistor, and a reset operation is performed at the source (SL) terminal. The transistor with selection function is a planar transistor or a FinFET.

[0024] refer to Figure 2 This invention controls the application of a turn-on voltage, for example, 0.5 to 3 times Vdd, to the gate of the control transistor; a read voltage Vdd, for example, 0.2 to 0.8 times the set voltage (Vset), is applied to the SL terminal; and the current is read at the BL terminal. For devices in a high-resistivity state, such as those with a current value <1 uA, applying the read voltage to the SL terminal in the same direction as the set voltage has a relatively small impact. Applying the read voltage from the SL terminal increases the device resistance Vgs, thus the transistor can effectively divide the voltage to avoid overshoot voltage causing resistance changes. Figure 3 As shown. In the LRS state, the device's conductive filament is fully formed, and its breakage is affected by both the electric field and Joule heating. Joule heating has a square relationship with the voltage. Therefore, below the voltage threshold for conductive filament breakage, Joule heating will be dissipated through high thermal conductivity materials, thereby dynamically reducing the impact of resistance changes. This allows for a higher read voltage to be used when reading from the SL terminal, achieving a high current window.

[0025] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Those skilled in the art can modify or make equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be determined by the claims.

Claims

1. A method for reading from a memory, characterized in that, This memory is a non-volatile memory, comprising a CMOS transistor and a resistive random access memory (RRAM). The bottom electrode of the RRAM is connected to the drain terminal of the CMOS transistor. The RRAM is a four-terminal operating device. The read operation of the memory specifically includes the following steps: 1) Perform the Forming and Set steps at the drain terminal BL of the CMOS transistor, and perform the Reset operation at the source terminal SL of the CMOS transistor; 2) Apply an enable voltage to the gate of the CMOS transistor, apply a read voltage Vread at the SL terminal that is in the same direction as Reset, and read the current at the BL terminal. The range of the gate voltage applied is 0.5 to 3 times Vdd voltage, the range of the read voltage is 0.2 to 0.8 times Vset, and the pulse width of the read voltage is 1 to 10000 ns. For the LRS state, the filament of the resistive random access memory remains intact.

2. The reading method as described in claim 1, characterized in that, The CMOS transistor is a selective transistor, and can be a planar transistor or a FinFET.

3. The reading method as described in claim 1, characterized in that, The resistive switching memory uses metal, metal nitride or conductive metal oxide material as electrode layer, and uses one layer or two or more layers of resistive switching material as resistive switching layer.

4. The reading method as described in claim 3, characterized in that, The monolayer resistive switching material includes one or a combination of AlOx, HfOx, TaOx, ZrOx, SiOx, VOx, MnOx, TiOx, CuOx, ZnOx, WOx, AgOx, SrTiOx, CaTiOx, ferroelectric tunnel junction (FTJ), P(VDF-TrFE) based ferroelectric polymer, HfO2 based material (hafnium fluoride), PVDF and its copolymers, germanene, tinene and MoS2 monolayer two-dimensional materials, aluminum scandium nitrogen (AlScN) or organic materials.

5. The reading method as described in claim 3, characterized in that, Each of the two or more layers of material includes one or a combination of AlOx, HfOx, TaOx, ZrOx, SiOx, VOx, MnOx, TiOx, CuOx, ZnOx, WOx, AgOx, SrTiOx, CaTiOx, or organic materials.

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