A package structure and a semiconductor structure

Abstract

The present disclosure provides a packaging structure and a semiconductor structure, wherein a surface of a packaging substrate is provided with a ball grid array, the ball grid array comprises a plurality of data ball grids, and the data ball grids are used for transmitting data signals; at most 2 data ball grids are allowed to be arranged continuously in a second direction; the second direction refers to a direction in which rows of the ball grid array extend.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor, and in particular, to a packaging structure and a semiconductor structure. BACKGROUND

[0002] At present, semiconductor chips (for example, dynamic random access memory DRAM) involve various types of input / output signals (for example, command / address signals, data signals, data strobe signals, etc.), which need to be packaged through ball grids. However, due to the different number of types of signals, the level change rule, and the different functions, the position arrangement mode of the corresponding ball grid will affect the performance of the chip. SUMMARY

[0003] The present disclosure provides a packaging structure and a semiconductor structure.

[0004] The technical solution of the present disclosure is implemented as follows:

[0005] In a first aspect, the present disclosure provides a packaging structure, comprising a packaging substrate, a surface of the packaging substrate is provided with a ball grid array, the ball grid array comprises a plurality of data ball grids, and the data ball grids are used for transmitting data signals; at most 2 data ball grids are allowed to be arranged continuously in a second direction; the second direction refers to a row extension direction of the ball grid array.

[0006] In some embodiments, for a first part of the data ball grids, the data ball grids are located at an edge row and a non-edge column of the ball grid array, and any data ball grid of the first part is not linearly adjacent to other data ball grids; for a second part of the data ball grids, the data ball grids are located at a non-edge row and a non-edge column of the ball grid array, and every 2 data ball grids of the second part are adjacent in the second direction; wherein, only one row of the data ball grids is distributed in any adjacent 2 rows of the ball grid array.

[0007] In some embodiments, the ball grid array further comprises a plurality of command / address ball grids, the command / address ball grids are used for transmitting command / address signals; for a first part of the command / address ball grids, the command / address ball grids are located at an edge row and a non-edge column of the ball grid array, and any command / address ball grid of the first part is not linearly adjacent to other command / address ball grids; for a second part of the command / address ball grids, the command / address ball grids are located at a non-edge row and a non-edge column of the ball grid array, and at most 2 command / address ball grids of the second part are allowed to be arranged continuously in the second direction, and at most 3 command / address ball grids of the second part are allowed to be arranged continuously in a first direction, the first direction refers to a column extension direction of the ball grid array.

[0008] In some embodiments, the ball grid array has N rows, the data ball grids of the first part are located in the first row, the data ball grids of the second part are located in the second to A rows, the command address ball grids of the second part are located in the B to (N-1) rows, and the command address ball grids of the first part are located in the N row; A, B and N are positive integers, A is less than B, and B is less than N-1.

[0009] In some embodiments, the data ball grids located in the first to (C-1) rows are used to transmit high-bit data signals, and the data ball grids located in the (C+1) to A rows are used to transmit low-bit data signals; or, the data ball grids located in the first to (C-1) rows are used to transmit low-bit data signals, and the data ball grids located in the (C+1) to A rows are used to transmit high-bit data signals; the ball grids located in the C row are all ground ball grids or power ball grids, and the ground ball grids are used to transmit ground signals, and the power ball grids are used to transmit power signals; wherein C=(A+1) / 2.

[0010] In some embodiments, the ball grid array is divided into a first array, a center array and a second array, the first array, the center array and the second array are arranged in sequence along a second direction, the number of ball grids in the first array and the number of ball grids in the second array are the same, and all ball grids of the center array are removed.

[0011] Wherein, the data ball grids located in the first array are symmetric about the center array with the data ball grids located in the second array, and the command address ball grids located in the first array are symmetric about the center array with the command address ball grids located in the second array.

[0012] In some embodiments, the ball grid array further comprises a plurality of data strobe ball grids, the data strobe ball grids are used to transmit data strobe signals; in the second direction, each data strobe ball grid is adjacent to the center array, and the data strobe ball grid is allowed to be adjacent to the data ball grid in the first direction, and the data strobe ball grid is allowed to be adjacent to the data ball grid in the second direction; the ball grid array further comprises a plurality of mask control ball grids, the mask control ball grids are used to transmit mask flip control signals or terminal data strobe signals; the mask control ball grids are symmetric about the center array with the data strobe ball grids.

[0013] In some embodiments, the ball grid array further comprises a local data strobe ball grid, a local data ball grid, and a calibration indication ball grid; the local data strobe ball grid is located in an edge column, and the local data strobe ball grid is adjacent to the data ball grid along a second direction; the local data strobe ball grid is symmetric to the local data ball grid about the center array; the calibration indication ball grid is adjacent to the local data strobe ball grid along a first direction; wherein the local data ball grid is configured to transmit a local data signal, the local data strobe ball grid is configured to transmit a local data strobe signal, and the calibration indication ball grid is configured to transmit an impedance calibration signal.

[0014] In some embodiments, the ball grid array further comprises a plurality of chip select ball grids adjacent along a first direction, the chip select ball grids are configured to transmit chip select signals; a portion of the chip select ball grids are adjacent to one of the data ball grids along the first direction; another portion of the chip select ball grids are adjacent to one of the command address ball grids along a second direction and adjacent to another one of the command address ball grids along the first direction.

[0015] In some embodiments, the ball grid array further comprises a plurality of clock ball grids adjacent along a first direction, the clock ball grids are configured to transmit clock signals; a portion of the clock ball grids are not adjacent to any of the command address ball grids in a straight line and not adjacent to any of the data ball grids in a straight line; another portion of the clock ball grids are adjacent to one of the command address ball grids along a second direction and adjacent to another one of the command address ball grids along the first direction.

[0016] In some embodiments, a plurality of the chip select ball grids are located in the first array and adjacent to an edge column of the ball grid array; a plurality of the clock ball grids are located in the second array and adjacent to the center array; one of the chip select ball grids and one of the clock ball grids are located in a same row.

[0017] In some embodiments, the ball grid array further comprises a check error indication ball grid and a mirror mode ball grid, and the check error indication ball grid and the mirror mode ball grid are both located in an edge column of the ball grid array; the mirror mode ball grid is adjacent to one of the chip select ball grids along a second direction; the error indication ball grid is adjacent to another one of the chip select ball grids along the second direction; wherein the mirror mode ball grid is configured to transmit at least a mirror mode enable signal, and the error indication ball grid is configured to transmit a check error indication signal.

[0018] In some embodiments, the ball grid array further comprises a plurality of reserved ball grids, one test mode ball grid and two protocol ball grids, the test mode ball grid is used to transmit a test mode enable signal, and the protocol ball grid is used to transmit a protocol control signal; the plurality of reserved ball grids are symmetric to the plurality of chip select ball grids with respect to the center array; the second protocol ball grid is symmetric to the mirror mode ball grid with respect to the center array, the test mode ball grid is symmetric to the error indication ball grid with respect to the center array, and the first protocol ball grid, the second protocol ball grid and the test mode ball grid are arranged continuously in a first direction.

[0019] In some embodiments, the ball grid array further comprises a termination ball grid and a reset ball grid, the termination ball grid and the reset ball grid are located in the edge column of the ball grid array; the termination ball grid and the reset ball grid are symmetric to the center array; the straight-line adjacent ball grid of the termination ball grid is a ground ball grid and / or a power ball grid, the termination ball grid is in the same row as at least one command address ball grid, and the reset ball grid is in the same row as at least one command address ball grid; wherein the termination ball grid is used to transmit an on-chip termination command, and the reset ball grid is used to transmit a reset signal.

[0020] In a second aspect, the embodiments of the present disclosure provide a semiconductor structure, comprising the packaging structure of the first aspect and a chip; wherein the data bit width of the chip is 4 bits, 8 bits or 16 bits.

[0021] The embodiments of the present disclosure provide a packaging structure and a semiconductor structure, which can be compatible with chips of different specifications, have strong adaptability, and have a small overall area. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 A schematic diagram of a packaging structure provided by the embodiments of the present disclosure is shown;

[0023] Figure 2 A schematic diagram of a ball grid array provided by the embodiments of the present disclosure is shown;

[0024] Figure 3 A detailed structure schematic of a ball grid array provided by the embodiments of the present disclosure is shown; Figure 1

[0025] Figure 4 Another schematic diagram of a ball grid array provided by the embodiments of the present disclosure is shown;

[0026] Figure 5 A detailed structure schematic of a ball grid array provided by the embodiments of the present disclosure is shown; Figure 2

[0027] Figure 6 A structure schematic of a semiconductor structure provided by the embodiments of the present disclosure is shown. ​​DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in combination with the drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, it should be noted that, for the convenience of description, only the parts related to the application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure. In the following description, “some embodiments” are described, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms “first, second, third” involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that “first, second, third” can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described.

[0029] Static Random-Access Memory (SRAM);

[0030] Synchronous Dynamic Random Access Memory (SDRAM);

[0031] Double Data Rate SDRAM (DDR);

[0032] Fifth-generation DDR (DDR5);

[0033] Sixth-generation DDR (DDR6);

[0034] Two-wire bidirectional serial bus protocol (I3C);

[0035] Printed Circuit Board (PCB).

[0036] Before introducing the embodiments of the present disclosure, the following three directions for describing the three-dimensional structure that the plane can use are defined. Taking the Cartesian coordinate system as an example, the three directions can include the X-axis, Y-axis and Z-axis directions (not involved in the embodiments of the present disclosure). The package structure can include a top surface at the front and a bottom surface at the back opposite to the front; in the case of ignoring the flatness of the top surface and the bottom surface, the direction intersecting (for example, perpendicular) with the top surface and the bottom surface of the package structure is defined as the third direction. In the direction of the top surface and the bottom surface (i.e. the plane of the package structure), two directions intersecting with each other are defined, for example, the column extension direction of the ball grid array can be defined as the first direction, and the row extension direction of the ball grid array can be defined as the second direction, and the plane direction of the package structure can be determined based on the first direction and the second direction. In the embodiments of the present disclosure, the first direction and the second direction can be perpendicular to each other, and in other embodiments, the first direction and the second direction can also be not perpendicular.

[0037] In addition, the term "linearly adjacent" used in the present disclosure in connection with the ball grid array means and includes the ball grid directly above, directly below, directly left and directly right of a given ball grid when the ball grid array is parallel to the plane of the drawing; the term "diagonally arranged" used in the present disclosure in connection with the ball grid array means and includes the ball grid upper right, lower right, upper left and lower left of a given ball grid when the ball grid array is parallel to the plane of the drawing; the term "surrounding ball grid" used in the present disclosure in connection with the ball grid array means and includes the ball grid directly above, directly below, directly left, directly right, upper right, lower right, upper left and lower left of a given ball grid when the ball grid array is parallel to the plane of the drawing. The term "ball grid A and ball grid B are adjacent in the first direction" used in the present disclosure in connection with the ball grid array only includes that ball grid A and ball grid B are adjacent, and ball grid A is directly above or directly below ball grid B when the ball grid array is parallel to the plane of the drawing. The term "ball grid A and ball grid B are adjacent in the second direction" used in the present disclosure in connection with the ball grid array only includes that ball grid A and ball grid B are adjacent, and ball grid A is directly left or directly right of ball grid B when the ball grid array is parallel to the plane of the drawing.

[0038] In particular, the illustrations presented in the present disclosure are not meant to be actual views of any particular microelectronic device package, ball grid array, or component thereof, but are merely idealized representations used to describe the illustrative embodiments. Thus the drawings are not necessarily to scale.

[0039] Since the 4-bit data bit width (X4), 8-bit data bit width (X8) and 16-bit data bit width (X16) of the DDR6 chip are involved in the subsequent description of the embodiments of the present disclosure, Table 1 is provided to illustrate the number of related signals involved in the above chip packaging.

[0040] Table 1

[0041]

[0042] Specifically, for the X8 chip, the terminal data strobe signals tdqs_c and tdqs_t are required, while the X4 and X16 chips do not require them, but they do require the mask inversion control signals dmu_n and dml_n. Specifically, for the same design specification, the terminal data strobe signals can share a ball grid with the mask inversion control signals; that is, tdqs_c and dmu_n share a ball grid, and tdqs_t and dml_n share a ball grid.

[0043] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0044] In one embodiment of this disclosure, see Figure 1 This illustrates a schematic diagram of a packaging structure 10 provided in an embodiment of the present disclosure. For example... Figure 1 As shown, the packaging structure 10 includes a packaging substrate 11, and a ball grid array 20 is disposed on the surface of the packaging substrate 11.

[0045] It should be noted that the packaging structure 10 provided in this embodiment is at least applicable to DDR, and can simultaneously support DDR5 and DDR6 chips with data bit widths of 4 bits, 8 bits, and 16 bits. Specifically, the DDR chip includes a device substrate, which includes semiconductor material and bonding pads coupled to the active surface of the device substrate. The packaging substrate is fixed to the device substrate, and the aforementioned packaging substrate 11 is configured to route signals to / from the bonding pads. Meanwhile, the ball grid array 20 is supported on the packaging substrate 11 and electrically connected to it. In particular, the distribution position of the ball grid array 20 on the packaging substrate 11 is only illustrative and does not constitute a limitation. In fact, the surface of the packaging substrate 11 is not necessarily a perfectly regular rectangle, and the ball grid array 20 can be distributed in any area of ​​the surface of the packaging substrate 11.

[0046] In the following description, the first direction is the column extension direction of the ball grid array 20, and the second direction is the row extension direction of the ball grid array 20.

[0047] like Figure 1 As shown, the ball grid array 20 includes multiple data ball grids ( Figure 1 Only a portion is shown in the table, i.e., 201~204), and the data ball grid is used to transmit data signals (e.g., dqu[7:0], dql[7:0] in Table 1); in the second direction, a maximum of two data ball grids are allowed to be arranged consecutively.

[0048] Thus, in this embodiment of the disclosure, allowing two data ball grids to be arranged adjacently can compress the number of rows occupied by the data ball grid array, thereby reducing the package size. It also helps to reduce the wiring length from data pins to chip input / output I / O terminals, which is beneficial for high-speed memory products. Conversely, if three or more data ball grids are arranged adjacently, it will generate significant inter-signal crosstalk, causing signal distortion.

[0049] In some embodiments, only one row of data ball grid exists in any two adjacent rows of the ball grid array 20, i.e. no other data ball grid exists in the row before and after the row where each data ball grid exists. For example, referring to Figure 2 , another schematic diagram of a ball grid array 20 is shown. As shown in Figure 2 , data ball grids are distributed in the 1st, 3rd, 5th and 7th rows. In this way, at most one other data ball grid exists around each data ball grid (directly above, directly below, directly left, directly right, upper left, lower left, upper right, lower right), thereby improving the signal distortion problem caused by magnetic field superposition.

[0050] In some embodiments, referring to Figure 2 , the data ball grids can be divided into two parts according to the distribution position:

[0051] (1) For the data ball grids (207, 208) in the first part, Figure 2 , they are located in the edge rows and non-edge columns of the ball grid array 20, and any data ball grid in the first part is not linearly adjacent to other data ball grids, i.e. the data ball grid 205 (or 206) is not linearly adjacent to any data ball grid (whether in the first part or the second part).

[0052] (2) For the data ball grids (201-206) in the second part, Figure 2 , they are located in the non-edge rows and non-edge columns of the ball grid array 20, and every two data ball grids in the second part are adjacent in the second direction, i.e. the data ball grid 201 is adjacent to the data ball grid 202 in the second direction, the data ball grid 203 is adjacent to the data ball grid 204, and the data ball grid 205 is adjacent to the data ball grid 206.

[0053] It should be noted that, Figure 2 this is only one possible distribution form of the data ball grid, and adaptive adjustment can be made without departing from the literal description, such as shifting the whole or part of the data ball grids 201-206 one position to the right.

[0054] In this way, in the disclosed embodiments, the data ball grid is allowed to be distributed in the edge rows, which can reduce the number of ball grid rows of the ball grid array 20 as a whole and reduce the substrate area occupation; at the same time, the data ball grid is not allowed to be distributed in the edge columns, which can reduce the distribution width of the data ball grid in the second direction as much as possible, shorten the transmission distance of the data signal, and better ensure the quality of the data signal.

[0055] In addition, as mentioned before, the ball grid array 20 can be compatible with X4, X8 and X16 chips, and the number of data signals of these chips is different, so some or all of the data ball grids can be selectively enabled according to the actual application scenario.

[0056] In some embodiments, as shown in FIG. 1, the ball grid array 20 further comprises a plurality of command / address balls (301-307 and 311-317), which are used to transmit command / address signals ca. Figure 2

[0057] (1) For the command / address balls (301) of the first part, they are located at the edge row and non-edge column of the ball grid array 20, and any command / address ball of the first part is not linearly adjacent to other command / address balls; as shown in FIG. 1, the command / address ball 301 (or 307) is not linearly adjacent to any command / address ball (whether of the first part or the second part). Figure 2

[0058] (2) For the command / address balls (302-306) of the second part, they are located at the non-edge row and non-edge column of the ball grid array 20, and at most 2 command / address balls of the second part are allowed to be arranged continuously and adjacently in the second direction, and at most 3 command / address balls of the second part are allowed to be arranged continuously and adjacently in the first direction; as shown in FIG. 1, the command / address ball 302, the command / address ball 303 and the command / address ball 304 are arranged continuously along the first direction, and the command / address ball 303 and the command / address ball 305 are arranged continuously along the second direction. Figure 2

[0059] It should be noted that, Figure 2 only one possible distribution form of the command / address balls is shown, and adaptive adjustment can be made without departing from the literal description, for example, the whole or part of the command / address balls 305-307 is translated downward by one position, and the command / address ball 301 is translated leftward by one position, or the command / address balls 305 and 306 are translated leftward by one position, and the command / address ball 307 is translated rightward by one position.

[0060] In this way, in the embodiments of the present disclosure, the command / address balls are allowed to be distributed at the edge row, the area of the ball grid array 20 is reduced, the number of rows occupied by the command / address balls in the ball grid array 20 can be compressed, space can be further saved, and the timing between the clock and the address signal can be better matched. At the same time, the command / address balls are not allowed to be distributed at the edge column, so as to reduce the distribution width of the command / address balls along the second direction as much as possible, shorten the transmission path of the command / address signal, and improve the signal transmission quality.

[0061] In some embodiments, the ball grid array 20 has N rows, the data balls of the first part are located at the first row, the data balls of the second part are located at the second row to the A-th row, the command / address balls of the second part are located at the B-th row to the (N-1)-th row, and the command / address balls of the first part are located at the N-th row; A, B and N are positive integers, A is less than B, and B is less than N-1.​​​

[0062] by Figure 2 For example, N=13, A=7, B=9, but this can be adjusted in actual applications. For instance, N can be adjusted to 14, etc.

[0063] In one specific embodiment, B > A + 1. For example... Figure 2 As shown, the ball grid array 20 can be divided into a data transmission area, an isolation area, and a command transmission area along the first direction. Data ball grids are all distributed in the data transmission area, and command address ball grids are all distributed in the control transmission area. At the same time, the data transmission area and the control transmission area are separated by the isolation area.

[0064] For ease of explanation, please refer to Figure 3 This is a schematic diagram of the ball grid array 20 for the specific application scenario of DDR6 chips. (This is only for...) Figure 3 For example, N=13, A=7, B=9, but this does not constitute a corresponding limitation. The ball grid array 20 has 13 rows × 11 columns, including 16 data ball grids (DQ) and 14 command address ball grids (CA). It should be understood that... Figure 3 This is only one specific embodiment of the present disclosure. Without departing from the following description, the size of the ball grid array 20, the number of different types of signals, and the detailed arrangement of each signal can be adaptively adjusted.

[0065] Please refer to Figure 3 The ball grids located in row C are either ground grids (VSS) or power ball grids. The ground grids (VSS) are used to transmit ground signals (vss), and the power ball grids (VDD, VDDQ) are used to transmit power signals (vdd, vddq). When A is odd, C = (A+1) / 2, that is... Figure 4 C=4.

[0066] In one possibility, the data ball grids (DQs) located in rows 1 to (C-1) are used to transmit high-order data signals (e.g., dqu[7:0] in Table 1), and the data ball grids (DQs) located in rows (C+1) to A are used to transmit low-order data signals (e.g., dql[7:0] in Table 1). Specifically, for the X4 chip, only the four data ball grids (DQs) located in rows (C+1) to A are enabled; for the X4 chip, only the eight data ball grids (DQs) located in rows (C+1) to A are enabled; and for the X16 chip, only all data ball grids (DQs) are enabled.

[0067] In another possible implementation, the data ball grid DQ in the 1~(C-1) row is used to transmit low-bit data signals (for example, dql[7:0] in Table 1), and the data ball grid DQ in the (C+1)~A row is used to transmit high-bit data signals (for example, dqu[7:0] in Table 1). Specifically, for an X4 chip, only 4 data ball grids DQ in the 1~(C-1) row are enabled; for an X8 chip, only 8 data ball grids DQ in the 1~(C-1) row are enabled; and for an X16 chip, all data ball grids DQ are enabled.

[0068] In this way, the low-bit data ball grid and the high-bit data ball grid are independent of each other, and the two regions are separated by the ball grids in the C row, the arrangement is reasonable, and signal distortion caused by magnetic field superposition can be improved.

[0069] As shown in Figure 3 , the ball grid array 20 is divided into a first array, a center array, and a second array, the first array, the center array, and the second array are arranged along the second direction, the number of ball grids in the first array is the same as the number of ball grids in the second array, and all ball grids in the center array are removed. That is, after the ball grid array 20 is completed, all ball grids in the center column need to be removed to facilitate the wiring of the PCB or the substrate. Figure 3 The center column in Figure 3 contains 3 columns, but this does not constitute a limitation, and the number of columns contained in the center column can be more or less. In particular, in Figure 3 , the length of each column (i.e., the 5th / 6th / 7th column) in the center column along the second direction is short, but this is only to save page space, and in fact the length of each column of the ball grid array 20 along the second direction is basically the same.

[0070] In some embodiments, referring to Figure 3 , the data ball grids DQ in the first array are symmetric about the center array with the data ball grids in the second array. For example, the even-numbered data ball grids DQ are distributed in the 2nd, 3rd, and 4th columns, and the odd-numbered data ball grids DQ are distributed in the 8th, 9th, and 10th columns; or, the even-numbered data ball grids DQ are distributed in the 8th, 9th, and 10th columns, and the odd-numbered data ball grids DQ are in the 2nd, 3rd, and 4th columns. In this way, the data ball grids DQ in the first array and the second array are mirror images of each other, so that the through holes can be shared when the PCB is designed for front and back pasting.

[0071] It should be noted that Figure 3The ball grid array 20 includes 16 data ball grids (DQs), supporting chips with 4-bit, 8-bit, and 16-bit data widths. Simply put, if package structure 10 is applied to a 4-bit data width (X4) chip, only 4 data ball grids are enabled, and the remaining 12 are disabled; if package structure 10 is applied to an 8-bit data width (X8) chip, only 8 data ball grids are enabled, and the remaining 8 are disabled; if package structure 10 is applied to a 16-bit data width (X16) chip, all data ball grids are enabled.

[0072] In some embodiments, the command address ball grids CA in the first array and the command address ball grids CA in the second array are symmetrical about the central array. For example, even-numbered command address ball grids CA are distributed in columns 2, 3, and 4, and odd-numbered command address ball grids CA are distributed in columns 8, 9, and 10. Alternatively, even-numbered command address ball grids CA are distributed in columns 8, 9, and 10, and odd-numbered command address ball grids CA are distributed in columns 2, 3, and 4. In this way, the command address ball grids CA in the first and second arrays are mirror images of each other, so that vias can be shared when performing reverse mounting designs on the PCB.

[0073] In some embodiments, the ball grid array 20 further includes a plurality of data gating ball grids (e.g. Figure 3 Two DQS_T and two DQS_C are used to transmit data gating signals (e.g., dqsl_t, dqsl_c, dqsu_t, and dqsu_c in Table 1). In the second direction, each data gating ball grid is adjacent to the central array, and data gating ball grids are allowed to be adjacent to data ball grids DQ along the first direction and along the second direction, thereby reducing the area of ​​the ball grid array 20.

[0074] It should be noted that, Figure 3 The diagram shows four data gating spheres, but in real-world scenarios, the number of data gating spheres can be more or less.

[0075] It should also be noted that one data gating ball grid DQS_T and one data gating ball grid DQS_C are adjacent along the first direction and are used to transmit a pair of differential signals (dqsl_t and dqsl_c are one pair of differential signals, and dqsu_t and dqsu_c are another pair of differential signals), which can be referred to as a set of data gating ball grids. Different sets of data gating ball grids are not adjacent along the first direction to reduce signal interference. Meanwhile, in Figure 3 In this configuration, all data gating gates are placed in the same column, but this is not mandatory; different groups of data gating gates can be placed in different columns (see [link to documentation]). Figure 3 However, it must be adjacent to the center column to facilitate PCB or substrate routing.

[0076] In some embodiments, the ball grid array 20 further comprises a plurality of mask control ball grid DMs, which are used to transmit mask flip control signals (e.g., dmu, dml in Table 1) or terminal data strobe signals (e.g., tdqs_t, tdqs_c in Table 1).

[0077] It should be noted that, Figure 5 Two mask control ball grids are shown, but in fact the number of mask control ball grids can be more or less. However, the number of mask control ball grid DMs is less than or equal to the number of data strobe ball grids, and one mask control ball grid DM is symmetric to one data strobe ball grid about the center array. Similarly, although Figure 3 The mask control ball grid DM in the center array is located on the same side of the center column, but in fact the mask control ball grid DM can also be located on different sides of the center array (see Figure 3 ).

[0078] As Figure 5 shown, each mask control ball grid DM is "and only and" linearly adjacent to one data ball grid DQ to Figure 3 For example, one mask control ball grid DM is adjacent to one data ball grid DQ in the first direction, and the other mask control ball grid DM is adjacent to one data ball grid DQ in the second direction, so as to minimize the magnetic field overlap.

[0079] In some embodiments, as Figure 3 shown, the ball grid array 20 further comprises a local data strobe ball grid LBDQS, a local data ball grid LBDQ and a calibration indication ball grid ZQ; the local data strobe ball grid LBDQS is located in the edge column, and the local data strobe ball grid LBDQS is adjacent to the data ball grid DQ in the second direction; the local data ball grid LBDQ is symmetric to the local data strobe ball grid LBDQ about the center array, that is, the local data ball grid LBDQ is also located in the edge column and is adjacent to only one data ball grid LBDQ in the second direction.

[0080] Here, the local data ball grid LBDQ is used to transmit a local data signal lbdq, and the local data strobe ball grid LBDQS is used to transmit a local data strobe signal lbdqs.

[0081] As Figure 3 shown, in the second direction, the local data ball grid LBDQ, one data ball grid DQ, and the other data ball grid DQ are continuously arranged adjacent to each other; one data ball grid DQ, the other data ball grid DQ, and the local data strobe ball grid LBDQS are continuously arranged adjacent to each other.

[0082] In some embodiments, the calibration indication ball grid ZQ is adjacent to the local data strobe ball grid LBDQS in the first direction; in Figure 3In this configuration, the calibration indicator ball grid ZQ is located above the local data gating ball grid LBDQS, but it can also be located below the local data gating ball grid LBDQS. The calibration indicator ball grid ZQ is used to transmit the impedance calibration signal zq.

[0083] In other embodiments, the calibration indicator ball grid ZQ is adjacent to the local data ball grid LBDQ along a first direction, i.e. Figure 3 The calibration indicator ball grid ZQ is swapped with the power ball grid VPP in column 1.

[0084] like Figure 3 As shown, for the first to A ( Figure 3 In the case of A=7), the remaining unmentioned ball grids are either power ball grids or grounding ground grids (VSS). Depending on their function and / or voltage value, the power ball grids are identified as VDD, VDDQ, and VPP. Thus, each data ball grid (DQ) is surrounded by at least one grounding ground grid (VSS) and one power ball grid. Here, "surrounding the data ball grid (DQ)" includes the ball grids directly above, below, to the left, to the right, to the upper left, to the lower left, to the upper right, and to the lower right of the data ball grid (DQ). This not only provides isolation but also facilitates the generation of data signals.

[0085] In some embodiments, see Figure 4 The ball grid array 20 also includes a plurality of chip select ball grids CS adjacent to each other along a first direction. The chip select ball grids CS are used to transmit chip select signals (e.g., cs_n[1:0] in Table 1). A portion of the chip select ball grids CS are adjacent to a data ball grid DQ along the first direction. Another portion of the chip select ball grids CS are adjacent to a command address ball grid CA along a second direction and to another command address ball grid CA along the first direction.

[0086] It should be noted that, Figure 4 Two chip select ball grids (CS) are shown, but in real-world scenarios, there can be more or fewer. This allows the chip select ball grids (CS) to be adjacent to the data ball grids (DQ) or command address ball grids (CA), and at most two command address ball grids (CA), resulting in a more concentrated signal arrangement and further compression of the ball grid array 20, thus occupying less substrate area.

[0087] In some embodiments, the ball grid array 20 further includes a plurality of clock ball grids CK adjacent along a first direction, the clock ball grids CK being used to transmit clock signals (e.g., ck_c or ck_n in Table 1); a portion of the clock ball grids CK are not directly adjacent to any command address ball grid CA and are not directly adjacent to any data ball grid DQ; another portion of the clock ball grids CK are adjacent to one command address ball grid CA along a second direction and to another command address ball grid CA along the first direction.

[0088] It should be noted that,Figure 4 Two clock balls CK are shown, but more or less can be in actual scenarios. In this way, the clock balls are close to the command address balls, so that the clock and address delays can be better matched, the overall transmission path is closer, the signal integrity is improved, and the overall product competitiveness is improved.

[0089] In some embodiments, the plurality of chip select balls CS are located in a first array and adjacent to the edge columns of the ball grid array 20; the plurality of clock balls CK are located in a second array and adjacent to the center array, and one chip select ball CS and one clock ball CK are located in the same row.

[0090] For example, as shown in Figure 3 , two chip select balls can be represented as CS_N[0] and CS_N[1], respectively, for transmitting cs_n[0] and cs_n[1], and there is at least one valid among cs_n[0] and cs_n[1]; two clock balls can be represented as CK_C and CK_T, respectively, for transmitting a pair of differential signals ck_c and ck_t. In addition, the chip select ball CS_N[0] and the clock ball CK_T are located in the same row, and the chip select ball CS_N[1] and the clock ball CK_C are located in the same row.

[0091] It should be noted that in Figure 3 , the clock ball CK is located in the 8th column, but the clock ball CK can also be located in the 4th column (see Figure 5 ), as long as the clock ball CK is adjacent to the center array, so that it is easier to realize the PCB or substrate wiring.

[0092] In some embodiments, as shown in Figure 3 , the ball grid array 20 further includes a check error indication ball ALERT_N and a mirror mode ball MIR, and the check error indication ball ALERT_N and the mirror mode ball MIR are located in the edge columns of the ball grid array 20; the mirror mode ball MIR is adjacent to one chip select ball CS_N[0] along the second direction; the error indication ball ALERT_N is adjacent to another chip select ball CS_N[1] along the second direction; wherein the mirror mode ball MIR is used to transmit at least a mirror mode enable signal mir, and the error indication ball ALERT_N is used to transmit a check error indication signal alert_n.

[0093] In other embodiments, the positions of the check error indication ball ALERT_N and the error indication ball ALERT_N can be interchanged.

[0094] In some embodiments, the ball grid array 20 further comprises a plurality of reserved ball grids RFU, one test mode ball grid TEN for transmitting a test mode enable signal ten, and two protocol ball grids (i.e. MSCL and MSDA) for transmitting protocol control signals mscl and msda (related to I3C protocol) respectively; the plurality of reserved ball grids RFU are symmetric to the plurality of chip select ball grids CS with respect to the center array; the second protocol ball grid is symmetric to the mirror mode ball grid MIR with respect to the center array, the test mode ball grid TEN is symmetric to the alert ball grid ALERT_N with respect to the center array, and the first protocol ball grid MSDA, the second protocol ball grid MSCL and the test mode ball grid TEN are arranged in series along the first direction.

[0095] In other embodiments, the positions of the plurality of reserved ball grids RFU, one test mode ball grid TEN and two protocol ball grids (i.e. MSCL and MSDA) can be flexibly adjusted, mainly depending on the arrangement of internal circuits, as long as the input / output of signals is facilitated.

[0096] In some embodiments, the ball grid array 20 further comprises a termination ball grid CA_ODT and a reset ball grid RESET, which are located in the edge column of the ball grid array 20; the termination ball grid CA_ODT and the reset ball grid RESET are symmetric with respect to the center array; the straight-line adjacent ball grids of the termination ball grid CA_ODT are all ground ball grids VSS and / or power ball grids, and the termination ball grid CA_ODT is in the same row as at least one command address ball grid CA; the straight-line adjacent ball grids of the reset ball grid RESET are all ground ball grids VSS and / or power ball grids, and the reset ball grid RESET is in the same row as at least one command address ball grid CA; wherein the termination ball grid CA_ODT is used for transmitting an on-chip termination command, and the reset ball grid RESET is used for transmitting a reset signal.

[0097] Similarly, in other embodiments, the positions of the termination ball grid CA_ODT and the reset ball grid RESET can be flexibly adjusted.

[0098] In addition to the above-mentioned signals, the other ball grids in the ball grid array 20 are all power ball grids or ground ball grids VSS.

[0099] In other embodiments, the positions of the following ball grids can be flexibly exchanged: mask control ball grid DM, test mode enable ball grid TEN, reserved ball grid RFU, mirror mode enable ball grid MIR (for controlling the chip to enter / exit mirror mode), error indication ball grid (for prompting an error detected in a cyclic redundancy check operation) ALERT_N, protocol ball grid MSDA / MSCL, termination ball grid CA_ODT, reset ball grid RESET, and calibration ball grid ZQ. Please refer to Figure 5 , Figure 5Another possible ball grid arrangement is provided.

[0100] In some embodiments, referring to Figure 3 or Figure 5 , the ball grid array 20 has 13 rows, the first array has 4 columns, the second array has 4 columns, and a total of 104 ball grids are provided, which can support signal packaging of X4, X8, and X16 chips.

[0101] In some embodiments, the distance between every 2 ball grid center points along the first direction is 800 microns, the distance between every 2 ball grid center points along the second direction is also 800 microns, and the overall size of the ball grid array is 10 mm x 11 mm, which is relatively small, and more packaging structures can be made on the same substrate.

[0102] As can be seen from the above, the packaging structure provided by the embodiments of the present disclosure can make X4, X8, and X16 share a substrate, and the overall size of the ball grid array is small, so that more chip units can be cut out on a substrate to reduce costs. At the same time, the design cycle can be reduced, and different substrates do not need to be designed for chips of different bit widths. At the same time, it is found through testing that the solder joint life of the ball grid array 20 provided by the present disclosure is longer, the plastic strain is smaller, and the fatigue life is longer.

[0103] In another embodiment of the present disclosure, referring to Figure 6 , a schematic diagram of a semiconductor structure 60 is shown. As Figure 6 indicated, the semiconductor structure 60 at least includes the aforementioned packaging structure 10 and a chip, and the data bit width of the chip is 4 bits, 8 bits, or 16 bits.

[0104] Here, the chip can be placed on the packaging structure 10, and the chip can be electrically connected to the ball grid array on the packaging structure 10, so that various signals involved in the chip are output / input through the packaging structure 10.

[0105] The above merely describes preferred embodiments of the present disclosure, but is not intended to limit the protection scope of the present disclosure. It should be explained that, in the present disclosure, the terms “comprising”, “containing” or any other variants thereof are intended to cover non-exclusive containing, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement “including a…” does not exclude the presence of other identical elements in the process, method, article or device including the element. The above sequence number of the embodiments of the present disclosure is only for description, and does not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new method or device embodiments. The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A packaging structure, characterized in that, The package includes a packaging substrate, the surface of which is provided with a ball grid array, the ball grid array including a plurality of data ball grids, and the data ball grids being used to transmit data signals; In the second direction, at most two of the data ball grids are allowed to be arranged consecutively; the second direction refers to the row extension direction of the ball grid array. For the data gratings in the first part, which are located in the edge rows and not the edge columns of the grating array, and any of the data gratings in the first part are not directly adjacent to any of the other data gratings; The ball grid array also includes multiple command address ball grids, which are used to transmit command / address signals; For the command address ball grids in the first part, they are located in the edge rows and not the edge columns of the ball grid array, and any of the command address ball grids in the first part are not directly adjacent to other command address ball grids. The ball grid array also includes a plurality of clock ball grids adjacent to each other along a first direction, the clock ball grids being used to transmit clock signals; A portion of the clock ball grid is not directly adjacent to any of the command address ball grids, nor is it directly adjacent to any of the data ball grids; Another portion of the clock ball grid is adjacent to one of the command address ball grids along a second direction and to another of the command address ball grids along a first direction, the first direction being the column extension direction of the ball grid array.

2. The packaging structure according to claim 1, characterized in that, For the data ball grids in the second part, which are located in the non-edge rows and non-edge columns of the ball grid array, and every two data ball grids in the second part are adjacent to each other along the second direction; In this configuration, only one row in any two adjacent rows of the spherical grid array contains the data spherical grid.

3. The packaging structure according to claim 1, characterized in that, The ball grid array also includes multiple command address ball grids, which are used to transmit command / address signals; For the command address ball grid of the second part, which is located in the non-edge row and non-edge column of the ball grid array, and at most two of the command address ball grids of the second part are allowed to be arranged consecutively in the second direction, and at most three of the command address ball grids of the second part are allowed to be arranged consecutively in the first direction.

4. The packaging structure according to claim 3, characterized in that, The ball grid array has N rows. The data ball grids of the first part are located in row 1, the data ball grids of the second part are all located in rows 2 to A, the command address ball grids of the second part are all located in rows B to (N-1), and the command address ball grids of the first part are located in row N. A, B and N are all positive integers, A is less than B, and B is less than N-1.

5. The packaging structure according to claim 4, characterized in that, The data ball grids located in rows 1 to (C-1) are used to transmit high-order data signals, and the data ball grids located in rows (C+1) to A are used to transmit low-order data signals; or, the data ball grids located in rows 1 to (C-1) are used to transmit low-order data signals, and the data ball grids located in rows (C+1) to A are used to transmit high-order data signals. All ball grids located in row C are either ground grids or power ball grids, and the ground grids are used to transmit ground signals, while the power ball grids are used to transmit power signals; where C = (A+1) / 2.

6. The packaging structure according to any one of claims 3-5, characterized in that, The ball grid array is divided into a first array, a central array, and a second array. The first array, the central array, and the second array are arranged sequentially along a second direction. The number of ball grids in the first array and the number of ball grids in the second array are the same. All ball grids in the central array are removed. The data ball grid located in the first array and the data ball grid located in the second array are symmetrical about the central array, and the command address ball grid located in the first array and the command address ball grid located in the second array are symmetrical about the central array.

7. The packaging structure according to claim 6, characterized in that, The ball grid array also includes multiple data gating ball grids, which are used to transmit data gating signals; In the second direction, each of the data gating ball grids is adjacent to the central array, and the data gating ball grids are allowed to be adjacent to the data ball grids along the first direction, and the data gating ball grids are allowed to be adjacent to the data ball grids along the second direction; The ball grid array also includes multiple mask control ball grids, which are used to transmit mask flip control signals or terminal data gating signals; The mask control ball grid and the data gating ball grid are symmetrical about the central array.

8. The packaging structure according to claim 7, characterized in that, The ball grid array also includes a local data gating ball grid, a local data ball grid, and a calibration indicator ball grid; The local data gating ball grid is located in the edge column, and the local data gating ball grid is adjacent to the data ball grid along the second direction; The local data gating ball grid is symmetrical to the local data ball grid about the central array; The calibration indicator ball grid is adjacent to the local data gating ball grid along a first direction; The local data ball grid is used to transmit local data signals, the local data gating ball grid is used to transmit local data gating signals, and the calibration indicator ball grid is used to transmit impedance calibration signals.

9. The packaging structure according to claim 6, characterized in that, The ball grid array further includes a plurality of chip select ball grids adjacent to each other along the first direction, the chip select ball grids being used to transmit chip select signals; A portion of the chip select ball grid is adjacent to one of the data ball grids along a first direction; Another portion of the chip select ball grid is adjacent to one of the command address ball grids along a second direction and to another of the command address ball grids along a first direction.

10. The packaging structure according to claim 9, characterized in that, Multiple chip select ball grids are located in the first array and are adjacent to the edge columns of the ball grid array; Multiple clock ball grids are located in the second array and are adjacent to the central array; One of the chip select ball grids and one of the clock ball grids are located in the same row.

11. The packaging structure according to claim 9, characterized in that, The ball grid array further includes a check error indicator ball grid and a mirror mode ball grid, and both the check error indicator ball grid and the mirror mode ball grid are located in the edge column of the ball grid array; The mirror mode ball grid is adjacent to one of the chip select ball grids along the second direction; The error indication ball grid is adjacent to another chip select ball grid along a second direction; The mirror mode ball grid is used to transmit at least the mirror mode enable signal, and the error indication ball grid is used to transmit the check error indication signal.

12. The packaging structure according to claim 11, characterized in that, The ball grid array also includes multiple reserved ball grids, one test mode ball grid, and two protocol ball grids. The test mode ball grid is used to transmit test mode enable signals, and the protocol ball grids are used to transmit protocol control signals. The plurality of reserved ball grids and the plurality of chip select ball grids are symmetrical about the central array; The second protocol ball grid is symmetrical to the mirror mode ball grid about the central array, the test mode ball grid is symmetrical to the error indication ball grid about the central array, and the first protocol ball grid, the second protocol ball grid, and the test mode ball grid are arranged continuously along the first direction.

13. The packaging structure according to claim 6, characterized in that, The ball grid array further includes a terminating ball grid and a resetting ball grid, wherein the terminating ball grid and the resetting ball grid are located in the edge column of the ball grid array; The terminating ball grid and the resetting ball grid are symmetrical about the central array; The terminating ball grid is adjacent to the ground ball grid and / or the power ball grid. The terminating ball grid is in the same row as at least one of the command address ball grids. The reset ball grid is in the same row as at least one of the command address ball grids. The termination ball grid is used to transmit on-chip termination commands, and the reset ball grid is used to transmit reset signals.

14. A semiconductor structure, characterized in that, It includes the packaging structure and chip as described in any one of claims 1-13; wherein the data bit width of the chip is 4 bits, 8 bits, or 16 bits.

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