Dual-channel multi-gate high-voltage GaN HEMT device and manufacturing method
By using a dual-channel multi-gate structure and pGaN ohmic contact design, the problems of insufficient current and on-resistance in traditional GaN HEMT devices are solved, realizing high-voltage and high-current GaN HEMT devices and improving the device's voltage withstand performance and current capacity.
Patent Information
- Application Number
- CN202411209760.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2026-02-10
- Estimated Expiration
- 2044-08-30
AI Technical Summary
Traditional GaN HEMT devices have only one channel, and their current and on-resistance cannot compete with SiC-based MOS devices. Furthermore, existing dual-channel GaN HEMT devices have relatively weak breakdown voltage performance.
A dual-channel multi-gate structure is adopted, and the 2DHG is led out through pGaN ohmic contacts, so that both barrier layers are depletion layers, achieving a uniform electric field and improving the breakdown voltage performance of the device. The 2DEG is led out through the source and drain.
This effectively improves the breakdown voltage performance of GaN HEMT devices, increases the operating current, and reduces the on-resistance.
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Figure CN119092541B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor discrete device technology, and more particularly to dual-channel multi-gate high-voltage GaN HEMT devices and their manufacturing methods. Background Technology
[0002] In AlGaN / GaN heterojunctions, the polarization effect generates high-density, high-mobility 2DEGs, making them highly promising for power semiconductor devices requiring high blocking voltage, large current capacity, high switching speed, and low on-resistance. However, traditional HEMT devices only have one channel, and their current and on-resistance cannot compete with SiC-based MOS.
[0003] Currently, dual-channel GaN HEMT devices are also available to achieve low resistance and high current, but their voltage withstand capability is relatively weak. Summary of the Invention
[0004] This application provides a dual-channel multi-gate high-voltage GaN HEMT device and its manufacturing method. The dual-channel multi-gate high-voltage GaN HEMT device has a secondary epitaxial growth and a multi-gate structure. When the device is turned off, the 2DHG can be led out through the ohmic contact of pGaN, so that both barrier layers are depletion layers, retaining only fixed charges, which can achieve the purpose of uniform electric field, thereby effectively improving the breakdown voltage performance of GaN HEMT device and realizing high breakdown voltage of device.
[0005] A first aspect of this application provides a dual-channel multi-gate high-voltage GaN HEMT device, including a substrate layer and GaN high-resistivity layer, GaN channel layer and first AlGaN barrier layer sequentially grown on the substrate layer. The surface of the first AlGaN barrier layer has a first undoped GaN layer, a second AlGaN barrier layer and a second undoped GaN layer sequentially grown near the center. A source and a drain are symmetrically formed on both sides of the first undoped GaN layer. The first undoped GaN layer and the second AlGaN barrier layer are connected to the source and the drain at their respective ends. A gap is maintained between the two ends of the second undoped GaN layer and the source and the drain.
[0006] A first pGaN layer and a first gate are sequentially grown on the surface of the second undoped GaN layer, and the upper 2DHG layer is led out through the first gate.
[0007] On the surface of the first undoped GaN layer, a secondary epitaxial undoped GaN layer, a secondary epitaxial pGaN layer, and a second gate are sequentially grown between the first pGaN layer and the source. The secondary epitaxial pGaN layer and the second gate maintain the same height as the first pGaN layer and the first gate, respectively. The secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer both maintain a gap with the second AlGaN barrier layer and the second undoped GaN layer. The lower 2DHG layer is led out through the second gate.
[0008] In one possible implementation, the substrate is a sapphire substrate.
[0009] In one possible implementation, both the source and the drain are made of Ni / Al / Ni / Au metal alloy.
[0010] In one possible implementation, both the first gate and the second gate are made of Ni / Au metal alloy.
[0011] A second aspect of this application provides a method for manufacturing the aforementioned dual-channel multi-gate high-voltage GaN HEMT device, comprising the following steps:
[0012] S10, GaN high resistivity layer, GaN channel layer, first AlGaN barrier layer, uGaN-1 layer, AlGaN-2 layer, uGaN-2 layer and pGaN-1 layer are sequentially grown on the substrate layer;
[0013] S20, the secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer are sequentially formed at predetermined positions on the surface of the pGaN-1 layer;
[0014] S30, repeating the photolithography, etching and resist removal cleaning steps to sequentially form the first pGaN layer, the second undoped GaN layer and the second AlGaN barrier layer at predetermined positions on the surface of the pGaN-1 layer;
[0015] S40, the first gate and the second gate are photolithographically patterned on the surfaces of the first pGaN layer and the secondary epitaxial pGaN layer, respectively. Then, the P-ohm contact is evaporated by PVD process, stripped and cleaned, and then subjected to RTA annealing to form the first gate and the second gate.
[0016] S50, the source and drain patterns are etched at predetermined positions on the surface of the pGaN-1 layer, then the N-ohm contacts are evaporated using PVD process, stripped and cleaned, and finally subjected to RTA annealing to form the source and drain.
[0017] In one possible implementation, step S20, which involves sequentially forming the secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer at predetermined positions on the surface of the pGaN-1 layer, specifically includes:
[0018] S21, using positive photolithography, the area of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer is etched on the surface of the pGaN-1 layer. The original AlGaN-2 layer, uGaN-2 layer, and pGaN-1 layer at the location of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer are removed using ICP etching technology. After etching, the photoresist is removed and the surface is cleaned.
[0019] S22, a SiO2 layer is fabricated on the surface of the pGaN-1 layer. The patterns of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer are etched using a positive photolithography process. Then, the SiO2 layer of the patterned portion of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer is removed using wet HF etching. Finally, the photoresist is removed using a cleaning process.
[0020] S23, the secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer are grown sequentially at the positions of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer by MOCVD secondary epitaxy. Then, the SiO2 layer except for the secondary epitaxial pGaN layer is removed by wet HF etching, so that the peripheral sides of the secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer are maintained with voids.
[0021] In one possible implementation, in step S40, the RTA annealing environment is an atmospheric environment, and the RTA annealing temperature is 600℃~650℃.
[0022] In one possible implementation, in step S50, the RTA annealing environment is an N2@1SLM environment, and the RTA annealing temperature is 750℃~950℃.
[0023] Beneficial effects: Compared with the prior art, the dual-channel multi-gate high-voltage GaN HEMT device and manufacturing method provided in this application can utilize secondary epitaxy and multi-gate structure to lead out 2DHG through ohmic contact when the device is turned off. The first gate leads out the upper 2DHG and the second gate leads out the lower 2DHG, realizing the depletion of 2DHG under reverse bias. At the same time, 2DEG is led out through the source and drain. The first AlGaN barrier layer and the second AlGaN barrier layer are both depletion layers, retaining only fixed charges, which can achieve the purpose of uniform electric field, thereby effectively improving the breakdown voltage performance of GaN HEMT device.
[0024] In addition, dual-channel devices form dual 2DEGs, which can significantly increase the device's operating current and reduce on-resistance.
[0025] These and other objects, features and advantages of the present invention will become fully apparent from the following detailed description. Attached Figure Description
[0026] Figure 1 A three-dimensional structural schematic diagram of the dual-channel multi-gate high-voltage GaN HEMT device of this application is shown.
[0027] Figure 2 This application shows Figure 1 A schematic diagram of the cross-sectional structure at point A in the middle.
[0028] Figure 3 This application shows Figure 1 A schematic diagram of the structure at section B in the middle. Detailed Implementation
[0029] The following description is intended to disclose the present invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the invention.
[0030] Those skilled in the art should understand that, in the disclosure of this specification, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting the present invention.
[0031] It is understood that the term "a" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple, and the term "a" should not be understood as a limitation on the number.
[0032] refer to Figures 1 to 3One embodiment of this application provides a dual-channel multi-gate high-voltage GaN HEMT device, including a substrate layer and GaN high-resistivity layer, GaN channel layer and first AlGaN barrier layer sequentially grown on the substrate layer. The substrate layer is preferably a sapphire substrate. The surface of the first AlGaN barrier layer has a first undoped GaN layer, a second AlGaN barrier layer and a second undoped GaN layer sequentially grown near the middle. A source electrode S and a drain electrode D are symmetrically grown on both sides of the first undoped GaN layer. The first undoped GaN layer and the second AlGaN barrier layer are connected to the source electrode S and the drain electrode D at their respective ends. At the same time, the two ends of the second undoped GaN layer are separated from the source electrode S and the drain electrode D by a gap.
[0033] Furthermore, a first pGaN layer and a first gate G1 are sequentially grown on the surface of the second undoped GaN layer, thereby enabling the upper 2DHG layer to be led out through the first gate G1.
[0034] In addition, a secondary epitaxial undoped GaN layer uGaN, a secondary epitaxial pGaN layer pGaN-2, and a second gate G2 are sequentially grown on the surface of the first undoped GaN layer between the first pGaN layer and the source. The secondary epitaxial pGaN layer pGaN-2 and the second gate G2 maintain the same height as the first pGaN layer and the first gate G1, respectively. At the same time, the secondary epitaxial undoped GaN layer uGaN and the secondary epitaxial pGaN layer pGaN-2 maintain a gap with the second AlGaN barrier layer and the second undoped GaN layer, so that the lower 2DHG layer can be led out through the second gate G2.
[0035] In a conventional dual-channel structure, 2DHG, or two-dimensional hole gas, is generated between the lower AlGaN barrier layer and the GaN layer between the double barrier layers. The generation of 2DHG will lead to the concentration of electric field. If the 2DHG is not brought out, it will inevitably reduce the breakdown voltage performance of the device and seriously affect the quality and service life of the device.
[0036] The dual-channel multi-gate high-voltage GaN provided in this application In HEMT devices, due to the polarization effect between AlGaN and GaN, a two-dimensional electron gas (2DEG) is generated on the surface of the GaN layer below AlGaN. Specifically, 2DEG is generated between the first AlGaN barrier layer and the GaN channel layer, and between the second AlGaN barrier layer and the first undoped GaN layer. Simultaneously, a two-dimensional hole gas (2DHG) is generated on the surface of the GaN layer above AlGaN. Specifically, 2DHG is generated between the second undoped GaN layer and the second AlGaN barrier layer, and between the first undoped GaN layer and the first AlGaN barrier layer. These are the upper and lower 2DHG layers, respectively. When a reverse voltage is applied to the first gate G1 and the second gate G2, the upper 2DHG flows to the first gate G1, and the lower 2DHG flows to the second gate G2. At the same time, the 2DEG is led out through the source and drain, respectively. This achieves the depletion of 2DEG and 2DHG in the first and second AlGaN barrier layers, resulting in a more uniform electric field distribution and thus improving the breakdown voltage performance of the device. At the same time, when the device is turned on, the on-resistance decreases and the current increases because it is a dual-channel device.
[0037] In one embodiment, both the source and the drain are made of Ni / Al / Ni / Au metal alloy.
[0038] In one embodiment, both the first gate G1 and the second gate G2 are made of Ni / Au metal alloy.
[0039] Another aspect of this application provides a method for manufacturing the aforementioned dual-channel multi-gate high-voltage GaN HEMT device, comprising the following steps:
[0040] S10, GaN high resistivity layer, GaN channel layer, first AlGaN barrier layer, uGaN-1 layer, AlGaN-2 layer, uGaN-2 layer and pGaN-1 layer are sequentially grown on the substrate layer (preferably sapphire substrate);
[0041] S20, the secondary epitaxial undoped GaN layer uGaN and the secondary epitaxial pGaN layer pGaN-2 are sequentially formed at predetermined positions on the surface of the pGaN-1 layer. More specifically:
[0042] S21, First, the range of the secondary epitaxial pGaN layer pGaN-2 and the secondary epitaxial undoped GaN layer uGaN is etched on the surface of the pGaN-1 layer using a positive photoresist photolithography process. Then, the original AlGaN-2 layer, uGaN-2 layer, and pGaN-1 layer at the positions of the secondary epitaxial pGaN layer pGaN-2 and the secondary epitaxial undoped GaN layer uGaN are removed using ICP etching technology. After etching, the photoresist is removed and the surface is cleaned.
[0043] S22, a SiO2 layer is fabricated on the surface of the pGaN-1 layer using processes such as ALD / PVD / CVD. The patterns of the secondary epitaxial pGaN layer pGaN-2 and the secondary epitaxial undoped GaN layer uGaN are etched using positive photolithography. Then, the SiO2 layer of the patterned portions of the secondary epitaxial pGaN layer pGaN-2 and the secondary epitaxial undoped GaN layer uGaN is removed using wet HF etching. Finally, the photoresist is removed using a cleaning process.
[0044] S23, the second epitaxial undoped GaN layer uGaN and the second epitaxial pGaN layer pGaN-2 are grown sequentially at the positions of the second epitaxial pGaN layer pGaN-2 and the second epitaxial undoped GaN layer uGaN using the MOCVD secondary epitaxial method. Then, the SiO2 layer except for the second epitaxial pGaN layer pGaN-2 is removed by wet HF etching, so that the second epitaxial undoped GaN layer uGaN and the second epitaxial pGaN layer pGaN-2 maintain a gap on their periphery, that is, they do not contact the subsequent second undoped GaN layer and the second AlGaN barrier layer.
[0045] S30, repeating the photolithography, etching, and resist removal and cleaning steps to sequentially form the first pGaN layer, the second undoped GaN layer, and the second AlGaN barrier layer at predetermined positions on the surface of the pGaN-1 layer. That is, firstly, the pattern of the first pGaN layer is photolithographically formed using a positive resist photolithography process, then its pattern is etched using an ICP etching process, and the resist is removed and cleaned. Next, the pattern of the second undoped GaN layer is photolithographically formed using a positive resist photolithography process, then its pattern is etched using an ICP etching process, and the resist is removed and cleaned. Finally, the pattern of the second AlGaN barrier layer is photolithographically formed using a positive resist photolithography process, then its pattern is etched using an ICP etching process, and the resist is removed and cleaned.
[0046] S40, the first gate G1 and the second gate G2 are patterned on the surface of the first pGaN layer and the secondary epitaxial pGaN layer pGaN-2 respectively using a positive photoresist photolithography process. Then, the P-ohmic contact (Ni / Au) is evaporated using a PVD process, stripped and cleaned, and then subjected to RTA annealing to form the first gate G1 and the second gate G2. The RTA annealing environment is an atmospheric environment, and the RTA annealing temperature is 600℃~650℃.
[0047] S50, the source and drain patterns are photolithographically patterned at predetermined positions on the surface of the pGaN-1 layer using a positive photoresist photolithography process. Then, the N-ohm contacts are evaporated using a PVD process, stripped to remove the photoresist, and cleaned. Finally, an RTA annealing process is performed to form the source and drain. The RTA annealing environment is an N2@1SLM environment, and the RTA annealing temperature is 750℃~950℃.
[0048] It should be noted that the terms "first" and "second" used in this application are for descriptive purposes only and do not indicate any order. They should not be construed as indicating or implying relative importance, and can be interpreted as names.
[0049] Those skilled in the art should understand that the embodiments of the present invention described above and shown in the accompanying drawings are merely examples and do not limit the invention. The advantages of the present invention have been fully and effectively realized. The functional and structural principles of the present invention have been demonstrated and explained in the embodiments; any variations or modifications can be made to the implementation of the present invention without departing from these principles.
Claims
1. A dual-channel, multi-gate, high-voltage GaN HEMT device, characterized in that, The device includes a substrate layer and GaN high-resistivity layer, GaN channel layer and first AlGaN barrier layer sequentially grown on the substrate layer. The surface of the first AlGaN barrier layer has a first undoped GaN layer, a second AlGaN barrier layer and a second undoped GaN layer sequentially grown near the middle. A source and a drain are symmetrically formed on both sides of the first undoped GaN layer. The first undoped GaN layer and the second AlGaN barrier layer are connected to the source and the drain at their respective ends. The two ends of the second undoped GaN layer are separated from the source and the drain by a gap. A first pGaN layer and a first gate are sequentially grown on the surface of the second undoped GaN layer. The upper 2DHG is led out through the first gate. The 2DHG generated between the second undoped GaN layer and the second AlGaN barrier layer is the upper 2DHG. On the surface of the first undoped GaN layer, a secondary epitaxial undoped GaN layer, a secondary epitaxial pGaN layer, and a second gate are sequentially grown between the first pGaN layer and the source. The secondary epitaxial pGaN layer and the second gate maintain the same height as the first pGaN layer and the first gate, respectively. The secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer both maintain a gap with the second AlGaN barrier layer and the second undoped GaN layer. The lower 2DHG is led out through the second gate, wherein the 2DHG generated between the first undoped GaN layer and the first AlGaN barrier layer is the lower 2DHG.
2. The dual-channel multi-gate high-voltage GaN HEMT device as described in claim 1, characterized in that, The substrate is a sapphire substrate.
3. The dual-channel multi-gate high-voltage GaN HEMT device as described in claim 1, characterized in that, Both the source and the drain are made of Ni / Al / Ni / Au metal alloy.
4. The dual-channel multi-gate high-voltage GaN HEMT device as described in claim 3, characterized in that, Both the first gate and the second gate are made of Ni / Au metal alloy.
5. A method for manufacturing the dual-channel multi-gate high-voltage GaN HEMT device according to claim 1, characterized in that, Includes the following steps: S10, GaN high resistivity layer, GaN channel layer, first AlGaN barrier layer, uGaN-1 layer, AlGaN-2 layer, uGaN-2 layer and pGaN-1 layer are sequentially grown on the substrate layer; S20, the secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer are sequentially formed at predetermined positions on the surface of the pGaN-1 layer; S30, repeat the photolithography, etching and resist removal cleaning steps to sequentially form the first pGaN layer, the second undoped GaN layer and the second AlGaN barrier layer at predetermined positions on the surface of the pGaN-1 layer; S40, the first gate and the second gate are photolithographically patterned on the surfaces of the first pGaN layer and the secondary epitaxial pGaN layer, respectively. Then, the P-ohm contact is evaporated by PVD process, stripped and cleaned, and then subjected to RTA annealing to form the first gate and the second gate. S50, the source and drain patterns are etched at predetermined positions on the surface of the pGaN-1 layer, then the N-ohm contacts are evaporated using PVD process, stripped and cleaned, and finally subjected to RTA annealing to form the source and drain.
6. The method for manufacturing a dual-channel multi-gate high-voltage GaN HEMT device as described in claim 5, characterized in that, In step S20, the sequential formation of the secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer at predetermined positions on the surface of the pGaN-1 layer specifically includes: S21, using positive photolithography, the area of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer is etched on the surface of the pGaN-1 layer. The original AlGaN-2 layer, uGaN-2 layer, and pGaN-1 layer at the location of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer are removed using ICP etching technology. After etching, the photoresist is removed and the surface is cleaned. S22, a SiO2 layer is fabricated on the surface of the pGaN-1 layer. The patterns of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer are etched using a positive photolithography process. Then, the SiO2 layer of the patterned portion of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer is removed using wet HF etching. Finally, the photoresist is removed using a cleaning process. S23, the secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer are grown sequentially at the positions of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer by MOCVD secondary epitaxy. Then, the SiO2 layer except for the secondary epitaxial pGaN layer is removed by wet HF etching, so that the peripheral sides of the secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer are maintained with voids.
7. The method for manufacturing a dual-channel multi-gate high-voltage GaN HEMT device as described in claim 6, characterized in that, In step S40, the RTA annealing environment is an atmospheric environment, and the RTA annealing temperature is 600℃~650℃.
8. The method for manufacturing a dual-channel multi-gate high-voltage GaN HEMT device as described in claim 6, characterized in that, In step S50, the RTA annealing environment is an N2@1SLM environment, and the RTA annealing temperature is 750℃~950℃.
Citation Information
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