An antistatic LED device and a method of manufacturing the same

Abstract

The application relates to an antistatic LED device and a preparation method thereof. The device structure comprises a substrate layer, a first semiconductor layer, a first stress release layer, a second stress release layer, an active layer, a second semiconductor layer and an electrode layer in sequence, and further comprises a first antistatic layer located between the first stress release layer and the second stress release layer, wherein the first antistatic layer is an n-type doped GaN layer; the first semiconductor layer and the second semiconductor layer are semiconductor layers with opposite conductive types; the silicon doping concentration of the first antistatic layer is different from the silicon doping concentration of the first stress release layer, and the silicon doping concentration of the first antistatic layer is different from the silicon doping concentration of the second stress release layer. The antistatic LED device provided by the application can effectively improve the antistatic ability and electrical performance of the LED device, and further improve the reliability and service life of the device in various applications.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of anti-static LED devices, in particular to an anti-static LED device and a preparation method thereof. BACKGROUND

[0002] Electrostatic discharge (ESD) refers to the phenomenon of instantaneous transfer of electric charge when two objects with different charges are in contact or close to each other. ESD can cause damage to electronic devices and components, so anti-static measures need to be taken during electronic manufacturing and assembly to prevent damage caused by electrostatic discharge.

[0003] For LED products, their ESD resistance cannot be ignored. LED products may be affected by electrostatic discharge during production, transportation and use, resulting in product damage, performance degradation or even failure. Therefore, LED products with good ESD protection capabilities are more popular in the market.

[0004] Human body model (HBM) is a standard method for testing the anti-static capability of electronic components. The anti-static capability (HBM) of large-size LEDs is generally required to reach 5kV, and some high-performance LEDs may reach a higher level to meet the needs of different application scenarios. However, the existing epitaxial structure of LED devices does not have an anti-static structure, so it is easily affected by electrostatic discharge, thereby reducing the electrical performance of the LED device and reducing the reliability and life of the device.

[0005] Therefore, a solution is needed to effectively improve the anti-static capability and electrical performance of LED devices through the design and optimization of LED epitaxial structures, thereby improving the reliability and life of the device in various applications. SUMMARY

[0006] Therefore, the present application provides an anti-static LED device and a preparation method thereof to solve the problem that the existing epitaxial structure of LED devices does not have an anti-static structure, so it is easily affected by electrostatic discharge, thereby reducing the electrical performance of the LED device and reducing the reliability and life of the device.

[0007] The present application provides an anti-static LED device, comprising:

[0008] a substrate layer;

[0009] a first semiconductor layer located on one side of the substrate layer;

[0010] a first stress release layer located on the surface of the first semiconductor layer away from the substrate layer;

[0011] a second stress release layer located on a side of the first stress release layer away from the first semiconductor layer;

[0012] an active layer located on a surface of the second stress release layer away from the first stress release layer;

[0013] a second semiconductor layer located on a surface of the active layer away from the second stress release layer;

[0014] an electrode layer located on a surface of the second semiconductor layer away from the active layer;

[0015] further comprising a first anti-static layer located between the first stress release layer and the second stress release layer, the first anti-static layer being an n-type doped GaN layer;

[0016] wherein the first semiconductor layer and the second semiconductor layer are semiconductor layers of opposite conductivity types; the silicon doping concentration of the first anti-static layer is different from the silicon doping concentration of the first stress release layer, and the silicon doping concentration of the first anti-static layer is different from the silicon doping concentration of the second stress release layer.

[0017] Optionally, the doping concentration of the first anti-static layer is 2E17 / cm 3 ~ 1E19 / cm 3 ;

[0018] The thickness of the first anti-static layer is 2nm~30nm.

[0019] Optionally, the first stress release layer is a superlattice layer composed of first and second sub stress release layers alternately stacked in pairs; the first sub stress release layer is an In x Ga (1-X) N layer, and the second sub stress release layer is a GaN layer, an AlGaN layer or an n-GaN layer;

[0020] The second stress release layer is a superlattice layer composed of third and fourth sub stress release layers alternately stacked in pairs; the third sub stress release layer is an In x Ga (1-X) N layer, and the fourth sub stress release layer is a GaN layer, an AlGaN layer or an n-GaN layer;

[0021] wherein the In content in the second stress release layer is greater than the In content in the first stress release layer; the thickness of the second sub stress release layer is greater than the thickness of the fourth sub stress release layer; and the number of pairs of sub stress release layers in the second stress release layer is greater than the number of pairs of sub stress release layers in the first stress release layer;

[0022] Optionally, the first sub stress release layer and the second sub stress release layer are alternately stacked in pairs, and the number of pairs is 1-20 pairs;

[0023] The third sub stress release layer and the fourth sub stress release layer are alternately stacked in pairs, and the number of pairs is 2-40 pairs;

[0024] The thickness of the first stress release layer is 2-1000 nm, and the thickness of the second stress release layer is 4-2000 nm.

[0025] Optionally, the silicon doping concentration of the first sub stress release layer, the silicon doping concentration of the second sub stress release layer, the silicon doping concentration of the third sub stress release layer, and the silicon doping concentration of the fourth sub stress release layer are the same;

[0026] The silicon doping concentration of the first antistatic layer is greater than the silicon doping concentration of the first stress release layer, and greater than the silicon doping concentration of the second stress release layer;

[0027] Alternatively:

[0028] The silicon doping concentration of the first sub stress release layer, the silicon doping concentration of the second sub stress release layer, the silicon doping concentration of the third sub stress release layer, and the silicon doping concentration of the fourth sub stress release layer are the same;

[0029] The silicon doping concentration of the first antistatic layer is less than the silicon doping concentration of the first stress release layer, and less than the silicon doping concentration of the second stress release layer;

[0030] Alternatively:

[0031] The first sub stress release layer and the third sub stress release layer are doped with silicon, and the second sub stress release layer and the fourth sub stress release layer are not doped with silicon; the silicon doping concentration of the first sub stress release layer and the third sub stress release layer is the same;

[0032] The silicon doping concentration of the first antistatic layer is greater than the silicon doping concentration of the first sub stress release layer, and greater than the silicon doping concentration of the third sub stress release layer;

[0033] Alternatively:

[0034] The first sub stress release layer and the third sub stress release layer are doped with silicon, and the second sub stress release layer and the fourth sub stress release layer are not doped with silicon; the silicon doping concentration of the first sub stress release layer and the third sub stress release layer is the same;

[0035] The silicon doping concentration of the first antistatic layer is less than the silicon doping concentration of the first sub stress release layer, and less than the silicon doping concentration of the third sub stress release layer.

[0036] Optionally, the silicon doping concentration of the first sub stress release layer, the silicon doping concentration of the second sub stress release layer, the silicon doping concentration of the third sub stress release layer and the silicon doping concentration of the fourth sub stress release layer are the same;

[0037] The difference between the silicon doping concentration of the first anti-static layer and the doping concentration of the first stress release layer is 0.1 / cm 3 ~1E3 / cm 3 ;

[0038] The difference between the silicon doping concentration of the first anti-static layer and the doping concentration of the second stress release layer is 0.1 / cm 3 ~1E3 / cm 3 ;

[0039] When the first sub stress release layer and the third sub stress release layer are doped with silicon, the second sub stress release layer and the fourth sub stress release layer are not doped with silicon; the silicon doping concentration of the first sub stress release layer and the third sub stress release layer is the same;

[0040] The difference between the silicon doping concentration of the first anti-static layer and the doping concentration of the first sub stress release layer is 0.1 / cm 3 ~1E3 / cm 3 ;

[0041] The difference between the silicon doping concentration of the first anti-static layer and the doping concentration of the third sub stress release layer is 0.1 / cm 3 ~1E3 / cm 3 .

[0042] Optionally, the anti-static LED device further comprises:

[0043] A second anti-static layer is located between the second stress release layer and the active layer, and the second anti-static layer is an n-type doped GaN layer;

[0044] The doping concentration of the second anti-static layer is 2E17 / cm 3 ~1E19 / cm 3 ;

[0045] The thickness of the second anti-static layer is 2nm~30nm.

[0046] Optionally, the active layer comprises a plurality of first and second multiple quantum well layers which are alternately stacked, the first multiple quantum well layer is In x Ga (1-X) N, and the second multiple quantum well layer is GaN.

[0047] The period of the first and second multiple quantum well layers is 3-10.

[0048] Optionally, the anti-static LED device further comprises:

[0049] A third anti-static layer between the first and second multiple quantum well layers; the third anti-static layer is an n-doped GaN layer.

[0050] The doping concentration of the third anti-static layer is 2E17 / cm 3 -1E19 / cm 3 ;

[0051] The thickness of the third anti-static layer is 2-30 nm.

[0052] Optionally, the anti-static LED device further comprises:

[0053] A first AlN buffer layer on the surface of the substrate layer facing the first semiconductor layer;

[0054] A GaN connecting layer on the surface of the first AlN buffer layer away from the substrate layer; the GaN connecting layer comprises, in order, a GaN nucleation layer, a second AlN buffer layer and an undoped GaN layer away from the first AlN buffer layer.

[0055] Optionally, the thickness of the first semiconductor layer is 1-4 μm, and the doping concentration of the first semiconductor layer is 1E18 / cm 3 -5E19 / cm 3 ;

[0056] The second semiconductor layer comprises, in order, a hole injection layer, an electron blocking layer, a lightly-doped second semiconductor layer and a heavily-doped second semiconductor layer away from the active layer.

[0057] The thickness of the hole injection layer is 10-30 nm, the thickness of the electron blocking layer is 10-30 nm, the thickness of the lightly-doped second semiconductor layer is 10-100 nm, and the thickness of the heavily-doped second semiconductor layer is 5-20 nm.

[0058] The application further provides a preparation method of the anti-static LED device, comprising the following steps: providing a substrate layer; forming an epitaxial layer; sequentially forming a first semiconductor layer, a first stress release layer, a second stress release layer, an active layer and a second semiconductor layer on the surface of the substrate layer; forming an electrode layer on the second semiconductor layer; further comprising: forming a first anti-static layer on the surface of the first stress release layer away from the first semiconductor layer after forming the first stress release layer and before forming the second stress release layer; and forming the second stress release layer on the surface of the first anti-static layer away from the first stress release layer.

[0059] The technical scheme of the application has the following advantages:

[0060] (1) The first anti-static layer (n-doped GaN layer) inserted between the first stress release layer and the second stress release layer can effectively improve the electrical performance and anti-static (ESD) ability of the LED. On the one hand, the n-doped GaN layer has high conductivity, which can improve the transmission efficiency of electrons in the first stress release layer and the second stress release layer, thereby reducing static accumulation and improving the anti-static ability of the LED. On the other hand, the inserted n-doped GaN layer can make the charge in the first stress release layer and the second stress release layer more evenly distributed, reduce local charge accumulation, reduce the risk of electrostatic discharge, improve the electrical performance of the LED, and improve the reliability and service life of the device.

[0061] (2) The second anti-static layer (n-doped GaN layer) inserted between the second stress release layer and the active layer can improve the transmission efficiency of electrons in the second stress release layer and the active layer, thereby reducing static accumulation, and also making the charge in the second stress release layer and the active layer more evenly distributed, reducing local charge accumulation, reducing the risk of electrostatic discharge, and improving the anti-static performance of the LED. In addition, since the active layer is a multi-quantum well structure, the introduction of the second anti-static layer can also optimize the energy band structure of the multi-quantum well, improve the overall electrical performance and static resistance of the multi-quantum well.

[0062] (3) The anti-static LED device provided by the application inserts a third anti-static layer (n-doped GaN layer) between the first multi-quantum well layer and the second multi-quantum well layer, which can optimize the energy band structure of the first multi-quantum well layer and the second multi-quantum well layer, improve the overall electrical performance and static resistance of the LED device. At the same time, the n-doped GaN layer can improve the transmission efficiency of electrons in the first multi-quantum well layer and the second multi-quantum well layer, make the charge in the first multi-quantum well layer and the second multi-quantum well layer more evenly distributed, reduce local charge and static accumulation, reduce the risk of electrostatic discharge, and improve the anti-static performance of the LED.

[0063] The anti-static LED device preparation method provided by the application can prepare the anti-static LED device provided by the application. By inserting the first anti-static layer (n-doped GaN layer) between the first stress release layer and the second stress release layer, the electrical performance and the anti-static (ESD) capability of the LED can be effectively improved. On the one hand, since the n-doped GaN layer has a high conductivity, the transmission efficiency of electrons in the first stress release layer and the second stress release layer can be improved, thereby reducing the static accumulation and improving the anti-static capability of the LED. On the other hand, the inserted n-doped GaN layer can make the charge more uniformly distributed in the first stress release layer and the second stress release layer, reduce the local charge accumulation, reduce the risk of electrostatic discharge, and improve the electrical performance of the LED. BRIEF DESCRIPTION OF DRAWINGS

[0064] In order to more clearly illustrate the specific embodiments of the application or the technical solutions in the prior art, the drawings needed to be used in the specific embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0065] Figure 1 A structure diagram of an anti-static LED device according to an embodiment of the application;

[0066] Figure 2a A result diagram of an anti-static test experiment of a traditional structure;

[0067] Figure 2b A result diagram of an anti-static test experiment according to an embodiment of the application;

[0068] Figure 3 A structure diagram of a first stress release layer according to an embodiment of the application;

[0069] Figure 4 A structure diagram of a second stress release layer according to an embodiment of the application;

[0070] Figure 5a A diagram of a silicon doping concentration according to an embodiment of the application;

[0071] Figure 5b A diagram of another silicon doping concentration according to an embodiment of the application;

[0072] Figure 5c A diagram of still another silicon doping concentration according to an embodiment of the application;

[0073] Figure 5d A diagram of yet another silicon doping concentration according to an embodiment of the application;

[0074] Figure 6 Structure diagram of another anti-static LED device for an embodiment of the present application;

[0075] Figure 7 Structure diagram of an active layer for an embodiment of the present application;

[0076] Figure 8 Structure diagram of another anti-static LED device for an embodiment of the present application;

[0077] Figure 9 Flow diagram of a preparation method of an anti-static LED device for an embodiment of the present application;

[0078] Figure 10 Specific flow diagram of a preparation method of an anti-static LED device for an embodiment of the present application;

[0079] Explanation of reference signs:

[0080] 1 - substrate layer; 2 - first semiconductor layer; 3 - first stress release layer; 31 - first sub stress release layer; 32 - second sub stress release layer; 4 - second stress release layer; 41 - third sub stress release layer; 42 - fourth sub stress release layer; 5 - first anti-static layer; 6 - active layer; 61 - first multi quantum well layer; 62 - second multi quantum well layer; 63 - third anti-static layer; 7 - second semiconductor layer; 8 - electrode layer; 9 - second anti-static layer; 10 - first AlN buffer layer; 11 - GaN connection layer. DETAILED DESCRIPTION

[0081] To solve the problems of high turn-on voltage of the anti-static LED device, small injection current of the device under alternating current signal, and low light intensity and poor light effect of the device, the present application provides an anti-static LED device, which comprises a substrate layer, a first semiconductor layer located on one side of the substrate layer, a first stress release layer located on the surface of the side of the first semiconductor layer away from the substrate layer, a second stress release layer located on the side of the first stress release layer away from the first semiconductor layer, an active layer located on the surface of the side of the second stress release layer away from the first stress release layer, a second semiconductor layer located on the surface of the side of the active layer away from the second stress release layer, and an electrode layer located on the surface of the side of the second semiconductor layer away from the active layer; and further comprises a first anti-static layer located between the first stress release layer and the second stress release layer, wherein the first anti-static layer is an n-type doped GaN layer; the first semiconductor layer and the second semiconductor layer are semiconductor layers with opposite conductive types; the silicon doping concentration of the first anti-static layer is different from the silicon doping concentration of the first stress release layer, and the silicon doping concentration of the first anti-static layer is different from the silicon doping concentration of the second stress release layer.

[0082] The application also provides a method for preparing an anti-static LED device, comprising the following steps: providing a substrate layer; forming an epitaxial layer; sequentially forming a first semiconductor layer, a first stress release layer, a second stress release layer, an active layer and a second semiconductor layer on the surface of the substrate layer; forming an electrode layer on the second semiconductor layer; further comprising: forming a first anti-static layer on the surface of the first stress release layer away from the first semiconductor layer after forming the first stress release layer and before forming the second stress release layer; and forming the second stress release layer on the surface of the first anti-static layer away from the first stress release layer.

[0083] The technical solutions of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application. In the description of the present application, it should be noted that the terms "first", "second", "third" are used for description purposes only, and cannot be understood as indicating or implying relative importance.

[0084] Embodiment 1

[0085] Reference Figure 1 The present embodiment provides an anti-static LED device, comprising:

[0086] a substrate layer 1;

[0087] a first semiconductor layer 2 located on one side of the substrate layer 1;

[0088] a first stress release layer 3 located on the surface of the first semiconductor layer 2 away from the substrate layer 1;

[0089] a second stress release layer 4 located on the side of the first stress release layer 3 away from the first semiconductor layer 2;

[0090] an active layer 6 located on the surface of the second stress release layer 4 away from the first stress release layer 3;

[0091] a second semiconductor layer 7 located on the surface of the active layer 6 away from the second stress release layer 4;

[0092] an electrode layer 8 located on the surface of the second semiconductor layer 7 away from the active layer 6;

[0093] Further comprising: a first anti-static layer 5 located between the first stress release layer 3 and the second stress release layer 4, the first anti-static layer 5 being an n-type doped GaN layer;

[0094] The first semiconductor layer 2 and the second semiconductor layer 7 are semiconductor layers with opposite conductive types; the silicon doping concentration of the first anti-static layer 5 is different from the silicon doping concentration of the first stress release layer 3, and the silicon doping concentration of the first anti-static layer 5 is different from the silicon doping concentration of the second stress release layer 4.

[0095] The present application verifies the improvement effect of the first anti-static layer 5 on the anti-static ability of the LED by experimental design. Two groups of LED samples are made, one group is a traditional structure, and the other group is an improved structure with the first anti-static layer 5 inserted between the first stress release layer 3 and the second stress release layer 4 (refer to the above Figure 1 ). The chip process flow is performed on the two groups of samples, and the standard HBM test is performed, the ESD tolerance ability is compared, if the ESD voltage level cannot be tolerated, the chip will be broken down and appear to be leaking, and the ESD level and yield are evaluated accordingly. In the specific experiment, thousands of chips will be made on the epitaxial wafer, and the sample test is performed, the sample number is 150, and the ESD resistance ability limit value is tested one by one, the whole epitaxial wafer structure is consistent, and the approximate ESD resistance ability of the epitaxial wafer can be obtained after statistics. The experimental results are shown in Figures 2a-2b .

[0096] Figure 2a The test results of the traditional structure are shown in Table 1, Figure 2b The test results of the structure of the present application are shown in Table 2. 4K means that the ESD voltage is applied to 4000V, and then the chip is tested whether it leaks, and if it does not leak, its chip ESD resistance ability can resist to 4K level, and the ESD resistance ability limit value is gradually tested to a larger ESD voltage.

[0097] It can be seen that, compared with the traditional structure, the ESD HBM level of the structure of the present application is improved from less than 4K to 8K, and the ESD HBM level of the whole epitaxial wafer is significantly improved, which proves that the technical scheme of the present application can effectively improve the anti-static ability of the LED.

[0098] The present application can effectively improve the electrical performance and anti-static (ESD) ability of the LED by inserting the first anti-static layer 5 (n-type doped GaN layer) between the first stress release layer 3 and the second stress release layer 4. On the one hand, the n-type doped GaN layer has high electrical conductivity, which can improve the transmission efficiency of electrons in the first stress release layer and the second stress release layer, thereby reducing static accumulation and improving the anti-static ability of the LED. On the other hand, the inserted n-type doped GaN layer can make the charge more evenly distributed in the first stress release layer 3 and the second stress release layer 4, reduce local charge accumulation, reduce the risk of electrostatic discharge, improve the electrical performance of the LED, and improve the reliability and life of the device.

[0099] Further, in the embodiment, the first anti-static layer 5 has a doping concentration of 2E17 / cm 3 ~1E19 / cm 3 The first anti-static layer 5 has a thickness of 2nm~30nm.

[0100] The silicon doping concentration of the first anti-static layer 5 is controlled at 2E17 / cm 3 ~1E19 / cm 3 , which can effectively improve the anti-static ability of the device. If it is lower than 2E17 / cm 3 , there is no obvious silicon doping, which cannot improve the anti-static ability. If it is higher than 1E19 / cm 3 , it will affect the light emitting efficiency of the device.

[0101] When the thickness of the first anti-static layer 5 is 2nm~30nm, the transmission efficiency of the electrons in the first stress release layer 3 and the second stress release layer 4 can be effectively improved, so that the charge is more evenly distributed in the first stress release layer 3 and the second stress release layer 4, the local charge accumulation is reduced, the risk of electrostatic discharge is reduced, and the electrical performance of the LED is improved. If the thickness of the first anti-static layer 5 is less than 2nm, the conductive effect is weak, and it cannot effectively disperse or absorb the charge of electrostatic discharge. If the thickness of the first anti-static layer 5 is greater than 30nm, it may increase the overall resistance and thickness of the LED, affect the electrical performance of the LED, and increase the process difficulty.

[0102] Further, in the embodiment, as shown in Figure 3 , the first stress release layer 3 is a superlattice layer composed of first sub stress release layers 31 and second sub stress release layers 32 alternately stacked in pairs; the first sub stress release layer 31 is an In x Ga (1-X) N layer, and the second sub stress release layer 32 is a GaN layer, an AlGaN layer or an n-GaN layer.

[0103] As shown in Figure 4 , the second stress release layer 4 is a superlattice layer composed of third sub stress release layers 41 and fourth sub stress release layers 42 alternately stacked in pairs; the third sub stress release layer 41 is an In x Ga (1-X) N layer, and the fourth sub stress release layer 42 is a GaN layer, an AlGaN layer or an n-GaN layer.

[0104] Wherein, the In content of the second stress relief layer 4 is greater than the In content of the first stress relief layer 3; the thickness of the second sub-stress relief layer 32 is greater than the thickness of the fourth sub-stress relief layer 42; and the number of pairs of sub-stress relief layers in the second stress relief layer 4 is greater than the number of pairs of sub-stress relief layers in the first stress relief layer 3.

[0105] Furthermore, in this embodiment, the number of pairs of alternating layers of the first sub-stress relief layer 31 and the second sub-stress relief layer 32 is 1 to 20.

[0106] The number of pairs of alternating layers of the third sub-stress relief layer 41 and the fourth sub-stress relief layer 42 is 2 to 40.

[0107] The thickness of the first stress relief layer 3 is 2nm to 1000nm, and the thickness of the second stress relief layer 4 is 4nm to 2000nm.

[0108] Furthermore, in some embodiments, the present invention controls the silicon doping concentration of the first antistatic layer 5 by taking into account different combinations of high and low silicon doping concentrations in the first stress relief layer 3 and the second stress relief layer 4, thereby improving the antistatic capability of the LED.

[0109] In one embodiment, such as Figure 5a As shown, the silicon doping concentration of the first sub-stress relief layer 31, the silicon doping concentration of the second sub-stress relief layer 32, the silicon doping concentration of the third sub-stress relief layer 41, and the silicon doping concentration of the fourth sub-stress relief layer 42 are the same.

[0110] The silicon doping concentration of the first antistatic layer 5 is greater than that of the first stress relief layer 3; and is also greater than that of the second stress relief layer 4.

[0111] By inserting a first antistatic layer 5 (n-type doped GaN layer) into the first stress relief layer 3 and the second stress relief layer 4, and controlling the silicon doping concentration of the first antistatic layer 5 to form a doping concentration difference with the stress relief layers on both sides, the electron transport efficiency can be improved, the antistatic discharge capability of the LED can be significantly improved, and the risk of damage caused by static electricity can be reduced.

[0112] In another embodiment, such as Figure 5b As shown, the silicon doping concentration of the first sub-stress relief layer 31, the silicon doping concentration of the second sub-stress relief layer 32, the silicon doping concentration of the third sub-stress relief layer 41, and the silicon doping concentration of the fourth sub-stress relief layer 42 are the same.

[0113] The silicon doping concentration of the first anti-static layer 5 is less than the silicon doping concentration of the first stress release layer 3 and the silicon doping concentration of the second stress release layer 4;

[0114] By inserting the first anti-static layer 5 (n-type doped GaN layer) in the first stress release layer 3 and the second stress release layer 4 and controlling the silicon doping concentration of the first anti-static layer 5 to form a doping concentration difference with the stress release layers on both sides, the electron transport efficiency can be improved, the anti-static discharge capability of the LED is significantly improved, and the damage risk caused by static electricity is reduced.

[0115] In yet another embodiment, as shown in Figure 5c The first sub-stress release layer 31 and the third sub-stress release layer 41 are doped with silicon, and the second sub-stress release layer 32 and the fourth sub-stress release layer 42 are not doped with silicon; the silicon doping concentration of the first sub-stress release layer 31 and the third sub-stress release layer 41 is the same;

[0116] The silicon doping concentration of the first anti-static layer 5 is greater than the silicon doping concentration of the first sub-stress release layer 31 and the silicon doping concentration of the third sub-stress release layer 41;

[0117] By inserting the first anti-static layer 5 (n-type doped GaN layer) in the first stress release layer 3 and the second stress release layer 4 and controlling the silicon doping concentration of the first anti-static layer 5 to form a doping concentration difference with the first sub-stress release layer 31 and the third sub-stress release layer 41 respectively, the electron transport efficiency can be improved, the anti-static discharge capability of the LED is significantly improved, the damage risk caused by static electricity is reduced, the durability and life of the LED are improved, and the early failure caused by static electricity and other electrical stress is reduced.

[0118] In yet another embodiment, as shown in Figure 5d The first sub-stress release layer 31 and the third sub-stress release layer 41 are doped with silicon, and the second sub-stress release layer 32 and the fourth sub-stress release layer 42 are not doped with silicon; the silicon doping concentration of the first sub-stress release layer 31 and the third sub-stress release layer 41 is the same;

[0119] The silicon doping concentration of the first anti-static layer 5 is less than the silicon doping concentration of the first sub-stress release layer 31 and the silicon doping concentration of the third sub-stress release layer 32.

[0120] By inserting the first anti-static layer 5 (n-type doped GaN layer) in the first stress release layer 3 and the second stress release layer 4 and controlling the silicon doping concentration of the first anti-static layer 5 to form a doping concentration difference with the first sub-stress release layer 31 and the third sub-stress release layer 41 respectively, the electron transport efficiency can be improved, the anti-static discharge capability of the LED is significantly improved,

[0121] Further, in the present embodiment, when the silicon doping concentration of the first sub stress release layer 31, the silicon doping concentration of the second sub stress release layer 32, the silicon doping concentration of the third sub stress release layer 41 and the silicon doping concentration of the fourth sub stress release layer 42 are the same (i.e. the case of the above Figure 5a and Figure 5b ),

[0122] The difference between the silicon doping concentration of the first antistatic layer 5 and the doping concentration of the first stress release layer 3 is 0.1 / cm 3 ~ 1E3 / cm 3 .

[0123] The difference between the silicon doping concentration of the first antistatic layer 5 and the doping concentration of the second stress release layer 4 is 0.1 / cm 3 ~ 1E3 / cm 3 .

[0124] When the difference between the silicon doping concentration of the first antistatic layer 5 and the silicon doping concentration of the first stress release layer 3 and the difference between the silicon doping concentration of the first antistatic layer 5 and the silicon doping concentration of the first stress release layer 3 are controlled at 0.1 / cm 3 ~ 1E3 / cm 3 , the antistatic ability of the device can be effectively improved. If it is lower than 0.1 / cm 3 , the antistatic ability cannot be improved. If it is higher than 1E3 / cm 3 , the luminous efficiency of the device will be affected.

[0125] Further, in the present embodiment, when the first sub stress release layer 31 and the third sub stress release layer 41 are doped with silicon, the second sub stress release layer 32 and the fourth sub stress release layer 42 are not doped with silicon; the silicon doping concentration of the first sub stress release layer 31 and the third sub stress release layer 41 are the same (i.e. the case of the above Figure 5c and Figure 5d );

[0126] The difference between the silicon doping concentration of the first antistatic layer 5 and the doping concentration of the first sub stress release layer 31 is 0.1 / cm 3 ~ 1E3 / cm 3 .

[0127] The difference between the silicon doping concentration of the first antistatic layer 5 and the doping concentration of the third sub stress release layer 41 is 0.1 / cm 3 ~ 1E3 / cm 3 .

[0128] The difference between the silicon doping concentration of the first anti-static layer 5 and the first sub stress release layer 31 and the difference between the silicon doping concentration of the first anti-static layer 5 and the third sub stress release layer 41 is controlled at 0.1 / cm 3 ~1E3 / cm 3 When the difference between the silicon doping concentration of the first anti-static layer 5 and the first sub stress release layer 31 and the difference between the silicon doping concentration of the first anti-static layer 5 and the third sub stress release layer 41 is less than 0.1 / cm 3 , the anti-static capability cannot be improved, and if it is higher than 1E3 / cm 3 , the light emitting efficiency will be affected.

[0129] Further, in some embodiments, as shown in Figure 6 , the anti-static LED device further comprises:

[0130] A second anti-static layer 9 is located between the second stress release layer 4 and the active layer 6, and the second anti-static layer 9 is an n-type doped GaN layer.

[0131] The doping concentration of the second anti-static layer 9 is 2E17 / cm 3 ~1E19 / cm 3 , and the thickness of the second anti-static layer 9 is 2nm~30nm.

[0132] The silicon doping concentration of the second anti-static layer 9 is controlled at 2E17 / cm 3 ~1E19 / cm 3 , which can effectively improve the anti-static capability of the device, and if it is less than 2E17 / cm 3 , the anti-static capability cannot be improved, and if it is higher than 1E19 / cm 3 , the light emitting efficiency of the device will be affected.

[0133] When the thickness of the second anti-static layer 9 is 2nm~30nm, the transmission efficiency of electrons in the second stress release layer 4 and the active layer 6 can be effectively improved, the charge distribution in the second stress release layer 4 and the active layer 6 is more uniform, the risk of electrostatic discharge is reduced, and the electrical performance of the LED is improved. If the thickness of the second anti-static layer 9 is less than 2nm, the conductivity is weak and cannot effectively disperse or absorb the charge of electrostatic discharge; if the thickness of the second anti-static layer 9 is greater than 30nm, the overall resistance and thickness of the LED may be increased, affecting the electrical performance of the LED and increasing the process difficulty.

[0134] This embodiment improves electron transport efficiency between the second stress relief layer 4 and the active layer 6 by inserting a second antistatic layer 9 (n-type doped GaN layer) between them, thereby reducing electrostatic accumulation. It also makes the charge distribution between the second stress relief layer 4 and the active layer 6 more uniform, reducing localized charge accumulation, lowering the risk of electrostatic discharge, and improving the LED's antistatic performance. Furthermore, since the active layer 6 has a multi-quantum-well structure, the introduction of the second antistatic layer 9 can optimize the band structure of the multi-quantum-well, improving its overall electrical performance and electrostatic tolerance.

[0135] Furthermore, in some embodiments, such as Figure 7 As shown, the active layer 6 includes multiple alternating layers of first multiple quantum well layers 61 and second multiple quantum well layers 62, wherein the first multiple quantum well layer is In x Ga (1-X) N, where the second quantum well layer is GaN;

[0136] The alternating stacking period of the first quantum well layer 61 and the second quantum well layer 62 is 3 to 10.

[0137] Furthermore, such as Figure 7 As shown, in some embodiments, the antistatic LED device further includes:

[0138] The third antistatic layer 63 is located between the first quantum well layer 61 and the second quantum well layer 62; the third antistatic layer 63 is an n-type doped GaN layer.

[0139] In specific implementation, a third antistatic layer 63 can be inserted between any two layers of the alternatingly stacked first multi-quantum well layer 61 and second multi-quantum well layer 62, or multiple layers of the third antistatic layer 63 can be inserted at multiple locations of the alternating stacking. This embodiment does not limit the scope of the comparison.

[0140] The doping concentration of the third antistatic layer 63 is 2E17 / cm³. 3 ~1E19 / cm 3 The thickness of the third antistatic layer 63 is 2nm to 30nm.

[0141] The silicon doping concentration of the third antistatic layer 63 is controlled at 2E17 / cm. 3 ~1E19 / cm 3 When this is done, it can effectively improve the anti-static capability of the device. If it is below 2E17 / cm 3 If it exceeds 1E19 / cm, it will not improve the antistatic ability. 3 This will affect the luminous efficiency of the device.

[0142] When the thickness of the third anti-static layer 63 is 2nm-30nm, the transmission efficiency of electrons in the first and second multi-quantum well layers 61 and 62 can be effectively improved, the charge distribution in the first and second multi-quantum well layers 61 and 62 is more uniform, the risk of electrostatic discharge is reduced, and the electrical performance of the LED is improved. If the thickness of the third anti-static layer 63 is less than 2nm, the conductive effect is weak, and the charge of electrostatic discharge cannot be effectively dispersed or absorbed; if the thickness of the first anti-static layer 63 is greater than 30nm, the overall resistance and thickness of the LED may be increased, the electrical performance of the LED is affected, and the process difficulty is increased.

[0143] The embodiment inserts the third anti-static layer 63 (n-type doped GaN layer) between the first and second multi-quantum well layers 61 and 62, which can optimize the energy band structure of the first and second multi-quantum well layers 61 and 62, improve the electrical performance and electrostatic resistance of the LED device. At the same time, the n-type doped GaN layer can improve the transmission efficiency of electrons in the first and second multi-quantum well layers 61 and 62, make the charge distribution of the first and second multi-quantum well layers 61 and 62 more uniform, reduce the accumulation of local charge and static electricity, reduce the risk of electrostatic discharge, and improve the anti-static performance of the LED.

[0144] Further, in the embodiment, as shown in Figure 8 the anti-static LED device further comprises:

[0145] a first AlN buffer layer 10 located on the surface of the substrate layer 1 towards the first semiconductor layer 2;

[0146] a GaN connection layer 11 located on the surface of the first AlN buffer layer 10 away from the substrate layer 1; the GaN connection layer comprises a GaN nucleation layer, a second AlN buffer layer and an undoped GaN layer in turn away from the first AlN buffer layer 10.

[0147] Further, in the embodiment, the thickness of the first semiconductor layer 2 is 1μm-4μm, and the doping concentration of the first semiconductor layer 2 is 1E18 / cm 3 -5E19 / cm 3 ;

[0148] The second semiconductor layer 7 comprises a hole injection layer, an electron blocking layer, a lightly doped second semiconductor layer and a heavily doped second semiconductor layer in turn away from the active layer;

[0149] The thickness of the hole injection layer is 10-30 nm, the thickness of the electron blocking layer is 10-30 nm, the thickness of the lightly doped second semiconductor layer is 10-100 nm, and the thickness of the heavily doped second semiconductor layer is 5-20 nm.

[0150] Embodiment 2

[0151] Reference Figure 9 The application further provides a method for preparing the anti-static LED device of Embodiment 1, comprising the following steps:

[0152] S101, providing a substrate layer;

[0153] S102, forming an epitaxial layer: sequentially growing a first semiconductor layer, a first stress release layer, a first anti-static layer, a second stress release layer, an active layer and a second semiconductor layer on the surface of the substrate layer;

[0154] S103, forming an electrode layer on the second semiconductor layer.

[0155] In the embodiment, the first anti-static layer is formed on the surface of the first stress release layer away from the first semiconductor layer after the formation of the first stress release layer and before the formation of the second stress release layer; and the second stress release layer is formed on the surface of the first anti-static layer away from the first stress release layer.

[0156] The method for preparing the anti-static LED device can be used to prepare the anti-static LED device. The first anti-static layer (n-type doped GaN layer) is inserted between the first stress release layer and the second stress release layer, which can effectively improve the electrical performance and the anti-static (ESD) ability of the LED. On the one hand, the n-type doped GaN layer has high conductivity, which can improve the transmission efficiency of electrons in the first stress release layer and the second stress release layer, thereby reducing the static accumulation and improving the anti-static ability of the LED. On the other hand, the inserted n-type doped GaN layer can make the charge more evenly distributed in the first stress release layer and the second stress release layer, reduce the local charge accumulation, reduce the risk of electrostatic discharge, and improve the electrical performance of the LED.

[0157] Embodiment 3

[0158] Reference Figure 10 The application further provides a specific method for preparing the anti-static LED device, which is used to prepare the anti-static LED device of Embodiment 1, and specifically comprises the following steps:

[0159] S201, depositing a first AlN buffer layer on a substrate using PVD (Physical Vapor Deposition). The general substrate is sapphire material with a size of 4 inches, 6 inches or larger, and silicon or silicon carbide material substrate can also be used, the substrate surface is flat or has a patterned design, and AlN material is first deposited on the substrate using PVD, and the thickness of AlN is 10 nm to 30 nm.

[0160] S202, epitaxially growing a GaN buffer layer on the substrate using MOCVD (Metal Organic Chemical Vapor Deposition). The substrate buffer layer includes three layers of materials: 1) a low-temperature GaN nucleation layer (growth temperature: 500-550°C, TMGa (trimethyl gallium) and NH3 (ammonia) sources are introduced); 2) a second AlN buffer layer (growth temperature: 900-1100°C, TMAl (trimethyl aluminum) and NH3 (ammonia) sources are introduced); 3) an undoped GaN layer (growth temperature: 1000-1100°C, TMGa (trimethyl gallium) and NH3 (ammonia) sources are introduced). The thickness of this layer is between 1 μm and 2.5 μm.

[0161] S203, growing a first semiconductor layer n-GaN layer using MOCVD. The thickness of n-GaN is between 1 μm and 4 μm (growth temperature: 1000-1200°C, TMGa (trimethyl gallium) and NH3 (ammonia) sources are introduced), and silicon is used as the n-type doping atom, and the silicon doping concentration is in the range of 1E18 / cm 3 to 5E19 / cm 3 .

[0162] S204, growing a first stress release layer using MOCVD. The first stress release layer includes 1-20 pairs of In x Ga (1-X) N and GaN (or AlGaN or n-GaN) superlattices, the Ga source in the material is TMGa (trimethyl gallium) or TEGa (triethyl gallium), the In source is TMIn (trimethyl indium), the proportion of indium x is 0.1-5%, the thickness of In x Ga (1-X) N is 1 nm to 10 nm, and the thickness of GaN (or AlGaN or n-GaN) is 1 nm to 40 nm.

[0163] S205, growing a first antistatic layer using MOCVD. The first antistatic layer is an n-type doped GaN layer, the growth temperature is 760-900 degrees, the silicon doping concentration is in the range of 2E17 / cm 3 to 1E19 / cm 3 , and the thickness is 2 nm to 30 nm.

[0164] S206, growing the second stress release layer using MOCVD. The second stress release layer is composed of 2-40 pairs of In x Ga (1-X) N and GaN (or AlGaN or n-GaN), the Ga source in the material is TMGa (trimethyl gallium) or TEGa (triethyl gallium), the In source is TMIn (trimethyl indium), the proportion of indium x is 5-25%, the thickness of In x Ga (1-X) N is 1 nm-10 nm, and the thickness of GaN (or AlGaN or n-GaN) is 1 nm-40 nm.

[0165] S207, growing the light-emitting active layer structure using MOCVD. The light-emitting active layer is a multiple quantum well structure composed of In x Ga (1-X) N and GaN, the period is 3-10, the indium component is 10-30%, the thickness of In x Ga (1-X) N is 2 nm-4 nm, and the thickness of GaN is 10 nm-15 nm.

[0166] S208, growing the second semiconductor layer p-GaN using MOCVD. The p-GaN is composed of the following layers in sequence: a p-GaN hole injection layer, an electron blocking layer, a lightly doped p-GaN layer, and a heavily doped p-GaN layer. The thickness of the p-GaN hole injection layer is 10 nm-30 nm, the Mg doping concentration is 5E18 / cm 3 -2E20 / cm 3 ; the electron blocking layer is composed of Mg-doped AlGaN, the thickness of the electron blocking layer is 10 nm-30 nm; the thickness of the lightly doped p-GaN is 10 nm-100 nm, the Mg doping concentration is 5E18 / cm 3 -1E19 / cm 3 ; the thickness of the heavily doped p-GaN is 5 nm-20 nm, the Mg doping concentration is 5E19 / cm 3 -5E20 / cm 3 .

[0167] S209, chip processing. Cleaning → evaporation of a transparent electrode layer → transparent electrode pattern photolithography → etching → glue removal → platform pattern photolithography → dry etching → glue removal → annealing → SiO2 deposition → window pattern photolithography → SiO2 etching → glue removal → N-pole pattern photolithography → pre-cleaning → film plating → stripping → annealing → P-pole pattern photolithography → film plating → stripping → grinding → cutting → chip → finished product testing.

[0168] S210, chip EL test. Different currents and voltages are applied to obtain the electrical characteristics (such as turn-on voltage, leakage current, etc.) and light-emitting characteristics (wavelength, external quantum efficiency EQE, etc.) of the chip. In addition, the anti-static capability in MM (machine model) and HBM modes is tested to obtain the anti-static yield of the LED.

[0169] Obviously, the above embodiments are only examples for clearly illustrating the present application, and are not intended to limit the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. All the embodiments are not required to be enumerated here. The changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. An antistatic LED device, characterized by, The LED device comprises: a substrate layer; a first semiconductor layer located on one side of the substrate layer; a first stress release layer located on the side surface of the first semiconductor layer away from the substrate layer; a second stress release layer located on the side of the first stress release layer away from the first semiconductor layer; an active layer located on the side surface of the second stress release layer away from the first stress release layer; a second semiconductor layer located on the side surface of the active layer away from the second stress release layer; an electrode layer located on the side surface of the second semiconductor layer away from the active layer; The LED device further comprises: a first anti-static layer located between the first stress release layer and the second stress release layer, the first anti-static layer being an n-type doped GaN layer; wherein the first semiconductor layer and the second semiconductor layer are semiconductor layers with opposite conductive types; the silicon doping concentration of the first anti-static layer is different from the silicon doping concentration of the first stress release layer, and the silicon doping concentration of the first anti-static layer is different from the silicon doping concentration of the second stress release layer; The anti-static LED device further comprises: The active layer comprises a plurality of first and second multiple quantum well layers alternately stacked, the first multiple quantum well layer is In x Ga (1-X) N, and the second multiple quantum well layer is GaN. a second anti-static layer located between the second stress release layer and the active layer, the second anti-static layer being an n-type doped GaN layer; The anti-static LED device further comprises: a third anti-static layer located between the first multi-quantum well layer and the second multi-quantum well layer, the third anti-static layer being an n-type doped GaN layer. The first antistatic layer has a doping concentration of 2E17 / cm 3 1E19 / cm 3 ; 2. The anti-static LED device according to claim 1, wherein the thickness of the first anti-static layer is 2 nm to 30 nm. The first stress relief layer is a superlattice layer composed of alternating layers of a first sub-stress relief layer and a second sub-stress relief layer; the first sub-stress relief layer is In x Ga (1-X) N-layer, the second sub-stress relief layer is a GaN layer, an AlGaN layer or an n-GaN layer; The second stress release layer is a superlattice layer composed of pairs of alternately stacked third and fourth sub stress release layers; the third sub stress release layer is an InGaN layer, and the fourth sub stress release layer is a GaN layer, an AlGaN layer or an n-GaN layer. x Ga (1-X) N layer, and the fourth sub stress release layer is a GaN layer, an AlGaN layer or an n-GaN layer.

3. The anti-static LED device according to claim 1, wherein wherein the In content in the second stress release layer is greater than the In content in the first stress release layer; the thickness of the second sub-stress release layer is greater than the thickness of the fourth sub-stress release layer; and the number of pairs of the sub-stress release layers in the second stress release layer is greater than the number of pairs of the sub-stress release layers in the first stress release layer.

4. The anti-static LED device according to claim 3, wherein the number of pairs of the first sub-stress release layer and the second sub-stress release layer alternately stacked in pairs is 1 pair to 20 pairs; the number of pairs of the third sub-stress release layer and the fourth sub-stress release layer alternately stacked in pairs is 2 pairs to 40 pairs; the thickness of the first stress release layer is 2 nm to 1000 nm, and the thickness of the second stress release layer is 4 nm to 2000 nm.

5. The anti-static LED device according to claim 4, wherein the silicon doping concentration of the first sub-stress release layer, the silicon doping concentration of the second sub-stress release layer, the silicon doping concentration of the third sub-stress release layer, and the silicon doping concentration of the fourth sub-stress release layer are the same; the silicon doping concentration of the first anti-static layer is greater than the silicon doping concentration of the first stress release layer, and is greater than the silicon doping concentration of the second stress release layer; or The silicon doping concentration of the first sub stress release layer, the silicon doping concentration of the second sub stress release layer, the silicon doping concentration of the third sub stress release layer and the silicon doping concentration of the fourth sub stress release layer are the same; The silicon doping concentration of the first anti-static layer is less than the silicon doping concentration of the first stress release layer and the silicon doping concentration of the second stress release layer; Or: The first sub stress release layer and the third sub stress release layer are doped with silicon, and the second sub stress release layer and the fourth sub stress release layer are not doped with silicon; the silicon doping concentration of the first sub stress release layer and the third sub stress release layer is the same; The silicon doping concentration of the first anti-static layer is greater than the silicon doping concentration of the first sub stress release layer and the silicon doping concentration of the third sub stress release layer; Or: The first sub stress release layer and the third sub stress release layer are doped with silicon, and the second sub stress release layer and the fourth sub stress release layer are not doped with silicon; the silicon doping concentration of the first sub stress release layer and the third sub stress release layer is the same; The silicon doping concentration of the first anti-static layer is less than the silicon doping concentration of the first sub stress release layer and the silicon doping concentration of the third sub stress release layer.

6. The anti-static LED device according to claim 5, wherein, when the silicon doping concentration of the first sub stress release layer, the silicon doping concentration of the second sub stress release layer, the silicon doping concentration of the third sub stress release layer and the silicon doping concentration of the fourth sub stress release layer are the same; a difference between the silicon doping concentration of the first antistatic layer and the doping concentration of the first stress release layer is 0.1 / cm 3 1E3 / cm 3 ; The difference between the silicon doping concentration of the first antistatic layer and the doping concentration of the second stress release layer is 0.1 / cm 3 1E3 / cm 3 ; when the first sub stress release layer and the third sub stress release layer are doped with silicon, and the second sub stress release layer and the fourth sub stress release layer are not doped with silicon; the silicon doping concentration of the first sub stress release layer and the third sub stress release layer is the same; The difference between the silicon doping concentration of the first antistatic layer and the doping concentration of the first sub-stress release layer is 0.1 / cm 3 1E3 / cm 3 ; The difference between the silicon doping concentration of the first antistatic layer and the doping concentration of the third sub-stress release layer is 0.1 / cm 3 1E3 / cm 3 .

7. The anti-static LED device according to claim 1, wherein, The second antistatic layer has a doping concentration of 2E17 / cm 3 1E19 / cm 3 ; The thickness of the second anti-static layer is 2nm-30nm.

8. The anti-static LED device according to claim 1, wherein, The alternating layering period of the first multi-quantum well layer and the second multi-quantum well layer is 3-10.

9. The anti-static LED device according to claim 8, wherein, The third antistatic layer has a doping concentration of 2E17 / cm 3 1E19 / cm 3 ; The thickness of the third anti-static layer is 2nm-30nm.

10. The anti-static LED device according to claim 1, wherein, The anti-static LED device further comprises: A first AlN buffer layer located on the surface of the substrate layer towards the first semiconductor layer side; A GaN connection layer located on the surface of the first AlN buffer layer away from the substrate layer side; the GaN connection layer in the direction away from the first AlN buffer layer comprises a GaN nucleation layer, a second AlN buffer layer and an undoped GaN layer in sequence.

11. The anti-static LED device according to claim 1, wherein, The thickness of the first semiconductor layer is 1 μm ~ 4 μm, and the doping concentration of the first semiconductor layer is 1E18 / cm 3 ~ 5E19 / cm 3 ; The second semiconductor layer in the direction away from the active layer comprises a hole injection layer, an electron blocking layer, a lightly doped second semiconductor layer and a heavily doped second semiconductor layer in sequence. The thickness of the hole injection layer is 10-30 nm, the thickness of the electron blocking layer is 10-30 nm, the thickness of the lightly doped second semiconductor layer is 10-100 nm, and the thickness of the heavily doped second semiconductor layer is 5-20 nm.

12. A method of manufacturing an antistatic LED device, characterized by, A method for preparing an antistatic LED device as claimed in any one of claims 1-11, comprising the steps of: providing a substrate layer; forming an epitaxial layer: sequentially forming a first semiconductor layer, a first stress release layer, a second stress release layer, an active layer and a second semiconductor layer on the surface of the substrate layer; forming an electrode layer on the second semiconductor layer; Further comprising: forming a first antistatic layer on the surface of the first stress release layer away from the first semiconductor layer after forming the first stress release layer and before forming the second stress release layer; and forming the second stress release layer on the surface of the first antistatic layer away from the first stress release layer.

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