Data receiving device, method and electronic equipment with clock synchronization

Abstract

The present invention discloses a data receiving device, method and electronic device with clock synchronization, wherein a clock edge detector detects the clock edge corresponding to input data to generate a pulse signal, a clock processing unit calculates a recovery clock signal and a system clock signal according to the pulse signal, a clock splitting unit splits the recovery clock signal into a first recovery clock signal and a second recovery clock signal, a clock downconverter downconverts the system clock signal into a first system clock signal and a second system clock signal, a sampling unit samples the input data respectively through the first recovery clock signal and the second recovery clock signal to obtain initial data, and samples the initial data respectively through the first system clock signal and the second system clock signal to obtain first synchronization data and second synchronization data. The present invention collects data respectively through multiple system clock signals, thereby improving the time margin of data sampling and the accuracy of data received by the receiving end.

Description

Technical Field

[0001] The present invention relates to the field of data processing, and in particular to a data receiving device, method and electronic equipment with clock synchronization. Background Art

[0002] As people's requirements for high-pixel video and high-fidelity audio increase, the requirements for data transmission speed and reliability continue to increase. Data transmission chips are the key technology to solve data interconnection. Their main function is to send data from the transmitter chip A to the receiver chip B through the transmission line. In the traditional data transmission process, in order for the receiver to correctly collect data, the transmitter must not only send data, but also send a clock with a certain phase relationship with the data. The receiver uses the received clock signal to sample the received data signal and synchronize it to the local clock domain for subsequent clock processing.

[0003] In the prior art, the receiving chip will recover the clock information of the data through the data signal of the transmitting end. The chip of the transmitting end and the chip of the receiving end work in independent system clock domains. The receiving end can correctly collect the transmitted data by recovering the clock signal of the transmitting end. However, this system clock synchronization is limited by the noise of the phase-locked loop of the transmitting end and the receiving end, the frequency of the reference clock and the tracking bandwidth of the phase-locked loop of the receiving end. Its clock synchronization will have a certain clock jitter. When the clock jitter is greater than the sampling time margin, it will affect the accuracy of data sampling. Summary of the invention

[0004] The embodiments of the present invention provide a data receiving device, method and electronic device for clock synchronization, so as to improve the accuracy of data received by a receiving end.

[0005] An embodiment of the present invention provides a data receiving device with clock synchronization, comprising: a clock edge detector, a clock processing unit, a clock splitting unit, a clock frequency reducer and a sampling unit;

[0006] The clock edge detector is used to detect the clock edge corresponding to the received input data to generate a clock edge pulse signal, wherein the clock edge pulse signal includes a leading pulse signal and a data pulse signal;

[0007] The clock processing unit is used to obtain the recovery clock signal and the system clock signal of the data receiving device according to the leading pulse signal and the data pulse signal in the clock edge pulse signal;

[0008] The clock splitting unit is used to split the recovered clock signal into at least a first recovered clock signal and a second recovered clock signal, and the clock downconverter is used to downconvert the system clock signal into a first system clock signal and a second system clock signal;

[0009] The sampling unit is used to sample the input data respectively through the first recovered clock signal and the second recovered clock signal to obtain the first initial data and the second initial data, and to sample the first initial data and the second initial data respectively through the first system clock signal and the second system clock signal to obtain the first synchronization data and the second synchronization data.

[0010] In one embodiment, the clock processing unit includes a first clock processing unit and a second clock processing unit;

[0011] The first clock processing unit is used to delay the data pulse signal according to two preset clock cycles respectively, and merge the two delayed sub-clock signals with different phases to obtain the recovered clock signal;

[0012] The second clock processing unit is used to generate a reference clock signal according to the time when the pulse signal is input, and calculate a system clock signal with the same frequency and phase as the reference clock signal.

[0013] In one embodiment, the first clock processing unit includes a preamble signal filtering unit, a clock delay unit, and a clock synthesis unit;

[0014] The leading signal filtering unit is used to filter out the leading pulse signal in the pulse signal to obtain a data pulse signal;

[0015] The clock delayer is used to process the data pulse signal according to the delay control code corresponding to two preset clock cycles to obtain two sub-clock signals with different phases;

[0016] The clock synthesis unit is used to perform a logic OR operation on two sub-clock signals to obtain a combined recovery clock signal.

[0017] In one embodiment, the first clock processing unit further includes a data signal filtering unit, a time-to-digital converter, and a phase difference calculation logic unit;

[0018] The data signal filtering unit is used to filter out the data pulse signal in the pulse signal to obtain a leading pulse signal;

[0019] The time-to-digital converter is used to calculate the system clock cycle according to the leading pulse signal and convert the system clock cycle into a digital signal;

[0020] The phase difference calculation logic unit is used to calculate the delay control code corresponding to two preset clock cycles according to the digital signal.

[0021] In one embodiment, the second clock processing unit includes a reference clock generating unit and a data receiver system clock unit;

[0022] The reference clock generating unit is used to generate a reference clock signal according to the first input moment of the pulse signal;

[0023] The data receiver system clock unit is used to calculate the phase difference between the reference clock signal and the pilot pulse signal, and generate a system clock signal with the same frequency and the same phase as the reference clock signal based on the phase difference.

[0024] In one embodiment, the sampling unit includes a first data sampling unit, a second data sampling unit, a first clock synchronization sampling unit, and a second clock synchronization sampling unit;

[0025] The first data sampling unit is used to sample input data through a first recovered clock signal to obtain first initial data;

[0026] The second data sampling unit is used to sample the input data through the second recovered clock signal to obtain second initial data;

[0027] The first clock synchronization sampling unit is used to sample the first initial data through the first system clock signal to obtain the first synchronization data;

[0028] The second clock synchronization sampling unit is used to sample the second initial data through the second system clock signal to obtain second synchronization data.

[0029] In one embodiment, the device further comprises:

[0030] The data merging unit is used to output the first synchronization data when the first system clock signal is at a high level, and to output the second synchronization data when the second system clock signal is at a high level.

[0031] In one embodiment, the frequency of the first recovered clock signal and the second recovered clock signal is half of the recovered clock signal, and the phase difference is 180 degrees, and the frequency of the first system clock signal and the second system clock signal is half of the system clock signal, and the phase difference is 180 degrees.

[0032] The embodiment of the present invention further provides a data receiving method with clock synchronization, comprising the following steps:

[0033] Detecting a clock edge corresponding to the received input data to generate a clock edge pulse signal, wherein the clock edge pulse signal includes a leading pulse signal and a data pulse signal;

[0034] Obtaining a recovery clock signal and a system clock signal of the data receiving device according to the leading pulse signal and the data pulse signal in the clock edge pulse signal;

[0035] Splitting the recovered clock signal into at least a first recovered clock signal and a second recovered clock signal, and down-converting the system clock signal into a first system clock signal and a second system clock signal;

[0036] The input data is sampled by the first recovery clock signal and the second recovery clock signal respectively to obtain the first initial data and the second initial data, and the first initial data and the second initial data are sampled by the first system clock signal and the second system clock signal respectively to obtain the first synchronization data and the second synchronization data.

[0037] An embodiment of the present invention further provides an electronic device, comprising any one of the above-mentioned data receiving devices with clock synchronization.

[0038] As can be seen from the above, the data receiving device with clock synchronization provided by the embodiment of the present application includes a clock edge detector, a clock processing unit, a clock splitting unit, a clock downconverter and a sampling unit, the clock edge detector is used to detect the clock edge corresponding to the received input data to generate a pulse signal, the clock processing unit is used to calculate the recovery clock signal and the system clock signal according to the pulse signal, the clock splitting unit is used to split the recovery clock signal into a first recovery clock signal and a second recovery clock signal, the clock downconverter is used to downconvert the system clock signal into a first system clock signal and a second system clock signal, and the sampling unit is used to sample the input data respectively through the first recovery clock signal and the second recovery clock signal to obtain the first initial data and the second initial data, and sample the first initial data and the second initial data respectively through the first system clock signal and the second system clock signal to obtain the first synchronization data and the second synchronization data. The present invention collects data respectively through multiple system clock signals, improves the data width and the time margin of data sampling, reduces the clock noise requirements, and improves the accuracy of data received by the receiving end. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 It is a structural schematic diagram of a data receiving device with clock synchronization provided by the present invention;

[0041] Figure 2It is another structural schematic diagram of the data receiving device with clock synchronization provided by the present invention;

[0042] Figure 3 It is another structural schematic diagram of a data receiving device with clock synchronization provided by the present invention;

[0043] Figure 4 It is a schematic diagram of a signal processing flow provided by the present invention;

[0044] Figure 5 is another signal processing flow diagram provided by the present invention;

[0045] Figure 6 It is another signal processing flow diagram provided by the present invention;

[0046] Figure 7 It is a flow chart of a data receiving method with clock synchronization provided by the present invention. DETAILED DESCRIPTION

[0047] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0048] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0049] It should be understood that, although the various steps in the flowchart in the embodiment of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily performed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and it can be performed in other orders. Moreover, at least a portion of the steps in the figure may include a plurality of sub-steps or a plurality of stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and their execution order is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0050] It should be noted that, in this article, step codes such as 101, 102, etc. are used for the purpose of expressing the corresponding content more clearly and concisely, and do not constitute a substantial limitation on the sequence. When implementing the step, those skilled in the art may execute 102 first and then 101, etc., but these should all be within the scope of protection of this application.

[0051] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0052] like Figure 1 As shown, Figure 1 It is a structural schematic diagram of a data receiving device with clock synchronization provided by an embodiment of the present invention, and the data receiving device with clock synchronization includes: a clock edge detector, a clock processing unit, a clock splitting unit, a clock downconverter and a sampling unit.

[0053] The clock edge detector is used to detect the clock edge corresponding to the received input data to generate a clock edge pulse signal, wherein the clock edge pulse signal includes a leading pulse signal and a data pulse signal. The leading pulse signal is used to generate a reference clock and a clock cycle of the measured data at the receiving end, so that the receiving end and the transmitting end can establish synchronization. The data pulse signal refers to a pulse signal that carries actual data information. Specifically, the data pulse signal can represent specific information through a combination of its high level and low level (or called "1" and "0").

[0054] Specifically, Figure 4As shown in the figure, first, the transmitter sends data to the transmission line with a frequency and phase synchronized with the system clock source_clk. After passing through the transmission line, the data enters the receiving chip as the input data_in of the receiving unit. The receiving end receives the data data_in input by the transmitter and passes through the clock edge detector. At the rising and falling edges of the data, a pulse signal ed_out is generated.

[0055] The clock processing unit is used to calculate the recovery clock signal and the system clock signal based on the leading pulse signal and the data pulse signal in the pulse signal. Specifically, firstly, a reference clock signal ref_clk is generated according to the input ed_out, and then a system clock signal sys_clk with the same phase and frequency as ref_clk is generated. The recovery clock signal is obtained by delaying and merging the data pulse signal according to two preset clock cycles. Among them, the recovery clock signal is a clock signal obtained after delay processing based on the data pulse signal. The recovery clock signal is used in the subsequent data sampling process. In order to further improve the data accuracy, the recovery clock signal can be further split into a first recovery clock signal and a second recovery clock signal. The input data is sampled by these recovery clock signals to generate an initial data sample.

[0056] Furthermore, the clock splitting unit is used to split the recovered clock signal into a first recovered clock signal and a second recovered clock signal, and the clock downconverter is used to downconvert the system clock signal into a first system clock signal and a second system clock signal. It should be noted that the number of the first recovered clock signal and the second recovered clock signal after the split is the same as the number of the first system clock signal and the second system clock signal after the downconversion, so as to facilitate the subsequent two samplings. The sampling unit is used to sample the input data through the first recovered clock signal and the second recovered clock signal respectively to obtain the first initial data and the second initial data. Specifically, the input data can be sampled through the first sampling channel and the second sampling channel respectively, and then the first initial data and the second initial data are sampled through the first system clock signal and the second system clock signal respectively to obtain the first synchronization data and the second synchronization data. Specifically, the first initial data and the second initial data can be sampled through the third sampling channel and the fourth sampling channel respectively. It should be noted that the above-mentioned data sampling channel is a basic unit in data acquisition, which is responsible for receiving continuous signals and converting them into discrete digital samples. Each sampling channel can independently configure parameters such as sampling rate, gain, and filtering. This embodiment uses multiple data acquisition channels to perform data sampling to increase data redundancy, thereby improving data reliability and accuracy. At the same time, it can also reduce interference between different channels while performing synchronous acquisition and improve the signal-to-noise ratio of the signal.

[0057] In one embodiment, the clock processing unit may include a first clock processing unit and a second clock processing unit. Figure 2 . The first clock processing unit is used to delay the data pulse signal according to two preset clock cycles, and merge the two sub-clock signals with different phases after the delay to obtain a recovered clock signal. The preset clock cycle can be a time unit preset in order to control the timing and synchronization of the signal. By delaying the data pulse signal through these two preset clock cycles, two sub-clock signals with different phases can be obtained, and the phase difference between the two sub-clock signals depends on the delay amount. It should be noted that in other embodiments, the number of the preset clock cycles can also be greater than 2, for example, the data pulse signal is delayed by 4 preset clock cycles respectively, and the 4 sub-clock signals with different phases obtained after the delay are merged to obtain a recovered clock signal. The second clock processing unit is used to generate a reference clock signal according to the moment of the input pulse signal, and calculate a system clock signal with the same frequency and phase as the reference clock signal.

[0058] The transmitting end chip may include a data transmission source system clock, a data processing unit and a data transmission unit. Figure 3 The data sending unit can send the data generated by the data processing unit to the transmission line with the frequency and phase synchronized with the system clock source_clk. After passing through the transmission line, the data enters the receiving end chip as the input data_in of the receiving unit. The sent data data_in includes a preamble signal and a data signal, wherein the preamble signal is mainly used for the receiving end to generate a reference clock and measure the data clock cycle, and the data signal is valid information data.

[0059] Further reading Figure 3 In this embodiment, the first clock processing unit includes a leading signal filtering unit, a clock delayer, and a clock synthesis unit, wherein the leading signal filtering unit is used to filter out the leading pulse signal in the pulse signal to obtain a data pulse signal. The clock delayer is used to process the data pulse signal according to the delay control code corresponding to two preset clock cycles to obtain two sub-clock signals with different phases. The clock synthesis unit is used to perform a logical OR operation on the two sub-clock signals to obtain a combined recovered clock signal.

[0060] Furthermore, the first clock processing unit further includes a data signal filtering unit, a time digital converter and a phase difference operation logic unit. The data signal filtering unit is used to filter out the data pulse signal in the pulse signal to obtain a leading pulse signal. The time digital converter is used to calculate the system clock cycle according to the leading pulse signal and convert the system clock cycle into a digital signal. The phase difference operation logic unit is used to calculate the delay control code corresponding to two preset clock cycles according to the digital signal. The combination of the time digital converter and the phase difference operation logic unit enables the system to accurately measure the system clock cycle according to the leading pulse signal and calculate the delay control code accordingly. This adaptive mechanism helps the system to adjust in the face of clock drift or phase error, ensuring the accuracy and reliability of data transmission.

[0061] For details, please refer to Figure 5 , the data signal filtering unit can filter out the pulse signal generated by the data part, that is, the data pulse signal, leaving only the pulse signal tdc_in generated by the leading signal, that is, the leading pulse signal. At this time, the time-to-digital converter can measure the time difference 2∙T between the first and third pulses of tdc_in, where T is the system clock cycle, and then convert the system clock cycle into an N-bit digital signal tdc_out. The phase difference operation logic unit can calculate the control codes for the 90 and 270 degree clock cycle delays based on tdc_out, respectively, phs_90_code and phs_270_code, that is, the delay control codes corresponding to the above two preset clock cycles. At the same time, the leading signal filtering unit can filter out the pulse signal generated by the leading signal in ed_out, and obtain the pulse signal ed_data_out generated only by the data signal. Then, the control clock delayer processes ed_data_out through phs_90_code and phs_270_code to generate clock signals phs_90_clk and phs_270_clk with phase shifts of 90 and 270 degrees respectively with the data pulse signal. The clock synthesis unit performs a logic OR operation on phs_90_clk and phs_270_clk, and the combined clock is the above-mentioned recovered clock signal cdr_clk_out.

[0062] In one embodiment, the second clock processing unit may include a reference clock generating unit and a data receiver system clock unit. The reference clock generating unit is used to generate a reference clock signal according to the first input moment of the pulse signal. The data receiver system clock unit is used to generate a system clock signal with the same frequency and phase as the reference clock signal based on the multi-frame leading pulse signal through an internal phase-locked loop. Figure 4For reference, the reference clock generating unit generates the reference clock signal ref_clk according to the first pulse signal of the input ed_out. The phase-locked loop inside the data receiver system clock unit uses ref_clk as the reference clock, and after passing through multiple frames of leading signals, it can recover a sys_clk with the same phase and frequency as ref_clk. Because ref_clk is a clock signal synchronized with source_clk. Thus, the receiving end chip and the transmitting end chip complete the synchronization of the system clock signal.

[0063] It should be noted that the above-mentioned recovered clock signal cdr_clk_out is just in the middle of the signal of the input data data_in, and data_in can be directly sampled, such as Figure 6 As shown, the data after sampling is ds_direct. After that, the local system clock sys_clk that has completed synchronization with the transmitting end system clock source_clk is used to sample ds_direct to obtain ds_direct_sys. Since sys_clk and source_clk are signals of the same frequency and phase, there will be a 90-degree phase difference between sys_clk and ds_direct data. Therefore, the sampling data time margin at this time is t1, which is 1 / 4 of the clock cycle T. However, in actual applications, both source_clk and sys_clk will be affected by their own device noise and power supply noise to produce clock errors. At the same time, limited by the frequency of the reference clock ref_clk and the phase-locked loop bandwidth inside the data receiver system clock unit, sys_clk cannot track the phase of source_clk in real time. Therefore, when the phase difference between source_clk and sys_clk introduced by noise is greater than t1, sys_clk will have errors in sampling ds_direct.

[0064] In view of this situation, the embodiment of the present application can decompose the recovered clock signal cdr_clk_out into a first recovered clock signal and a second recovered clock signal through a clock decomposition unit, that is, Figure 5 The frequencies of cdr_clk_s1 and cdr_clk_s2 are half of cdr_clk_out and their phases are 180 degrees apart. Figure 3The sampling unit includes a first data sampling unit, a second data sampling unit, a first clock synchronization sampling unit and a second clock synchronization sampling unit. Specifically, cdr_clk_s1 and cdr_clk_s2 respectively sample the data data_in through the first data sampling unit and the second data sampling unit, and the sampled data are the first initial data and the second initial data, namely ds1 and ds2. Compared with the above ds_direct, the data width of each code of ds1 and ds2 is increased by 1 times, which effectively increases the data width.

[0065] Furthermore, the clock divider can reduce the frequency of the system clock to obtain two first system clock signals and second system clock signals with half the frequency of the original, namely, sys_dclk1 and sys_dclk2, and sys_dclk1 and sys_dclk2 are 180 degrees out of phase. Then, the above sys_dclk1 and sys_dclk2 can sample ds1 and ds2 respectively through the first clock synchronization sampling unit and the second clock synchronization sampling unit, so as to obtain the first synchronization data and the second synchronization data synchronized with the system clock, namely, dsyn1 and dsyn2. At this time, the time margin t2 of data sampling is 1 / 2 of the clock period T, which is doubled compared with the solution of direct sampling using cdr_clk_out, greatly reducing the time jitter error requirements between souce_clk and sys_clk.

[0066] Furthermore, the data receiving device also includes a data merging unit, which is used to output the first synchronization data dsyn1 when the first system clock signal sys_dclk1 is at a high level, and output the second synchronization data dsyn2 when the second system clock signal sys_dclk2 is at a high level, thereby obtaining the synthesized data dcom_syn, and dcom_syn is synchronized with the sys_clk clock. The above-mentioned data merging unit can intelligently select and output the corresponding synchronization data (dsyn1 and dsyn2) according to the state of the system clock signal (sys_dclk1 and sys_dclk2). This design ensures the strict synchronization of the synthesized data (dcom_syn) with the system clock (sys_clk), thereby improving the stability of data transmission.

[0067] In other embodiments, more sampling channels can be added to split the recovered clock signal into K signals and perform data sampling and time synchronization sampling respectively, thereby increasing the data width by K times. This parallel processing mechanism not only improves the efficiency of data processing, but also reduces the performance requirements of a single sampling channel. Increasing the number of sampling channels and increasing the data width by K times can more effectively reduce the noise requirements of source_clk (source clock) and sys_clk (system clock). This is because the impact of noise on multiple parallel channels will be averaged, thereby reducing the negative impact of noise on the overall data transmission performance.

[0068] In the prior art, clocks souce_clk and sys_clk can reduce the phase noise of the phase-locked loop by increasing power consumption and area, but this is achieved at the cost of power consumption and chip area. The embodiment of the present application increases the tolerance to clock noise of souce_clk and sys_clk by increasing the effective time of data, thereby increasing the robustness of clock synchronization operation and the accuracy of data transmission. Therefore, the data merging unit in the data receiving device provides a stable, reliable and efficient solution for the high-speed data transmission system through an efficient data synchronization and merging mechanism, flexible data processing capabilities, and the ability to reduce the impact of noise. At the same time, by optimizing the data synchronization and merging mechanism, and improving the parallelism of data processing, the device can meet the needs of modern high-speed data transmission systems.

[0069] As can be seen from the above, the data receiving device with clock synchronization provided in this embodiment includes a clock edge detector, a clock processing unit, a clock splitting unit, a clock downconverter and a sampling unit, the clock edge detector is used to detect the clock edge corresponding to the received input data to generate a pulse signal, the clock processing unit is used to calculate the recovery clock signal and the system clock signal according to the pulse signal, the clock splitting unit is used to split the recovery clock signal into a first recovery clock signal and a second recovery clock signal, the clock downconverter is used to downconvert the system clock signal into a first system clock signal and a second system clock signal, the sampling unit is used to sample the input data through the first recovery clock signal and the second recovery clock signal respectively to obtain the first initial data and the second initial data, and sample the first initial data and the second initial data through the first system clock signal and the second system clock signal respectively to obtain the first synchronization data and the second synchronization data. In the present invention, when sys_dclk1 is at a high level, the data merging unit outputs the dsyn1 data, and when sys_dclk2 is at a high level, the dsyn2 data is output to obtain the synthesized data dcom_syn, and dcom_syn realizes sys_clk clock synchronization. It is understandable that this solution can increase the data width by K times through a higher sampling channel, and further reduce the noise requirements of souce_clk and sys_clk. Therefore, this embodiment collects data separately through multiple system clock signals, increases the data width and the time margin of data sampling, reduces the clock noise requirements, and improves the accuracy of data received by the receiving end.

[0070] An embodiment of the present invention further provides a data receiving method with clock synchronization. The execution subject of the data receiving method may be the data receiving device with clock synchronization provided by the embodiment of the present invention, or a server integrating the data receiving device with clock synchronization.

[0071] Please continue reading Figure 7 , Figure 7 : is a flow chart of a data receiving method with clock synchronization provided by an embodiment of the present invention. The specific flow of the method may be as follows:

[0072] 101, detecting a clock edge corresponding to received input data to generate a clock edge pulse signal.

[0073] Specifically, the transmitting chip sends the data to the transmission line with a frequency and phase synchronized with the system clock, and sends it to the receiving chip through the transmission line. After receiving the input signal, the receiving chip can generate a clock edge pulse signal at the rising edge and falling edge of the data through a clock edge detector, where the clock edge pulse signal can specifically include a leading pulse signal and a data pulse signal.

[0074] 102. Obtain a recovery clock signal and a system clock signal of a data receiving device according to a leading pulse signal and a data pulse signal in a clock edge pulse signal.

[0075] Among them, the pulse signal can be separated into a leading pulse signal and a data pulse signal. First, a reference clock signal is generated according to the moment of pulse signal input, and the internal phase-locked loop is controlled to use the signal as the reference clock, and after multiple frames of leading signals, a system clock signal with the same frequency and phase as the reference clock signal is restored.

[0076] Secondly, the leading pulse signal can obtain two delay control codes corresponding to the preset clock cycles after time-to-digital conversion and phase difference calculation, and the data pulse signal can obtain two clock signals with phase shifts of 90 degrees and 270 degrees respectively with the data pulse signal after being processed by these two delay control codes. The two signals are combined to form the recovered clock signal.

[0077] 103 , split the recovered clock signal into a first recovered clock signal and a second recovered clock signal, and down-convert the system clock signal into a first system clock signal and a second system clock signal.

[0078] 104. Sample the input data respectively by using the first recovered clock signal and the second recovered clock signal to obtain the first initial data and the second initial data, and sample the first initial data and the second initial data respectively by using the first system clock signal and the second system clock signal to obtain the first synchronization data and the second synchronization data.

[0079] Specifically, the recovered clock signal is split into a first recovered clock signal and a second recovered clock signal, whose frequency is half of the recovered clock signal and whose phase difference is 180 degrees. At this time, the input data is sampled by the first recovered clock signal and the second recovered clock signal respectively to obtain the first initial data and the second initial data. Correspondingly, the system clock signal is down-converted into the first system clock signal and the second system clock signal, whose frequency is half of the system clock signal and whose phase difference is 180 degrees, and then the first initial data and the second initial data are sampled by the first system clock signal and the second system clock signal respectively to obtain the first synchronization data and the second synchronization data. Finally, when the first system clock signal is at a high level, the first synchronization data can be output, and when the second system clock signal is at a high level, the second synchronization data can be output, thereby obtaining the synthesized data.

[0080] Compared with the prior art method of reducing the clock jitter between synchronous clocks by reducing the noise of the phase-locked loop, the solution of the present application does not need to increase the area and power consumption of the phase-locked loop, but instead reduces the equivalent rate of the data at the receiving end chip and increases the effective data sampling time margin to improve the tolerance of data sampling to the phase-locked loop noise and the accuracy of data transmission.

[0081] All of the above technical solutions can be arbitrarily combined to form optional embodiments of the present application, which will not be described in detail here.

[0082] As can be seen from the above, the data receiving method with clock synchronization proposed in the embodiment of the present invention can detect the clock edge corresponding to the received input data to generate a clock edge pulse signal, obtain the recovery clock signal and the system clock signal of the data receiving device according to the leading pulse signal and the data pulse signal in the clock edge pulse signal, split the recovery clock signal into a first recovery clock signal and a second recovery clock signal, and down-convert the system clock signal into a first system clock signal and a second system clock signal, sample the input data respectively through the first recovery clock signal and the second recovery clock signal to obtain the first initial data and the second initial data, and sample the first initial data and the second initial data respectively through the first system clock signal and the second system clock signal to obtain the first synchronization data and the second synchronization data. The embodiment of the present application collects data respectively through multiple system clock signals, improves the data width and the time margin of data sampling, reduces the clock noise requirements, and improves the accuracy of data received by the receiving end.

[0083] A person of ordinary skill in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be completed by instructions, or by controlling related hardware through instructions. The instructions may be stored in a computer-readable storage medium and loaded and executed by a processor.

[0084] The storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0085] Since the computer program stored in the storage medium can execute the steps in any one of the data receiving methods with clock synchronization provided in the embodiments of the present application, the beneficial effects that can be achieved by any one of the data receiving methods with clock synchronization provided in the embodiments of the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0086] The above is a detailed introduction to a data receiving device, method and electronic device with clock synchronization provided by an embodiment of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A data receiving device with clock synchronization, characterized in that: include: A clock edge detector, a clock processing unit, a clock splitting unit, a clock downconverter, and a sampling unit; The clock edge detector is used to detect the clock edge corresponding to the received input data to generate a clock edge pulse signal, wherein the clock edge pulse signal includes a leading pulse signal and a data pulse signal; The clock processing unit is used to obtain a recovered clock signal and a system clock signal of the data receiving device according to the leading pulse signal and the data pulse signal in the clock edge pulse signal, wherein the clock processing unit includes a first clock processing unit and a second clock processing unit, the first clock processing unit is used to delay the data pulse signal according to two preset clock cycles respectively, and merge the two delayed sub-clock signals of different phases to obtain the recovered clock signal, and the second clock processing unit is used to generate a reference clock signal according to the moment when the clock edge pulse signal is input, calculate the phase difference between the reference clock signal and the leading pulse signal, and generate a system clock signal with the same frequency and the same phase as the reference clock signal based on the phase difference; The clock splitting unit is used to split the recovered clock signal into at least a first recovered clock signal and a second recovered clock signal; The clock downconverter is used to downconvert the system clock signal into a first system clock signal and a second system clock signal; The sampling unit is used to sample the input data respectively through the first recovered clock signal and the second recovered clock signal to obtain the first initial data and the second initial data, and to sample the first initial data and the second initial data respectively through the first system clock signal and the second system clock signal to obtain the first synchronization data and the second synchronization data.

2. The data receiving device according to claim 1, characterized in that: The first clock processing unit includes a leading signal filtering unit, a clock delay unit and a clock synthesis unit; The leading signal filtering unit is used to filter the leading pulse signal in the clock edge pulse signal to obtain a data pulse signal; The clock delayer is used to process the data pulse signal according to the delay control code corresponding to two preset clock cycles to obtain two sub-clock signals with different phases; The clock synthesis unit is used to perform a logic OR operation on two sub-clock signals to obtain a combined recovery clock signal.

3. The data receiving device according to claim 2, characterized in that: The first clock processing unit also includes a data signal filtering unit, a time-to-digital converter, and a phase difference calculation logic unit; The data signal filtering unit is used to filter out the data pulse signal in the clock edge pulse signal to obtain a leading pulse signal; The time-to-digital converter is used to calculate the system clock cycle according to the leading pulse signal and convert the system clock cycle into a digital signal; The phase difference calculation logic unit is used to calculate the delay control code corresponding to two preset clock cycles according to the digital signal.

4. The data receiving device according to claim 1, characterized in that: The second clock processing unit includes a reference clock generating unit and a system clock generating unit; The reference clock generating unit is used to generate a reference clock signal according to the first pulse signal timing of the clock edge pulse signal; The system clock generating unit is used to calculate the phase difference between the reference clock signal and the pilot pulse signal, and generate a system clock signal with the same frequency and the same phase as the reference clock signal based on the phase difference.

5. The data receiving device according to claim 1, characterized in that: The sampling unit includes a first data sampling unit, a second data sampling unit, a first clock synchronization sampling unit and a second clock synchronization sampling unit; The first data sampling unit is used to sample input data through a first recovered clock signal to obtain first initial data; The second data sampling unit is used to sample the input data through the second recovered clock signal to obtain second initial data; The first clock synchronization sampling unit is used to sample the first initial data through the first system clock signal to obtain the first synchronization data; The second clock synchronization sampling unit is used to sample the second initial data through the second system clock signal to obtain second synchronization data.

6. The data receiving device according to claim 5, characterized in that: The device also includes: A data merging unit is used to output the first synchronization data when the first system clock signal is at a high level, and to output the second synchronization data when the second system clock signal is at a high level, so as to merge the first synchronization data and the second synchronization data.

7. The data receiving device according to any one of claims 1 to 5, characterized in that: The frequencies of the first recovered clock signal and the second recovered clock signal are both half of the recovered clock signal, and the phase difference is 180 degrees; The frequencies of the first system clock signal and the second system clock signal are both half of the system clock signal, and the phase difference is 180 degrees.

8. A data receiving method with clock synchronization, characterized in that: The following steps are involved: Detecting a clock edge corresponding to the received input data to generate a clock edge pulse signal, wherein the clock edge pulse signal includes a leading pulse signal and a data pulse signal; A recovered clock signal and a system clock signal are obtained according to the leading pulse signal and the data pulse signal in the clock edge pulse signal, wherein the data pulse signal is delayed according to two preset clock cycles respectively, and the two delayed sub-clock signals with different phases are merged to obtain the recovered clock signal, a reference clock signal is generated according to the moment when the clock edge pulse signal is input, a phase difference between the reference clock signal and the leading pulse signal is calculated, and a system clock signal with the same frequency and the same phase as the reference clock signal is generated based on the phase difference; Splitting the recovered clock signal into at least a first recovered clock signal and a second recovered clock signal, and down-converting the system clock signal into a first system clock signal and a second system clock signal; The input data is sampled by the first recovery clock signal and the second recovery clock signal respectively to obtain the first initial data and the second initial data, and the first initial data and the second initial data are sampled by the first system clock signal and the second system clock signal respectively to obtain the first synchronization data and the second synchronization data.

9. An electronic device, characterized in that: The data receiving device with clock synchronization comprises any one of claims 1 to 7.

Images