Leakage screening based on power prediction

Abstract

This document describes systems and methods for power prediction based leakage screening. In particular, the described systems and methods estimate use case power (e.g., low power, ambient power, high power, gaming power) during a silicon manufacturing process to apply leakage screening for a part (e.g., a chip package). In some aspects, measurable silicon parameters (e.g., leakage values, bin values, processor sensor values) can be used for use case power prediction. Using the described methods, a maximum allowed predicted use case power can be determined and used for leakage screening regardless of individual rail leakage or voltage bin assignments.

Description

BACKGROUND

[0001] Silicon manufacturing involves producing silicon-based materials, such as silicon wafers, for a wide range of consumer electronics devices. During silicon manufacturing, some silicon-based components can develop defects, causing current to unexpectedly flow through the silicon. Leaky silicon components can be discarded to avoid wasting power, but the criteria for determining which components should be discarded often depends on screening limits determined based on where and how the components are expected to be used. Some screening limits are set based on worst-case leakage values predicted for use of the components, which are determined based on estimates derived from silicon foundry models. SUMMARY

[0002] This document describes systems and methods for power prediction based leakage screening. In particular, the described systems and techniques estimate use case power (e.g., low power, ambient power, high power, gaming power) during a silicon manufacturing process to apply leakage screening to a part (e.g., a chip package) based on a multi-track test that tests the tracks of a chip package in an aggregated manner to determine a final bin for the part. In some aspects, measurable silicon parameters (e.g., leakage values, bin values, processor sensor values) can be used for use case power prediction. Using the described techniques, a maximum allowed predicted use case power can be determined and used for leakage screening regardless of individual track leakage or voltage bin assignments.

[0003] Accordingly, these techniques provide enhanced screening over conventional screening systems that classify a part based on individual track leakage not meeting individual track threshold limits. Moreover, while one or more individual tracks can not meet leakage threshold values, other tracks in a chip package can compensate such that the chip package can meet an overall performance level (e.g., a global limit such as power or temperature) in an aggregated manner. Furthermore, a part whose tracks each barely pass a conventional screening test can exceed the global limit (e.g., an operating temperature threshold) for the part in an aggregated manner, but such a part can be classified by the leakage screening techniques described herein.

[0004] This summary is provided to introduce simplified concepts of power prediction based leakage screening, which are further described below in the DETAILED DESCRIPTION. This summary is not intended to identify key features of the claimed subject matter, nor is it intended to be used to determine the scope of the claimed subject matter. BRIEF DESCRIPTION OF DRAWINGS

[0005] Details of one or more aspects of power prediction based leakage screening are described in the document with reference to the following drawings. The same numbers are used in the drawings to reference like features and components:

[0006] Figure 1 An example flowchart of a silicon manufacturing process according to the techniques described herein is shown;

[0007] Figure 2 An example implementation of per-ASV bin leakage targets is shown;

[0008] Figure 3 An example implementation of per-component leakage targets is shown;

[0009] Figure 4 An example method of a silicon manufacturing process according to the techniques described herein is shown; and

[0010] Figure 5 Various components of an example test system that can implement aspects of the disclosed systems and methods are shown. DETAILED DESCRIPTION

[0011] SUMMARY

[0012] This document describes systems and methods for power prediction based leakage screening. In particular, the described systems and techniques estimate use case power (e.g., low power, ambient power, high power, gaming power) during a silicon manufacturing process to apply leakage screening to a component (e.g., a chip package) based on a multi-track test that tests the tracks of a chip package in an aggregated manner to determine a final bin for the component. In some aspects, measurable silicon parameters (e.g., leakage values, bin values, processor sensor values) can be used for use case power prediction. Using the described techniques, a maximum allowed predicted use case power can be determined and used for leakage screening regardless of individual track leakage or voltage bin assignments.

[0013] Accordingly, these techniques provide enhanced screening over conventional screening systems that classify a component based on individual track leakage not meeting individual track threshold limits. Moreover, while one or more individual tracks can not meet leakage thresholds, other tracks in a chip package can compensate such that the chip package can meet an overall performance level (e.g., a global limit such as power or temperature) in an aggregated manner. Furthermore, a component whose tracks each barely pass a conventional screening test can exceed a global limit (e.g., an operating temperature threshold) for the component in an aggregated manner, but such a component can be classified by the leakage screening techniques described herein.

[0014] In aspects, a method performed by a test system is disclosed. The method includes receiving a chip package that has been subjected to wafer testing, die cutting, packaging, and binning, where the chip package has a plurality of tracks, and each track of the plurality of tracks is assigned to a corresponding voltage bin of a plurality of voltage bins based on an adaptive supply voltage value. The method further includes obtaining one or more silicon parameters associated with the chip package, where the one or more silicon parameters are determined during wafer level testing of the chip package and include at least a leakage current value for each track. Additionally, the method includes performing multi-track testing of the plurality of tracks of the chip package to provide results for each track across the plurality of voltage bins, where each track of the plurality of tracks is tested based on the corresponding leakage current value and the adaptive supply voltage value of the corresponding voltage bin. Moreover, the method includes determining an aggregated value based on an aggregation of the results for each track across the plurality of voltage bins. The method further includes classifying the chip package based on the aggregated value.

[0015] This document further describes computer-readable media having instructions for performing the methods outlined above and other methods set forth herein, as well as test systems and apparatuses for performing these methods.

[0016] While features and concepts of the described power prediction based leakage screening techniques can be implemented in any number of different environments, aspects are described in the context of the following examples.

[0017] Example Implementation

[0018] Figure 1 An example flowchart 100 of a silicon manufacturing process in accordance with the techniques described herein is shown. During the silicon manufacturing process, leakage screening 102 is performed at the silicon wafer level. For example, wafer testing 104 is applied to remove highly leaky parts to limit power consumption under different scenarios. Typically, the screening limit is set to the worst case leakage value predicted using worst case estimates derived from silicon foundry models during the implementation phase. Each wafer is tested to determine a current leakage value (referred to as current from drain (D) to source (S), IDS) associated with each die on the wafer. Another parameter measured at the wafer level includes an adaptive supply voltage (ASV) for each die on the wafer.

[0019] At 106, the system determines, for each die on the wafer, whether the die meets the specification based on the die’s corresponding IDS. Dices on the wafer with associated IDSs that meet the corresponding specification threshold are labeled, for example, “good,” and dices with associated IDSs that do not meet the corresponding specification threshold are labeled, for example, “bad.” The dices are then singulated from the wafer. For example, the wafer is cut into multiple dices or dies that include the labeled dices. The dices or dies labeled “bad” can be discarded or recycled. A single die can include one or more of the dices labeled “good.”

[0020] At 108, the good dices or dies are packaged, forming a die package. Due to variations and imperfections in the silicon manufacturing process, some dices can tend to leak more current but can still operate at lower voltages, while other dices can tend to leak less current but can need higher voltages to operate. Current leakage increases exponentially with voltage.

[0021] At 110, voltage binning is applied to the die package to determine the minimum voltage for safe operation of the components. Generally, faster (and more current-leaking) components can operate at lower voltages, and slower (and less current-leaking) components need higher voltages to operate. When voltage binning is applied, the components can be sorted into bins, each of which has a unique current leakage limit. This is referred to as bin-by-bin current leakage screening. Typically, during the manufacturing flow, after the components are binned (e.g., the minimum voltage for safe operation of the components is determined), current leakage screening based on the assigned bin is applied. In aspects, each power supply rail (e.g., voltage domain) of a die in a die package is assigned a bin value (e.g., bin voltage assignment) based on its corresponding AVS value.

[0022] Conventional systems test the power supply rail of the die package at the bin voltage assigned to each power supply rail. The die package is then sorted into different ASV categories 112 (e.g., ASV-1 112-1, ASV-2 112-2, ASV-3 112-3, …, ASV-n 112-n). According to conventional screening techniques that implement per-ASV bin-by-bin current leakage screening, if any rail fails, the entire component can be downgraded or discarded because it does not meet the specification. For example, if a single rail does not meet the bin voltage of its assigned bin, the entire component is moved to a different bin (e.g., with a lower voltage limit) because of that one rail. As additional rails are tested, the component can be further downgraded each time a rail fails the test.

[0023] However, the techniques described herein enable classifying chip packages 114 based on testing the rails in an aggregated manner and comparing to a single scaled number (e.g., IDS<Spec-1 114-1, IDS<Spec-2 114-2, IDS<Spec-3 114-3, …, IDS<Spec-n 114-n IDS<Spec-1 114-1, IDS<Spec-2 114-2, IDS<Spec-3 114-3, …, IDS<Spec-n 114-n) based on the rails. For example, a multi-rail test is performed on the rails (e.g., all power supply rails) of a chip package using the IDS and ASV values obtained at the wafer level to provide a result for each rail across the bins (e.g., all bins assigned to the rails of the chip package). The result for each rail is input into an aggregation function to determine an aggregated value (e.g., aggregated power value, aggregated temperature value). The aggregated value is then compared to a target metric value (e.g., target power value, target temperature value, global limit) to predict the performance of the chip package with respect to a particular metric (e.g., power, temperature).

[0024] In one example, the target metric value can be battery life, and the multi-rail test uses the IDS and ASV values of the rails to determine whether the component will last, for example, 23 hours. If the component is a slower component and leaks less power, it can last, for example, 24 hours. Thus, in this example, the multi-rail test can accept components that meet the minimum of 23 hours and reject components that are below 23 hours (e.g., due to being faster and leaking more power). In another example, the target metric value can be temperature, and the component is for a handheld gaming device. In this case, the multi-rail test can use the IDS and ASV values of the rails in a temperature function to accept components that do not exceed a temperature limit based on the amount of power output by the component and reject components that do exceed the temperature limit.

[0025] Based on the comparison between the aggregate value and the target metric value, the component can be moved to a different bin (e.g., a lower bin, a higher bin), or remain in the currently assigned bin. The bin-to-bin voltage difference can be any suitable voltage, including, for example, a difference of 5 millivolts (mV), 10 mV, 20 mV, 25 mV, etc. In one example, if a central processing unit (CPU) rail of a particular frequency is expected to operate at, for example, 0.75 mV at a nominal bin (e.g., a bin at the center of a distribution), then one bin higher can be, for example, 0.7 mV, which can enable the component to operate at a lower voltage to save power, but the component can leak more. Because the component has already passed the wafer-level leakage screening 102, the likelihood of a catastrophic failure of the component at this time is substantially negligible, so it can be reasonably assumed that the component is not likely to “fail” and need to be discarded. However, the component can be more suitable for a different bin, but this is based on the aggregate of the rails rather than a single rail.

[0026] The aggregation techniques described herein improve yield over conventional per-rail screening techniques because some rails can compensate for other rails (e.g., one rail can be above a leakage limit, but can not affect the effective power metric of the chip package). These techniques also reduce test time compared to conventional per-rail screening techniques that test each rail against its own leakage limit, because all rails are tested in an aggregate manner and the aggregate result is compared to a single value.

[0027] The flow diagram 100 is shown as a collection of blocks that specify operations to be performed, but no implication should be made that the operations are performed in the order shown or that all of the blocks are necessary for the operation to be performed. Further, any one or more of the operations can be repeated, combined, re-organized, or linked to provide a large number of additional and / or alternative methods. In the following discussion, reference can be made to the example flow diagram 100 or the entities or implementations detailed in Figure 1 and Figure 2 and Figure 3 of the present disclosure, which reference is made only by way of example. The techniques are not limited to being performed by one entity or multiple entities operating on one device. Rather, the collection of blocks in the flow diagram 100 can be performed by a single device or multiple different devices. In some implementations, different devices can perform each block of the flow diagram 100.

[0028] Figure 2An example implementation 200 of per-ASV bin leakage target is shown. In the example shown, it can be assumed that all tracks of a chip package are assigned to the same bin. An algorithmic model (e.g., a random forest regression model) is used to estimate the use case power or power limit (e.g., low power, ambient power, high power, gaming power) to apply leakage screening for the part during the silicon manufacturing process. Although the examples herein are described with respect to power, the model can be adapted to estimate any suitable parameter, including power, temperature, battery life, battery undervoltage, etc. Accordingly, the model can be adapted as a power model, a thermal model, a battery life model, a battery undervoltage model, etc. The algorithmic model can be a machine learning model, a curve fitting model, or any other suitable model for estimating a required parameter of a part based on an aggregation of the IDS and ASV values of the tracks of the part.

[0029] For example, a power metric 202 is projected to an ASV bin (e.g., ASV bin 204). A test system measures and segments the dynamic power (e.g., P dyn ) and actual leakage power (e.g., P lkg ) of each track. Leakage is based on the target leakage current (IDS TT ) of each track. A global limit (P limit ) is established for the power metric across all bins (also referred to as a target aggregate threshold or power limit). The aggregate value (e.g., aggregate power value) is then determined using IDS as input and compared to the global limit P limit using IDS as input to the algorithmic model, which can be based on the following equation:

[0030]

[0031] According to Equation 1, the aggregation of the dynamic power P dyn with the leakage current IDS multiplied by the actual leakage power P lkg divided by the factor of the target leakage current IDS TT is compared to the global limit P limit(For example, power limit) are compared. As shown, Equation 1 is a quadratic polynomial equation derived using the ASV and IDS values of all tracks of a component (for example, a chip package). For large datasets (for example, about 30,000 multi-product semiconductor components), the model can use the top-most (for example, top 10, top 25) ASV and IDS features in the dataset. Note that Equation 1 (and Equation 2 below) is a combination of constant terms with linear and square terms (for example, no cross terms). Further, the model can provide a reported output based on a 99th percentile limit on predicted days of use (DoU) estimated using a plot of predicted DoU versus estimated DoU. Such a model can be implemented for high power use cases involving heat dissipation, such as mobile devices that do not have cooling fans.

[0032] Figure 3 An example implementation 300 of per-component leakage targets is shown. In the example shown, one or more tracks on a given component can be in a different ASV bin than at least one other track on the component. In some aspects, each track on a component can be in a different ASV bin. In this case, the test system can select ASV-bin pairs from different tracks. For this scenario, Equation 1 can be adjusted as follows:

[0033]

[0034] The test system can use Equation 2 for per-component leakage targets. The aggregate power of the ASV-bin pair is compared to the power limit (for example, global limit P limit , target power value) of the component to determine the final bin for the component.

[0035] Equations 1 and 2 enable the test system to predict the power required for operation of a chip package and classify the chip package according to its predicted power. As described above, the global limit P limit may be any suitable limit that corresponds to a particular use case scenario, such as low power, ambient power, high power, gaming power, and so on.

[0036] While these techniques implement additional calculations at the test system, they improve the accuracy and optimal yield-power tradeoff of the silicon manufacturing process compared to conventional leakage screening techniques that use per-track screening. Further, these techniques improve the reliability of the overall product produced by the silicon manufacturing process.

[0037] Example method

[0038] Figure 4An example method 400 of a silicon manufacturing process in accordance with the techniques described herein is shown. At block 402, the example method 400 involves receiving a chip package that has been subjected to wafer testing, die cutting, packaging, and / or binning. The chip package can include a plurality of tracks, and each track of the plurality of tracks can be assigned to a corresponding voltage bin of a plurality of voltage bins. In some implementations, the assignment of each track can be based on an adaptive supply voltage value.

[0039] At block 404, the example method 400 involves obtaining one or more silicon parameters associated with the chip package. The one or more silicon parameters can be determined during wafer-level testing of the chip package. The silicon parameters can include a leakage current value for each track of the plurality of tracks.

[0040] At block 406, the example method 400 involves performing a multi-track test on the plurality of tracks of the chip package to provide a result for each track across the plurality of voltage bins. Each track of the plurality of tracks that is tested can be based on the corresponding leakage current value and the adaptive supply voltage value of the corresponding voltage bin.

[0041] At block 408, the example method 400 involves determining an aggregated value based on an aggregation of the results for each track across the plurality of voltage bins.

[0042] At block 410, the example method 400 involves classifying the chip package based on the aggregated value.

[0043] Example test system

[0044] In addition to the descriptions above, the techniques described herein can be performed by a test system. Figure 5 Various components of an example test system 500 that can implement aspects of the disclosed systems and methods are shown. As shown, the test system 500 can include a communication device 502 that enables wired and / or wireless communication of device data 504. The device data 504 or other device content can include configuration settings of the device, test information stored on the test system, and / or information associated with a silicon manufacturing process, including wafer test results and / or silicon parameters. The test system 500 also includes one or more data inputs 506 via which any type of data, information and / or input can be received, for example, from a user.

[0045] The test system 500 further includes a communication interface 508 that can be implemented as one or more of a serial and / or parallel interface, a wireless interface, any type of network interface, a modem, or any other type of communication interface. The communication interface 508 provides a connection and / or communication links from / to the test system 500 to / from one or more communication networks, other electronic, computing, and / or communication devices.

[0046] The test system 500 includes one or more processors 510 (e.g., any of microprocessors, microcontrollers, or other controllers) that can process various computer- executable instructions to control the operation of the test system 500 and implement methods discussed herein. The processor(s) 510 can include single- or multi-core processors consisting of a variety of materials, such as silicon, polysilicon, high-K dielectric, copper, and so on. Alternatively or additionally, the test system 500 can be implemented with any one or combination of hardware, firmware, or fixed logic circuitry that is

[0047] The test system 500 can also include a computer-readable medium 514 (CRM 514) having a multi-track test manager application 516 and / or an operating system 518. The CRM 514 of the system can be a machine-readable hardware-based storage medium that does not comprise a transitory signal or carrier wave. As an example, the CRM 514 can include one or more of read-only memory (ROM), flash memory, dynamic random access memory (DRAM), static random access memory (SRAM), and so on. The CRM 514 includes executable code or instructions of at least the multi-track test manager application 516. The one or more processors 510 of the test system 500 execute instructions stored in the CRM 514 to instruct operational elements of the test system 500 to implement the multi-track test manager application 516 to perform power prediction-based leakage screening.

[0048] Additional Examples

[0049] In the following sections, additional examples are provided.

[0050] Example 1 : A method for power prediction based leakage screening, the method comprising: receiving a chip package that has been through wafer testing, die cutting, packaging, and binning, the chip package having a plurality of tracks, each track of the plurality of tracks being assigned to a corresponding voltage bin of a plurality of voltage bins based on an adaptive supply voltage value; obtaining one or more silicon parameters associated with the chip package, the one or more silicon parameters being determined during wafer level testing of the chip package and including at least a leakage current value for each track of the plurality of tracks; performing a multi-track test on the plurality of tracks of the chip package to provide a result for each track across the plurality of voltage bins, each track of the plurality of tracks being tested based on the corresponding leakage current value and the adaptive supply voltage value of the corresponding voltage bin; determining an aggregate value based on an aggregation of the results for each track across the plurality of voltage bins; and classifying the chip package based on the aggregate value.

[0051] Example 2: The method of example 1, wherein classifying the chip package comprises assigning the chip package to a final bin based on the aggregate value.

[0052] Example 3: The method of any of the preceding examples, wherein at least one track of the plurality of tracks does not satisfy an individual track threshold associated with the final bin, but the aggregate value satisfies a global limit associated with the final bin.

[0053] Example 4: The method of any of the preceding examples, wherein: the aggregate value is an aggregate power value; and the classification of the chip package is based on a comparison of the aggregate power value to a target power value.

[0054] Example 5: The method of any of the preceding examples, wherein the chip package is classified based on the comparison of the aggregate power value and the target power value.

[0055] Example 6: The method of any of the preceding examples, further comprising: testing a wafer to determine the leakage current values; cutting the wafer into a plurality of dies; packaging at least one die of the plurality of dies to provide one or more chip packages; and applying voltage binning to the one or more chip packages to determine the adaptive supply voltage for each track on the one or more chip packages.

[0056] Example 7: The method of any of the preceding examples, wherein the method is performed by a processor of a test system, the processor executing instructions stored in a memory of the test system.

[0057] Example 8: A test system configured to perform the method of at least one of examples 1 to 7.

[0058] Example 9: A machine-readable storage medium storing instructions that, when executed by at least one processor, cause the at least one processor to perform the method of at least one of Examples 1-7.

[0059] Conclusions

[0060] Unless otherwise defined, the use of the term “or” herein can be considered as an inclusive-inclusive or as a term that permits inclusion or application of one or more items from a list of items that are conjunctively linked by the term “or” (e.g., the phrase “A or B” can be interpreted as permitting only “A,” only “B,” or both “A” and “B”). Further, as used herein, the phrase “at least one of’ a list of items refers to any combination of one or more of the items in the list, including single membership. For example, “at least one of a, b, or c” can cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination of the same with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c, or any other ordering of a, b, and c). Further, items represented in the accompanying figures and terms discussed herein can refer to one or more items or terms, and thus the terms can be used interchangeably in a singular or plural context.

[0061] While implementations for leakage screening based on power prediction have been described in specific language, the subject matter of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as example implementations of leakage screening based on power prediction, and other equivalent features and methods are intended to be within the scope of the appended claims. Further, various aspects are described, and it should be understood that each described aspect can be implemented independently or in combination with one or more other described aspects. For example, these techniques can be implemented using Figures 1 to 5 One or more of the entities or components shown can be implemented using a number of different architectures, and the entities or components can be further divided, combined, etc. Thus, these figures show some of the many possible systems or devices that can employ the described techniques.

Claims

1. A method for power prediction based leakage screening, the method comprising: receiving (402) a chip package that has been subjected to wafer testing, die cutting, packaging, and binning, the chip package having a plurality of tracks, each track of the plurality of tracks being assigned to a corresponding voltage bin of a plurality of voltage bins based on an adaptive supply voltage value; obtaining (404) one or more silicon parameters associated with the chip package, the one or more silicon parameters being determined during wafer level testing of the chip package and including at least a leakage current value for each track of the plurality of tracks; performing (406) a multi-track test on the plurality of tracks of the chip package to provide results for each track across the plurality of voltage bins, each track of the plurality of tracks being tested based on the corresponding leakage current value and the adaptive supply voltage value for the corresponding voltage bin; determining (408) an aggregate value based on an aggregation of the results for the each track across the plurality of voltage bins; and classifying (410) the chip package based on the aggregate value. Classifying the chip package includes assigning the chip package to a final bin based on the aggregate value.

2. The method of claim 1, wherein, At least one of the tracks of the plurality of tracks does not satisfy an individual track threshold associated with the final bin, but the aggregate value satisfies a global limit associated with the final bin.

3. The method of claim 2, wherein, 4. The method of claim 1, wherein: the aggregate value is an aggregate power value; and the classification of the chip package is based on a comparison of the aggregate power value to a target power value. The chip package is classified based on a comparison of an aggregate power value to a target power value.

5. The method of claim 1, wherein, 6. The method of claim 1, further comprising: testing a wafer to determine the leakage current values; cutting the wafer into a plurality of dies; packaging at least one die of the plurality of dies to provide one or more chip packages; and applying voltage binning to the one or more chip packages to determine an adaptive supply voltage for each track on the one or more chip packages. The method is performed by a processor of a test system, the processor executing instructions stored in a memory of the test system.

7. The method of any one of claims 1 to 6, wherein, 8. A test system configured to perform the method of at least one of claims 1 to 7.

9. A machine-readable storage medium storing instructions that, when executed by at least one processor of a test system, cause the at least one processor to perform the method of at least one of claims 1 to 7. ​

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