Pixel circuit, driving method, display substrate, display panel, and display device

Abstract

A pixel circuit, a driving method, a display substrate, a display panel, and a display device. The pixel circuit includes a light-emitting element (E0), a driving circuit (10), a first light-emitting control circuit (11), a first control circuit (12), a second control circuit (13), and a data writing circuit (32); the first control circuit (12) provides a first control voltage to a second control node (N2) under the control of a first reset control signal, and controls a first light-emitting control line (E1) to provide a first light-emitting control signal to a first control node (N1) under the control of the potential of the second control node (N2); the second control circuit (13) writes a second control voltage into a third control node (N3) under the control of a second reset control signal, and controls a second light-emitting control line (Hf) to provide a second light-emitting control signal to the first control node (N1) under the control of the potential of the third control node (N3).

Description

[0001] This application claims the priority of the PCT application with the filing date of March 31, 2023 and the application number of PCT / CN2023 / 085358. Technical Field

[0002] The present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method, a display substrate, a display panel, and a display device. Background Art

[0003] Related pixel circuits including micro light-emitting diodes or mini light-emitting diodes adopt a first data line and a second data line. Among them, the first data line is used to provide a light-emitting time data voltage, the second data line is used to provide a display data voltage, and the first data line and the second data line are arranged between two columns of pixel circuits, resulting in a large number of side signals. Due to the coupling effect of the signals on the first data line and the signals on the second data line during the charging compensation stage, the voltage jump brought by the display data voltage during the charging compensation stage will cause column-direction defects in the related pixel circuits. Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a pixel circuit, including a light-emitting element and a pixel driving circuit; the pixel driving circuit includes a driving circuit, a first light-emitting control circuit, a first control circuit, a second control circuit, and a data writing circuit;

[0005] The driving circuit is configured to generate a driving current for driving the light-emitting element;

[0006] The first light-emitting control circuit is electrically connected to a first control node, a first end of the driving circuit, and the light-emitting element respectively, and is configured to control the connection between the first end of the driving circuit and the light-emitting element under the control of the potential of the first control node;

[0007] The first control circuit is electrically connected to a data line, a first reset control line, a first light-emitting control line, the first control node, and a second control node respectively, and is configured to provide a first control voltage provided by the data line to the second control node under the control of a first reset control signal provided by the first reset control line, and control the first light-emitting control line to provide a first light-emitting control signal to the first control node under the control of the potential of the second control node;

[0008] The second control circuit is electrically connected to the data line, the second reset control line, the second light-emitting control line, the first control node, and the third control node respectively, and is configured to write the second control voltage provided by the data line into the third control node under the control of the second reset control signal provided by the second reset control line, and control the second light-emitting control line to provide a second light-emitting control signal to the first control node under the control of the potential of the third control node;

[0009] The data writing circuit is electrically connected to the scanning line, the data line, and the second end of the driving circuit respectively, and is configured to write the display data voltage provided by the data line into the second end of the driving circuit under the control of the scanning signal provided by the scanning line;

[0010] The first control circuit, the second control circuit, and the data writing circuit are configured to access corresponding voltage signals on the data line in a time-sharing manner;

[0011] The pulse width of the scanning signal, the pulse width of the first reset control signal, and the pulse width of the second reset control signal are the same; or at least two of the pulse width of the scanning signal, the pulse width of the first reset control signal, and the pulse width of the second reset control signal are different.

[0012] Optionally, the scanning line, the first reset control line, and the second reset control line are electrically connected to different GOA circuits in the same GOA module respectively, and access the driving signals provided by the different GOA circuits; or,

[0013] The scanning line, the first reset control line, and the second reset control line are electrically connected to a GOA circuit in different GOA modules respectively, and access the driving signals provided by a GOA circuit in different GOA modules; or,

[0014] Two of the scanning line, the first reset control line, and the second reset control line are electrically connected to different GOA circuits in the first GOA module respectively, and access the driving signals provided by the different GOA circuits in the first GOA module, and the other of the scanning line, the first reset control line, and the second reset control line is electrically connected to a GOA circuit in the second GOA module, and accesses the driving signal provided by a GOA circuit in the second GOA module.

[0015] Optionally, the first control circuit includes a first writing control circuit, a first energy storage circuit, and a second writing control circuit;

[0016] The first writing control circuit is electrically connected to the first reset control line, the data line, and the second control node respectively, and is configured to provide the first control voltage provided by the data line to the second control node under the control of the first reset control signal;

[0017] The first energy storage circuit is electrically connected to the second control node and is used for the energy storage circuit;

[0018] The second writing control circuit is electrically connected to the second control node, the first light emission control line, and the first control node respectively, and is configured to control the first light emission control line to provide a first light emission control signal to the first control node under the control of the potential of the second control node.

[0019] Optionally, the second control circuit includes a third writing control circuit, a second energy storage circuit, and a fourth writing control circuit;

[0020] The third writing control circuit is electrically connected to the second reset control line, the data line, and the third control node respectively, and writes the second control voltage provided by the data line into the third control node under the control of the second reset control signal;

[0021] The second energy storage circuit is electrically connected to the third control node and is used for storing electrical energy;

[0022] The fourth writing control circuit is electrically connected to the third control node, the second light emission control line, and the first control node respectively, and is configured to control the second light emission control line to provide a second light emission control signal to the first control node under the control of the potential of the third control node.

[0023] Optionally, the first writing control circuit includes a first transistor, the first energy storage circuit includes a first capacitor, and the second writing control circuit includes a second transistor;

[0024] The gate of the first transistor is electrically connected to the first reset control line, the first pole of the first transistor is electrically connected to the data line, and the second pole of the first transistor is electrically connected to the second control node;

[0025] The first plate of the first capacitor is electrically connected to the second control node, and the second plate of the first capacitor is electrically connected to the first initial voltage line;

[0026] The gate of the second transistor is electrically connected to the second control node, the first pole of the second transistor is electrically connected to the first light emission control line, and the second pole of the second transistor is electrically connected to the first control node.

[0027] Optionally, the third writing control circuit includes a third transistor, the second energy storage circuit includes a second capacitor, and the fourth writing control circuit includes a fourth transistor;

[0028] The gate of the third transistor is electrically connected to the second reset control line, the first pole of the third transistor is electrically connected to the data line, and the second pole of the third transistor is electrically connected to the third control node;

[0029] The first electrode plate of the second capacitor is electrically connected to the third control node, and the second electrode plate of the second capacitor is electrically connected to the second initial voltage line;

[0030] The gate of the fourth transistor is electrically connected to the third control node, the first pole of the fourth transistor is electrically connected to the second light emission control line, and the second pole of the fourth transistor is electrically connected to the first control node.

[0031] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a second light emission control circuit;

[0032] The second light emission control circuit is respectively electrically connected to the first light emission control line, the power supply voltage line, and the second end of the driving circuit, and is configured to control the connection between the power supply voltage line and the second end of the driving circuit under the control of the first light emission control signal.

[0033] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a compensation control circuit and a third energy storage circuit;

[0034] The compensation control circuit is respectively electrically connected to the scanning line, the control end of the driving circuit, and the first end of the driving circuit, and is configured to control the connection between the control end of the driving circuit and the first end of the driving circuit under the control of the scanning signal;

[0035] The third energy storage circuit is electrically connected to the control end of the driving circuit and is configured to store electrical energy.

[0036] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first reset circuit;

[0037] The first reset circuit is respectively electrically connected to the third reset control line, the third initial voltage line, and the control end of the driving circuit, and is configured to write the third initial voltage provided by the third initial voltage line into the control end of the driving circuit under the control of the third reset control signal provided by the third reset control line.

[0038] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a second reset circuit;

[0039] The second reset circuit is electrically connected to the fourth reset control line, the fourth initial voltage line, and the first pole of the light-emitting element respectively, and is configured to write the fourth initial voltage provided by the fourth initial voltage line into the first pole of the light-emitting element under the control of the fourth reset control signal provided by the fourth reset control line;

[0040] The second pole of the light-emitting element is electrically connected to the first voltage line.

[0041] Optionally, the third reset control line is the first reset control line or the second reset control line;

[0042] The fourth reset control line is the first reset control line or the second reset control line.

[0043] Optionally, the second light control circuit includes a fifth transistor;

[0044] The gate of the fifth transistor is electrically connected to the first light control line, the first pole of the fifth transistor is electrically connected to the power supply voltage line, and the second pole of the fifth transistor is electrically connected to the second end of the driving circuit.

[0045] Optionally, the data writing circuit includes a sixth transistor, the compensation control circuit includes a seventh transistor, the third energy storage circuit includes a third capacitor; the driving circuit includes a driving transistor;

[0046] The gate of the sixth transistor is electrically connected to the scanning line, the first pole of the sixth transistor is electrically connected to the data line, and the second pole of the sixth transistor is electrically connected to the second pole of the driving transistor;

[0047] The gate of the seventh transistor is electrically connected to the scanning line, the first pole of the seventh transistor is electrically connected to the gate of the driving transistor, and the second pole of the seventh transistor is electrically connected to the first pole of the driving transistor;

[0048] The first plate of the third capacitor is electrically connected to the gate of the driving transistor, and the second plate of the third capacitor is electrically connected to the power supply voltage line.

[0049] Optionally, the first reset circuit includes an eighth transistor;

[0050] The gate of the eighth transistor is electrically connected to the third reset control line, the first pole of the eighth transistor is electrically connected to the third initial voltage line, and the second pole of the eighth transistor is electrically connected to the control end of the driving circuit.

[0051] Optionally, the second reset circuit includes a ninth transistor;

[0052] The gate of the ninth transistor is electrically connected to the fourth reset control line, the first pole of the ninth transistor is electrically connected to the fourth initial voltage line, and the second pole of the ninth transistor is electrically connected to the first pole of the light-emitting element.

[0053] Optionally, the pixel circuit according to at least one embodiment of the present disclosure includes a multiplexing control circuit;

[0054] The multiplexing control circuit is respectively electrically connected to the multiplexing control terminal, the voltage output terminal of the source driver, and the data line, and is configured to control the connection between the voltage output terminal and the data line under the control of the multiplexing control signal provided by the multiplexing control terminal.

[0055] In a second aspect, an embodiment of the present disclosure provides a driving method applied to the above pixel circuit. The display stage includes a first writing stage and a second writing stage; the driving method includes:

[0056] In the first writing stage, the first control circuit provides the first control voltage provided by the data line to the second control node under the control of the first reset control signal, and the first control circuit controls whether to provide the first light-emitting control signal to the first control node under the control of the potential of the second control node;

[0057] In the second writing stage, the second control circuit writes the second control voltage provided by the data line into the third control node under the control of the second reset control signal, and the second control circuit controls whether to provide the second light-emitting control signal to the first control node under the control of the potential of the third control node.

[0058] Optionally, the driving method according to at least one embodiment of the present disclosure includes:

[0059] When performing medium-high gray-scale display, in the first writing stage, the first control circuit controls to provide the first light-emitting control signal to the first control node under the control of the potential of the second control node, and in the second writing stage, the second control circuit controls to stop providing the second light-emitting control signal to the first control node under the control of the potential of the third control node;

[0060] When performing low gray-scale display, in the first writing stage, the first control circuit stops controlling to provide the first light-emitting control signal to the first control node under the control of the potential of the second control node, and in the second writing stage, the second control circuit controls to provide the second light-emitting control signal to the first control node under the control of the potential of the third control node.

[0061] In a third aspect, an embodiment of the present disclosure provides a display substrate, including a substrate and a plurality of rows and columns of the above-mentioned pixel circuits disposed in a display area on the substrate.

[0062] Optionally, the pixel circuits in the same column are disposed between two data lines; the data lines extend along a first direction;

[0063] The pixel circuit in the a-th row is disposed between the a-th row scanning line and the a-th row first voltage line, where a is a positive integer;

[0064] The a-th row scanning line and the a-th row first voltage line extend along a second direction;

[0065] The first direction and the second direction intersect.

[0066] Optionally, the pixel circuit includes a light-emitting element and a pixel driving circuit;

[0067] A gap is provided between at least two adjacent pixel driving circuits in the second direction, and at least one of the light-emitting elements is disposed in the gap;

[0068] The orthographic projection of the light-emitting element on the substrate does not overlap with the pixel driving circuit on the substrate.

[0069] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a first signal line; most of the signal line portions included in the first signal line extend along the second direction;

[0070] The first signal line bends around the light-emitting element to form a first avoidance space, and at least a part of the light-emitting element is disposed in the first avoidance space.

[0071] Optionally, the display substrate according to at least one embodiment of the present disclosure includes multiple rows of light-emitting units, and each light-emitting unit includes at least three of the light-emitting elements;

[0072] At least one of the first signal lines bends toward a first side around at least one of the light-emitting elements in the odd-row light-emitting units to form a first avoidance space;

[0073] At least one of the first signal lines bends toward a second side around at least one of the light-emitting elements in the even-row light-emitting units to form another first avoidance space;

[0074] The first side and the second side are opposite sides.

[0075] Optionally, the pixel circuit includes a light-emitting element and a pixel driving circuit;

[0076] The light-emitting element is disposed on a side of the pixel driving circuit away from the substrate;

[0077] The orthographic projection of the light-emitting element on the substrate substantially overlaps with the orthographic projection of the pixel driving circuit on the substrate.

[0078] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a light-emitting control signal generation module and a second signal line. The light-emitting control signal generation module includes a multi-stage light-emitting control signal generation circuit; the light-emitting control signal generation circuit is disposed in the display area;

[0079] The display substrate includes a plurality of rows and columns of pixel driving groups, and each pixel driving group includes at least one pixel driving circuit;

[0080] At least one stage of the light-emitting control signal generation circuit is located between adjacent pixel driving groups;

[0081] Most of the signal line portions included in the second signal line extend in a first direction;

[0082] At least one of the second signal lines is bent around the at least one stage of the light-emitting control signal generation circuit to form a second avoidance space, and a part of the at least one stage of the light-emitting control signal generation circuit is disposed in the second avoidance space.

[0083] Optionally, the orthographic projection of the light-emitting control signal generation circuit on the substrate does not overlap with the orthographic projection of the pixel driving group on the substrate.

[0084] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a gate driving module. The gate driving module includes a multi-stage gate driving circuit; the gate driving circuit is disposed in the display area;

[0085] The display substrate includes a plurality of rows and columns of pixel driving groups, and each pixel driving group includes at least one pixel driving circuit;

[0086] At least one stage of the gate driving circuit is located between adjacent pixel driving groups.

[0087] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a second signal line; most of the signal line portions included in the second signal line extend in a first direction;

[0088] At least one of the second signal lines is bent around the at least one stage of the gate driving circuit to form a third avoidance space, and a part of the at least one stage of the gate driving circuit is disposed in the third avoidance space.

[0089] Optionally, a positive projection of the gate driving circuit on the substrate does not overlap with a positive projection of the pixel driving group on the substrate. In a fourth aspect, an embodiment of the present disclosure provides a display panel including the above-mentioned display substrate.

[0090] Optionally, the display panel according to at least one embodiment of the present disclosure further includes a source driver, multiple columns of data lines, and a multiplexing circuit;

[0091] Multiple pixel circuits located in the same column are all electrically connected to the same column of data lines;

[0092] The multiplexing circuit is electrically connected to multiple voltage output terminals, multiple multiplexing control terminals of the source driver, and the multiple columns of data lines respectively, and is configured to write a voltage signal provided by the source driver through its voltage output terminal into the data lines under the control of a multiplexing control signal provided by the multiplexing control terminal.

[0093] Optionally, the multiplexing circuit is electrically connected to N multiplexing control terminals respectively, and the multiplexing circuit includes M multiplexing sub-circuits, where N and M are integers greater than 1;

[0094] Each multiplexing sub-circuit is electrically connected to the voltage output terminal of the source driver, the N multiplexing control terminals, and N columns of the data lines, and is configured to control writing the voltage signal provided by the voltage output terminal to the nth data line among the N columns of data lines under the control of an nth multiplexing control signal provided by the nth multiplexing control terminal;

[0095] n is a positive integer less than or equal to N.

[0096] In a fifth aspect, an embodiment of the present disclosure provides a driving method applied to the above-mentioned display panel. The display period includes a first writing time period and a second writing time period; the first writing time period includes a first data writing time period and a second data writing time period, and the second writing time period includes a third data writing time period and a fourth data writing time period; the driving method includes:

[0097] In the first data writing time period, the multiplexing circuit writes a first control voltage provided by the source driver through its voltage output terminal into the data lines under the control of a reset control signal;

[0098] In the second data writing time period, the first control circuit provides the first control voltage provided by the data line to a second control node under the control of a first reset control signal, and the first control circuit controls whether to provide a first light emission control signal to a first control node under the control of the potential of the second control node;

[0099] In the third data writing time period, under the control of the reset control signal, the multiplexing circuit writes the second control voltage provided by the source driver through its voltage output terminal into the data line;

[0100] In the fourth data writing time period, under the control of the second reset control signal, the second control circuit writes the second control voltage provided by the data line into the third control node, and the second control circuit controls whether to provide the second light emission control signal to the first control node under the control of the potential of the third control node.

[0101] Optionally, the first data writing time period and the second data writing time period are set successively, and the third data writing time period and the fourth data writing time period are set successively; or,

[0102] The first data writing time period is included in the second data writing time period, and the third data writing time period is included in the fourth data writing time period.

[0103] In a sixth aspect, an embodiment of the present disclosure provides a display device including the above-mentioned display panel. Description of the Drawings

[0104] Figure 1 is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0105] Figure 2 is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0106] Figure 3 is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0107] Figure 4 is a circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0108] Figure 5 is the present disclosure Figure 4 a working timing diagram of at least one embodiment of the pixel circuit shown;

[0109] Figure 6 is the present disclosure Figure 4 a working timing diagram of at least one embodiment of the pixel circuit shown;

[0110] Figure 7 is the present disclosure Figure 4 a working timing diagram of at least one embodiment of the pixel circuit shown;

[0111] Figure 8A is a circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0112] Figure 8BIt is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0113] Figure 9 It is Figure 4 a layout diagram of at least one embodiment of the pixel circuit shown;

[0114] Figure 10 It is Figure 9 a layout diagram of the first gate metal layer in;

[0115] Figure 11 It is Figure 9 a layout diagram of the semiconductor layer in;

[0116] Figure 12 It is Figure 9 a layout diagram of the second gate metal layer in;

[0117] Figure 13 It is Figure 9 a layout diagram of the source / drain metal layer in;

[0118] Figure 14A It is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0119] Figure 14B It is Figure 14A a layout diagram of the first gate metal layer in;

[0120] Figure 14C It is Figure 14A a schematic diagram of the signal lines disposed on the first gate metal layer and the positions of the respective light-emitting elements in;

[0121] Figure 15 It is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0122] Figure 16 It is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0123] Figure 17 It is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0124] Figure 18 It is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0125] Figure 19 It is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0126] Figure 20 It is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0127] Figure 21 It is a circuit diagram of a display panel according to at least one embodiment of the present disclosure;

[0128] Figure 22 is the timing diagram of at least one embodiment of the display panel shown in the present disclosure; Figure 21 shown in the display panel;

[0129] Figure 23 is the timing diagram of at least one embodiment of the display panel shown in the present disclosure; Figure 21 shown in the display panel;

[0130] Figure 24 is the timing diagram of at least one embodiment of the display panel shown in the present disclosure; Figure 21 shown in the display panel;

[0131] Figure 25 is the timing diagram of at least one embodiment of the display panel shown in the present disclosure; Figure 21 shown in the display panel;

[0132] Figure 26 is the timing diagram of the display panel according to at least one embodiment of the present disclosure. Detailed implementation manners

[0133] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0134] The transistors adopted in all embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two poles of the transistor other than the gate, one pole is referred to as the first pole and the other pole is referred to as the second pole.

[0135] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be the drain and the second pole can be the source; or, the first pole can be the source and the second pole can be the drain.

[0136] As Figure 1 shown, the pixel circuit according to at least one embodiment of the present disclosure includes a light emitting element E0 and a pixel driving circuit; the pixel driving circuit includes a driving circuit 10, a first light emitting control circuit 11, a first control circuit 12, a second control circuit 13, and a data writing circuit 32;

[0137] The driving circuit 10 is used to generate a driving current for driving the light emitting element E0;

[0138] The first light emission control circuit 11 is electrically connected to the first control node N1, the first end of the driving circuit 10, and the light emitting element E0 respectively, and is configured to control the connection between the first end of the driving circuit 10 and the light emitting element E0 under the control of the potential of the first control node N1;

[0139] The first control circuit 12 is electrically connected to the data line DT, the first reset control line RA, the first light emission control line E1, the first control node N1, and the second control node N2 respectively, and is configured to provide the first control voltage provided by the data line DT to the second control node N2 under the control of the first reset control signal provided by the first reset control line RA, and to control the first light emission control line E1 to provide a first light emission control signal to the first control node N1 under the control of the potential of the second control node N2;

[0140] The second control circuit 13 is electrically connected to the data line DT, the second reset control line RB, the second light emission control line Hf, the first control node N1, and the third control node N3 respectively, and is configured to write the second control voltage provided by the data line DT into the third control node N3 under the control of the second reset control signal provided by the second reset control line RB, and to control the second light emission control line Hf to provide a second light emission control signal to the first control node N1 under the control of the potential of the third control node N3;

[0141] The data writing circuit 32 is electrically connected to the scan line G1, the data line DT, and the second end of the driving circuit 10 respectively, and is configured to write the display data voltage provided by the data line DT into the second end of the driving circuit 10 under the control of the scan signal provided by the scan line G1;

[0142] The first control circuit 12, the second control circuit 13, and the data writing circuit 32 are configured to access corresponding voltage signals on the data line DT in a time-division manner;

[0143] The pulse width of the scan signal, the pulse width of the first reset control signal, and the pulse width of the second reset control signal are the same; alternatively, at least two of the pulse width of the scan signal, the pulse width of the first reset control signal, and the pulse width of the second reset control signal are different.

[0144] In the present disclosure Figure 1In at least one embodiment of the pixel circuit shown, only one data line is used to provide the display data voltage Data_I and the emission time control data voltage Data_T in a time-division manner, which can reduce the number of side signals. At the same time, the situation of gray-scale signal loss when adding multiplexing transistors can be solved. Moreover, the integration of the display data voltage Data_I and the emission time control data voltage Data_T also avoids the coupling effect of the two signals during the charging compensation stage, reduces the voltage jump brought by the display data voltage Data_I during the charging compensation stage, and thus solves the column-wise defect of the original pixel circuit.

[0145] In at least one embodiment of the present disclosure, the scan line, the first reset control line, and the second reset control line are respectively electrically connected to different GOA circuits in the same GOA module, and are respectively connected to the driving signals provided by the different GOA circuits; or,

[0146] The scan line, the first reset control line, and the second reset control line are respectively electrically connected to a GOA circuit in different GOA modules, and are respectively connected to the driving signals provided by a GOA circuit in different GOA modules; or,

[0147] Two of the scan line, the first reset control line, and the second reset control line are electrically connected to different GOA circuits in the first GOA module, and are respectively connected to the driving signals provided by the different GOA circuits in the first GOA module. The other one of the scan line, the first reset control line, and the second reset control line is electrically connected to a GOA circuit in the second GOA module, and is connected to the driving signal provided by a GOA circuit in the second GOA module.

[0148] In specific implementation, the GOA module may include a plurality of cascaded GOA circuits; each stage of GOA circuit provides corresponding driving signals respectively;

[0149] The driving signal output terminal of the (a - 1)-th stage GOA circuit may be electrically connected to the input terminal of the a-th stage GOA circuit to provide an input signal for the a-th stage GOA circuit;

[0150] a is a positive integer.

[0151] In at least one embodiment of the present disclosure,

[0152] The pulse width of the scan signal, the pulse width of the first reset control signal, and the pulse width of the second reset control signal may be the same. Different stages of GOA circuits in the same GOA module may respectively provide corresponding driving signals for the scan line, the first reset control line, and the second reset control line to reduce the number of GOA modules used, which is beneficial to realizing a narrow border; or,

[0153] The pulse width of the scanning signal, the pulse width of the first reset control signal, and the pulse width of the second reset control signal may be different from each other. One level of GOA circuit in different GOA modules may respectively provide corresponding driving signals for the scanning line, the first reset control line, and the second reset control line; or,

[0154] Two of the pulse width of the scanning signal, the pulse width of the first reset control signal, and the pulse width of the second reset control signal may be the same. Different levels of GOA circuits in the first GOA module may provide corresponding driving signals for two of the scanning line, the first reset control line, and the second reset control line, and one GOA circuit in the second GOA module may provide a corresponding driving signal for the other of the scanning line, the first reset control line, and the second reset control line.

[0155] For example, the pulse width of the first reset control signal and the pulse width of the second reset control signal may be the same, and the pulse width of the scanning signal may be different from the pulse width of the first reset control signal. Different levels of GOA circuits in the first GOA module may respectively provide the first reset control signal and the second reset control signal for the first reset control line and the second reset control line, and one level of GOA circuit in the second GOA module may provide the scanning signal for the scanning line.

[0156] In at least one embodiment of the present disclosure, the first control voltage and the second control voltage may be light emission time control data voltages.

[0157] Optionally, the light emitting element may be a Mini LED (mini light emitting diode) or a Micro LED (micro light emitting diode), but not limited thereto. In a specific implementation, the light emitting element may also be an organic light emitting diode.

[0158] The present disclosure Figure 1 When at least one embodiment of the pixel circuit shown is operating,

[0159] When performing medium and high gray scale display, control is performed to provide a first light emission control signal to the first control node N1 on the first light emission control line E1, and different light emission currents are generated by different voltage values of the input display data voltages;

[0160] When performing low gray scale display, a control method of light emission current + light emission time is adopted, and a second light emission control signal on the second light emission control line Hf is provided to the first control node N1. The second light emission control signal is a high frequency signal, reducing the flicker problem in low gray scales.

[0161] The present disclosure Figure 1When at least one embodiment of the pixel circuit shown is operating, the display phase may include a first writing phase and a second writing phase; the driving method includes:

[0162] In the first writing phase, the first control circuit 12, under the control of the first reset control signal, provides the first control voltage provided by the data line DT to the second control node N2, and the first control circuit 12 controls whether to provide the first light emission control signal to the first control node N1 under the control of the potential of the second control node N2;

[0163] In the second writing phase, the second control circuit 13, under the control of the second reset control signal, writes the second control voltage provided by the data line DT to the third control node N3, and the second control circuit 13 controls whether to provide the second light emission control signal to the first control node N1 under the control of the potential of the third control node N3.

[0164] This disclosure Figure 1 When at least one embodiment of the pixel circuit shown is operating,

[0165] When performing medium-high gray-scale display, in the first writing phase, the first control circuit 12 controls to provide the first light emission control signal to the first control node N1 under the control of the potential of the second control node N2, and in the second writing phase, the second control circuit 13 controls to stop providing the second light emission control signal to the first control node N1 under the control of the potential of the third control node N3;

[0166] When performing low gray-scale display, in the first writing phase, the first control circuit 12 stops controlling to provide the first light emission control signal to the first control node N1 under the control of the potential of the second control node N2, and in the second writing phase, the second control circuit 13 controls to provide the second light emission control signal to the first control node N1 under the control of the potential of the third control node N3.

[0167] In at least one embodiment of this disclosure, the first control circuit includes a first writing control circuit, a first energy storage circuit, and a second writing control circuit;

[0168] The first writing control circuit is electrically connected to the first reset control line, the data line, and the second control node respectively, and is used to provide the first control voltage provided by the data line to the second control node under the control of the first reset control signal;

[0169] The first energy storage circuit is electrically connected to the second control node and is used for the energy storage circuit;

[0170] The second writing control circuit is electrically connected to the second control node, the first light-emitting control line, and the first control node respectively, and is configured to control the first light-emitting control line to provide a first light-emitting control signal to the first control node under the control of the potential of the second control node.

[0171] In a specific implementation, the first control circuit may include a first writing control circuit, a first energy storage circuit, and a second writing control circuit. The first writing control circuit controls to write a first control voltage to the second control node, and the second writing control circuit controls to write a first light-emitting control signal to the first control node.

[0172] In at least one embodiment of the present disclosure, the second control circuit includes a third writing control circuit, a second energy storage circuit, and a fourth writing control circuit;

[0173] The third writing control circuit is electrically connected to the second reset control line, the data line, and the third control node respectively, and writes the second control voltage provided by the data line to the third control node under the control of the second reset control signal;

[0174] The second energy storage circuit is electrically connected to the third control node and is configured to store electrical energy;

[0175] The fourth writing control circuit is electrically connected to the third control node, the second light-emitting control line, and the first control node respectively, and is configured to control the second light-emitting control line to provide a second light-emitting control signal to the first control node under the control of the potential of the third control node.

[0176] In a specific implementation, the second control circuit may include a third writing control circuit, a second energy storage circuit, and a fourth writing control circuit. The third writing control circuit controls to write a second control voltage to the third control node, and the fourth writing control circuit controls to provide a second light-emitting control signal to the first control node.

[0177] As Figure 2 shown, on the basis of at least one embodiment of the pixel circuit shown in Figure 1 shown,

[0178] The first control circuit includes a first writing control circuit 21, a first energy storage circuit 22, and a second writing control circuit 23;

[0179] The first writing control circuit 21 is electrically connected to the first reset control line RA, the data line DT, and the second control node N2 respectively, and is configured to provide the first control voltage provided by the data line DT to the second control node N2 under the control of the first reset control signal;

[0180] The first energy storage circuit 22 is electrically connected to the second control node N2 and is used for storing electrical energy;

[0181] The second writing control circuit 23 is respectively electrically connected to the second control node N2, the first light-emitting control line E1, and the first control node N1, and is used for controlling the first light-emitting control line E1 to provide a first light-emitting control signal to the first control node N1 under the control of the potential of the second control node N2;

[0182] The second control circuit includes a third writing control circuit 24, a second energy storage circuit 25, and a fourth writing control circuit 26;

[0183] The third writing control circuit 24 is respectively electrically connected to the second reset control line RB, the data line DT, and the third control node N3, and writes the second control voltage provided by the data line DT into the third control node N3 under the control of the second reset control signal;

[0184] The second energy storage circuit 25 is electrically connected to the third control node N3 and is used for storing electrical energy;

[0185] The fourth writing control circuit 26 is respectively electrically connected to the third control node N3, the second light-emitting control line Hf, and the first control node N1, and is used for controlling the second light-emitting control line Hf to provide a second light-emitting control signal to the first control node N1 under the control of the potential of the third control node N3.

[0186] Optionally, the first writing control circuit includes a first transistor, the first energy storage circuit includes a first capacitor, and the second writing control circuit includes a second transistor;

[0187] The gate of the first transistor is electrically connected to the first reset control line, the first pole of the first transistor is electrically connected to the data line, and the second pole of the first transistor is electrically connected to the second control node;

[0188] The first plate of the first capacitor is electrically connected to the second control node, and the second plate of the first capacitor is electrically connected to the first initial voltage line;

[0189] The gate of the second transistor is electrically connected to the second control node, the first pole of the second transistor is electrically connected to the first light-emitting control line, and the second pole of the second transistor is electrically connected to the first control node.

[0190] Optionally, the third writing control circuit includes a third transistor, the second energy storage circuit includes a second capacitor, and the fourth writing control circuit includes a fourth transistor;

[0191] The gate of the third transistor is electrically connected to the second reset control line, the first pole of the third transistor is electrically connected to the data line, and the second pole of the third transistor is electrically connected to the third control node;

[0192] The first plate of the second capacitor is electrically connected to the third control node, and the second plate of the second capacitor is electrically connected to the second initial voltage line;

[0193] The gate of the fourth transistor is electrically connected to the third control node, the first pole of the fourth transistor is electrically connected to the second light emission control line, and the second pole of the fourth transistor is electrically connected to the first control node.

[0194] The pixel circuit according to at least one embodiment of the present disclosure further includes a second light emission control circuit;

[0195] The second light emission control circuit is respectively electrically connected to the first light emission control line, the power supply voltage line, and the second end of the driving circuit, and is configured to control the connection between the power supply voltage line and the second end of the driving circuit under the control of the first light emission control signal.

[0196] In a specific implementation, the pixel circuit may further include a second light emission control circuit, and the second light emission control circuit controls the connection between the power supply voltage line and the second end of the driving circuit under the control of the first light emission control signal.

[0197] The pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit, a compensation control circuit, and a third energy storage circuit;

[0198] The data writing circuit is respectively electrically connected to the scanning line, the data line, and the second end of the driving circuit, and is configured to write the display data voltage provided by the data line into the second end of the driving circuit under the control of the scanning signal provided by the scanning line;

[0199] The compensation control circuit is respectively electrically connected to the scanning line, the control end of the driving circuit, and the first end of the driving circuit, and is configured to control the connection between the control end of the driving circuit and the first end of the driving circuit under the control of the scanning signal;

[0200] The third energy storage circuit is electrically connected to the control end of the driving circuit and is configured to store electrical energy.

[0201] In a specific implementation, the pixel circuit may further include a data writing circuit, a compensation control circuit, and a third energy storage circuit. The data writing circuit writes the display data voltage into the second end of the driving circuit under the control of the scanning signal, and the compensation control circuit controls the connection between the control end of the driving circuit and the first end of the driving circuit under the control of the scanning signal to perform threshold voltage compensation control.

[0202] The pixel circuit according to at least one embodiment of the present disclosure further includes a first reset circuit;

[0203] The first reset circuit is electrically connected to a third reset control line, a third initial voltage line, and a control terminal of the driving circuit respectively, and is configured to write a third initial voltage provided by the third initial voltage line into the control terminal of the driving circuit under the control of a third reset control signal provided by the third reset control line.

[0204] In a specific implementation, the pixel circuit may further include a first reset circuit;

[0205] The first reset circuit writes a third initial voltage into the control terminal of the driving circuit under the control of a third reset control signal, so that a driving transistor included in the driving circuit can be turned on at the beginning of a charge compensation stage.

[0206] The pixel circuit according to at least one embodiment of the present disclosure further includes a second reset circuit;

[0207] The second reset circuit is electrically connected to a fourth reset control line, a fourth initial voltage line, and a first pole of the light-emitting element respectively, and is configured to write a fourth initial voltage provided by the fourth initial voltage line into the first pole of the light-emitting element under the control of a fourth reset control signal provided by the fourth reset control line;

[0208] A second pole of the light-emitting element is electrically connected to a first voltage line.

[0209] Optionally, the first voltage line may be a low voltage line, but not limited thereto.

[0210] In a specific implementation, the pixel circuit may further include a second reset circuit; the second reset circuit writes a fourth initial voltage into the first pole of the light-emitting element under the control of a fourth reset control signal to control the light-emitting element not to emit light and clear residual charges at the first pole of the light-emitting element.

[0211] Optionally, the third reset control line is the first reset control line or the second reset control line;

[0212] The fourth reset control line is the first reset control line or the second reset control line.

[0213] In at least one embodiment of the present disclosure, the third reset control line may be the first reset control line or the second reset control line, and the fourth reset control line may be the first reset control line or the second reset control line, so as to reduce the number of control lines used.

[0214] As Figure 3 shown, in Figure 2Based on at least one embodiment of the pixel circuit shown, at least one embodiment of the pixel circuit described in the present disclosure further includes a second light emission control circuit 31, a compensation control circuit 33, a third energy storage circuit 34, a first reset circuit 35, and a second reset circuit 36;

[0215] The second light emission control circuit 31 is respectively electrically connected to a first light emission control line E1, a power supply voltage line VDD, and a second end of the driving circuit 10, and is configured to control the connection between the power supply voltage line VDD and the second end of the driving circuit 10 under the control of a first light emission control signal provided by the first light emission control line E1;

[0216] The compensation control circuit 33 is respectively electrically connected to the scan line G1, a control end of the driving circuit 10, and a first end of the driving circuit 10, and is configured to control the connection between the control end of the driving circuit 10 and the first end of the driving circuit 10 under the control of the scan signal;

[0217] The third energy storage circuit 34 is electrically connected to the control end of the driving circuit 10 and is configured to store electrical energy.

[0218] The first reset circuit 35 is respectively electrically connected to a first reset control line RA, a third initial voltage line I3, and the control end of the driving circuit 10, and is configured to write a third initial voltage provided by the third initial voltage line I3 into the control end of the driving circuit 10 under the control of a first reset control signal provided by the first reset control line RA;

[0219] The second reset circuit 36 is respectively electrically connected to the first reset control line RA, a fourth initial voltage line I4, and a first pole of the light emitting element E0, and is configured to write a fourth initial voltage provided by the fourth initial voltage line I4 into the first pole of the light emitting element E0 under the control of a first reset control signal provided by the first reset control line RA;

[0220] A second pole of the light emitting element E0 is electrically connected to a first voltage line.

[0221] In Figure 3 at least one embodiment shown, the third reset control line is the first reset control line, and the fourth reset control line is the first reset control line.

[0222] In specific implementation, the third reset control line and the fourth reset control line may also both be the second reset control line, or the third reset control line is the first reset control line and the fourth reset control line is the second reset control line; or the third reset control line is the second reset control line and the fourth reset control line is the first reset control line.

[0223] In at least one embodiment of the present disclosure, the first initial voltage line, the second initial voltage line, the third initial voltage line, and the fourth initial voltage line may be the same initial voltage line to reduce the number of initial voltage lines used.

[0224] Optionally, the second light-emitting control circuit includes a fifth transistor;

[0225] The gate of the fifth transistor is electrically connected to the first light-emitting control line, the first pole of the fifth transistor is electrically connected to the power supply voltage line, and the second pole of the fifth transistor is electrically connected to the second end of the driving circuit.

[0226] Optionally, the data writing circuit includes a sixth transistor, the compensation control circuit includes a seventh transistor, the third energy storage circuit includes a third capacitor; the driving circuit includes a driving transistor;

[0227] The gate of the sixth transistor is electrically connected to the scanning line, the first pole of the sixth transistor is electrically connected to the data line, and the second pole of the sixth transistor is electrically connected to the second pole of the driving transistor;

[0228] The gate of the seventh transistor is electrically connected to the scanning line, the first pole of the seventh transistor is electrically connected to the gate of the driving transistor, and the second pole of the seventh transistor is electrically connected to the first pole of the driving transistor;

[0229] The first plate of the third capacitor is electrically connected to the gate of the driving transistor, and the second plate of the third capacitor is electrically connected to the power supply voltage line.

[0230] Optionally, the first reset circuit includes an eighth transistor;

[0231] The gate of the eighth transistor is electrically connected to the third reset control line, the first pole of the eighth transistor is electrically connected to the third initial voltage line, and the second pole of the eighth transistor is electrically connected to the control end of the driving circuit.

[0232] Optionally, the second reset circuit includes a ninth transistor;

[0233] The gate of the ninth transistor is electrically connected to the fourth reset control line, the first pole of the ninth transistor is electrically connected to the fourth initial voltage line, and the second pole of the ninth transistor is electrically connected to the first pole of the light-emitting element.

[0234] As Figure 4 shown, on the basis of at least one embodiment of the pixel circuit shown in Figure 3 shown, the first writing control circuit includes a first transistor M1, the first energy storage circuit includes a first capacitor C1, and the second writing control circuit includes a second transistor M2;

[0235] The gate of the first transistor M1 is electrically connected to the first reset control line RA, the source of the first transistor M1 is electrically connected to the data line DT, and the drain of the first transistor M1 is electrically connected to the second control node N2;

[0236] The first plate of the first capacitor C1 is electrically connected to the second control node N2, and the second plate of the first capacitor C1 is electrically connected to the initial voltage line I0; the initial voltage line I0 is used to provide an initial voltage Vinit;

[0237] The gate of the second transistor M2 is electrically connected to the second control node N2, the source of the second transistor M2 is electrically connected to the first light emission control line E1, and the drain of the second transistor M2 is electrically connected to the first control node N1;

[0238] The third writing control circuit includes a third transistor M3, the second energy storage circuit includes a second capacitor C2, and the fourth writing control circuit includes a fourth transistor M4;

[0239] The gate of the third transistor M3 is electrically connected to the second reset control line RB, the source of the third transistor M3 is electrically connected to the data line DT, and the drain of the third transistor M3 is electrically connected to the third control node N3;

[0240] The first plate of the second capacitor C2 is electrically connected to the third control node N3, and the second plate of the second capacitor C2 is electrically connected to the initial voltage line I0;

[0241] The gate of the fourth transistor M4 is electrically connected to the third control node N3, the source of the fourth transistor M4 is electrically connected to the second light emission control line Hf, and the drain of the fourth transistor M4 is electrically connected to the first control node N1;

[0242] The second light emission control circuit includes a fifth transistor M5;

[0243] The gate of the fifth transistor M5 is electrically connected to the first light emission control line E1, the source of the fifth transistor M5 is electrically connected to the power supply voltage line VDD, and the drain of the fifth transistor M5 is electrically connected to the source of the driving transistor M0;

[0244] The data writing circuit includes a sixth transistor M6, the compensation control circuit includes a seventh transistor M7, the third energy storage circuit includes a third capacitor C3; the driving circuit includes a driving transistor M0;

[0245] The gate of the sixth transistor M6 is electrically connected to the scan line G1, the source of the sixth transistor M6 is electrically connected to the data line DT, and the drain of the sixth transistor M6 is electrically connected to the drain of the driving transistor M0;

[0246] The gate of the seventh transistor M7 is electrically connected to the scan line G1, the source of the seventh transistor M7 is electrically connected to the gate of the driving transistor M0, and the drain of the seventh transistor M7 is electrically connected to the drain of the driving transistor M0;

[0247] The first plate of the third capacitor C3 is electrically connected to the gate of the driving transistor M0, and the second plate of the third capacitor C3 is electrically connected to the power supply voltage line VDD;

[0248] The first reset circuit includes an eighth transistor M8;

[0249] The gate of the eighth transistor M8 is electrically connected to the first reset control line RA, the source of the eighth transistor M8 is electrically connected to the initial voltage line I0, and the drain of the eighth transistor M8 is electrically connected to the gate of the driving transistor M0;

[0250] The second reset circuit includes a ninth transistor M9;

[0251] The gate of the ninth transistor M9 is electrically connected to the first reset control line RA, the source of the ninth transistor M9 is electrically connected to the initial voltage line I0, and the drain of the ninth transistor M9 is electrically connected to the anode of the micro light-emitting diode ML;

[0252] The cathode of the micro light-emitting diode ML is electrically connected to the low voltage line VSS;

[0253] The first light emission control circuit includes a tenth transistor M10;

[0254] The gate of M10 is electrically connected to the first control node N1, the source of M10 is electrically connected to the drain of M0, and the drain of M10 is electrically connected to the anode of ML.

[0255] In Figure 4 At least one embodiment of the pixel circuit shown, all the transistors are p-type transistors, but not limited thereto.

[0256] In Figure 4 At least one embodiment of the pixel circuit shown, the light-emitting element is the micro light-emitting diode ML, but not limited thereto.

[0257] In Figure 4In at least one embodiment of the pixel circuit shown, the gate of M8 can also be electrically connected to the second reset control line RB. At this time, in the second writing stage S2, M8 is turned on to initialize the potential of the gate of M0.

[0258] In Figure 4 In at least one embodiment of the pixel circuit shown, the gate signals of M6, M1, and M3 are separated to achieve time-division writing of the display data voltage, the first control voltage, and the second control voltage. The first control voltage and the second control voltage can be the emission time control data voltage.

[0259] As Figure 5 shown, the present disclosure Figure 4 In at least one embodiment of the pixel circuit shown, during operation, the display cycle includes a first writing stage S1, a second writing stage S2, a charge compensation stage S3, and a light emission stage S4 that are set successively;

[0260] In the first writing stage S1, RA provides a low voltage signal, RB provides a high voltage signal, G1 provides a high voltage signal, EM and Hf provide high voltage signals, DT provides the first control voltage, and M1 is turned on to write the first control voltage Data_T1 to the second control node N2. When performing medium-high gray-scale display, the first control voltage is a low voltage signal, and M2 is turned on to control the connection between E1 and the first control node N1; when performing low gray-scale display, the first control voltage is a high voltage signal, M2 is turned off, and C1 maintains the potential of the second control node N2;

[0261] In the first writing stage S1, RA provides a low voltage signal, M8 and M9 are turned on, and I0 provides the initial voltage Vinit to the gate of M0 and the anode of ML, so that at the beginning of the charge compensation stage, M0 can conduct, control ML not to emit light, and clear the charge remaining at the anode of ML;

[0262] In the second writing stage S2, RA provides a high voltage signal, RB provides a low voltage signal, G1 provides a high voltage signal, EM and Hf provide high voltage signals, DT provides the second control voltage, and M3 is turned on to write the second control voltage Data_T2 to the third control node N3; when performing medium-high gray-scale display, the second control voltage is a high voltage signal, and M4 is turned off; when performing low gray-scale display, the second control voltage is a low voltage signal, and M4 is turned on to control the connection between Hf and N1, and C2 maintains the potential of the third control node N3;

[0263] In the charging compensation stage S3, RA provides a high voltage signal, RB provides a high voltage signal, G1 provides a low voltage signal, EM and Hf provide high voltage signals, DT provides a display data voltage Data_I, M6 and M7 are turned on, and the display data voltage Data_I is written into the source of M0, and the connection between the gate and the drain of M3 is established;

[0264] At the start of the charging compensation stage S3, M0 is turned on, and the display data voltage Data_I charges C3 through the turned-on M0 and M7 until M0 is turned off. At this time, the potential of the gate of M0 is Data_I + Vth, where Vth is the threshold voltage of M0;

[0265] In the light-emitting stage S4, EM provides a low voltage signal. During some time periods included in the light-emitting stage S4, Hf provides a low voltage signal;

[0266] When performing medium-high gray-scale display, the connection between N1 and EM is established, and in the light-emitting stage S4, M3 drives ML to emit light;

[0267] When performing low gray-scale display, the connection between N1 and Hf is established. When Hf outputs a low voltage signal, M3 drives ML to emit light.

[0268] As Figure 5 shown, the low-level pulse widths of the first reset control signal provided by RA, the second reset control signal provided by RB, and the low-level pulse width of the scan signal provided by G1 are equal. Therefore, a single GOA (Gate On Array) circuit can be used to provide the first reset control signal, the second reset control signal, and the scan signal, reducing the number of GOA circuits employed and facilitating the implementation of a narrow bezel.

[0269] In at least one embodiment of the present disclosure, the low-level pulse widths of the first reset control signal provided by RA, the second reset control signal provided by RB, and the low-level pulse width of the scan signal provided by G1 are adjustable and may not be consistent.

[0270] In at least one embodiment of the present disclosure, the low-level pulse width of the scan signal provided by G1 may be greater than or equal to 2 μs to enable sufficient charging and threshold voltage compensation.

[0271] Figure 6 is Figure 4 the working timing diagram of at least one embodiment of the pixel circuit shown, Figure 6 and Figure 5The difference lies in that: the low-level pulse width of the scanning signal provided by G1 is relatively long, the low-level pulse width of the scanning signal provided by G1 is greater than the low-level pulse width of the first reset control signal provided by RSTA, and the low-level pulse width of the scanning signal provided by G1 is greater than the low-level pulse width of the second reset control signal provided by RSTB, so as to increase the time for charge compensation and enable sufficient threshold voltage compensation.

[0272] As Figure 6 shown, the low-level pulse width of the first reset control signal is the same as that of the second reset control signal, and the low-level pulse width of the scanning signal is greater than the low-level pulse width of the first reset control signal;

[0273] The first reset control signal can be provided by the nth-level GOA circuit of the first GOA module, the second reset control signal can be provided by the (n + 1)th-level GOA circuit of the first GOA module, and the scanning signal can be provided by the mth-level GOA circuit in the second GOA module;

[0274] n and m are positive integers.

[0275] In Figure 6 at least one of the embodiments shown, the first reset control signal provided by RA can be interchanged with the second reset control signal provided by RB.

[0276] As Figure 7 shown, when at least one of the embodiments of the pixel circuit shown in the present disclosure Figure 4 works, the display period includes a first writing stage S1, a second writing stage S2, a charge compensation stage S3, and a light emitting stage S4 set in sequence;

[0277] In the first writing stage S1, RA provides a high voltage signal, RB provides a low voltage signal, G1 provides a high voltage signal, EM and Hf provide high voltage signals, DT provides a first control voltage Data_T1, M1 is turned off, M3 is turned on, DT provides the first control voltage Data_T1 to the third control node N3, C2 maintains the potential of the third control node N3. When performing medium-high gray-scale display, the first control voltage Data_T1 is a high voltage signal. When performing low gray-scale display, the first control voltage Data_T1 is a low voltage signal, M4 is turned on, and the first control node N1 is connected to Hf;

[0278] In the second writing stage S2, RA provides a low voltage signal, RB provides a high voltage signal, G1 provides a high voltage signal, EM and Hf provide high voltage signals, DT provides a second control voltage Data_T2, M1 is turned on, M3 is turned off, DT provides the second control voltage Data_T2 to the second control node N2, and C1 maintains the potential of the second control node N2; when performing medium-high gray-scale display, the second control voltage Data_T2 is a low voltage signal, M2 is turned on, and the first control node N1 is connected to E1; when performing low gray-scale display, the second control voltage Data_T2 is a high voltage signal.

[0279] In the charge compensation stage S3, RA provides a high voltage signal, RB provides a high voltage signal, G1 provides a low voltage signal, EM and Hf provide high voltage signals, DT provides a display data voltage Data_I, M6 and M7 are turned on, the display data voltage Data_I is written to the source of M0, and the gate and drain of M3 are connected.

[0280] At the start of the charge compensation stage S3, M0 is turned on, and the display data voltage Data_I charges C3 through the turned-on M0 and M7 until M0 is turned off. At this time, the potential of the gate of M0 is Data_I + Vth, where Vth is the threshold voltage of M0.

[0281] In the light-emitting stage S4, EM provides a low voltage signal, and in some time periods included in the light-emitting stage S4, Hf provides a low voltage signal.

[0282] When performing medium-high gray-scale display, N1 is connected to EM, and in the light-emitting stage S4, M3 drives ML to emit light.

[0283] When performing low gray-scale display, N1 is connected to Hf, and when Hf outputs a low voltage signal, M3 drives ML to emit light.

[0284] In Figure 7 Among them, the low-level pulse width of the scan signal provided by G1 is greater than the low-level pulse width of the first reset control signal, and the low-level pulse width of the scan signal provided by G1 is greater than the low-level pulse width of the second reset control signal, so that the charge compensation stage lasts for a long time and can fully compensate the threshold voltage of the driving transistor. In actual operation, the low-level pulse width of the scan signal provided by G1, the low-level pulse width of the first reset control signal, and the low-level pulse width of the second reset control signal can also be equal.

[0285] In at least one embodiment of the present invention, the low-level pulse width of the scanning signal, the low-level pulse width of the first reset control signal, and the low-level pulse width of the second reset control signal may be equal. The second reset control signal may be provided by the nth-stage GOA circuit of the first GOA module, the first reset control signal may be provided by the (n + 1)th-stage GOA circuit of the first GOA module, and the scanning signal may be provided by the (n + 2)th-stage GOA circuit of the first GOA module, so as to reduce the number of GOA modules used and facilitate the realization of a narrow border; n is a positive integer.

[0286] The present disclosure Figure 8A At least one embodiment of the pixel circuit shown and the present disclosure Figure 4 The difference between at least one embodiment of the pixel circuit shown and at least one embodiment of the pixel circuit shown is that the gates of M8 and M9 are both electrically connected to the second reset control line RB.

[0287] The pixel circuit according to at least one embodiment of the present disclosure further includes a multiplexing control circuit;

[0288] The multiplexing control circuit is respectively electrically connected to the multiplexing control terminal, the voltage output terminal of the source driver, and the data line, and is configured to control the connection between the voltage output terminal and the data line under the control of the multiplexing control signal provided by the multiplexing control terminal.

[0289] In specific implementation, the pixel circuit may further include a multiplexing control circuit, which controls the electrical connection between the voltage output terminal of the source driver and the data line under the control of the multiplexing control signal, so as to reduce the number of voltage output terminals of the source driver.

[0290] Such as Figure 8B shown, on the basis of at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present disclosure may further include a multiplexing control circuit 80; Figure 3

[0291] The multiplexing control circuit 80 is respectively electrically connected to the multiplexing control terminal MX, the voltage output terminal CH of the source driver SD, and the data line DT, and is configured to control the connection between the voltage output terminal CH and the data line DT under the control of the multiplexing control signal provided by the multiplexing control terminal MX.

[0292] The driving method according to an embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the display stage includes a first writing stage and a second writing stage; the driving method includes:

[0293] ​In the first writing stage, under the control of the first reset control signal, the first control circuit provides the first control voltage provided by the data line to the second control node. The first control circuit controls whether to provide the first light-emitting control signal to the first control node under the control of the potential of the second control node;

[0294] In the second writing stage, under the control of the second reset control signal, the second control circuit writes the second control voltage provided by the data line into the third control node. The second control circuit controls whether to provide the second light-emitting control signal to the first control node under the control of the potential of the third control node.

[0295] The driving method according to at least one embodiment of the present disclosure includes:

[0296] When performing medium and high gray-scale display, in the first writing stage, the first control circuit controls to provide the first light-emitting control signal to the first control node under the control of the potential of the second control node. In the second writing stage, the second control circuit controls to stop providing the second light-emitting control signal to the first control node under the control of the potential of the third control node;

[0297] When performing low gray-scale display, in the first writing stage, the first control circuit stops controlling to provide the first light-emitting control signal to the first control node under the control of the potential of the second control node. In the second writing stage, the second control circuit controls to provide the second light-emitting control signal to the first control node under the control of the potential of the third control node.

[0298] The display substrate according to an embodiment of the present disclosure includes a substrate substrate and a plurality of rows and columns of the above pixel circuits disposed in a display area on the substrate substrate.

[0299] In at least one embodiment of the present disclosure, pixel circuits located in the same column are disposed between two columns of data lines; the data lines extend in a first direction;

[0300] The pixel circuit of the a-th row is disposed between the a-th row scanning line and the a-th row first voltage line, where a is a positive integer;

[0301] The a-th row scanning line and the a-th row first voltage line extend in a second direction;

[0302] The first direction and the second direction intersect.

[0303] Optionally, the first direction may be the vertical direction, and the second direction may be the horizontal direction, but it is not limited thereto.

[0304] In the related art, two data lines are provided between two adjacent pixel circuits. One of the data lines is used to provide the emission time data voltage, and the other data line is used to provide the display data voltage. In at least one embodiment of the present disclosure, only one data line is provided between two adjacent pixel circuits.

[0305] Figure 9 is Figure 4 a layout diagram of at least one embodiment of the pixel circuit shown. Figure 10 is Figure 9 a layout diagram of the first gate metal layer in Figure 11 is Figure 9 a layout diagram of the semiconductor layer in Figure 12 is Figure 9 a layout diagram of the second gate metal layer in Figure 13 is Figure 9 a layout diagram of the source-drain metal layer in

[0306] In at least one embodiment of the present disclosure, the first gate metal layer, the semiconductor layer, the second gate metal layer, and the source-drain metal layer may be arranged in sequence along a direction away from the substrate.

[0307] As Figure 9 shown, the one labeled VSS is the low voltage line, the one labeled DT is the data line, the one labeled I0 is the initial voltage line, the one labeled RA is the first reset control line, the one labeled RB is the second reset control line, the one labeled E1 is the first emission control line, and the one labeled G1 is the scan line.

[0308] In Figure 9 the at least one embodiment shown, the second emission control line Hf may include a first emission control line portion Hf1 extending in the vertical direction and a second emission control line portion Hf2 extending in the horizontal direction that are electrically connected to each other.

[0309] As Figure 9 shown, VSS, I0, RB, RA, E1, VDD, and G1 all extend in the horizontal direction;

[0310] DT extends in the vertical direction;

[0311] The first capacitor C1 and the second capacitor C2 are disposed between VSS and I0;

[0312] M3 is disposed between RB and I0;

[0313] M1, M8, M9, M4, and M2 are all disposed between RA and VDD;

[0314] C3, M5, M10, M6, M0, and M7 are all disposed between E1 and G1.

[0315] In Figure 10Among them, the one labeled C2b1 is the first plate part of the second capacitor, the one labeled C1b1 is the first plate part of the first capacitor, the one labeled C3b1 is the first plate part of the third capacitor, and the one labeled G0a is the bottom gate of M0.

[0316] In Figure 11 Among them, the one labeled A0 is the active pattern of M0, the one labeled A1 is the active pattern of M1, the one labeled A2 is the active pattern of M2, the one labeled A3 is the active pattern of M3, the one labeled A4 is the active pattern of M4, the one labeled A5 is the active pattern of M5, the one labeled A6 is the active pattern of M6, the one labeled A7 is the active pattern of M7, the one labeled A8 is the active pattern of M8, the one labeled A9 is the active pattern of M9, and the one labeled A10 is the active pattern of M10.

[0317] In Figure 12 Among them, the one labeled G0b is the top gate of G0, the one labeled C1a is the first plate of the first capacitor, the one labeled C2a is the first plate of the second capacitor, and the one labeled C3a is the first plate of the third capacitor.

[0318] In Figure 13 Among them, the one labeled C2b2 is the second plate part of the second capacitor, the one labeled C1b2 is the second plate part of the first capacitor, and the one labeled C3b2 is the second plate part of the third capacitor.

[0319] In Figures 9 - 13 In at least one embodiment, C1b1 and C1b2 are electrically connected, and C1b1 and C1b2 form the second plate of C1; C2b1 and C2b2 are electrically connected, and C2b1 and C2b2 form the second plate of C2; C3b1 and C3b2 are electrically connected, and C3b1 and C3b2 form the second plate of C3.

[0320] In at least one embodiment of the present disclosure, the pixel circuit includes a light-emitting element and a pixel driving circuit;

[0321] A gap is provided between at least two adjacent pixel driving circuits in the second direction, and at least one of the light-emitting elements is disposed in the gap;

[0322] The orthographic projection of the light-emitting element on the substrate does not overlap with the pixel driving circuit on the substrate.

[0323] In specific implementation, a gap is provided between at least two adjacent pixel driving circuits in the second direction, at least one light-emitting element is disposed in the gap, and the light-emitting element and the pixel driving circuit do not overlap in the direction perpendicular to the substrate.

[0324] Optionally, the second direction may be the horizontal direction, but is not limited thereto.

[0325] In at least one embodiment of the present disclosure, the light-emitting element may be disposed in the gap between pixel driving circuits so that the light-emitting element and the pixel driving circuit do not affect each other.

[0326] The display substrate according to at least one embodiment of the present disclosure further includes a first signal line; most of the signal line portions included in the first signal line extend in a second direction;

[0327] The first signal line is bent around the light-emitting element to form a first avoidance space, and at least part of the light-emitting element is disposed in the first avoidance space.

[0328] In a specific implementation, the display substrate may further include a first signal line, and the first signal line is bent around the light-emitting element to form a first avoidance space so that the light-emitting element is disposed in the first avoidance space.

[0329] In at least one embodiment of the present disclosure, most of the signal line portions in the first signal line extend in the horizontal direction, and the first signal line is bent downward or upward around the light-emitting element to form a first avoidance space to facilitate the layout of the light-emitting element.

[0330] Optionally, the first signal line may include a low-voltage line, an initial voltage line, a first reset control line, a second reset control line, a first light emission control line, and a scan line.

[0331] The display substrate according to at least one embodiment of the present disclosure includes multiple rows of light-emitting units, and each light-emitting unit includes at least three of the light-emitting elements;

[0332] At least one of the first signal lines is bent toward a first side around at least one of the light-emitting elements in the odd-numbered row light-emitting units to form a first avoidance space;

[0333] At least one of the first signal lines is bent toward a second side around at least one of the light-emitting elements in the even-numbered row light-emitting units to form another first avoidance space;

[0334] The first side and the second side are opposite sides.

[0335] Optionally, the first side may be the lower side and the second side may be the upper side; or, the first side may be the upper side and the second side may be the lower side; but it is not limited thereto.

[0336] Such as Figure 14AAs shown, the display substrate according to at least one embodiment of the present disclosure may include a first row and first column light-emitting unit, a first row and second column light-emitting unit, a first row and third column light-emitting unit, a first row and fourth column light-emitting unit, a first row and fifth column light-emitting unit, a first row and sixth column light-emitting unit, a second row and first column light-emitting unit, a second row and second column light-emitting unit, a second row and third column light-emitting unit, a second row and fourth column light-emitting unit, a second row and fifth column light-emitting unit, a second row and sixth column light-emitting unit, a third row and first column light-emitting unit, a third row and second column light-emitting unit, a third row and third column light-emitting unit, a third row and fourth column light-emitting unit, a third row and fifth column light-emitting unit, and a third row and sixth column light-emitting unit;

[0337] The first row and first column light-emitting unit includes a first row and first column blue light-emitting element B11, a first row and first column green light-emitting element G11, and a first row and first column red light-emitting element R11 from top to bottom;

[0338] The first row and second column light-emitting unit includes a first row and second column blue light-emitting element B12, a first row and second column green light-emitting element G12, and a first row and second column red light-emitting element R12 from top to bottom;

[0339] The first row and third column light-emitting unit includes a first row and third column blue light-emitting element B13, a first row and third column green light-emitting element G13, and a first row and third column red light-emitting element R13 from top to bottom;

[0340] The first row and fourth column light-emitting unit includes a first row and fourth column blue light-emitting element B14, a first row and fourth column green light-emitting element G14, and a first row and fourth column red light-emitting element R14 from top to bottom;

[0341] The second row and fifth column light-emitting unit includes a second row and fifth column blue light-emitting element B25, a second row and fifth column green light-emitting element G25, and a second row and fifth column red light-emitting element R25 from top to bottom;

[0342] The second row and sixth column light-emitting unit includes a second row and sixth column blue light-emitting element B26, a second row and sixth column green light-emitting element G26, and a second row and sixth column red light-emitting element R26 from top to bottom;

[0343] The second row and first column light-emitting unit includes a second row and first column blue light-emitting element B21, a second row and first column green light-emitting element G21, and a second row and first column red light-emitting element R21 from top to bottom;

[0344] The second row and second column light-emitting unit includes a second row and second column blue light-emitting element B22, a second row and second column green light-emitting element G22, and a second row and second column red light-emitting element R22 from top to bottom;

[0345] The light-emitting unit in the second row and third column includes a blue light-emitting element B23, a green light-emitting element G23, and a red light-emitting element R23 in the second row and third column from top to bottom;

[0346] The light-emitting unit in the second row and fourth column includes a blue light-emitting element B24, a green light-emitting element G24, and a red light-emitting element R24 in the second row and fourth column from top to bottom;

[0347] The light-emitting unit in the second row and fifth column includes a blue light-emitting element B25, a green light-emitting element G25, and a red light-emitting element R25 in the second row and fifth column from top to bottom;

[0348] The light-emitting unit in the second row and sixth column includes a blue light-emitting element B26, a green light-emitting element G26, and a red light-emitting element R26 in the second row and sixth column from top to bottom;

[0349] In Figure 14A among them, the one labeled P1 is the first pixel driving unit, the one labeled P2 is the second pixel driving unit, the one labeled P3 is the third pixel driving unit, the one labeled P4 is the fourth pixel driving unit, the one labeled P5 is the fifth pixel driving unit, the one labeled P6 is the sixth pixel driving unit, the one labeled P7 is the seventh pixel driving unit, the one labeled P8 is the eighth pixel driving unit, and the one labeled P9 is the ninth pixel driving unit;

[0350] Each pixel driving unit includes at least one pixel driving circuit;

[0351] The one labeled VSS is the low-voltage line, the one labeled I0 is the initial voltage line, the one labeled RB is the second reset control line, the one labeled RA is the first reset control line, the one labeled VDD is the power supply voltage line, the one labeled E1 is the first light-emitting control line, and the one labeled G1 is the scanning line;

[0352] VSS, I0, RA, E1, and G1 can be formed on the first gate metal layer;

[0353] RB and VDD can be formed on the second gate metal layer;

[0354] Most of the low-voltage line part included in VSS, most of the initial voltage line part included in I0, most of the second reset control line part included in RB, most of the first reset control line part included in RA, most of the power supply voltage line part included in VDD, most of the first light-emitting control line part included in E1, and most of the scanning line part included in G1 all extend in the horizontal direction;

[0355] R11, G11, B11, R21, G21, and B21 are arranged in the gap on the left side of the first pixel driving unit;

[0356] R12, G12, B12, R22, G22, and B22 are disposed in the gap between the second pixel driving unit and the third pixel driving unit;

[0357] R13, G13, B13, R23, G23, and B23 are disposed in the gap between the third pixel driving unit and the fourth pixel driving unit;

[0358] R14, G14, B14, R24, G24, and B24 are disposed in the gap between the fifth pixel driving unit and the sixth pixel driving unit;

[0359] R15, G15, B15, R25, G25, and B25 are disposed in the gap between the sixth pixel driving unit and the seventh pixel driving unit;

[0360] R16, G16, B16, R26, G26, and B26 are disposed in the gap between the eighth pixel driving unit and the ninth pixel driving unit;

[0361] The orthographic projection of each of the light-emitting elements on the substrate does not overlap with the pixel driving circuit included in each pixel driving unit on the substrate.

[0362] In at least one embodiment of the present disclosure, each light-emitting element may be an LED (light-emitting diode).

[0363] Figure 14B is Figure 14A a layout diagram of the first gate metal layer in Figure 14C is Figure 14A a schematic diagram of the signal lines disposed on the first gate metal layer and the positions of each light-emitting element in

[0364] As Figure 14B shown, in order to place R11, the initial voltage line I0 is bent downward to form the first first avoidance space A11; as Figure 14C shown, a part of R11 is disposed in A11;

[0365] As Figure 14B shown, in order to place R12, the initial voltage line I0 is bent downward to form the second first avoidance space A21; as Figure 14C shown, a part of R12 is disposed in A21;

[0366] As Figure 14B shown, in order to place R13, the initial voltage line I0 is bent downward to form the third first avoidance space A31; as Figure 14C shown, a part of R13 is disposed in A31;

[0367] As Figure 14BAs shown, in order to place R14, the initial voltage line I0 is bent downward to form the fourth first avoidance space A41; as Figure 14C shown, a part of R14 is disposed within A41;

[0368] As Figure 14B shown, in order to place R15, the initial voltage line I0 is bent downward to form the fifth first avoidance space A51; as Figure 14C shown, a part of R15 is disposed within A51;

[0369] As Figure 14B shown, in order to place R16, the initial voltage line I0 is bent downward to form the sixth first avoidance space A61; as Figure 14C shown, a part of R16 is disposed within A61;

[0370] As Figure 14B shown, in order to place B21, the first light emission control line E1 is bent upward to form the seventh first avoidance space A71; as Figure 14C shown, a part of B21 is disposed within A71;

[0371] As Figure 14B shown, in order to place B22, the first light emission control line E1 is bent upward to form the eighth first avoidance space A81; as Figure 14C shown, a part of B22 is disposed within A81;

[0372] As Figure 14B shown, in order to place B23, the first light emission control line E1 is bent upward to form the ninth first avoidance space A91; as Figure 14C shown, a part of B23 is disposed within A91;

[0373] As Figure 14B shown, in order to place B24, the first light emission control line E1 is bent upward to form the tenth first avoidance space A101; as Figure 14C shown, a part of B24 is disposed within A101;

[0374] As Figure 14B shown, in order to place B25, the first light emission control line E1 is bent upward to form the eleventh first avoidance space A111; as Figure 14C shown, a part of B25 is disposed within A111;

[0375] As Figure 14B shown, in order to place B26, the first light emission control line E1 is bent upward to form the twelfth first avoidance space A121; as Figure 14C shown, a part of B26 is disposed within A121.

[0376] In at least one embodiment of the present disclosure, each light-emitting element may be disposed between each pixel driving unit, and the pixel driving unit may include at least one pixel driving circuit;

[0377] Optionally, the display substrate may include a second signal line;

[0378] Most of the signal line portions included in the second signal line extend in a first direction;

[0379] The second signal line bends around the light-emitting element to form a fourth avoidance space, and at least a part of the light-emitting element is disposed in the fourth avoidance space.

[0380] In a specific implementation, the display substrate may include second signal lines that mostly extend in the vertical direction. The second signal lines may bend around the light-emitting element to form a fourth avoidance space to facilitate the placement of the light-emitting element.

[0381] In at least one embodiment of the present disclosure, the pixel circuit includes a light-emitting element and a pixel driving circuit;

[0382] The light-emitting element is disposed on a side of the pixel driving circuit away from the substrate;

[0383] The orthographic projection of the light-emitting element on the substrate at least partially overlaps with the orthographic projection of the pixel driving circuit on the substrate.

[0384] In a specific implementation, the pixel driving circuit may be disposed between the light-emitting element and the substrate, and the orthographic projection of the light-emitting element on the substrate at least partially overlaps with the orthographic projection of the pixel driving circuit on the substrate.

[0385] As Figure 15 shown, the one labeled P1 is the first pixel driving unit;

[0386] P1 includes a plurality of pixel driving circuits;

[0387] The one labeled B11 is the blue light-emitting element in the first row and the first column, the one labeled G11 is the green light-emitting element in the first row and the first column, and the one labeled R11 is the red light-emitting element in the first row and the first column;

[0388] The one labeled B12 is the blue light-emitting element in the first row and the second column, the one labeled G12 is the green light-emitting element in the first row and the second column, and the one labeled R12 is the red light-emitting element in the first row and the second column;

[0389] The one labeled B13 is the blue light-emitting element in the first row and the third column, the one labeled G13 is the green light-emitting element in the first row and the third column, and the one labeled R13 is the red light-emitting element in the first row and the third column;

[0390] The blue light-emitting element at the fourth column of the first row is labeled B14, the green light-emitting element at the fourth column of the first row is labeled G14, and the red light-emitting element at the fourth column of the first row is labeled R14;

[0391] The blue light-emitting element at the first column of the second row is labeled B21, the green light-emitting element at the first column of the second row is labeled G21, and the red light-emitting element at the first column of the second row is labeled R21;

[0392] The blue light-emitting element at the second column of the second row is labeled B22, the green light-emitting element at the second column of the second row is labeled G22, and the red light-emitting element at the second column of the second row is labeled R22;

[0393] The blue light-emitting element at the third column of the second row is labeled B23, the green light-emitting element at the third column of the second row is labeled G23, and the red light-emitting element at the third column of the second row is labeled R23;

[0394] The blue light-emitting element at the fourth column of the second row is labeled B24, the green light-emitting element at the fourth column of the second row is labeled G24, and the red light-emitting element at the fourth column of the second row is labeled R24;

[0395] The orthographic projection of R11 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of G11 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of B11 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate;

[0396] The orthographic projection of R12 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of G12 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of B12 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate;

[0397] The orthographic projection of R13 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of G13 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of B13 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate;

[0398] The orthographic projection of R14 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of G14 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of B14 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate;

[0399] The orthographic projection of R21 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of G21 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of B21 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate;

[0400] The orthographic projection of R22 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of G22 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of B22 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate;

[0401] The orthographic projection of R23 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of G23 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of B23 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate;

[0402] The orthographic projection of R24 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of G24 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of B24 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate.

[0403] In Figure 15 In at least one of the illustrated embodiments, the first pixel driving unit, R11, G11, B11, R12, G12, B12, R13, G13, B13, R14, G14, B14, R21, G21, B21, R22, G22, B22, R23, G23, B23, R24, G24, and B14 form a pixel driving group.

[0404] The display substrate according to at least one embodiment of the present disclosure further includes a light emission control signal generation module and a second signal line, the light emission control signal generation module includes a multi-stage light emission control signal generation circuit; the light emission control signal generation circuit is disposed in the display area;

[0405] The display substrate includes multiple rows and multiple columns of pixel driving groups, and each pixel driving group includes at least one pixel driving circuit;

[0406] At least one stage of the light emission control signal generation circuit is located between adjacent pixel driving groups;

[0407] Most of the signal line portions included in the second signal line extend in a first direction;

[0408] At least one of the second signal lines is bent around the at least one - stage light - emitting control signal generation circuit to form a second avoidance space, and a part of the at least one - stage light - emitting control signal generation circuit is disposed in the second avoidance space.

[0409] In a specific implementation, the at least one - stage light - emitting control signal generation circuit included in the light - emitting control signal generation module may be located between adjacent pixel driving groups. At least one second signal line is bent around the at least one - stage light - emitting control signal generation circuit to form a second avoidance space, and a part of the at least one - stage light - emitting control signal generation circuit is disposed in the second avoidance space to facilitate placing the at least one - stage light - emitting control signal generation circuit; the light - emitting control signal generation circuit may be disposed in the display area, which is conducive to achieving a narrow border.

[0410] In an embodiment of the present disclosure, the orthographic projection of the light - emitting control signal generation circuit on the substrate does not overlap with the orthographic projection of the pixel driving group on the substrate.

[0411] In a specific implementation, the light - emitting control signal generation circuit and the pixel driving group do not overlap in a direction perpendicular to the substrate, so that the light - emitting control signal generation circuit and the pixel driving group do not affect each other.

[0412] Optionally, the second signal line may include a data line and a second light - emitting control line, but is not limited thereto.

[0413] In at least one embodiment of the present disclosure, the second light - emitting control line may extend in the vertical direction; or, the second light - emitting control line may include a first light - emitting control line portion extending in the vertical direction and a second light - emitting control line portion extending in the horizontal direction.

[0414] In a specific implementation, the display substrate may further include a first signal line, and most of the signal line portions included in the first signal line extend in a second direction;

[0415] At least one of the first signal lines is bent around the at least one - stage light - emitting control signal generation circuit to form a fifth avoidance space, and a part of the at least one - stage light - emitting control signal generation circuit is disposed in the fifth avoidance space.

[0416] In a specific implementation, the display substrate may include first signal lines that mostly extend in the horizontal direction. The first signal lines may be bent around the light - emitting control signal generation circuit to form a fifth avoidance space to facilitate placing the light - emitting control signal generation circuit.

[0417] The display substrate according to at least one embodiment of the present disclosure further includes a gate driving module, and the gate driving module includes a multi-stage gate driving circuit; the gate driving circuit is disposed in the display area;

[0418] The display substrate includes a plurality of rows and columns of pixel driving groups, and each pixel driving group includes at least one pixel driving circuit;

[0419] At least one stage of the gate driving circuit is located between adjacent pixel driving groups.

[0420] In a specific implementation, at least one stage of the gate driving circuit included in the gate driving module is disposed between adjacent pixel driving groups, and the gate driving circuit can be disposed in the display area, which is beneficial to realizing a narrow border.

[0421] The display substrate according to at least one embodiment of the present disclosure further includes a second signal line; most of the signal line portions included in the second signal line extend along a first direction;

[0422] At least one of the second signal lines is bent around the at least one stage of the gate driving circuit to form a third avoidance space, and a part of the at least one stage of the gate driving circuit is disposed in the third avoidance space.

[0423] In a specific implementation, at least one second signal line is bent around the at least one stage of the gate driving circuit to form a third avoidance space, and a part of the at least one stage of the gate driving circuit is disposed in the third avoidance space so as to place the at least one stage of the gate driving circuit.

[0424] In at least one embodiment of the present disclosure, the orthographic projection of the gate driving circuit on the substrate does not overlap with the orthographic projection of the pixel driving group on the substrate.

[0425] In a specific implementation, the gate driving circuit and the pixel driving group do not overlap in a direction perpendicular to the substrate, so that the gate driving circuit and the pixel driving group do not affect each other.

[0426] In at least one embodiment of the present disclosure, the display substrate may further include a first signal line, and most of the signal line portions included in the first signal line extend along a second direction;

[0427] At least one of the first signal lines is bent around the at least one stage of the gate driving circuit to form a sixth avoidance space, and a part of the at least one stage of the gate driving circuit is disposed in the sixth avoidance space.

[0428] In a specific implementation, the display substrate may include first signal lines that mostly extend in the horizontal direction. The first signal lines may bend around the gate driving circuit to form a sixth avoidance space for placing the gate driving circuit.

[0429] As Figure 16 shown, the pixel driving group labeled F11 is the first-row and first-column pixel driving group, the pixel driving group labeled F12 is the first-row and second-column pixel driving group, and the pixel driving group labeled F13 is the first-row and third-column pixel driving group;

[0430] The pixel driving group labeled F21 is the second-row and first-column pixel driving group, the pixel driving group labeled F22 is the second-row and second-column repeating unit, and the pixel driving group labeled F23 is the second-row and third-column pixel driving group;

[0431] The light emission control signal generation circuit labeled EA1 is the first-stage light emission control signal generation circuit, and the light emission control signal generation circuit labeled EA2 is the second-stage light emission control signal generation circuit;

[0432] The gate driving circuit labeled GA1 is the first-stage gate driving circuit, the gate driving circuit labeled GA2 is the second-stage gate driving circuit, and the gate driving circuit labeled GA3 is the third-stage gate driving circuit;

[0433] EA1 and EA2 are arranged between F11, F21, F21, and F22;

[0434] GA1, GA2, and GA3 are arranged between F12, F22, F13, and F23.

[0435] In at least one embodiment of the present disclosure, the pixel driving group may include a 2-row and 2-column pixel driving circuit, a 2-row and 3-column pixel driving circuit, a 2-row and 4-column pixel driving circuit, or a 3-row and 3-column pixel circuit. The specific values of the number of rows and columns of the pixel driving circuits included in the pixel driving group are not limited. In Figure 16Among them, the one labeled HF1 is the first second light emission control line, the one labeled DT1 is the first data line, the one labeled HF2 is the second second light emission control line, the one labeled DT2 is the second data line, the one labeled HF3 is the third second light emission control line, the one labeled DT3 is the third data line, the one labeled HF4 is the fourth second light emission control line, the one labeled DT4 is the fourth data line, the one labeled HF5 is the fifth second light emission control line, the one labeled DT5 is the fifth data line, the one labeled HF6 is the sixth second light emission control line, the one labeled DT6 is the sixth data line, the one labeled HF7 is the seventh second light emission control line, the one labeled DT7 is the seventh data line, the one labeled HF8 is the eighth second light emission control line, the one labeled DT8 is the eighth data line, the one labeled HF9 is the ninth second light emission control line, the one labeled DT9 is the ninth data line, the one labeled HF10 is the tenth second light emission control line, the one labeled DT10 is the tenth data line, the one labeled HF11 is the eleventh second light emission control line, the one labeled DT11 is the eleventh data line, the one labeled HF12 is the twelfth second light emission control line, the one labeled DT12 is the twelfth data line; the one labeled HF13 is the thirteenth second light emission control line, the one labeled DT13 is the thirteenth data line, the one labeled HF14 is the fourteenth second light emission control line, the one labeled DT14 is the fourteenth data line, the one labeled HF15 is the fifteenth second light emission control line, the one labeled DT15 is the fifteenth data line, the one labeled HF16 is the sixteenth second light emission control line, the one labeled DT16 is the sixteenth data line, the one labeled HF17 is the seventeenth second light emission control line, the one labeled DT17 is the seventeenth data line, the one labeled HF18 is the eighteenth second light emission control line, the one labeled DT18 is the eighteenth data line;

[0436] As Figure 16 shown, most of the second light emission control line parts of each second light emission control line extend in the vertical direction, and most of the data line parts included in each data line extend in the vertical direction;

[0437] EA1 and EA2 are arranged between DT6 and HF7;

[0438] DT6 bends to the left to form the first second avoidance space A12;

[0439] HF7 bends to the right to form the second second avoidance space A22;

[0440] Parts of EA1 and parts of EA2 are arranged within A12, and parts of EA1 and parts of EA2 are arranged within A22;

[0441] HF6 is bent leftward, DT5 is bent leftward, HF5 is bent leftward, DT4 is bent leftward, HF4 is bent leftward, so that the distance between HF6 and DT6, the distance between DT5 and HF6, the distance between HF5 and DT5, the distance between DT4 and HF5, and the distance between HF4 and DT4 are approximately equal, so as to evenly distribute each signal line;

[0442] DT7 is bent rightward, HF8 is bent rightward, DT8 is bent rightward, HF9 is bent rightward, DT9 is bent rightward, HF10 is bent rightward, DT10 is bent rightward, HF11 is bent rightward, DT11 is bent rightward, HF12 is bent rightward, DT12 is bent rightward, so that the distance between HF7 and DT7, the distance between DT7 and HF8, the distance between HF8 and DT8, the distance between DT8 and HF9, and the distance between HF9 and DT9 are approximately equal, so as to evenly distribute each signal line.

[0443] As Figure 17 shown, the one labeled GA1 is the first-stage gate driving circuit, the one labeled GA2 is the second-stage gate driving circuit, and the one labeled GA3 is the third-stage gate driving circuit;

[0444] GA1, GA2 and GA3 are arranged between F12, F22, F13 and F23.

[0445] DT12 is bent leftward to form the first third avoidance space A13;

[0446] HF13 is bent rightward to form the second third avoidance space A23;

[0447] Part of GA1, part of GA2, and part of GA3 are arranged in A13;

[0448] Part of GA1, part of GA2, and part of GA3 are arranged in A23.

[0449] In at least one embodiment of the present disclosure, in the display area, on one side close to the Fanout area, a third area is provided. In the third area, a pixel driving circuit is provided, but a light-emitting control signal generation circuit and a gate driving circuit are not provided. Therefore, in the first area in the display area close to the third area, between adjacent pixel driving groups, the number of stages of the light-emitting control signal generation circuit provided is greater than that in the second area in the display area except for the first area and the third area, between adjacent pixel driving groups, the number of stages of the light-emitting control signal generation circuit provided;

[0450] In the first region included in the display region, the number of stages of the gate driving circuit provided between adjacent pixel driving groups is greater than that in the second region in the display region, and the number of stages of the gate driving circuit provided between adjacent pixel driving groups.

[0451] For example, in the first region, three or four stages of light emission control signal generation circuits may be provided between adjacent pixel driving groups, and in the second region, two stages of light emission control signal generation circuits may be provided between adjacent pixel driving groups;

[0452] In the first region, three or four stages of gate driving circuits may be provided between adjacent pixel driving groups, and in the second region, two stages of gate circuits may be provided between adjacent pixel driving groups;

[0453] However, it is not limited thereto.

[0454] As Figure 18 shown, the one labeled A0 is the display region, the one labeled A1 is the first region, the one labeled A2 is the second region, the one labeled A3 is the third region, and the one labeled FA is the fan-out region;

[0455] The display region A0 includes the first region A1, the second region A2, and the third region A3;

[0456] In Figure 18 , the one labeled F11 is the first row and first column pixel driving group, the one labeled F12 is the first row and second column pixel driving group, the one labeled F13 is the first row and third column pixel driving group, the one labeled F14 is the first row and fourth column pixel driving group, and the one labeled F15 is the first row and fifth column pixel driving group;

[0457] The one labeled F21 is the second row and first column pixel driving group, the one labeled F22 is the second row and second column pixel driving group, the one labeled F23 is the second row and third column pixel driving group, the one labeled F24 is the second row and fourth column pixel driving group, and the one labeled F25 is the second row and fifth column pixel driving group;

[0458] The one labeled F31 is the third row and first column pixel driving group, the one labeled F32 is the third row and second column pixel driving group, the one labeled F33 is the third row and third column pixel driving group, the one labeled F34 is the third row and fourth column pixel driving group, and the one labeled F35 is the third row and fifth column pixel driving group;

[0459] The one labeled F41 is the fourth row and first column pixel driving group, the one labeled F42 is the fourth row and second column pixel driving group, the one labeled F43 is the fourth row and third column pixel driving group, the one labeled F44 is the fourth row and fourth column pixel driving group, and the one labeled F45 is the fourth row and fifth column pixel driving group;

[0460] The pixel driving group labeled F51 is the pixel driving group of the first column in the fifth row, the pixel driving group labeled F52 is the pixel driving group of the second column in the fifth row, the pixel driving group labeled F53 is the pixel driving group of the third column in the fifth row, the pixel driving group labeled F54 is the pixel driving group of the fourth column in the fifth row, and the pixel driving group labeled F55 is the pixel driving group of the fifth column in the fifth row;

[0461] The pixel driving group labeled F61 is the pixel driving group of the first column in the sixth row, the pixel driving group labeled F62 is the pixel driving group of the second column in the sixth row, the pixel driving group labeled F63 is the pixel driving group of the third column in the sixth row, the pixel driving group labeled F64 is the pixel driving group of the fourth column in the sixth row, and the pixel driving group labeled F65 is the pixel driving group of the fifth column in the sixth row;

[0462] The pixel driving group labeled F71 is the pixel driving group of the first column in the seventh row, the pixel driving group labeled F72 is the pixel driving group of the second column in the seventh row, the pixel driving group labeled F73 is the pixel driving group of the third column in the seventh row, the pixel driving group labeled F74 is the pixel driving group of the fourth column in the seventh row, and the pixel driving group labeled F75 is the pixel driving group of the fifth column in the seventh row;

[0463] F71, F72, F73, F74 and F75 are arranged in the third region A3;

[0464] Each of the above pixel driving groups includes at least one pixel driving circuit;

[0465] The light emission control signal generation circuit EA11 of the first column in the first row and the light emission control signal generation circuit EA21 of the first column in the second row are arranged between F11, F12, F21 and F22;

[0466] The light emission control signal generation circuit EA31 of the first column in the third row and the light emission control signal generation circuit EA41 of the first column in the fourth row are arranged between F21, F22, F31 and F32;

[0467] The light emission control signal generation circuit EA51 of the first column in the fifth row and the light emission control signal generation circuit EA61 of the first column in the sixth row are arranged between F31, F32, F41 and F42;

[0468] The light emission control signal generation circuit EA71 of the first column in the seventh row, the light emission control signal generation circuit EA81 of the first column in the eighth row and the light emission control signal generation circuit EA91 of the first column in the ninth row are arranged between F41, F42, F51 and F52;

[0469] The light emission control signal generation circuit EA111 of the first column in the tenth row, the light emission control signal generation circuit EA111 of the first column in the eleventh row, the light emission control signal generation circuit EA121 of the first column in the twelfth row and the light emission control signal generation circuit EA131 of the first column in the thirteenth row are arranged between F51, F52, F61 and F62;

[0470] The gate driving circuit GA11 in the first row and first column and the gate driving circuit EA21 in the second row and first column are disposed between F12, F13, F22, and F23;

[0471] The gate driving circuit GA31 in the third row and first column and the gate driving circuit GA41 in the fourth row and first column are disposed between F22, F23, F32, and F33;

[0472] The gate driving circuit GA51 in the fifth row and first column and the gate circuit GA61 in the sixth row and first column are disposed between F32, F33, F42, and F43;

[0473] The gate driving circuit GA71 in the seventh row and first column, the gate driving circuit GA81 in the eighth row and first column, and the gate driving circuit GA91 in the ninth column and first column are disposed between F42, F43, F52, and F53;

[0474] The gate driving circuit GA111 in the tenth row and first column, the gate driving circuit GA111 in the eleventh row and first column, the gate driving circuit GA121 in the twelfth row and first column, and the gate driving circuit GA131 in the thirteenth row and first column are disposed between F52, F53, F62, and F63;

[0475] The light emission control signal generation circuit EA12 in the first row and second column and the light emission control signal generation circuit EA22 in the second row and second column are disposed between F13, F14, F23, and F24;

[0476] The light emission control signal generation circuit EA31 in the third row and second column and the light emission control signal generation circuit EA42 in the fourth row and second column are disposed between F23, F24, F33, and F34;

[0477] The light emission control signal generation circuit EA52 in the fifth row and second column and the light emission control signal generation circuit EA62 in the sixth row and second column are disposed between F33, F34, F43, and F44;

[0478] The light emission control signal generation circuit EA72 in the seventh row and second column, the light emission control signal generation circuit EA82 in the eighth row and second column, and the light emission control signal generation circuit EA92 in the ninth column and second column are disposed between F43, F44, F53, and F54;

[0479] The light emission control signal generation circuit EA112 in the tenth row and second column, the light emission control signal generation circuit EA112 in the eleventh row and second column, the light emission control signal generation circuit EA122 in the twelfth row and second column, and the light emission control signal generation circuit EA132 in the thirteenth row and second column are disposed between F53, F54, F63, and F64;

[0480] The gate driving circuit GA12 in the first row and the second column and the gate driving circuit EA22 in the second row and the second column are disposed between F14, F15, F24, and F25;

[0481] The gate driving circuit GA32 in the third row and the second column and the gate driving circuit GA42 in the fourth row and the second column are disposed between F24, F25, F34, and F35;

[0482] The gate driving circuit GA52 in the fifth row and the second column and the gate circuit GA62 in the sixth row and the second column are disposed between F34, F35, F44, and F45;

[0483] The gate driving circuit GA72 in the seventh row and the second column, the gate driving circuit GA82 in the eighth row and the second column, and the gate driving circuit GA92 in the ninth column and the second column are disposed between F44, F45, F54, and F55;

[0484] The gate driving circuit GA112 in the tenth row and the second column, the gate driving circuit GA112 in the eleventh row and the second column, the gate driving circuit GA122 in the twelfth row and the second column, and the gate driving circuit GA132 in the thirteenth row and the second column are disposed between F54, F55, F64, and F65;

[0485] As Figure 18 shown, F51, F52, F53, F54, F55, F61, F62, F63, F64, F65, EA71, EA81, EA91, EA101, EA111, EA121, EA131, GA71, GA81, GA91, GA101, GA111, GA121, GA131, EA72, EA82, EA92, EA102, EA112, EA122, EA132, GA72, GA82, GA92, GA102, GA112, GA122, and GA132 are all disposed in the first area A1. The first area A1 is close to the third area A3, and the third area A3 is close to the fan-out area FA;

[0486] In the first area A1, in adjacent pixel driving groups, a three-stage or four-stage light emission control signal generation circuit is provided, and a three-stage or four-stage gate driving circuit is provided.

[0487] In Figure 18 it, the number of rows and columns in which each pixel driving group is located is only for illustration, in order to illustrate the position where each pixel driving group is located, and is not the actual corresponding row and column of the pixel driving group. The display panel described in the embodiments of the present disclosure includes the above-mentioned display substrate.

[0488] The display panel according to at least one embodiment of the present disclosure further includes a source driver, a plurality of columns of data lines, and a multiplexing circuit;

[0489] Multiple pixel circuits located in the same column are all electrically connected to the same column data line;

[0490] The multiplexing circuit is electrically connected to multiple voltage output terminals, multiple multiplexing control terminals of the source driver, and the multiple columns of data lines respectively, and is configured to write the voltage signal provided by the source driver through its voltage output terminal into the data line under the control of the multiplexing control signal provided by the multiplexing control terminal.

[0491] In a specific implementation, the display panel may further include a source driver, multiple columns of data lines, and a multiplexing circuit. The multiplexing circuit writes the voltage signal provided by the source driver through its voltage output terminal into the data line under the control of the multiplexing control signal.

[0492] As Figure 19 shown, the display panel according to at least one embodiment of the present disclosure further includes a source driver SD, a multiplexing circuit 90, a first column data line DL1, a second column data line DL2, a third column data line DL3, a fourth column data line DL4, a fifth column data line DL5, a sixth column data line DL6, a seventh column data line DL7, an eighth column data line DL8, a ninth column data line DL9, a tenth column data line DL10, an eleventh column data line DL11, a twelfth column data line DL12, a thirteenth column data line DL13, a fourteenth column data line DL14, a fifteenth column data line DL15, a sixteenth column data line DL16, a seventeenth column data line DL17, and an eighteenth column data line DL18;

[0493] The source driver SD includes a first voltage output terminal CH1, a second voltage output terminal CH2, and a third voltage output terminal CH3;

[0494] The first voltage output terminal CH1, the second voltage output terminal CH2, and the third voltage output terminal CH3 are respectively electrically connected to the input terminal of the multiplexing circuit 90;

[0495] The output terminals of the multiplexing circuit 90 are respectively electrically connected to DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8, DL9, DL10, DL11, DL12, DL13, DL14, DL15, DL16, DL17, and DL18;

[0496] The multiplexing circuit 90 is respectively electrically connected to a first multiplexing control terminal MX1, a second multiplexing control terminal MX2, a third multiplexing control terminal MX3, a fourth multiplexing control terminal MX4, a fifth multiplexing control terminal MX5, and a sixth multiplexing control terminal MX6, and is configured to control the connection or disconnection between each voltage output terminal and each data line under the control of the multiplexing control signals provided by each multiplexing control terminal.

[0497] In at least one embodiment of the present disclosure, the multiplexing circuit is electrically connected to N multiplexing control terminals respectively, and the multiplexing circuit includes M multiplexing sub-circuits, where N and M are integers greater than 1;

[0498] Each of the multiplexing sub-circuits is electrically connected to the voltage output terminal of the source driver, the N multiplexing control terminals, and N columns of the data lines, and is configured to control, under the control of the nth multiplexing control signal provided by the nth multiplexing control terminal, to supply the voltage signal provided by the voltage output terminal to the nth data line among the N columns of data lines;

[0499] n is a positive integer less than or equal to N.

[0500] In a specific implementation, when the multiplexing circuit is electrically connected to N multiplexing control terminals respectively, the multiplexing circuit may include M multiplexing sub-circuits; the multiplexing sub-circuit supplies the voltage signal provided by the voltage output terminal of the source driver to the data line under the control of the nth multiplexing control signal.

[0501] As Figure 20 shown, based on at least one embodiment of the display panel shown in Figure 19 the multiplexing circuit includes a first multiplexing sub-circuit 101, a second multiplexing sub-circuit 102, and a third multiplexing sub-circuit 103;

[0502] The first multiplexing sub-circuit 101 is electrically connected to a first multiplexing control terminal MX1, a second multiplexing control terminal MX2, a third multiplexing control terminal MX3, a fourth multiplexing control terminal MX4, a fifth multiplexing control terminal MX5, and a sixth multiplexing control terminal MX6, a first voltage output terminal CH1, a first column of data lines DL1, a fourth column of data lines DL4, a seventh column of data lines DL7, a tenth column of data lines DL10, a thirteenth column of data lines DL13, and a sixteenth column of data lines DL16 respectively, and is configured to control, under the control of the first multiplexing control signal provided by MX1, to connect or disconnect CH1 and DL1, under the control of the second multiplexing control signal provided by MX2, to connect CH1 and DL4, under the control of the third multiplexing control signal provided by MX3, to connect or disconnect CH1 and DL7, under the control of the fourth multiplexing control signal provided by MX4, to connect or disconnect CH1 and DL10, under the control of the fifth multiplexing control signal provided by MX5, to connect or disconnect CH1 and DL13, and under the control of the sixth multiplexing control signal provided by MX6, to connect or disconnect CH1 and DL16;

[0503] The second multiplexing sub-circuit 102 is electrically connected to a first multiplexing control terminal MX1, a second multiplexing control terminal MX2, a third multiplexing control terminal MX3, a fourth multiplexing control terminal MX4, a fifth multiplexing control terminal MX5, a sixth multiplexing control terminal MX6, a first voltage output terminal CH1, a second column data line DL2, a fifth column data line DL5, an eighth column data line DL8, an eleventh column data line DL11, a fourteenth column data line DL14, and a seventeenth column data line DL17, respectively, and is configured to control the connection or disconnection between CH1 and DL2 under the control of a first multiplexing control signal provided by MX1, control the connection between CH1 and DL5 under the control of a second multiplexing control signal provided by MX2, control the connection or disconnection between CH1 and DL8 under the control of a third multiplexing control signal provided by MX3, control the connection or disconnection between CH1 and DL11 under the control of a fourth multiplexing control signal provided by MX4, control the connection or disconnection between CH1 and DL14 under the control of a fifth multiplexing control signal provided by MX5, and control the connection or disconnection between CH1 and DL17 under the control of a sixth multiplexing control signal provided by MX6;

[0504] The third multiplexing sub-circuit 103 is electrically connected to a first multiplexing control terminal MX1, a second multiplexing control terminal MX2, a third multiplexing control terminal MX3, a fourth multiplexing control terminal MX4, a fifth multiplexing control terminal MX5, a sixth multiplexing control terminal MX6, a first voltage output terminal CH1, a third column data line DL3, a sixth column data line DL6, a ninth column data line DL9, a twelfth column data line DL12, a fifteenth column data line DL15, and an eighteenth column data line DL18, respectively, and is configured to control the connection or disconnection between CH1 and DL3 under the control of a first multiplexing control signal provided by MX1, control the connection between CH1 and DL6 under the control of a second multiplexing control signal provided by MX2, control the connection or disconnection between CH1 and DL9 under the control of a third multiplexing control signal provided by MX3, control the connection or disconnection between CH1 and DL12 under the control of a fourth multiplexing control signal provided by MX4, control the connection or disconnection between CH1 and DL15 under the control of a fifth multiplexing control signal provided by MX5, and control the connection or disconnection between CH1 and DL18 under the control of a sixth multiplexing control signal provided by MX6.

[0505] As Figure 21 shown, based on at least one embodiment of the display panel shown in Figure 20 the first multiplexing sub-circuit may include a first multiplexing transistor T1, a second multiplexing transistor T2, a third multiplexing transistor T3, a fourth multiplexing transistor T4, a fifth multiplexing transistor T5, and a sixth multiplexing transistor T6;

[0506] The gate of T1 is electrically connected to MX1, the source of T1 is electrically connected to CH1, and the drain of T1 is electrically connected to DL1;

[0507] The gate of T2 is electrically connected to MX2, the source of T2 is electrically connected to CH1, and the drain of T2 is electrically connected to DL4;

[0508] The gate of T3 is electrically connected to MX3, the source of T3 is electrically connected to CH1, and the drain of T3 is electrically connected to DL7;

[0509] The gate of T4 is electrically connected to MX4, the source of T4 is electrically connected to CH1, and the drain of T4 is electrically connected to DL10;

[0510] The gate of T5 is electrically connected to MX5, the source of T5 is electrically connected to CH1, and the drain of T5 is electrically connected to DL13;

[0511] The gate of T6 is electrically connected to MX6, the source of T6 is electrically connected to CH1, and the drain of T6 is electrically connected to DL16;

[0512] The second multiplexing sub-circuit may include a seventh multiplexing transistor T7, an eighth multiplexing transistor T8, a ninth multiplexing transistor T9, a tenth multiplexing transistor T10, an eleventh multiplexing transistor T11, and a twelfth multiplexing transistor T12;

[0513] The gate of T7 is electrically connected to MX1, the source of T7 is electrically connected to CH2, and the drain of T7 is electrically connected to DL2;

[0514] The gate of T8 is electrically connected to MX2, the source of T8 is electrically connected to CH2, and the drain of T8 is electrically connected to DL5;

[0515] The gate of T9 is electrically connected to MX3, the source of T9 is electrically connected to CH2, and the drain of T9 is electrically connected to DL8;

[0516] The gate of T10 is electrically connected to MX4, the source of T10 is electrically connected to CH2, and the drain of T10 is electrically connected to DL11;

[0517] The gate of T11 is electrically connected to MX5, the source of T11 is electrically connected to CH2, and the drain of T11 is electrically connected to DL14;

[0518] The gate of T12 is electrically connected to MX6, the source of T12 is electrically connected to CH2, and the drain of T12 is electrically connected to DL17;

[0519] The third multiplexing sub-circuit may include a thirteenth multiplexing transistor T13, a fourteenth multiplexing transistor T14, a fifteenth multiplexing transistor T15, a sixteenth multiplexing transistor T16, a seventeenth multiplexing transistor T17, and an eighteenth multiplexing transistor T18;

[0520] The gate of T13 is electrically connected to MX1, the source of T13 is electrically connected to CH3, and the drain of T13 is electrically connected to DL3;

[0521] The gate of T14 is electrically connected to MX2, the source of T14 is electrically connected to CH3, and the drain of T14 is electrically connected to DL6;

[0522] The gate of T15 is electrically connected to MX3, the source of T15 is electrically connected to CH3, and the drain of T15 is electrically connected to DL9;

[0523] The gate of T16 is electrically connected to MX4, the source of T16 is electrically connected to CH3, and the drain of T16 is electrically connected to DL12;

[0524] The gate of T17 is electrically connected to MX5, the source of T17 is electrically connected to CH3, and the drain of T17 is electrically connected to DL15;

[0525] The gate of T18 is electrically connected to MX6, the source of T18 is electrically connected to CH3, and the drain of T18 is electrically connected to DL18.

[0526] In Figure 21 In at least one embodiment of the display panel shown, all transistors are p-type transistors, but this is not limiting.

[0527] In Figure 21 In at least one embodiment of the display panel shown, DL1, DL4, DL7, DL10, DL13, and DL16 can be red data lines, DL2, DL5, DL8, DL11, DL14, and DL17 can be green data lines, and DL3, DL6, DL9, DL12, DL15, and DL18 can be blue data lines, but this is not limiting;

[0528] Among them, the red data line can be a data line that provides a data voltage for the red pixel circuit, the green data line can be a data line that provides a data voltage for the green pixel circuit, and the blue data line can be a data line that provides a data voltage for the blue pixel circuit.

[0529] The present disclosure Figure 21 In at least one embodiment of the display panel shown during operation,

[0530] When MX1 provides a low voltage signal, MX2, MX3, MX4, MX5, and MX6 all output high voltage signals, T1, T7, and T13 are turned on, and other multiplexing transistors are turned off. CH1 is connected to DL1, CH2 is connected to DL2, and CH3 is connected to DL3;

[0531] When MX2 provides a low-voltage signal, MX1, MX3, MX4, MX5, and MX6 all output high-voltage signals, T2, T8, and T14 are turned on, other multiplexing transistors are turned off, CH1 is connected to DL4, CH2 is connected to DL5, and CH3 is connected to DL6;

[0532] When MX3 provides a low-voltage signal, MX1, MX2, MX4, MX5, and MX6 all output high-voltage signals, T3, T9, and T15 are turned on, other multiplexing transistors are turned off, CH1 is connected to DL7, CH2 is connected to DL8, and CH3 is connected to DL9;

[0533] When MX4 provides a low-voltage signal, MX1, MX2, MX3, MX5, and MX6 all output high-voltage signals, T4, T10, and T16 are turned on, other multiplexing transistors are turned off, CH1 is connected to DL10, CH2 is connected to DL11, and CH3 is connected to DL12;

[0534] When MX5 provides a low-voltage signal, MX1, MX2, MX3, MX4, and MX6 all output high-voltage signals, T5, T11, and T17 are turned on, other multiplexing transistors are turned off, CH1 is connected to DL13, CH2 is connected to DL14, and CH3 is connected to DL15;

[0535] When MX6 provides a low-voltage signal, MX1, MX2, MX3, MX4, and MX5 all output high-voltage signals, T6, T12, and T18 are turned on, other multiplexing transistors are turned off, CH1 is connected to DL16, CH2 is connected to DL17, and CH3 is connected to DL18.

[0536] As Figure 22 shown, when at least one embodiment of the display panel shown in the present disclosure Figure 21 operates, the display cycle includes a first writing time period XT1, a second writing time period XT2, a third writing time period XT3, and a light-emitting stage FT that are set successively;

[0537] The first writing time period XT1 includes a first data writing time period t11 and a second data writing time period t12 that are set successively;

[0538] The second writing time period XT2 includes a third data writing time period t21 and a fourth data writing time period t22 that are set successively;

[0539] The third writing time period XT3 includes a fifth data writing time period t31 and a sixth data writing time period t32 that are set successively;

[0540] During the first data writing time period t11, MX1, MX2, MX3, MX4, MX5, and MX6 sequentially output low voltage signals;

[0541] When MX1 outputs a low voltage signal, T1, T7, and T13 turn on, and other multiplexing transistors turn off. CH1 is connected to DL1, CH2 is connected to DL2, and CH3 is connected to DL3. CH1 provides a first light emission time control data voltage to DL1, CH2 provides a second light emission time control data voltage to DL2, and CH3 provides a third light emission time control data voltage to DL3;

[0542] When MX2 outputs a low voltage signal, T2, T8, and T14 turn on, and other multiplexing transistors turn off. CH1 is connected to DL4, CH2 is connected to DL5, and CH3 is connected to DL6. CH1 provides a fourth light emission time control data voltage to DL4, CH2 provides a fifth light emission time control data voltage to DL5, and CH3 provides a ninth light emission time control data voltage to DL6;

[0543] When MX3 outputs a low voltage signal, T3, T9, and T15 turn on, and other multiplexing transistors turn off. CH1 is connected to DL7, CH2 is connected to DL8, and CH3 is connected to DL9. CH1 provides a fourth light emission time control data voltage to DL7, CH2 provides a fifth light emission time control data voltage to DL8, and CH3 provides a ninth light emission time control data voltage to DL9;

[0544] When MX4 provides a low voltage signal, T4, T10, and T16 turn on, and other multiplexing transistors turn off. CH1 is connected to DL10, CH2 is connected to DL11, and CH3 is connected to DL12. CH1 provides a tenth light emission time control data voltage to DL10, CH2 provides an eleventh light emission time control data voltage to DL11, and CH3 provides a twelfth light emission time control data voltage to DL12;

[0545] When MX5 provides a low voltage signal, T5, T11, and T17 turn on, and other multiplexing transistors turn off. CH1 is connected to DL13, CH2 is connected to DL14, and CH3 is connected to DL15. CH1 provides a thirteenth light emission time control data voltage to DL13, CH2 provides a fourteenth light emission time control data voltage to DL14, and CH3 provides a fifteenth light emission time control data voltage to DL15;

[0546] When MX6 provides a low-voltage signal, T6, T12, and T18 are turned on, and other multiplexing transistors are turned off. CH1 is connected to DL16, CH2 is connected to DL17, and CH3 is connected to DL18. CH1 provides the sixteenth emission time control data voltage to DL16, CH2 provides the seventeenth emission time control data voltage to DL17, and CH3 provides the eighteenth emission time control data voltage to DL18;

[0547] Due to the parasitic capacitance on each data line, each emission time control data voltage is charged to the parasitic capacitance of each data line;

[0548] In the second data writing period t12, RA provides a low-voltage signal, RB provides a high-voltage signal, and the first transistor M1 in the pixel circuit is turned on to write the emission time control data voltage on each data line to the second control node N2;

[0549] In the third data writing period t21, MX1, MX2, MX3, MX4, MX5, and MX6 sequentially output low-voltage signals;

[0550] When MX1 outputs a low-voltage signal, T1, T7, and T13 are turned on, and other multiplexing transistors are turned off. CH1 is connected to DL1, CH2 is connected to DL2, and CH3 is connected to DL3. CH1 provides the nineteenth emission time control data voltage to DL1, CH2 provides the twentieth emission time control data voltage to DL2, and CH3 provides the twenty-first emission time control data voltage to DL3;

[0551] When MX2 outputs a low-voltage signal, T2, T8, and T14 are turned on, and other multiplexing transistors are turned off. CH1 is connected to DL4, CH2 is connected to DL5, and CH3 is connected to DL6. CH1 provides the twenty-second emission time control data voltage to DL4, CH2 provides the twenty-third emission time control data voltage to DL5, and CH3 provides the twenty-fourth emission time control data voltage to DL6;

[0552] When MX3 outputs a low-voltage signal, T3, T9, and T15 are turned on, and other multiplexing transistors are turned off. CH1 is connected to DL7, CH2 is connected to DL8, and CH3 is connected to DL9. CH1 provides the twenty-fifth emission time control data voltage to DL7, CH2 provides the twenty-sixth emission time control data voltage to DL8, and CH3 provides the twenty-seventh emission time control data voltage to DL9;

[0553] When MX4 provides a low voltage signal, T4, T10, and T16 turn on, and other multiplexing transistors turn off. CH1 is connected to DL10, CH2 is connected to DL11, and CH3 is connected to DL12. CH1 provides the twenty-eighth emission time control data voltage to DL10, CH2 provides the twenty-ninth emission time control data voltage to DL11, and CH3 provides the thirtieth emission time control data voltage to DL12;

[0554] When MX5 provides a low voltage signal, T5, T11, and T17 turn on, and other multiplexing transistors turn off. CH1 is connected to DL13, CH2 is connected to DL14, and CH3 is connected to DL15. CH1 provides the thirty-first emission time control data voltage to DL13, CH2 provides the thirty-second emission time control data voltage to DL14, and CH3 provides the thirty-third emission time control data voltage to DL15;

[0555] When MX6 provides a low voltage signal, T6, T12, and T18 turn on, and other multiplexing transistors turn off. CH1 is connected to DL16, CH2 is connected to DL17, and CH3 is connected to DL18. CH1 provides the thirty-fourth emission time control data voltage to DL16, CH2 provides the thirty-fifth emission time control data voltage to DL17, and CH3 provides the thirty-sixth emission time control data voltage to DL18;

[0556] Due to the parasitic capacitance on each data line, each emission time control data voltage is charged to the parasitic capacitance of each data line;

[0557] In the fourth data writing time period t22, RB provides a low voltage signal, RA provides a high voltage signal, and M3 in the pixel circuit conducts to write the emission time control data voltage on each data line to the third control node N3;

[0558] In the fifth data writing time period t31, MX1, MX2, MX3, MX4, MX5, and MX6 sequentially output low voltage signals;

[0559] When MX1 outputs a low voltage signal, T1, T7, and T13 turn on, and other multiplexing transistors turn off. CH1 is connected to DL1, CH2 is connected to DL2, and CH3 is connected to DL3. CH1 provides the first display data voltage to DL1, CH2 provides the second display data voltage to DL2, and CH3 provides the third display data voltage to DL3;

[0560] When MX2 outputs a low voltage signal, T2, T8, and T14 are turned on, and other multiplexing transistors are turned off. CH1 is connected to DL4, CH2 is connected to DL5, and CH3 is connected to DL6. CH1 provides the fourth display data voltage to DL4, CH2 provides the fifth display data voltage to DL5, and CH3 provides the sixth display data voltage to DL6;

[0561] When MX3 outputs a low voltage signal, T3, T9, and T15 are turned on, and other multiplexing transistors are turned off. CH1 is connected to DL7, CH2 is connected to DL8, and CH3 is connected to DL9. CH1 provides the seventh display data voltage to DL7, CH2 provides the eighth display data voltage to DL8, and CH3 provides the ninth display data voltage to DL9;

[0562] When MX4 provides a low voltage signal, T4, T10, and T16 are turned on, and other multiplexing transistors are turned off. CH1 is connected to DL10, CH2 is connected to DL11, and CH3 is connected to DL12. CH1 provides the tenth display data voltage to DL10, CH2 provides the eleventh display data voltage to DL11, and CH3 provides the twelfth display data voltage to DL12;

[0563] When MX5 provides a low voltage signal, T5, T11, and T17 are turned on, and other multiplexing transistors are turned off. CH1 is connected to DL13, CH2 is connected to DL14, and CH3 is connected to DL15. CH1 provides the thirteenth display data voltage to DL13, CH2 provides the fourteenth display data voltage to DL14, and CH3 provides the fifteenth display data voltage to DL15;

[0564] When MX6 provides a low voltage signal, T6, T12, and T18 are turned on, and other multiplexing transistors are turned off. CH1 is connected to DL16, CH2 is connected to DL17, and CH3 is connected to DL18. CH1 provides the sixteenth display data voltage to DL16, CH2 provides the seventeenth display data voltage to DL17, and CH3 provides the eighteenth display data voltage to DL18;

[0565] Due to the parasitic capacitance on each data line, each emission time control data voltage charges the parasitic capacitance of each data line;

[0566] In the sixth data writing time period t32, G1 provides a low voltage signal, and M6 and M7 in the pixel circuit are turned on for charging and threshold voltage compensation to achieve the writing of the display data voltage;

[0567] In the emission stage FT, E1 provides a low voltage signal, and M5 is turned on to control the connection between the power supply voltage line VDD and the source of the driving transistor M0;

[0568] When performing medium-high gray-scale display, M2 in the pixel circuit is turned on to control the connection between the first light-emitting control line E1 and the first control node N1;

[0569] When performing low gray-scale display, M4 in the pixel circuit is turned on to control the connection between the second light-emitting control line Hf and the first control node N1.

[0570] When the display panel according to at least one embodiment of the present disclosure is working, it is also possible to control RA to provide a high-voltage signal and control RB to provide a low-voltage signal during the second data writing period, and control RA to provide a low-voltage signal and control RB to provide a high-voltage signal during the fourth data writing period.

[0571] In at least one embodiment of the present disclosure, the opening time of each multiplexing control terminal can be reduced to quickly complete the storage of the light-emitting time control data voltage on the data line, so as to increase the opening time of RA, the opening time of RB, and the opening time of G1, providing more sufficient time for data voltage writing, charging, and threshold voltage compensation inside the pixel circuit.

[0572] In at least one embodiment of the present disclosure, through the timing control of GOA (Gate On Array), all low-level stages of the second light-emitting control line Hf are in the light-emitting stage, avoiding the coupling effect on the writing of the display data voltage caused by the potential of the second light-emitting control signal being pulled low by high frequency and disturbing the gate voltage of the driving transistor. Thus, compared with the related pixel circuit, one transistor for preventing the coupling effect of Hf is reduced.

[0573] In specific implementation, due to the existence of parasitic capacitance on the data line, the data lines will affect each other through coupling and change the voltage.

[0574] As Figure 23 shown, when performing medium-high gray-scale display, if RB provides a low-voltage signal and RA provides a high-voltage signal during the second data writing period, and RA provides a low-voltage signal and RB provides a high-voltage signal during the fourth data writing stage;

[0575] During the first data writing period t11, the data voltage Vdata accessed by DL1 can be 18V;

[0576] During the third data writing period t21, the data voltage Vdata accessed by DL1 can be 0V;

[0577] During the fifth data writing period t31, the data voltage Vdata accessed by DL1 can be 13V;

[0578] When MX1 is turned on, DL1 writes the data voltage, and DL1 maintains the potential of the previous moment after MX1 is turned off. AsFigure 23 The ideal voltage VDL10 of DL1 in Figure 23 , the 18V voltage signal and the 0V voltage signal are respectively signals for controlling the access of the first light-emitting control line and the second light-emitting control line, and have little influence on grayscale display. When it jumps from 0V to 13V, it is the turn-on moment of G1, and the voltage on DL1 will jump with the voltage on DL4, which will affect the writing of the data voltage, resulting in a relatively high potential of the writing voltage, thus causing the pixel electrically connected to DL1 to display darker than expected.

[0579] In Figure 23 Figure 23 , VDL40 is the ideal voltage on DL4, and VDL1 is the actual voltage on DL1.

[0580] As Figure 24 shown, when performing medium-high grayscale display, if in the second data writing period t12, RA provides a low voltage signal and RB provides a high voltage signal, and in the fourth data writing period t22, RB provides a low voltage signal and RA provides a high voltage signal;

[0581] In the first data writing period t11, the data voltage Vdata accessed by DL1 can be 0V;

[0582] In the third data writing period t21, the data voltage Vdata accessed by DL1 can be 18V;

[0583] In the fifth data writing period t31, the data voltage Vdata accessed by DL1 can be 13V;

[0584] By setting as above, at the turn-on moment of G1, the data voltage on DL1 jumps from 18V to 13V, reducing the jump amplitude of the data voltage and improving the problem of different pixel displays.

[0585] As Figure 25 shown, when at least one embodiment of the display panel shown in the present disclosure Figure 25 is working, the display cycle includes a first writing period, a second writing period, a third writing period, and a light-emitting stage FT set successively; Figure 21 Figure 21 The first writing period includes a first data writing period t11 and a second data writing period t12; the first data writing period is included in the second data writing period t12;

[0586] The second writing period includes a third data writing period t21 and a fourth data writing period t22; the third data writing period t21 is included in the fourth data writing period t22;

[0587] The third writing period includes a fifth data writing period t31 and a sixth data writing period t32 set successively;

[0588] The third writing period includes a fifth data writing period t31 and a sixth data writing period t32 set successively;

[0589] During the first data writing period t11, MX1, MX2, MX3, MX4, MX5, and MX6 sequentially output low voltage signals, and the transistors controlled by MX1, MX2, MX3, MX4, MX5, and MX6 are sequentially turned on to write the corresponding light emission time control data voltages.

[0590] During the second data writing period t12, RA provides a low voltage signal, RB and G1 provide high voltage signals, and the first transistor M1 in the pixel circuit is turned on to write the light emission time control data voltages on the respective data lines to the second control node N2.

[0591] During the third data writing period t21, MX1, MX2, MX3, MX4, MX5, and MX6 sequentially output low voltage signals, and the transistors controlled by MX1, MX2, MX3, MX4, MX5, and MX6 are sequentially turned on to write the corresponding light emission time control data voltages.

[0592] During the fourth data writing period t22, RB provides a low voltage signal, RA and G1 provide high voltage signals, and M3 in the pixel circuit is turned on to write the light emission time control data voltages on the respective data lines to the third control node N3.

[0593] During the fifth data writing period t31, MX1, MX2, MX3, MX4, MX5, and MX6 sequentially output low voltage signals, and the transistors controlled by MX1, MX2, MX3, MX4, MX5, and MX6 are sequentially turned on to write the corresponding display data voltages.

[0594] During the sixth data writing period t32, G1 provides a low voltage signal, RA and RB provide high voltage signals, and M6 and M7 in the pixel circuit are turned on to perform charging and threshold voltage compensation to achieve the writing of the display data voltage.

[0595] During the light emission stage FT, EM outputs a low voltage signal.

[0596] During a partial time period included in the light emission stage FT, Hf outputs a low voltage signal.

[0597] When performing medium to high gray scale display, during the light emission stage FT, the driving transistor M0 in the pixel circuit drives the micro light emitting diode ML to emit light.

[0598] When performing low gray-scale display, during the light-emitting phase FT, when Hf provides a low-voltage signal, the driving transistor M0 in the pixel circuit drives the micro light-emitting diode ML to emit light.

[0599] In Figure 25 the one labeled E1_N is the next row light-emitting control line adjacent to E1.

[0600] In the related art, current + time control is usually adopted, with shorter light emission time at a fixed current to achieve low gray-scale display. However, after shorter light emission time within one frame display time, the LED (light-emitting diode) enters the black state, and the human eye can clearly feel the flicker, thus causing discomfort to the viewer. Based on this, at least one embodiment of the present disclosure provides a pixel circuit, which disperses the short light-emitting duration within one frame time by high-frequency control of the light-emitting duration, reducing the flicker.

[0601] In at least one embodiment of the present disclosure, since the time during which the light-emitting control signal provided by E1 remains at a low-voltage signal is relatively long, during the entire time when the light-emitting control signal provided by E1 remains at a low-voltage signal, the light-emitting control signal provided by Hf is a high-frequency pulse signal.

[0602] Figure 26 is the working timing diagram of the display panel according to at least one embodiment of the present disclosure.

[0603] In Figure 26 the one labeled ESTV is the first starting voltage, the one labeled ECK is the first clock signal, the one labeled ECB is the second clock signal, the one labeled GSTV is the second starting voltage, the one labeled GCK is the third clock signal, the one labeled GCB is the fourth clock signal, the one labeled Hf is the second light-emitting control line, the one labeled MX1 is the first multiplexing control terminal, the one labeled MX2 is the second multiplexing control terminal, the one labeled MX3 is the third multiplexing control terminal, the one labeled MX4 is the fourth multiplexing control terminal, the one labeled MX5 is the fifth multiplexing control terminal, the one labeled MX6 is the sixth multiplexing control terminal, and the one labeled Vdata is the data voltage.

[0604] The driving method according to the embodiment of the present disclosure is applied to the above display panel, and the display period includes a first writing time period and a second writing time period; the first writing time period includes a first data writing time period and a second data writing time period, and the second writing time period includes a third data writing time period and a fourth data writing time period; the driving method includes:

[0605] In the first data writing time period, the multiplexing circuit writes the first control voltage provided by the source driver through its voltage output terminal into the data line under the control of the reset control signal;

[0606] In the second data writing time period, under the control of the first reset control signal, the first control circuit provides the first control voltage provided by the data line to the second control node, and under the control of the potential of the second control node, the first control circuit controls whether to provide the first light emission control signal to the first control node;

[0607] In the third data writing time period, under the control of the reset control signal, the multiplexing circuit writes the second control voltage provided by the source driver through its voltage output terminal into the data line;

[0608] In the fourth data writing time period, under the control of the second reset control signal, the second control circuit writes the second control voltage provided by the data line into the third control node, and under the control of the potential of the third control node, the second control circuit controls whether to provide the second light emission control signal to the first control node.

[0609] In at least one embodiment of the present disclosure, the first data writing time period and the second data writing time period are set successively, and the third data writing time period and the fourth data writing time period are set successively; or,

[0610] The first data writing time period is included in the second data writing time period, and the third data writing time period is included in the fourth data writing time period.

[0611] The display device described in the embodiments of the present disclosure includes the above-mentioned display panel.

[0612] The above are the preferred embodiments of the present disclosure. It should be noted that for those of ordinary skill in the art, without departing from the principle described in the present disclosure, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present disclosure.

Claims

1. A pixel circuit includes a light-emitting element and a pixel driving circuit; the pixel driving circuit includes a driving circuit, a first light-emitting control circuit, a first control circuit, a second control circuit, and a data writing circuit; The driving circuit is configured to generate a driving current for driving the light-emitting element; The first light-emitting control circuit is electrically connected to a first control node, a first end of the driving circuit, and the light-emitting element respectively, and is configured to control the connection between the first end of the driving circuit and the light-emitting element under the control of the potential of the first control node; The first control circuit is electrically connected to a data line, a first reset control line, a first light-emitting control line, the first control node, and a second control node respectively, and is configured to provide a first control voltage provided by the data line to the second control node under the control of a first reset control signal provided by the first reset control line, and to control the first light-emitting control line to provide a first light-emitting control signal to the first control node under the control of the potential of the second control node; The second control circuit is electrically connected to the data line, a second reset control line, a second light-emitting control line, the first control node, and a third control node respectively, and is configured to write a second control voltage provided by the data line into the third control node under the control of a second reset control signal provided by the second reset control line, and to control the second light-emitting control line to provide a second light-emitting control signal to the first control node under the control of the potential of the third control node; The data writing circuit is electrically connected to a scan line, the data line, and a second end of the driving circuit respectively, and is configured to write a display data voltage provided by the data line into the second end of the driving circuit under the control of a scan signal provided by the scan line; The first control circuit, the second control circuit, and the data writing circuit are configured to access corresponding voltage signals on the data line in a time-division manner; The pulse width of the scan signal, the pulse width of the first reset control signal, and the pulse width of the second reset control signal are the same; or at least two of the pulse width of the scan signal, the pulse width of the first reset control signal, and the pulse width of the second reset control signal are different.

2. The pixel circuit according to claim 1, wherein, The scan line, the first reset control line, and the second reset control line are electrically connected to different GOA circuits in the same GOA module respectively, and access driving signals provided by the different GOA circuits; or, The scan line, the first reset control line, and the second reset control line are electrically connected to a GOA circuit in different GOA modules respectively, and access driving signals provided by a GOA circuit in different GOA modules; or, Two of the scan line, the first reset control line, and the second reset control line are electrically connected to different GOA circuits in the first GOA module, and are respectively connected to drive signals provided by different GOA circuits in the first GOA module. The other of the scan line, the first reset control line, and the second reset control line is electrically connected to a GOA circuit in the second GOA module, and is connected to a drive signal provided by a GOA circuit in the second GOA module.

3. The pixel circuit according to claim 1 or 2, wherein, The first control circuit includes a first writing control circuit, a first energy storage circuit, and a second writing control circuit; The first writing control circuit is respectively electrically connected to the first reset control line, the data line, and the second control node, and is configured to provide a first control voltage provided by the data line to the second control node under the control of the first reset control signal; The first energy storage circuit is electrically connected to the second control node and is used for the energy storage circuit; The second writing control circuit is respectively electrically connected to the second control node, the first light emission control line, and the first control node, and is configured to control the first light emission control line to provide a first light emission control signal to the first control node under the control of the potential of the second control node.

4. The pixel circuit according to claim 1 or 2, wherein, The second control circuit includes a third writing control circuit, a second energy storage circuit, and a fourth writing control circuit; The third writing control circuit is respectively electrically connected to the second reset control line, the data line, and the third control node, and writes a second control voltage provided by the data line into the third control node under the control of the second reset control signal; The second energy storage circuit is electrically connected to the third control node and is used for storing electrical energy; The fourth writing control circuit is respectively electrically connected to the third control node, the second light emission control line, and the first control node, and is configured to control the second light emission control line to provide a second light emission control signal to the first control node under the control of the potential of the third control node.

5. The pixel circuit according to claim 3, wherein, The first writing control circuit includes a first transistor, the first energy storage circuit includes a first capacitor, and the second writing control circuit includes a second transistor; The gate of the first transistor is electrically connected to the first reset control line, the first pole of the first transistor is electrically connected to the data line, and the second pole of the first transistor is electrically connected to the second control node; The first electrode plate of the first capacitor is electrically connected to the second control node, and the second electrode plate of the first capacitor is electrically connected to the first initial voltage line; The gate of the second transistor is electrically connected to the second control node, the first pole of the second transistor is electrically connected to the first light emission control line, and the second pole of the second transistor is electrically connected to the first control node.

6. The pixel circuit according to claim 4, wherein, The third writing control circuit includes a third transistor, the second energy storage circuit includes a second capacitor, and the fourth writing control circuit includes a fourth transistor; The gate of the third transistor is electrically connected to the second reset control line, the first pole of the third transistor is electrically connected to the data line, and the second pole of the third transistor is electrically connected to the third control node; The first electrode plate of the second capacitor is electrically connected to the third control node, and the second electrode plate of the second capacitor is electrically connected to the second initial voltage line; The gate of the fourth transistor is electrically connected to the third control node, the first pole of the fourth transistor is electrically connected to the second light emission control line, and the second pole of the fourth transistor is electrically connected to the first control node.

7. The pixel circuit according to claim 1, wherein, It further includes a second light emission control circuit; The second light emission control circuit is respectively electrically connected to the first light emission control line, the power supply voltage line and the second end of the driving circuit, and is configured to control the connection between the power supply voltage line and the second end of the driving circuit under the control of the first light emission control signal.

8. The pixel circuit according to claim 1 or 2, wherein, It further includes a compensation control circuit and a third energy storage circuit; The compensation control circuit is respectively electrically connected to the scanning line, the control end of the driving circuit and the first end of the driving circuit, and is configured to control the connection between the control end of the driving circuit and the first end of the driving circuit under the control of the scanning signal. The third energy storage circuit is electrically connected to the control end of the driving circuit and is used for storing electrical energy.

9. The pixel circuit according to claim 1 or 2, wherein, It further includes a first reset circuit; The first reset circuit is respectively electrically connected to the third reset control line, the third initial voltage line and the control end of the driving circuit, and is configured to write the third initial voltage provided by the third initial voltage line into the control end of the driving circuit under the control of the third reset control signal provided by the third reset control line.

10. The pixel circuit according to claim 9, wherein, It further includes a second reset circuit; The second reset circuit is respectively electrically connected to the fourth reset control line, the fourth initial voltage line and the first pole of the light emitting element, and is configured to write the fourth initial voltage provided by the fourth initial voltage line into the first pole of the light emitting element under the control of the fourth reset control signal provided by the fourth reset control line. The second pole of the light emitting element is electrically connected to the first voltage line.

11. The pixel circuit according to claim 10, wherein, The third reset control line is the first reset control line or the second reset control line; The fourth reset control line is the first reset control line or the second reset control line.

12. The pixel circuit according to claim 7, wherein, The second light emission control circuit includes a fifth transistor; The gate of the fifth transistor is electrically connected to the first light emission control line, the first pole of the fifth transistor is electrically connected to the power supply voltage line, and the second pole of the fifth transistor is electrically connected to the second end of the driving circuit.

13. The pixel circuit according to claim 8, wherein, The data writing circuit includes a sixth transistor, the compensation control circuit includes a seventh transistor, the third energy storage circuit includes a third capacitor; the driving circuit includes a driving transistor; The gate of the sixth transistor is electrically connected to the scanning line, the first pole of the sixth transistor is electrically connected to the data line, and the second pole of the sixth transistor is electrically connected to the second pole of the driving transistor; The gate of the seventh transistor is electrically connected to the scanning line, the first pole of the seventh transistor is electrically connected to the gate of the driving transistor, and the second pole of the seventh transistor is electrically connected to the first pole of the driving transistor; The first electrode plate of the third capacitor is electrically connected to the gate of the driving transistor, and the second electrode plate of the third capacitor is electrically connected to the power supply voltage line.

14. The pixel circuit according to claim 9, wherein, The first reset circuit includes an eighth transistor; A gate of the eighth transistor is electrically connected to the third reset control line, a first pole of the eighth transistor is electrically connected to a third initial voltage line, and a second pole of the eighth transistor is electrically connected to a control end of the driving circuit.

15. The pixel circuit according to claim 10, wherein, The second reset circuit includes a ninth transistor; A gate of the ninth transistor is electrically connected to the fourth reset control line, a first pole of the ninth transistor is electrically connected to the fourth initial voltage line, and a second pole of the ninth transistor is electrically connected to a first pole of the light-emitting element.

16. The pixel circuit according to claim 1 or 2, wherein, It includes a multiplexing control circuit; The multiplexing control circuit is respectively electrically connected to a multiplexing control end, a voltage output end of a source driver, and the data line, and is configured to control communication between the voltage output end and the data line under the control of a multiplexing control signal provided by the multiplexing control end.

17. A driving method is applied to the pixel circuit according to any one of claims 1 to 16. A display stage includes a first writing stage and a second writing stage; the driving method includes: In the first writing stage, a first control circuit provides a first control voltage provided by the data line to a second control node under the control of a first reset control signal, and the first control circuit controls whether to provide a first light-emitting control signal to a first control node under the control of a potential of the second control node; In the second writing stage, a second control circuit writes a second control voltage provided by the data line into a third control node under the control of a second reset control signal, and the second control circuit controls whether to provide a second light-emitting control signal to the first control node under the control of a potential of the third control node.

18. The driving method according to claim 17, wherein It includes: When performing medium-high gray-scale display, in the first writing stage, the first control circuit controls to provide the first light-emitting control signal to the first control node under the control of the potential of the second control node, and in the second writing stage, the second control circuit controls to stop providing the second light-emitting control signal to the first control node under the control of the potential of the third control node; When performing low gray-scale display, in the first writing stage, the first control circuit stops controlling to provide the first light-emitting control signal to the first control node under the control of the potential of the second control node, and in the second writing stage, the second control circuit controls to provide the second light-emitting control signal to the first control node under the control of the potential of the third control node.

19. A display substrate includes a substrate and a plurality of rows and columns of pixel circuits according to any one of claims 1 to 16 provided in a display area provided on the substrate.

20. The display substrate according to claim 19, wherein, Pixel circuits located in the same column are provided between two columns of data lines; the data lines extend in a first direction; The pixel circuit of the a-th row is provided between the a-th row scanning line and the a-th row first voltage line, where a is a positive integer; The a-th row scanning line and the a-th row first voltage line extend in a second direction; The first direction and the second direction intersect.

21. The display substrate according to claim 19, wherein, The pixel circuit includes a light-emitting element and a pixel driving circuit; A gap is provided between at least two pixel driving circuits adjacent in a second direction, and at least one of the light-emitting elements is disposed in the gap; The orthographic projection of the light-emitting element on the substrate does not overlap with the pixel driving circuit on the substrate.

22. The display substrate according to claim 21, wherein, It further includes a first signal line; most of the signal line portions included in the first signal line extend in the second direction; The first signal line is bent around the light-emitting element to form a first avoidance space, and at least a part of the light-emitting element is disposed in the first avoidance space.

23. The display substrate according to claim 22, wherein, It includes multiple rows of light-emitting units, and each light-emitting unit includes at least three of the light-emitting elements; At least one of the first signal lines is bent toward a first side around at least one of the light-emitting elements in the odd-row light-emitting units to form a first avoidance space; At least one of the first signal lines is bent toward a second side around at least one of the light-emitting elements in the even-row light-emitting units to form another first avoidance space; The first side and the second side are opposite sides.

24. The display substrate according to claim 19, wherein, The pixel circuit includes a light-emitting element and a pixel driving circuit; The light-emitting element is disposed on a side of the pixel driving circuit away from the substrate; The orthographic projection of the light-emitting element on the substrate at least partially overlaps with the orthographic projection of the pixel driving circuit on the substrate.

25. The display substrate according to claim 19, wherein, It further includes a light-emitting control signal generation module and a second signal line, and the light-emitting control signal generation module includes multiple levels of light-emitting control signal generation circuits; the light-emitting control signal generation circuits are disposed in the display area; The display substrate includes multiple rows and multiple columns of pixel driving groups, and each pixel driving group includes at least one pixel driving circuit; At least one level of the light-emitting control signal generation circuits is located between adjacent pixel driving groups; Most of the signal line portions included in the second signal line extend in a first direction; At least one of the second signal lines is bent around the at least one level of light-emitting control signal generation circuits to form a second avoidance space, and a part of the at least one level of light-emitting control signal generation circuits is disposed in the second avoidance space.

26. The display substrate according to claim 25, wherein, The orthographic projection of the light-emitting control signal generation circuit on the substrate does not overlap with the orthographic projection of the pixel driving group on the substrate.

27. The display substrate according to claim 19, wherein, It further includes a gate driving module, and the gate driving module includes multiple levels of gate driving circuits; the gate driving circuits are disposed in the display area; The display substrate includes multiple rows and multiple columns of pixel driving groups, and each pixel driving group includes at least one pixel driving circuit; At least one level of the gate driving circuits is located between adjacent pixel driving groups.

28. The display substrate according to claim 27, wherein, It further includes a second signal line; most of the signal line portions included in the second signal line extend in a first direction; At least one of the second signal lines is bent around the at least one level of gate driving circuits to form a third avoidance space, and a part of the at least one level of gate driving circuits is disposed in the third avoidance space.

29. The display substrate according to claim 27 or 28, wherein, The orthographic projection of the gate driving circuit on the substrate does not overlap with the orthographic projection of the pixel driving group on the substrate.

30. A display panel, including the display substrate according to any one of claims 19 to 29.

31. The display panel according to claim 30, wherein, It further includes a source driver, multiple columns of data lines, and a multiplexing circuit; Multiple pixel circuits located in the same column are all electrically connected to the same column of data lines; The multiplexing circuit is respectively electrically connected to multiple voltage output terminals of the source driver, multiple multiplexing control terminals, and the multiple columns of data lines, and is configured to write the voltage signal provided by the source driver through its voltage output terminal into the data lines under the control of the multiplexing control signal provided by the multiplexing control terminal.

32. The display panel according to claim 31, wherein, The multiplexing circuit is respectively electrically connected to N multiplexing control terminals, and the multiplexing circuit includes M multiplexing sub - circuits, where N and M are integers greater than 1; Each of the multiplexing sub - circuits is electrically connected to the voltage output terminal of the source driver, the N multiplexing control terminals, and N columns of the data lines, and is configured to control the voltage signal provided by the voltage output terminal to the nth data line among the N columns of data lines under the control of the nth multiplexing control signal provided by the nth multiplexing control terminal; n is a positive integer less than or equal to N.

33. A driving method, applied to the display panel as described in claim 31 or 32, where the display period includes a first writing time period and a second writing time period; the first writing time period includes a first data writing time period and a second data writing time period, and the second writing time period includes a third data writing time period and a fourth data writing time period; the driving method includes: In the first data writing time period, the multiplexing circuit writes a first control voltage provided by the source driver through its voltage output terminal into the data lines under the control of a reset control signal; In the second data writing time period, the first control circuit provides the first control voltage provided by the data lines to a second control node under the control of a first reset control signal, and the first control circuit controls whether to provide a first light - emitting control signal to the first control node under the control of the potential of the second control node; In the third data writing time period, the multiplexing circuit writes a second control voltage provided by the source driver through its voltage output terminal into the data lines under the control of a reset control signal; In the fourth data writing time period, the second control circuit writes the second control voltage provided by the data lines into a third control node under the control of a second reset control signal, and the second control circuit controls whether to provide a second light - emitting control signal to the first control node under the control of the potential of the third control node.

34. The driving method according to claim 33, wherein, The first data writing time period and the second data writing time period are set successively, and the third data writing time period and the fourth data writing time period are set successively; or, The first data writing time period is included in the second data writing time period, and the third data writing time period is included in the fourth data writing time period.

35. A display device includes the display panel as described in any one of claims 30 to 32.

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