Power supply voltage drop detection apparatus and system

Abstract

The present disclosure provides a power voltage drop detection device and system, belonging to the technical field of voltage detection. In the device, the gating unit outputs the power voltage to the first detection channel and the threshold voltage to the second detection channel in the first duration period of a control cycle; outputs the threshold voltage to the first detection channel and the power voltage to the second detection channel in the second duration period; the first detection channel detects the first voltage representation value in the first duration period and the second voltage representation value in the second duration period; compares the first voltage representation value with the second voltage representation value, and outputs the first alarm signal if the first voltage representation value is less than the second voltage representation value; the second detection channel detects the third voltage representation value in the first duration period and the fourth voltage representation value in the second duration period; compares the fourth voltage representation value with the third voltage representation value, and outputs the second alarm signal if the fourth voltage representation value is less than the third voltage representation value. The present disclosure is used to realize the detection of the power voltage drop.

Description

Technical Field

[0001] This invention relates to the field of voltage detection technology, and in particular to a power supply voltage drop detection device and system. Background Technology

[0002] As process dimensions continue to shrink, integrated circuits are becoming larger and more integrated, placing increasingly higher demands on power management modules. The power supply voltage of a System-on-Chip (SoC) needs to withstand large current load step changes within a few nanoseconds or tens of nanoseconds. However, the power management module cannot respond quickly enough, causing the power supply voltage to drop rapidly during these large current load step changes. When the power supply voltage drops low enough, it can lead to system malfunction. Summary of the Invention

[0003] This disclosure provides a power supply voltage drop detection device and system.

[0004] The first aspect of this disclosure provides a power supply voltage drop detection device, the device including a gating unit, a first detection channel and a second detection channel; the two input terminals of the gating unit are respectively connected to the power supply voltage and a threshold voltage, and the two output terminals are respectively connected to the first detection channel and the second detection channel;

[0005] The gating unit is configured to: output the power supply voltage to the first detection channel and the threshold voltage to the second detection channel during the first duration of each control cycle; and output the threshold voltage to the first detection channel and the power supply voltage to the second detection channel during the second duration of each control cycle, wherein each control cycle consists of a first duration and a second duration.

[0006] The first detection channel is used to: detect a first voltage characterization value of the power supply voltage during the first duration period; and detect a second voltage characterization value of the threshold voltage during the second duration period; compare the first voltage characterization value of the first duration period of each control cycle with the second voltage characterization value of the second duration period of the same control cycle, and output a first alarm signal when the first voltage characterization value is less than the second voltage characterization value;

[0007] The second detection channel is used to: detect a third voltage characterization value of the threshold voltage during the first duration period; and detect a fourth voltage characterization value of the power supply voltage during the second duration period; compare the third voltage characterization value of the first duration period of each control cycle with the fourth voltage characterization value of the second duration period of the same control cycle, and output a second alarm signal if the fourth voltage characterization value is less than the third voltage characterization value.

[0008] The second aspect of this disclosure provides a power supply voltage drop detection system, including the power supply voltage drop detection device described in the first aspect, a clock down-conversion unit, a power supply, and a processing core;

[0009] The power supply voltage drop detection device is used to output at least one of the first alarm signal and the second alarm signal to the clock down frequency unit;

[0010] The clock down frequency unit is used to reduce the system frequency of the processing core under the control of at least one of the first alarm signal and the second alarm signal.

[0011] This disclosure has the following advantages:

[0012] The gating unit outputs the power supply voltage to the first detection channel and a threshold voltage to the second detection channel during the first duration of each control cycle; during the second duration of each control cycle, it outputs the threshold voltage to the first detection channel and the power supply voltage to the second detection channel, causing the two output terminals to alternately output the power supply voltage and the threshold voltage. The first detection channel detects and obtains a first voltage characterization value of the power supply voltage during the first duration and a second voltage characterization value of the threshold voltage during the second duration. If the first voltage characterization value during the first duration of each control cycle is less than the second voltage characterization value during the second duration of the same control cycle, a first alarm signal is output. Similarly, the second detection channel detects and obtains a third voltage characterization value of the threshold voltage during the first duration and a fourth voltage characterization value of the power supply voltage during the second duration. If the fourth voltage characterization value during the second duration of each control cycle is less than the third voltage characterization value during the first duration of the same control cycle, a second alarm signal is output. This dual-channel time-division detection of the power supply voltage using the first and second detection channels, with the first and second detection channels re-detecting the threshold voltage for calibration during each control cycle, achieves online PVT calibration of the threshold voltage, improving the accuracy of rapid power supply voltage drop detection and simplifying the implementation process. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the structure of a power supply voltage drop detection device provided in an embodiment of this disclosure;

[0014] Figure 2 This is a schematic diagram of the structure of a first detection channel provided in an embodiment of this disclosure;

[0015] Figure 3 This is a schematic diagram of the structure of a second detection channel provided in an embodiment of this disclosure;

[0016] Figure 4 This is a schematic diagram of the structure of a first detection subunit provided in an embodiment of this disclosure;

[0017] Figure 5 This is a schematic diagram illustrating the principle of power supply voltage drop detection provided in an embodiment of this disclosure;

[0018] Figure 6 This is a schematic diagram of the structure of a second detection subunit provided in an embodiment of this disclosure;

[0019] Figure 7 This is a schematic diagram of a voltage divider circuit provided in an embodiment of the present disclosure;

[0020] Figure 8 This is a schematic diagram of another power supply voltage drop detection device provided in this embodiment of the present disclosure;

[0021] Figure 9 This is a schematic diagram of the working timing of a first detection channel and a second detection channel provided in an embodiment of this disclosure;

[0022] Figure 10 This is a schematic diagram illustrating the workflow of a first detection channel and a second detection channel provided in an embodiment of this disclosure;

[0023] Figure 11 This is a schematic diagram of a calibration process provided in an embodiment of this disclosure;

[0024] Figure 12 This is a schematic diagram of the structure of a power supply voltage drop detection system provided in an embodiment of this disclosure;

[0025] Figure 13 This is a schematic diagram of a delay chain provided in an embodiment of the present disclosure. Detailed Implementation

[0026] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0027] As used in this disclosure, the term "and / or" includes any and all combinations of one or more of the related enumerated entries.

[0028] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used in this disclosure, the singular forms “a” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0029] When the terms “comprising” and / or “made of” are used in this disclosure, they specify the presence of the said feature, integral, step, operation, element and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or groups thereof.

[0030] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so specified in this disclosure.

[0031] The inventors discovered during their research on existing technologies that:

[0032] In traditional power management modules, voltage drops are mitigated by increasing the operating voltage to prevent system malfunctions. However, this increases the voltage during normal operation, leading to wasted power. Existing power voltage drop detection mechanisms fall into two categories: analog and digital. Analog detection primarily uses a comparator to compare a reference threshold with the power supply voltage. An alarm signal is triggered when the power supply voltage is lower than the threshold. However, this method requires a reference power supply, resulting in a large area and necessitating two power supplies. Digital detection utilizes the relationship between power supply voltage and delay chains. As the power supply voltage decreases, the delay time of the delay chains increases, converting voltage to time. Time-to-digital converters (TDCs) then convert the time to digital, achieving voltage-to-digital conversion. However, the delay of the delay chain varies greatly with PVT (Process, Voltage, Temperature). The current mainstream solution is to use a lookup table scheme for calibration to eliminate the influence of PVT. However, this calibration method is complex, requires other sensors, and has limited accuracy.

[0033] Therefore, this disclosure provides a power supply voltage drop detection device. It is mainly used to detect voltage drops in a System-on-a-Chip (SOC) due to load changes, and to issue an alarm signal when a voltage drop is detected.

[0034] like Figure 1The diagram shows a power supply voltage drop detection device provided in an embodiment of this disclosure. The device mainly includes a gating unit 10, a first detection channel 11, and a second detection channel 12. One input terminal 1 of the gating unit 10 is connected to the power supply voltage, the other input terminal 2 is connected to the threshold voltage, one output terminal 3 is connected to the first detection channel 11, and the other output terminal 4 is connected to the second detection channel 12.

[0035] The gating unit 10 outputs a power supply voltage to the first detection channel 11 and a threshold voltage to the second detection channel 12 during the first duration of each control cycle; during the second duration of each control cycle, it outputs a threshold voltage to the first detection channel 11 and a power supply voltage to the second detection channel 12. Each control cycle consists of a first duration and a second duration. That is, within the same duration, one output terminal outputs a threshold voltage, and the other output terminal outputs a power supply voltage. The same output terminal outputs a threshold voltage in one duration and a power supply voltage in the next duration, so that the two output terminals alternately output power supply voltage and threshold voltage.

[0036] The first detection channel 11 detects a first voltage characterization value of the power supply voltage during a first duration period; and detects a second voltage characterization value of the threshold voltage during a second duration period; compares the first voltage characterization value of the first duration period in each control cycle with the second voltage characterization value of the second duration period in the same control cycle, and outputs a first alarm signal if the first voltage characterization value is less than the second voltage characterization value. The second detection channel 12 detects a third voltage characterization value of the threshold voltage during the first duration period; and detects a fourth voltage characterization value of the power supply voltage during the second duration period; compares the third voltage characterization value of the first duration period in each control cycle with the fourth voltage characterization value of the second duration period in the same control cycle, and outputs a second alarm signal if the fourth voltage characterization value is less than the third voltage characterization value.

[0037] In this embodiment, two detection channels are used to periodically detect power supply voltage drops according to a control cycle. During the first duration of each control cycle, one detection channel detects a threshold voltage, while the other detects the power supply voltage. During the second duration of each control cycle, the detection objects are reversed; that is, the detection channel that originally detected the threshold voltage detects the power supply voltage, and vice versa. Each detection channel compares its own detected threshold voltage with the power supply voltage within the same control cycle and outputs an alarm signal when the real-time detected power supply voltage is less than the threshold voltage. In this embodiment, the threshold voltage is set to be less than the power supply voltage. A drop in power supply voltage that remains above the threshold voltage is tolerable; an alarm is output when the power supply voltage drops below the threshold voltage.

[0038] In some embodiments, such as Figure 2 The diagram shows the structure of the first detection channel 11, which includes a first detection subunit 110, a first calibration subunit 111, and a first comparison subunit 112 connected in sequence. The first detection subunit 110 detects the first number of delay cells contained in each of the n detection windows within the first duration of each control cycle, using this first number as the first voltage characterization value, i.e., the number of delay cells corresponding to the power supply voltage. In each detection window, a number of delay cells characterizing the power supply voltage is detected. The first detection subunit 110 also detects the second number of delay cells contained in each of the m detection windows within the second duration of each control cycle, i.e., the number of delay cells corresponding to the threshold voltage. In each detection window, a number of delay cells characterizing the threshold voltage is detected. Here, n is an integer greater than or equal to 1, and m is an integer greater than or equal to 1. The first calibration subunit 111 averages the q second numbers for the same control cycle to obtain the second voltage characterization value for that control cycle, where q is less than or equal to m. The first comparison subunit 112 compares the first voltage characterization value of the first duration segment of each control cycle with the second voltage characterization value of the second duration segment of the same control cycle, and outputs a first alarm signal if the first voltage characterization value is less than the second voltage characterization value.

[0039] The value of n is related to the duration of the first duration segment and the duration of a single detection window. For example, n is the number of detection windows contained in the first duration segment. Similarly, the value of m is related to the duration of the second duration segment and the duration of a single detection window. For example, m is the number of detection windows contained in the second duration segment. The number of q depends on the number of times the second number is continuously acquired during the averaging time of the first calibration subunit. If m second numbers can be acquired during the averaging time, then q equals m; if m second numbers cannot be acquired, then q is less than m.

[0040] The delay duration of a single delay unit increases as the power supply voltage decreases.

[0041] In some embodiments, such as Figure 3The diagram shows the structure of the second detection channel 12, which includes a second detection subunit 120, a second calibration subunit 121, and a second comparison subunit 122 connected in sequence. The second detection subunit 120 detects the third number of delay units contained in each of the n detection windows within the first duration of each control cycle of the input threshold voltage, i.e., the number of delay units corresponding to the threshold voltage, detecting a number of delay units representing the magnitude of the threshold voltage in each detection window; and the second detection subunit detects the fourth number of delay units contained in each of the m detection windows within the second duration of each control cycle of the input power supply voltage, using the fourth number as the fourth voltage representation value, i.e., the number of delay units corresponding to the power supply voltage, detecting a number of delay units representing the magnitude of the power supply voltage in each detection window; where n is an integer greater than or equal to 1, and m is an integer greater than or equal to 1. The second calibration subunit 121 averages the p third numbers for the same control cycle to obtain the third voltage representation value for that control cycle, where p is less than or equal to n. The second comparison subunit 122 compares the third voltage characterization value of the first duration segment of each control cycle with the fourth voltage characterization value of the second duration segment of the same control cycle, and outputs a second alarm signal if the fourth voltage characterization value is less than the third voltage characterization value.

[0042] The value of n is related to the duration of the first duration segment and the duration of a single detection window. For example, n is the number of detection windows contained in the first duration segment. Similarly, the value of m is related to the duration of the second duration segment and the duration of a single detection window. For example, m is the number of detection windows contained in the second duration segment. The number of p depends on the number of times the third number is continuously acquired during the averaging time of the second calibration subunit. If n third numbers can be acquired during the averaging time, then p equals n; if n third numbers cannot be acquired, then p is less than n.

[0043] The delay duration of a single delay unit increases as the power supply voltage decreases.

[0044] In one example, the first and second comparison subunits are implemented using digital comparators.

[0045] In some embodiments, such as Figure 4The diagram shows the structure of the first detection subunit 110. The first detection subunit 110 includes a first frequency divider (div2) 41 and a first delay chain 42. The signal output terminal of the first frequency divider 41 is connected to the signal input terminal of the first delay chain 42, the power input terminal of the first delay chain 42 is connected to the power supply voltage, and the output terminal of the first delay chain 42 serves as the output terminal of the first detection subunit 110. The first frequency divider 41 outputs a divided-by-two signal through its signal output terminal, and the high-level time period of this divided-by-two signal is the detection window. The delay length of the first delay chain 42 increases as the power supply voltage decreases. The first frequency divider generates a clock with a 50% duty cycle, i.e., a divided-by-two signal. Assuming the input clock of the first frequency divider is 2GHz, the high-level time period is approximately 500ps. By detecting the number of delay units in the first delay chain within 500ps, the change in power supply voltage is monitored, and the delay units are used as the clock to convert 500ps into data, achieving time-to-data conversion, i.e., TDC. The first delay chain 42 includes multiple delay units. There is no limit to the number of delay units, as long as they can meet the TDC conversion requirements of the divided-by-two signal output by the first frequency divider.

[0046] like Figure 5 The diagram illustrates the principle of power supply voltage drop detection. Time period T1 is the detection window. After the first delay chain, the number of delay units within the detection window can be obtained. As the power supply voltage decreases, the number of delay units within the detection window gradually decreases. Therefore, the change in the number of delay units within the detection window can be used to determine whether a power supply voltage drop has occurred. Taking a detection window of 500ps as an example, when the power supply voltage increases, the number of delay units within 500ps increases; when the power supply voltage decreases, the number of delay units within 500ps decreases. The current power supply voltage level can be determined by the number of delay units within 500ps.

[0047] In some embodiments, such as Figure 6 The diagram shows the structure of the second detection subunit 120. The second detection subunit 120 includes a second frequency divider 61 and a second delay chain 62. The signal output terminal of the second frequency divider 61 is connected to the signal input terminal of the second delay chain 62, the power input terminal of the second delay chain 62 is connected to the power supply voltage, and the output terminal of the second delay chain 62 serves as the output terminal of the second detection subunit 120. The second frequency divider 61 outputs a divided-by-two signal through its signal output terminal, and the high-level time period of the divided-by-two signal is the detection window. The principle is the same as the first detection subunit; the second detection subunit converts the high-level time period of the divided-by-two signal into data, realizing the time-to-data conversion.

[0048] In some embodiments, the first duration segment and the second duration segment have the same duration. In an exemplary embodiment, the values ​​of the first duration segment and the second duration segment are each greater than or equal to 1 ms and less than or equal to 2 ms. It should be understood that the first duration segment and the second duration segment are two duration segments within one cycle of the timing signal. These two duration segments form a control cycle, under the control of the timing signal, the gating unit alternately outputs the threshold voltage and the power supply voltage at the two output terminals. The value ranges of the first duration segment and the second duration segment given here are an exemplary embodiment, and it is not mandatory to configure the first duration segment and the second duration segment according to these value ranges, nor are their value ranges limited by them.

[0049] In some embodiments, the threshold voltage can be obtained by dividing the power supply voltage using a sampling resistor voltage divider. In other embodiments, the threshold voltage can be obtained by externally inputting a fixed voltage, wherein the fixed voltage is set to the voltage value at which the alarm is desired.

[0050] In some embodiments, the power supply voltage drop detection device provided in this disclosure further includes a voltage divider circuit 70; such as Figure 7 The diagram shows the structure of a voltage divider circuit. The input terminal of the voltage divider circuit 70 is connected to the power supply voltage, and the output terminal of the voltage divider circuit 70 is connected to the second input terminal of the gating unit. The voltage divider circuit 70 divides the power supply voltage and outputs a threshold voltage. In some embodiments, the threshold voltage can be set to 90% to 95% of the power supply voltage. Figure 7 The example given is that the threshold voltage accounts for 93% of the power supply voltage. The actual threshold voltage can be set as needed, and there is no restriction on the specific value of the threshold voltage.

[0051] In some embodiments, Figure 8 In the schematic diagram of the power supply voltage drop detection device shown, the selection unit 10 includes two sets of switching elements, each set including two switches, sw1 and sw2. In the first set of switching elements, the two ends of sw1 are connected to the first detection channel and the threshold voltage Vth, respectively, and the two ends of sw2 are connected to the second detection channel and the threshold voltage, respectively. In the second set of switching elements, the two ends of sw1 are connected to the power supply voltage Vdd and the second detection channel, respectively, and the two ends of sw2 are connected to the power supply voltage and the first detection channel, respectively.

[0052] For example, in other embodiments, the gating unit includes a first single-pole double-throw switch and a second single-pole double-throw switch; the moving end of the first single-pole double-throw switch is connected to the threshold voltage, one stationary end is connected to the input terminal of the first detection channel, and the other stationary end is connected to the input terminal of the second detection channel; the moving end of the second single-pole double-throw switch is connected to the power supply voltage, one stationary end is connected to the input terminal of the second detection channel, and the other stationary end is connected to the input terminal of the first detection channel.

[0053] Figure 9 Shown is a schematic diagram of the working timing of the first detection channel and the second detection channel. Figure 10 Shown is a schematic diagram of the working process of the first detection channel and the second detection channel. Figure 11 Shown is a schematic diagram of the calibration process. In this embodiment, the first duration period and the second duration period are equal, both being T. Each control cycle is 2T, which is composed of an adjacent first duration period and second duration period. The channel voltage is selected by sw1 and sw2. During the first duration period of each control cycle, sw1 = 1, sw2 = 0, vth is used as the input voltage of the first detection subunit cha in the first detection channel, and vdd is used as the input voltage of the second detection subunit chb in the second detection channel. That is, the first detection channel is the threshold seeking channel, and the second detection channel is the working channel; the output data of cha is dout_a, dout_a is continuously output, and the number of dout_a is determined by the length of one duration period T of vth in cha. After being calibrated by the first calibration subunit, dout_a outputs dout_tha. For example, if the output rate of dout_a is 1 ns and T is 1 ms, then there are 1,000,000 dout_a in the T period, and 1,000,000 dout_a obtain dout_tha after the calibration algorithm.

[0054] In the next period T, that is, the second duration period, sw1 = 0, sw2 = 1, vth is used as the input voltage of the second detection subunit chb, and vdd is used as the input voltage of the first detection subunit cha. That is, the first detection channel is the working channel, and the second detection channel is the threshold seeking channel; the output data of the second detection subunit chb is dout_b, dout_b is continuously output, and the number of dout_b is determined by the length of one duration period T of vth in the second detection subunit chb. For example, if the output rate of dout_b is 1 ns and T is 1 ms, then there are 1,000,000 dout_b in the T period, and 1,000,000 dout_b obtain dout_thb after the calibration algorithm. In the same period, the output data of the first detection subunit cha is dout_a detected for vdd, dout_a is continuously output, and the first comparison subunit compares dout_a detected for vdd and dout_tha obtained in the previous duration period T. When dout_a < dout_tha, an alarm signal warning_a is issued.

[0055] Similarly, in the next time period T, the second comparison subunit detects vdd to obtain dout_b, compares dout_b with dout_thb, and when dout_b < dout_thb, issues an alarm signal warning_b.

[0056] It can be seen that the threshold voltage is calibrated once every interval T, that is, dout_tha and dout_thb are reselected, realizing the online calibration of the threshold voltage.

[0057] The first calibration subunit and the second calibration subunit use the digital domain averaging algorithm for calibration, which can achieve the effect of a low-pass filter in the digital domain, so as to obtain stable threshold voltage characterization values dout_tha and dout_thb. The bandwidth of the filter is determined by the length of T. The longer the length of T, the narrower the filter bandwidth and the better the filtering effect. However, considering that there is a continuous time period T between dout_tha and dout_a, and there is a continuous time period T between dout_thb and dout_b, a temperature deviation will be introduced. The length of T is limited within a certain range. The value of T does not exceed the set upper limit value. And considering that the temperature changes by 1 degree Celsius in about 1 ms, the range of T is set to be less than or equal to 1 ms and greater than or equal to 2 ms.

[0058] In some embodiments, as Figure 12 shown is a schematic structural diagram of a power supply voltage drop detection system provided by an embodiment of the present disclosure, including the power supply voltage drop detection device 1201, the clock downscaling unit (clockstrech) 1202, the power supply 1203, and the processing core (core) 1204 described above; the clock controller of the clock downscaling unit 1202 is respectively connected to the output ends of the first detection channel 11 and the second detection channel 12. The power supply voltage drop detection device 1201 outputs at least one of the first alarm signal and the second alarm signal to the clock downscaling unit 1202; the clock downscaling unit 1202 reduces the system frequency of the processing core 1204 under the control of at least one of the first alarm signal and the second alarm signal.

[0059] When the load of the power supply changes suddenly, such as Figure 12 in which the load current I_load suddenly increases, the power supply voltage vdd will drop. The power supply voltage drop is detected by the gating unit, the first detection channel and the second detection channel, and when the power supply voltage drops to less than the threshold voltage, that is, vdd < vth, the first alarm signal and / or the second alarm signal is issued ( Figure 12The alarm signal is displayed as a warning and is transmitted to the clock frequency reduction unit. The clock frequency reduction unit controls the processing core of the SOC system to reduce the frequency (freq_down). After the system frequency is reduced, the operating current will decrease and the power supply voltage will increase, so that the power supply voltage will not drop too much due to large load changes, which will cause the system to malfunction and ensure the normal operation of the system.

[0060] The power supply voltage drop detection device provided in this embodiment can quickly detect and reduce the system's operating frequency when a power supply voltage drops, thus slowing down the voltage drop and restoring it to a normal value. The gating unit outputs the power supply voltage to the first detection channel and a threshold voltage to the second detection channel during the first duration of each control cycle; during the second duration of each control cycle, it outputs the threshold voltage to the first detection channel and the power supply voltage to the second detection channel, allowing the two output terminals to alternately output the power supply voltage and the threshold voltage. The first detection channel detects and obtains a first voltage characterization value of the power supply voltage during the first duration and a second voltage characterization value of the threshold voltage during the second duration. If the first voltage characterization value is less than the second voltage characterization value, a first alarm signal is output. Similarly, the second detection channel outputs a second alarm signal. This dual-channel time-division detection of rapid power supply voltage drops, using both the first and second detection channels, allows for re-detection and calibration of the threshold voltage during each control cycle. This achieves online PVT calibration of the threshold voltage, improving the accuracy of rapid power supply voltage drop detection and simplifying the implementation process.

[0061] For example, in the above embodiments, the structure of any delay chain in the first delay chain and the second delay chain is as follows: Figure 13 As shown, the power supply terminals (not shown in the figure) of each component in the delay chain are connected to the power supply terminal. clkin is the clock signal, where the inverter is the delay unit. The inverter and the D flip-flop together form the delay chain. The delay_ctrl signal is the delay control signal, and the delay chain operates under the control of the delay control signal and clkin. Figure 13 The circled circuit is an amplifier circuit with a single inverter. This is merely an example, and the embodiments of this disclosure do not limit the specific circuit structure of the delay chain. Any delay chain structure that can be used for time-to-data conversion can be used in the embodiments of this disclosure.

[0062] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0063] Those skilled in the art will understand that although some embodiments described herein include certain features that are included in other embodiments but not others, combinations of features from different embodiments are meant to be within the scope of this embodiment and form different embodiments.

[0064] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A power supply voltage drop detection device, the device comprising a gating unit, a first detection channel, and a second detection channel; the two input terminals of the gating unit are respectively connected to a power supply voltage and a threshold voltage, and the two output terminals are respectively connected to the first detection channel and the second detection channel; The gating unit is configured to: output the power supply voltage to the first detection channel and the threshold voltage to the second detection channel during the first duration of each control cycle; and output the threshold voltage to the first detection channel and the power supply voltage to the second detection channel during the second duration of each control cycle, wherein each control cycle consists of a first duration and a second duration. The first detection channel is used to: detect a first voltage characterization value of the power supply voltage during the first duration period; and detect a second voltage characterization value of the threshold voltage during the second duration period; compare the first voltage characterization value of the first duration period of each control cycle with the second voltage characterization value of the second duration period of the same control cycle, and output a first alarm signal when the first voltage characterization value is less than the second voltage characterization value; The second detection channel is used to: detect a third voltage characterization value of the threshold voltage during the first duration period; and detect a fourth voltage characterization value of the power supply voltage during the second duration period; compare the third voltage characterization value of the first duration period of each control cycle with the fourth voltage characterization value of the second duration period of the same control cycle, and output a second alarm signal if the fourth voltage characterization value is less than the third voltage characterization value; The first detection channel includes a first detection subunit, a first calibration subunit, and a first comparison subunit connected in sequence; The first detection subunit is configured to: detect the first number of delay units contained in each of the n detection windows within the first duration period of each control cycle, and use the first number as the first voltage characterization value; and detect the second number of delay units contained in each of the m detection windows within the second duration period of each control cycle; wherein, n is an integer greater than or equal to 1, and m is an integer greater than or equal to 1. The first calibration subunit is used to: average q second numbers for the same control cycle to obtain the second voltage characterization value for that control cycle; wherein, q is less than or equal to m; The first comparison subunit is used to compare the first voltage characterization value during the first duration of each control cycle with the second voltage characterization value during the second duration of the same control cycle, and output a first alarm signal when the first voltage characterization value is less than the second voltage characterization value. The first detection subunit includes a first frequency divider and a first delay chain; The signal output terminal of the first frequency divider is connected to the signal input terminal of the first delay chain, the power input terminal of the first delay chain is connected to the power supply voltage, and the output terminal of the first delay chain serves as the output terminal of the first detection subunit. The first frequency divider is used to output a divided frequency signal through the signal output terminal, and the high-level time period of the divided frequency signal is the detection window.

2. The power supply voltage drop detection device according to claim 1, characterized in that, The second detection channel includes a second detection subunit, a second calibration subunit, and a second comparison subunit connected in sequence; The second detection subunit is used to detect the third number of delay units contained in each of the n detection windows within the first duration segment of each control cycle; and the second detection subunit detects the fourth number of delay units contained in each of the m detection windows within the second duration segment of each control cycle, and uses the fourth number as the fourth voltage characterization value; wherein, n is an integer greater than or equal to 1, and m is an integer greater than or equal to 1; The second calibration subunit is used to average p third numbers in the same control cycle to obtain the third voltage characterization value of that control cycle; wherein, p is less than or equal to n; The second comparison subunit is used to compare the third voltage characterization value of the first duration segment of each control cycle with the fourth voltage characterization value of the second duration segment of the same control cycle, and outputs a second alarm signal if the fourth voltage characterization value is less than the third voltage characterization value.

3. The power supply voltage drop detection device according to claim 2, characterized in that, The second detection subunit includes a second frequency divider and a second delay chain; The signal output terminal of the second frequency divider is connected to the signal input terminal of the second delay chain, the power input terminal of the second delay chain is connected to the power supply voltage, and the output terminal of the second delay chain serves as the output terminal of the second detection subunit. The second frequency divider is used to output a divided frequency signal through the signal output terminal, and the high-level time period of the divided frequency signal is the detection window.

4. The power supply voltage drop detection device according to claim 1, characterized in that, The gating unit includes a first group of switching elements and a second group of switching elements; The first set of switching elements includes a first switch and a second switch; one end of the first switch is connected to the threshold voltage, and the other end is connected to the input terminal of the first detection channel; one end of the second switch is connected to the threshold voltage, and the other end is connected to the input terminal of the second detection channel. The second set of switching elements includes a third switch and a fourth switch; one end of the third switch is connected to the power supply voltage, and the other end is connected to the input terminal of the second detection channel; one end of the fourth switch is connected to the power supply voltage, and the other end is connected to the input terminal of the first detection channel.

5. The power supply voltage drop detection device according to claim 1, characterized in that, The first duration segment and the second duration segment have the same duration.

6. The power supply voltage drop detection device according to claim 1, characterized in that, The device also includes a voltage divider circuit; The input terminal of the voltage divider circuit is connected to the power supply voltage, and the output terminal of the voltage divider circuit is connected to the second input terminal of the gating unit; The voltage divider circuit is used to divide the power supply voltage and output the threshold voltage.

7. A power supply voltage drop detection system, characterized in that, Includes the power supply voltage drop detection device, clock down-conversion unit, power supply, and processing core as described in any one of claims 1-6; The power supply voltage drop detection device is used to output at least one of the first alarm signal and the second alarm signal to the clock down frequency unit; The clock down frequency unit is used to reduce the system frequency of the processing core under the control of at least one of the first alarm signal and the second alarm signal.

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