Over-current detection circuit for Hall current sensor

Abstract

The invention provides an over current detection (OCD) circuit used for a Hall current sensor, and relates to an over current detection (OCD) circuit used for a Hall current sensor. The circuit can judge whether the measured current exceeds the detection range or not, so that the current measurement precision is further ensured.

Description

Technical Field

[0001] The invention relates to a Hall sensor ASIC circuit in the field of integrated electronic circuits, and in particular to a high-precision current detection circuit. Background Art

[0002] The Hall sensor chip can accurately measure the external magnetic field, so it can measure the current flowing through the conductor by detecting the magnetic induction intensity around the current-carrying conductor. The new generation of ASIC open-loop sensors uses ASIC technology, which integrates the Hall element and the conditioning circuit on a custom chip. In addition to being able to accurately measure the current value, the chip also needs to have an OCD function, that is, an over-current detection function (Over Current Detect), to further improve the current detection accuracy.

[0003] The OCD function output pin is usually connected to the middle pin INT of the subsequent MCU. When an overcurrent occurs, it will trigger an interrupt inside the microcontroller, notifying the MCU to handle the interrupt event. The power supply of the OCD pin pulled up to the microcontroller can be well matched with the working level of the MCU. If the distance from the OCD to the microcontroller is long, a small capacitor can be connected across the ground before entering the INT pin to prevent the noise coupled on the line from falsely triggering the MCU.

[0004] There are two traditional ways to implement the OCD (overcurrent detection) circuit of the Hall sensor, one is hardware implementation and the other is software implementation. Reference [He Guifang. Application of giant magnetoresistance in current detection and protection of switching power supply [J]. Industrial and Mining Automation, 2006 (04): 33-35.] In the OCD implementation circuit, the output voltage is sent to the inverting input terminal of the comparator A2 and compared with the reference voltage at the inverting terminal of A2. The reference voltage at the inverting terminal of the A2 comparator comes from the voltage of the power supply Vcc through the voltage divider on R5 and R6. The voltage on R6 is the threshold voltage of protection; when the output voltage of A1 is less than the voltage on R6, A2 outputs a high level, otherwise when the output voltage of A1 is greater than the voltage on R6, the output of A2 jumps to a low level. In normal operation, A2 outputs a high level and the drive circuit is in normal working state. When the power supply has an overcurrent or short circuit, the output voltage of the sensor increases and is greater than the threshold voltage of the comparator, and A2 outputs a low level. Literature [Zhao Wen. Current monitoring and overcurrent protection design based on Hall sensor [J]. Instrument Technology, 2019(02):10-12+46.DOI:10.19432 / j.cnki.issn1006-2394.2019.02.003.] Use software control for OCD. The current monitoring conditioning circuit is used to condition the sensor output signal. It is composed of an operational amplifier and a matching resistor. The output signal of the circuit is collected by the AD acquisition board of the tester and then read by the test software to realize the current monitoring function. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art, realize on-chip integrated over-current detection, have a simple structure, improve current detection accuracy and effectively reduce costs.

[0006] 5. The present invention provides an overcurrent detection circuit for a Hall current sensor as claimed in claim 1, characterized in that it comprises:

[0007] The first bandgap reference module consists of two parts: the core circuit and the startup circuit. The core circuit of the bandgap reference uses the negative temperature characteristic of the transistor base-emitter voltage VBE and the positive temperature characteristic of the difference ΔVBE of the base-emitter voltage of the transistor working at different current densities to output a zero temperature coefficient voltage V REF . It includes a first BJT (bipolar transistor, Q1) and a first resistor for generating a first current proportional to the absolute temperature, a second BJT (bipolar transistor, Q2) for generating a second current inversely proportional to the absolute temperature, and a third BJT (bipolar transistor, Q3) and a second resistor for outputting a third current independent of the absolute temperature, wherein the emitter junction area of ​​the second BJT is n times the emitter junction area of ​​the second BJT, and the emitter junction area of ​​the second BJT is n times the emitter junction area of ​​the third BJT; it further includes an operational amplifier circuit, the first resistor is connected to the first input terminal of the operational amplifier, the collector of the second BJT is connected to the second input terminal of the operational amplifier, MOSFET2 and the ninth MOSFET3 constitute the first current mirror as the load of the operational amplifier; MOSFET2 and MOSFET4 constitute the second current mirror, outputting a current IPATA positively correlated with the temperature, flowing through the resistor three, and outputting a voltage V independent of the temperature. REF The startup function module includes a first startup MOSFET, a fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth startup MOSFET, wherein the gates of the fifth, sixth, and seventh startup MOSFETs are connected to VSS, the electrodes are connected to the power supply VDD, and the drains are connected to the drain of the ninth startup MOSFET and the gate of the twelfth startup MOSFET; the gate and drain of the eighth startup MOSFET are connected, connected to the drain of the twelfth startup MOSFET, and its source is connected to the second, third, and fourth MOSFETs of the bias tube of the reference core function module to generate I PTAT The tenth startup MOSFET and the eleventh startup MOSFET form a current mirror structure, the gate and drain of the tenth startup MOSFET are connected to the drain of the first startup MOSFET, the drain of the eleventh startup MOSFET is connected to the source of the ninth startup MOSFET, and the gate of the ninth startup MOSFET is connected to the core reference output voltage VREF.

[0008] The second threshold level generating module is used to generate two threshold voltages VH and VL. REF The bandgap reference module is connected to the in-phase input terminal of the operational amplifier A2, and the first resistor R1, the second resistor R2, and the third resistor R3 are connected in series. The connection point of the second resistor R2 and the third resistor R3 is connected to the inverting input terminal of the operational amplifier, and the other end of the third resistor R3 is connected to the output of the operational amplifier to output the threshold voltage VH; the first resistor R1 and the second resistor R2 are connected to output a voltage of VL.

[0009] The third comparator module includes a first comparator C1, a non-inverting input terminal connected to VL, and an inverting input terminal connected to V IN ; The second comparator C2, the non-inverting input terminal is connected to V IN , the inverting input terminal is connected to VH; the outputs of the first comparator C1 and the second comparator C2 pass through the OR gate, output voltage A, and are connected to the timing processing module circuit.

[0010] In the fourth timing processing module, the comparator output voltage A passes through the first inverter and is input into the third D flip-flop DFF3, and the output Q is used as the reset signal of the counter Counter 2; the comparator output voltage A also serves as the reset signal of the counter Counter 1; the comparator output voltage A and the output of Counter 1 pass through the AND gate as the clock signal of the first D flip-flop DFF1; the output of Counter 2 passes through the second inverter and is output as the enable signal EN, which is the reset signal of the second D flip-flop DFF2. Counters Counter 1 and Counter 2 are both composed of D flip-flops connected in series. CP is the clock signal, which comes from the oscillator circuit.

[0011] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0012] The present invention discloses an overcurrent detection circuit for a Hall current sensor, which determines whether the circuit current exceeds the detection range by comparing the amplified sensing signal of the comparator with the current limiting threshold voltage signal. If the current exceeds the detection range, the circuit alarms. At the same time, an additional timing control circuit is introduced, and the overcurrent detection circuit starts the alarm after a period of time after the measured current exceeds the threshold, effectively preventing false alarms. The circuit can be integrated on a chip, with a small area and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is the block diagram of the overcurrent detection circuit system.

[0014] Figure 2 It is a schematic diagram of the bandgap reference circuit of the present invention.

[0015] Figure 3 It is a diagram of the architecture of the threshold level generating module of the present invention.

[0016] Figure 4 It is a comparator module circuit.

[0017] Figure 5 It is the timing processing circuit of the present invention. DETAILED DESCRIPTION

[0018] The following examples are further explanations and supplements of the present invention and do not constitute any limitation to the present invention. Figure 1 As shown, the overcurrent detection circuit for the Hall current sensor includes a first core reference voltage generation module, a second threshold voltage generation module, a third comparator module, and a fourth timing processing module circuit.

[0019] The first core reference generation circuit module realizes the bandgap reference structure by generating PTAT current. It includes a first BJT (Q1) and a first resistor (R1) for generating a first current proportional to the absolute temperature, a second BJT (Q2) for generating a second current inversely proportional to the absolute temperature, and a third BJT (Q3) and a second resistor (R2) for generating a third current that is independent of the absolute temperature. The specific working principle of the core reference circuit is as follows: the potential at point X is the base-emitter voltage V of transistor Q1. BE1 , from the virtual short and virtual open characteristics of op amp A1, we can know that the potential at point Y is the same as the potential at point X:

[0020] V Y =V X =V BE1 (1)

[0021] The potential at point Z is the base-emitter voltage V of transistor Q2. BE2 , so the voltage drop across resistor R1 is the difference between the base-emitter voltages of transistors Q1 and Q2, ΔV BE , ΔV BE It can be expressed as

[0022]

[0023] Where V T is the thermal voltage, I0 is the current flowing into the emitter of the transistor, I S1 is the saturation current of a single transistor, n is the number of transistors in parallel, so the saturation current of transistor Q2 is nI S1 In this design, the parallel number n of Q2 is designed to be 8.

[0024] Due to the voltage drop ΔV of resistor R1 BE is a positive temperature coefficient voltage, so the current flowing through R1 is a positive temperature coefficient current I PTAT , I PTAT It can be expressed as:

[0025]

[0026] The positive temperature coefficient current I flowing through R1 is copied through current mirrors M3 and M4. PTAT to R2, at this time the voltage drop on R2 is I PTAT *R2, so V REF It can be expressed as:

[0027]

[0028] By adjusting the ratio of R2 to R1, the weight of the positive temperature coefficient voltage in the output voltage can be changed. When the positive temperature coefficient and the negative temperature coefficient cancel each other, the bandgap reference will generate a reference voltage VBG that is independent of temperature. In the present invention, the first resistor R1 and the second resistor R2 need to satisfy the following formula: R2 / R1≈17.2ln8=8.83.

[0029] The core reference generation circuit module further includes an operational amplifier circuit A1, a first resistor is connected to a first input terminal of the operational amplifier, a collector of a second BJT is connected to a second input terminal of the operational amplifier, and an output of the operational amplifier controls the gates of the second core MOSFET, the third core MOSFET and the fourth core MOSFET of the current mirror.

[0030] The core reference generation circuit also includes a startup circuit module. When the power supply voltage starts to be powered on, the fifth startup MOSFET, the sixth startup MOSFET, and the seventh startup MOSFET are turned on, and the ninth startup MOSFET is turned off. Point Z is set to a high level. At this time, the twelfth startup MOSFET is turned on to pull the potential of point B down to the ground. The eighth startup MOSFET is turned on, and the gate voltage of the second startup MOSFET and the third startup MOSFET is lowered to generate current at the drain. The bandgap reference jumps out of the degeneracy point and starts to work. V REF Starts to rise when V REF When the voltage rises to exceed the threshold voltage of the ninth startup MOSFET, the ninth startup MOSFET is turned on, pulling down the potential of point Z to cause the twelfth startup MOSFET to turn off, the startup circuit stops working, and the bandgap reference startup process is completed. The bandgap reference voltage V REF Stable output.

[0031] The second threshold voltage generating module is used to generate two threshold levels VL and VH, such as Figure 3 As shown. The operational amplifier A2 is in a negative feedback connection state. According to the virtual short and virtual open, the relationship between the input and output of the structure is:

[0032]

[0033] In the present invention, the rated output of the Hall sensor is 2.5V±0.6V, and the primary current corresponding to the detection end is Ipn (rated current). In this design, the threshold of overcurrent detection is set to ±2.51Ipn, and the corresponding threshold voltages VH and VL are 4V and 1V respectively.

[0034] The third comparator module, OCD has high and low threshold levels, so two comparators are required, such as Figure 4 As shown, when the amplified signal V IN Greater than the high threshold level V H When V IN When it is less than the low threshold level VL, comparator C1 outputs a high level. When one of the two comparators outputs a high level, A is a high level.

[0035] In the fourth timing processing module, when the comparator output A signal jumps to a high level, Counter 1 starts counting. If signal A returns to a low level before the set alarm delay time is reached, Counter 1 is reset, and the output of Counter 1 remains at a low level. The subsequent circuits and Counter 2 do not work, and OCD remains at a low level without an alarm. If Counter 1 counts to the set alarm delay time and A remains at a high level at this time, a rising edge is generated at the CP end of DFF1, and Y jumps to a high level. Since OUTPUT of Counter 2 remains at a low level at this time, EN is at a high level, so DFF2 is not in a reset state. DFF2 captures the rising edge of the Y signal from low to high, OCD jumps to a high level, and an alarm starts.

[0036] When A returns to normal, the OCD alarm signal needs to be delayed to the specified time. When A jumps from high level to low level, DFF3 captures the falling edge of the A signal, and the output jumps from low level to high level. Counter 2 starts counting. When the count reaches the set alarm duration, OUTPUT ofCounter 2 output jumps to high level. At this time, EN jumps to low level to reset DFF2, the OCD alarm ends and all D flip-flops are reset.

[0037] In the present invention, when the measured current is within the measurement amplitude, the Hall sensor chip outputs normally; when the measured current exceeds the measurement threshold, the overcurrent detection current enters the warning state. If the detection current exceeds the measurement threshold for more than 2μs, the OCD pin outputs a high level and enters the alarm state; when the measured current returns to within the threshold, the OCD pin continues to output a high level for 1ms. If the measured current exceeds the threshold again at this time, the timing starts again.

Claims

1. An overcurrent detection circuit for a Hall current sensor, characterized in that: The amplified sensor signal V IN Linearly related to the input current, by comparing V IN If the sensing signal is between the two thresholds VH and VL, the output is low level, indicating that the current does not exceed the detection range, and the circuit does not alarm; if the sensing signal V IN When the current is higher than VH or lower than VL, the output jumps to a high level, indicating that the current exceeds the detection range and the circuit alarms. However, since there may be glitches near the detection threshold of the measured current, it may cause the overcurrent detection module to falsely alarm. Therefore, it is necessary to wait for a period of time after the measured current exceeds the threshold before the OCD jumps to a high level.

2. The overcurrent detection circuit for a Hall current sensor according to claim 1, characterized in that: It includes: The first bandgap reference module consists of two parts: the core circuit and the startup circuit. The core circuit of the bandgap reference uses the negative temperature characteristic of the transistor base-emitter voltage VBE and the positive temperature characteristic of the difference ΔVBE of the base-emitter voltage of the transistor working at different current densities to output a zero temperature coefficient voltage V REF . It includes a first BJT (bipolar transistor, Q1) and a first resistor for generating a first current proportional to the absolute temperature, a second BJT (bipolar transistor, Q2) for generating a second current inversely proportional to the absolute temperature, and a third BJT (bipolar transistor, Q3) and a second resistor for outputting a third current independent of the absolute temperature, wherein the emitter junction area of ​​the second BJT is n times the emitter junction area of ​​the second BJT, and the emitter junction area of ​​the second BJT is n times the emitter junction area of ​​the third BJT; it further includes an operational amplifier circuit, the first resistor is connected to the first input terminal of the operational amplifier, the collector of the second BJT is connected to the second input terminal of the operational amplifier, MOSFET2 and the ninth MOSFET3 constitute the first current mirror as the load of the operational amplifier; MOSFET2 and MOSFET4 constitute the second current mirror, outputting a current IPATA positively correlated with the temperature, flowing through the resistor three, and outputting a voltage V independent of the temperature. REF The startup function module includes a first startup MOSFET, a fifth, a sixth, a seventh, an eighth, a ninth, a tenth, an eleventh, and a twelfth startup MOSFET, wherein the gates of the fifth, sixth, and seventh startup MOSFETs are connected to VSS, the electrodes are connected to the power supply VDD, and the drains are connected to the drain of the ninth startup MOSFET and the gate of the twelfth startup MOSFET; The gate and drain of the eighth startup MOSFET are connected to each other, and are connected to the drain of the twelfth startup MOSFET, and the source thereof is connected to the second, third, and fourth MOSFETs of the bias tubes of the reference core functional module, generating I PTAT The tenth startup MOSFET and the eleventh startup MOSFET form a current mirror structure, the gate and drain of the tenth startup MOSFET are connected to the drain of the first startup MOSFET, the drain of the eleventh startup MOSFET is connected to the source of the ninth startup MOSFET, and the gate of the ninth startup MOSFET is connected to the core reference output voltage VREF. The second threshold level generating module is used to generate two threshold voltages VH and VL. REF The bandgap reference module is connected to the in-phase input terminal of the operational amplifier A2, and the first resistor R1, the second resistor R2, and the third resistor R3 are connected in series. The connection between the second resistor R2 and the third resistor R3 is connected to the inverting input terminal of the operational amplifier, and the other end of the third resistor R3 is connected to the output of the operational amplifier to output the threshold voltage VH; the first resistor R1 and the second resistor R2 are connected to output a voltage of VL. The third comparator module includes a first comparator C1, whose non-inverting input terminal is connected to VL and whose inverting input terminal is connected to V IN The second comparator C2 has its non-inverting input connected to V IN , the inverting input terminal is connected to VH; the outputs of the first comparator C1 and the second comparator C2 pass through the OR gate, output voltage A, and are connected to the timing processing module circuit. In the fourth timing processing module, the comparator output voltage A is input into the third D flip-flop DFF3 after passing through the first inverter, and the output Q is used as the reset signal of the counter Counter 2; the comparator output voltage A is also used as the reset signal of the counter Counter 1; the comparator output voltage A and the output of Counter 1 are used as the clock signal of the first D flip-flop DFF1 through the AND gate; the output of the counter Counter 2 is output as the enable signal EN through the second inverter, which is the reset signal of the second D flip-flop DFF2. Counters Counter 1 and Counter 2 are both composed of D flip-flops connected in series. CP is the clock signal, which comes from the oscillator circuit.

3. The output overcurrent detection circuit for a Hall current sensor as claimed in claim 2, characterized in that: In the first bandgap reference (Bandgap) module, the emitter junction area of ​​the second BJT is n times the emitter junction area of ​​the first BJT, the second, third and fourth MOSFETs have the same width-to-length ratio, and a bandgap voltage reference with a zero temperature coefficient can be obtained by selecting appropriate first, second and third resistors. The PSRR can be improved by increasing the transconductance of the op amp input pair tube and the width of the current mirror tube.

4. The output overcurrent detection circuit for a Hall current sensor according to claim 2, characterized in that: The fourth timing processing module, the timing processing circuit is composed of a trigger D, so that the OCD jumps to a high level after a period of time after the measured current exceeds the threshold, thereby avoiding false alarms.

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