Testing Method, Testing Device and Testing System for Wafer-Level Ultrasonic Chips

Abstract

This application is applicable to the field of semiconductor integrated circuit testing technology, and provides a testing method, a testing device and a testing system for wafer-level ultrasonic chips. The method includes measuring the first echo peak-to-peak value of the chip under test when there is no detachable baffle at a preset distance from the tip plane of the probe on the probe card. The first echo peak-to-peak value is the echo peak-to-peak value of the chip under test to the air. The probe is connected to the chip under test, and the probe card is connected to the tester through a cable; when there is a detachable baffle at a preset distance from the tip plane of the probe on the probe card, measuring the second echo peak-to-peak value of the chip under test at the detachable baffle; according to the second echo peak-to-peak value, the first echo peak-to-peak value, and the preset peak-to-peak value design parameters, determining the echo peak-to-peak value test result of the chip under test, and the echo peak-to-peak value test result is used to indicate the ranging ability of the chip under test. The technical solution provided by this application improves the accuracy of wafer-level ultrasonic chip testing.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor integrated circuit testing, and particularly to a testing method, a testing device, and a testing system for wafer-level ultrasonic chips. Background Art

[0002] An ultrasonic ranging chip is a chip designed based on the principle of ultrasonic time of flight (ToF). With the rapid development and application of robots, smart homes, portable devices, etc., micro ranging technology has become increasingly important. Compared with traditional ranging technologies such as radar ranging, laser ranging, and infrared ranging, ultrasonic ranging has the advantages of being unaffected by the transparency and color of the target object, being insensitive to environmental noise, and having low power consumption, and has been widely used.

[0003] When testing a wafer-level ultrasonic chip, since many chips are densely distributed and connected to each other on the same wafer, when the chip under test emits ultrasonic waves, due to the physical connection between other chips on the same wafer and the chip under test, other ultrasonic chips will also resonate, resulting in background noise and affecting the test results; on the other hand, the chip under test itself has a certain background noise to the air, which will also affect the test results, resulting in low test accuracy.

[0004] Therefore, how to improve the test accuracy of wafer-level ultrasonic chips has become an urgent problem to be solved. Summary of the Invention

[0005] Embodiments of this application provide a testing method, a testing device, and a testing system for wafer-level ultrasonic chips, aiming to solve the problem of low test accuracy of wafer-level ultrasonic chips.

[0006] In a first aspect, embodiments of this application provide a testing method for a wafer-level ultrasonic chip. The method includes: measuring a first echo peak-to-peak value of the chip under test, where the first echo peak-to-peak value is the echo peak-to-peak value of the chip under test to the air, when there is no detachable baffle set at a preset distance from the tip plane of the probe on the probe card, the probe is connected to the chip under test, and the probe card is connected to a tester through a cable; measuring a second echo peak-to-peak value of the chip under test at the detachable baffle when there is a detachable baffle set at a preset distance from the tip plane of the probe on the probe card; determining a test result of the echo peak-to-peak value of the chip under test according to the second echo peak-to-peak value, the first echo peak-to-peak value, and a preset peak-to-peak value design parameter, where the test result of the echo peak-to-peak value is used to indicate the ranging ability of the chip under test.

[0007] In a possible implementation, determining the echo peak-to-peak test result of the chip under test according to the second echo peak-to-peak value, the first echo peak-to-peak value, and a preset peak-to-peak design parameter includes: subtracting the first echo peak-to-peak value from the second echo peak-to-peak value to obtain a target echo peak-to-peak value; and determining the echo peak-to-peak test result of the chip under test based on the target echo peak-to-peak value and the preset peak-to-peak design parameter.

[0008] In a possible implementation, when there is no detachable baffle provided at a preset distance from the tip plane of the probe on the probe card, measuring the first echo peak-to-peak value of the chip under test includes: sending a sine wave with a preset frequency to the chip under test to determine the first main frequency of the chip under test; determining the single-cycle time of the first waveform based on the first main frequency of the chip under test; performing frequency acquisition of the echo of the chip under test for a first preset number of times based on the single-cycle time of the first waveform to obtain a plurality of first frequency measurement values corresponding to the first preset number of times; screening out a first target frequency measurement value set from the plurality of first frequency measurement values, where the first target frequency measurement value set includes the first frequency measurement values corresponding to the echo at the preset distance among the plurality of first frequency measurement values; determining a first wave peak value and a first wave trough value based on the first target frequency measurement value set; and determining the first echo peak-to-peak value based on the first wave peak value and the first wave trough value.

[0009] In a possible implementation, when there is a detachable baffle provided at a preset distance from the tip plane of the probe on the probe card, measuring the second echo peak-to-peak value of the chip under test at the detachable baffle includes: sending a sine wave with a preset frequency to the chip under test to determine the second main frequency of the chip under test; determining the single-cycle time of the second waveform based on the second main frequency of the chip under test; performing frequency acquisition of the echo of the chip under test for a second preset number of times based on the single-cycle time of the second waveform to obtain a plurality of second frequency measurement values corresponding to the second preset number of times; screening out a second target frequency measurement value set from the plurality of second frequency measurement values, where the second target frequency measurement value set includes the second frequency measurement values corresponding to the echo at the detachable baffle among the plurality of second frequency measurement values; determining a second wave peak value and a second wave trough value based on the second target frequency measurement value set; and determining the second echo peak-to-peak value based on the second wave peak value and the second wave trough value.

[0010] In a possible implementation, before measuring the first echo peak-to-peak value of the chip under test, the method further includes: performing a DC characteristic parameter test on the chip under test, where the DC characteristic parameter test includes an open / short test and a static current test; when the DC characteristic parameter test of the chip under test passes, performing the operation of measuring the first echo peak-to-peak value or the second echo peak-to-peak value of the chip under test.

[0011] In a possible implementation, performing the DC characteristic parameter test on the chip under test includes: when the voltages of other pins except the pins under test in the chip under test are at a first voltage value, using a pin precise measurement unit to provide a preset-intensity current for the pins under test, where the pins under test are the pins in the chip under test connected to the probes; using the pin precise measurement unit to measure the target voltage value of the pins under test; based on the target voltage value, determining the open / short test result of the chip under test, where the open / short test result is used to indicate the connectivity of the pins under test.

[0012] In a possible implementation, performing the DC characteristic parameter test on the chip under test includes: using a pin precise measurement unit to control the chip under test to enter a low-power mode; when the chip under test enters the low-power mode, measuring the target current value flowing into the drain power supply voltage VDD pin; based on the target current value, determining the static current test result of the chip under test, where the static current test result is used to indicate the static power consumption situation of the chip under test.

[0013] In a possible implementation, the preset distance is 6 cm.

[0014] In a second aspect, an embodiment of the present application provides a test device for a wafer-level ultrasonic chip, where the device includes: a measurement module, configured to measure the first echo peak-to-peak value of the chip under test when there is no detachable baffle at a preset distance from the tip plane of the probe on the probe card, where the first echo peak-to-peak value is the echo peak-to-peak value of the chip under test to the air, the probe is connected to the chip under test, and the probe card is connected to a tester through a cable; the measurement module is further configured to measure the second echo peak-to-peak value of the chip under test at the detachable baffle when there is a detachable baffle at a preset distance from the tip plane of the probe on the probe card; a determination module, configured to determine the echo peak-to-peak value test result of the chip under test according to the second echo peak-to-peak value, the first echo peak-to-peak value, and a preset peak-to-peak value design parameter.

[0015] In a third aspect, an embodiment of the present application provides a test system for a wafer-level ultrasonic chip. The system includes a probe card and a tester. The probe card is provided with probes and a detachable baffle disposed at a preset distance from the tip plane of the probes; the tester is configured to execute the method described in the first aspect or any one of its implementation manners.

[0016] In a fourth aspect, an embodiment of the present application provides a tester, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the method described in the first aspect or any one of its implementation manners is implemented.

[0017] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the method described in the first aspect or any one of its implementation manners is implemented.

[0018] In a sixth aspect, an embodiment of the present application provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps of the method described in the first aspect or any one of its implementation manners are implemented.

[0019] The beneficial effects of the embodiments of the present application compared with the prior art are as follows: When there is no detachable baffle disposed at a preset distance from the tip plane of the probes on the probe card, the first echo peak-to-peak value of the chip under test is measured. The first echo peak-to-peak value is the peak-to-peak value of the echo to the air of the chip under test. The probes are connected to the chip under test, and the probe card is connected to the tester through a cable; when there is a detachable baffle disposed at a preset distance from the tip plane of the probes on the probe card, the second echo peak-to-peak value of the chip under test at the detachable baffle is measured; according to the second echo peak-to-peak value, the first echo peak-to-peak value, and the preset peak-to-peak value design parameter, the echo peak-to-peak value test result of the chip under test is determined. Since the influence of the peak-to-peak value of the echo to the air of the chip under test is considered when measuring the echo peak-to-peak value of the chip under test, that is, the influence of the background noise generated by chip resonance and the background noise to the air of the chip itself is considered, rather than only measuring the echo peak-to-peak value of the chip under test at a preset distance to determine the test result, the technical solution provided by the present application can improve the accuracy of wafer-level ultrasonic chip testing.

[0020] It can be understood that a test device, a test system, a tester, a computer-readable storage medium, and a computer program product for a wafer-level ultrasonic chip provided by the embodiments of the present application have the same beneficial effects as the above-mentioned wafer-level ultrasonic chip test method, and will not be elaborated here. Description of the Drawings

[0021] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1 Schematic diagram of the architecture of a test system for a wafer-level ultrasonic chip provided by an embodiment of the present application;

[0023] Figure 2 Physical diagram of a probe card 110 provided by an embodiment of the present application;

[0024] Figure 3 Schematic diagram of the peripheral circuit of a probe card 110 provided by an embodiment of the present application;

[0025] Figure 4 Schematic flow chart of a test method for a wafer-level ultrasonic chip provided by an embodiment of the present application;

[0026] Figure 5 Schematic flow chart of another test method for a wafer-level ultrasonic chip provided by an embodiment of the present application;

[0027] Figure 6 Schematic diagram of an open / short circuit test provided by an embodiment of the present application;

[0028] Figure 7 Schematic diagram of another open / short circuit test provided by an embodiment of the present application;

[0029] Figure 8 Block diagram of the structure of a test device for a wafer-level ultrasonic chip provided by an embodiment of the present application;

[0030] Figure 9 Schematic diagram of the structure of a tester provided by an embodiment of the present application. Detailed implementation manners

[0031] In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present application.

[0032] It should be understood that when used in the specification of this application and the appended claims, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their combinations.

[0033] It should also be understood that the term "and / or" used in the specification of this application and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0034] As used in the specification of this application and the appended claims, the term "if" can be interpreted as "when", "once", "in response to determining", or "in response to detecting" depending on the context. Similarly, the phrases "if determined" or "if [the described condition or event] is detected" can be interpreted as meaning "once determined", "in response to determining", "once [the described condition or event] is detected", or "in response to detecting [the described condition or event]" depending on the context.

[0035] In addition, in the description of the specification of this application and the appended claims, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0036] The reference to "one embodiment" or "some embodiments" etc. described in the specification of this application means that a specific feature, structure or characteristic described in connection with the embodiment is included in one or more embodiments of this application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments" etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0037] An ultrasonic ranging chip refers to a chip designed using the ToF measurement principle. With the rapid development and application of robots, smart homes, and portable devices, micro ranging technology has become increasingly important. Compared with traditional ranging technologies such as radar ranging, laser ranging, and infrared ranging, ultrasonic ranging has the advantages of being unaffected by the transparency and color of the target object, being insensitive to environmental noise, and having low power consumption.

[0038] At present, there are two technical problems in wafer-level testing of ultrasonic chips: on the one hand, in wafer-level testing, since many chips are densely distributed and connected to each other on the same wafer, when the chip under test emits ultrasonic waves, due to the physical connection between other chips on the same wafer and the chip under test, other ultrasonic chips will also resonate, resulting in background noise, which affects the test results; on the other hand, the chip under test itself will have a certain background noise to the air, which will also affect the test results. In addition, the probe card for wafer-level testing of ultrasonic chips also has differences in structure from the probe card for conventional chip testing, and a reflection baffle needs to be designed and manufactured additionally.

[0039] To solve the above technical problems, the present application proposes a method for testing wafer-level ultrasonic chips. When there is no detachable baffle set at a preset distance from the tip plane of the probe on the probe card, the first echo peak-to-peak value of the chip under test is measured. The first echo peak-to-peak value is the echo peak-to-peak value of the chip under test to the air. The probe is connected to the chip under test, and the probe card is connected to the tester through a cable; when there is a detachable baffle set at a preset distance from the tip plane of the probe on the probe card, the second echo peak-to-peak value of the chip under test at the detachable baffle is measured; according to the second echo peak-to-peak value, the first echo peak-to-peak value, and the preset peak-to-peak value design parameters, the echo peak-to-peak value test result of the chip under test is determined. The echo peak-to-peak value test result is used to indicate the ranging ability of the chip under test, improving the accuracy of wafer-level ultrasonic chip testing.

[0040] For ease of understanding, the technical solution of the present application will be introduced in detail below in conjunction with the accompanying drawings.

[0041] Figure 1 The following is a schematic diagram of the architecture of a testing system for wafer-level ultrasonic chips provided by an embodiment of the present application. As Figure 1 shown, the wafer-level ultrasonic chip testing system 100 includes a probe card 110 and a tester 120. The probe card 110 is provided with a probe 111 and a detachable baffle 112 set at a preset distance from the tip plane of the probe 111.

[0042] Specifically, the probe card 110 is a medium for connecting the chip under test and the tester 120. The peripheral circuit required for testing the chip under test is designed on it. The probe 111 contacts the pin pads (pads) on the chip under test and is connected to the tester 120 using a cable.

[0043] As an example, the physical diagram of the probe card 110 can be seen in Figure 2 , and the schematic diagram of the peripheral circuit of the probe card 110 can be seen in Figure 3 .

[0044] Specifically, the tester 120 is used to test the direct current (DC) parameters and the echo peak-to-peak value of the chip under test. Among them, the DC parameter test includes open-short (OS) test and static current test.

[0045] As an example, the tester 120 selects the Chroma 3380P tester. The Chroma 3380P tester is a digital-analog hybrid tester, including boards such as multiplex bus (MXBUS), multiplex logic pin control (MXLPC), multiplex AWI2 (MXAWI2), and multiplex pulse generator 3 (MXPG3). Usually, the MXBUS board is used to provide signals for controlling relays; the perpin precision measurement unit (PPMU) and precision measurement unit (PMU) resources on the MXLPC board can perform operations such as current addition and voltage measurement, and pressure addition and current measurement. The main differences between the PPMU and the PMU are the test accuracy and range; the time measurement unit (TMU) tests frequencies and time-related parameters; the MXA WI2 board provides a waveform generator (WG) mode and a waveform digitizer (WD) mode. In the WG mode, the tester can send a sine wave with a preset frequency. In the WD mode, the tester can sample the echo of the sine wave. For example, the fastest send and sample rate is 50 nanoseconds (ns).

[0046] Exemplarily, the tester 120 uses the PPMU on the MXLPC board to test the DC parameters of the chip under test, and uses the WG mode and WD mode on the MXA WI2 board to test the echo peak-to-peak value of the chip under test.

[0047] In a possible implementation, the wafer-level ultrasonic chip test system 100 further includes a probe station, which is used to place the wafer on which the chip under test is located and accurately move the wafer so that the chip under test contacts the probe 111.

[0048] It can be understood that Figure 1The system architecture shown is only an example of the wafer-level ultrasonic chip testing system provided by this application. In some other embodiments of this application, the wafer-level ultrasonic chip testing system 100 may include more or fewer components than shown, or combine certain components, or split certain components, or have different component arrangements. The components shown can be implemented in hardware, software, or a combination of software and hardware, and this application does not limit this.

[0049] Figure 4 FIG. 4 is a schematic flowchart of a testing method for a wafer-level ultrasonic chip provided by an embodiment of this application. For ease of description, only the parts related to this embodiment are shown. The method provided by this embodiment is applied to Figure 1 the wafer-level ultrasonic chip testing system 100 shown, and is executed by the tester 120. The method provided by this embodiment includes the following steps:

[0050] S410, when there is no detachable baffle set at a preset distance from the tip plane of the probe on the probe card, measure the first echo peak-to-peak value of the chip under test. The first echo peak-to-peak value is the echo peak-to-peak value of the chip under test to the air. The probe is connected to the chip under test, and the probe card is connected to the tester through a cable.

[0051] Specifically, wafer testing is between wafer manufacturing and packaging in the entire chip manufacturing process, and tests each chip on the entire wafer. The chip under test is an ultrasonic chip connected to the probe among multiple chips on the wafer.

[0052] In a specific implementation, when there is no detachable baffle set at a preset distance from the tip plane of the probe on the probe card, use the WG mode and WD mode in the MXAWI2 board to measure the first echo peak-to-peak value of the chip under test. Since there is no detachable baffle at the preset position on the probe card at this time, the measured first echo peak-to-peak value is the echo peak-to-peak value of the chip under test to the air. The echo peak-to-peak value to the air indicates the background noise generated by the resonance of other chips on the same wafer with the chip under test, and the background noise to the air existing in the chip under test itself.

[0053] Preferably, the preset distance is 6 centimeters (cm).

[0054] S420, when there is a detachable baffle set at a preset distance from the tip plane of the probe on the probe card, measure the second echo peak-to-peak value of the chip under test at the detachable baffle.

[0055] In a specific implementation, when there is a detachable baffle set at a preset distance from the tip plane of the probe on the probe card, use the WG mode and WD mode in the MXAWI2 board to measure the second echo peak-to-peak value of the chip under test at the detachable baffle, that is, the echo peak-to-peak value of the chip under test at the preset position.

[0056] It should be noted that the execution order of S210 and S220 in this application is not limited. That is, the first echo peak value of the chip under test can be measured first, and then the second echo peak value of the chip under test can be measured; alternatively, the second echo peak value of the chip under test can be measured first, and then the first echo peak value of the chip under test can be measured.

[0057] S430. According to the second echo peak value and the first echo peak value, as well as the preset peak value design parameters, determine the echo peak value test result of the chip under test, and the echo peak value test result is used to indicate the ranging ability of the chip under test.

[0058] Specifically, different types of chips under test correspond to different preset peak value design parameters. The preset peak value design parameters include the preset range of the echo peak value, and the echo peak value test result includes pass and fail.

[0059] In a specific implementation, first determine the preset peak value design parameters corresponding to the chip under test, and then compare the measured second echo peak value and the first echo peak value of the chip under test with the preset peak value design parameters corresponding to the chip under test to determine the echo peak value test result of the chip under test.

[0060] In the technical solution provided in this embodiment, when there is no detachable baffle set at a preset distance from the tip plane of the probe on the probe card, measure the first echo peak value of the chip under test. The first echo peak value is the echo peak value of the chip under test to the air. The probe is connected to the chip under test, and the probe card is connected to the tester through a cable; when there is a detachable baffle set at a preset distance from the tip plane of the probe on the probe card, measure the second echo peak value of the chip under test at the detachable baffle; according to the second echo peak value and the first echo peak value, as well as the preset peak value design parameters, determine the echo peak value test result of the chip under test. Since the influence of the echo peak value of the chip under test to the air is considered when measuring the echo peak value of the chip under test, that is, the influence of the background noise generated by the chip resonance and the background noise of the chip itself to the air is considered, rather than only measuring the echo peak value of the chip under test at a preset distance to determine the test result, the technical solution provided in this application can improve the accuracy of wafer-level ultrasonic chip testing.

[0061] On the basis of the above embodiment, this embodiment further explains and optimizes the technical solution. Specifically, in this embodiment, determining the echo peak value test result of the chip under test according to the second echo peak value and the first echo peak value, as well as the preset peak value design parameters, includes:

[0062] Subtract the second echo peak value from the first echo peak value to obtain the target echo peak value;

[0063] Determine the test result of the echo peak-to-peak value of the chip under test based on the target echo peak-to-peak value and the preset peak-to-peak value design parameter.

[0064] In a specific implementation, subtract the second echo peak-to-peak value from the first echo peak-to-peak value to obtain the target echo peak-to-peak value. The target echo peak-to-peak value is the echo peak-to-peak value corresponding to the preset position after eliminating the resonance background noise of other chips on the same wafer and the background noise to the air existing in the chip under test itself; then compare the target echo peak-to-peak value with the preset peak-to-peak value design parameter corresponding to the chip under test to determine the test result of the echo peak-to-peak value of the chip under test.

[0065] As an example, if the preset peak-to-peak value design parameter corresponding to the chip under test is the preset range of the echo peak-to-peak value, then when the target echo peak-to-peak value is within the preset range of the echo peak-to-peak value, determine that the test result of the echo peak-to-peak value of the chip under test is passed, and when the target echo peak-to-peak value is not within the preset range of the echo peak-to-peak value, determine that the test result of the echo peak-to-peak value of the chip under test is failed.

[0066] The technical solution provided in this embodiment subtracts the second echo peak-to-peak value of the chip under test from the first echo peak-to-peak value to obtain the target echo peak-to-peak value that eliminates the resonance background noise of other chips on the same wafer and the background noise to the air existing in the chip under test itself, and then determines the test result of the echo peak-to-peak value of the chip under test based on the comparison between the target echo peak-to-peak value and the preset peak-to-peak value design parameter, improving the accuracy of the echo peak-to-peak value test.

[0067] Based on the above embodiment, this embodiment further explains and optimizes the technical solution. Specifically, in this embodiment, when there is no detachable baffle at a preset distance from the tip plane of the probe on the probe card, measuring the first echo peak-to-peak value of the chip under test includes:

[0068] Send a sine wave with a preset frequency to the chip under test to determine the first main frequency of the chip under test;

[0069] Based on the first main frequency of the chip under test, determine the time of a single cycle of the first waveform;

[0070] Based on the time of a single cycle of the first waveform, perform frequency acquisition on the echo of the chip under test for the first preset number of acquisitions to obtain a plurality of first frequency measurement values corresponding to the first preset number of acquisitions;

[0071] Select a set of first target frequency measurement values from the plurality of first frequency measurement values. The set of first target frequency measurement values includes the first frequency measurement values corresponding to the echo at the preset distance among the plurality of first frequency measurement values;

[0072] Based on the set of first target frequency measurement values, determine the first wave peak value and the first wave trough value;

[0073] Based on the first peak value and the first trough value, determine the first echo peak-to-peak value.

[0074] In a specific implementation, the preset frequency is 800 kilohertz (Khz), and the first preset number of acquisitions is 5 times. When there is no detachable baffle set at a preset distance from the tip plane of the probe on the probe card, use the WG mode of the MXAWI2 board card to send a sine wave of 800 Khz to the chip under test, and use the WD mode to measure the frequency of the echo of the sine wave by the chip under test 10 times, obtaining 10 frequency measurement values, and store these 10 frequency measurement values in the FREQ

[10] array. Traverse the FREQ

[10] array, take out the mode among them, store it in the min variable, and confirm the mode of the 10 frequency measurement values as the first main frequency of the chip under test; since the main frequency and the time of a single cycle of the waveform are reciprocal to each other, then based on the first main frequency of the chip under test, the first waveform single-cycle time can be obtained; based on the first waveform single-cycle time, use the WD mode of the MXAWI2 board card to measure the frequency of the echo of the sine wave by the chip under test 5 times. Each measurement in the 5 measurements grabs 9000 times at intervals of 50 ns, obtaining 9000 first frequency measurement values, and a total of 5 groups of 9000 first frequency measurement values are obtained in the 5 measurements; since 6 cm corresponds to the echo in the time range of 370 us to 410 us, the first frequency measurement values of the 7400th to 8200th grabs in each group of 9000 grabs are screened out and stored in the data

[800] array, obtaining 5 data

[800] arrays, that is, the first target frequency measurement value set. Traverse each data

[800] array, take out the maximum value (i.e., the first peak value) and store it in the MAX_VALUE1[5] array, take out the minimum value (i.e., the first trough value) and store it in the MAX_VALUE2[5] array, store the time point corresponding to the first peak value in the MAX_TIME1[5] array, and store the time point corresponding to the first trough value in the MAX_TIME2[5] array. Store the peak-to-peak values in each of the 5 data

[800] arrays in MAX_VALUE[5]. Traverse the MAX_VALUE[5] array, take out the maximum value as the first echo peak-to-peak value, and store it in the MAX_VALUE_final variable. Correspondingly, store the peak corresponding to the first echo peak-to-peak value and the time point when the peak appears in MAX_VALUE3 and MAX_TIME3 respectively, and store the trough corresponding to the first echo peak-to-peak value and the time point when the trough appears in MAX_VALUE4 and MAX_TIME4 respectively.

[0075] In the technical solution provided in this embodiment, when measuring the first main frequency of the chip under test, since the measured waveform is unstable, the method of measuring the frequency of the echo of the chip under test to the sine wave 10 times and taking the mode is used to determine the first main frequency of the chip under test, which improves the accuracy of determining the first main frequency of the chip under test; when measuring the first peak-to-peak value of the echo of the chip under test, since the echo of the chip under test in the empty state is relatively stable, the frequency of the echo of the chip under test to the sine wave is only measured 5 times, which improves the efficiency of determining the first peak-to-peak value of the echo of the chip under test.

[0076] On the basis of the above embodiment, this embodiment further explains and optimizes the technical solution. Specifically, in this embodiment, when a detachable baffle is provided on the probe card at a preset distance from the tip plane of the probe, measuring the second peak-to-peak value of the echo of the chip under test at the detachable baffle includes:

[0077] Sending a sine wave with a preset frequency to the chip under test to determine the second main frequency of the chip under test;

[0078] Based on the second main frequency of the chip under test, determining the time of a single cycle of the second waveform;

[0079] Based on the time of a single cycle of the second waveform, performing frequency acquisition on the echo of the chip under test for a second preset number of acquisitions to obtain a plurality of second frequency measurement values corresponding to the second preset number of acquisitions;

[0080] Selecting a second target frequency measurement value set from the plurality of second frequency measurement values, where the second target frequency measurement value set includes the second frequency measurement values corresponding to the echoes at the detachable baffle among the plurality of second frequency measurement values;

[0081] Based on the second target frequency measurement value set, determining the second peak value and the second trough value;

[0082] Based on the second peak value and the second trough value, determining the second peak-to-peak value of the echo.

[0083] In a specific implementation, the preset frequency is 800 Khz, and the second preset number of acquisitions is 50 times. When a detachable baffle is set on the probe card at a preset distance from the tip plane of the probe, a sine wave of 800 Khz is sent to the chip under test using the WG mode of the MXAWI2 board card, and the WD mode is used to measure the frequency of the echo of the sine wave by the chip under test 10 times, obtaining 10 frequency measurement values. These 10 frequency measurement values are stored in the FREQ

[10] array. Traverse the FREQ

[10] array, extract the mode among them, and store it in the min variable. The mode among the 10 frequency measurement values is confirmed as the second main frequency of the chip under test. Since the main frequency and the time of a single cycle of the waveform are reciprocals of each other, based on the second main frequency of the chip under test, the time of the second single cycle of the waveform can be obtained. Based on the time of the second single cycle of the waveform, the WD mode of the MXAWI2 board card is used to measure the frequency of the echo of the sine wave by the chip under test 50 times. Each measurement in the 50 measurements grabs 9000 times at an interval of 50 ns, obtaining 9000 second frequency measurement values. A total of 50 groups of 9000 second frequency measurement values are obtained in the 50 measurements. Since the detachable baffle at a distance of 6 cm corresponds to the echo within the time range of 370 us to 410 us, the second frequency measurement values of the 7400th to 8200th grabs in each group of 9000 grabs are stored in the data_6cm

[800] array, obtaining a total of 50 data_6cm

[800] arrays, that is, the second target frequency measurement value set. Traverse each data_6cm

[800] array in the 50 data_6cm

[800] arrays, extract the maximum value (i.e., the second peak value) and store it in the MAX_VALUE1_6cm

[50] array, extract the minimum value (i.e., the second trough value) and store it in the MAX_VALUE2_6cm

[50] array, store the time point corresponding to the peak in the MAX_TIME1_6cm

[50] array, and store the time point corresponding to the trough in the MAX_TIME2_6cm

[50] array. The peak-to-peak values of each data_6cm

[800] array in the 50 data_6cm

[800] arrays are stored in MAX_VALUE_6cm

[50] . Traverse the MAX_VALUE

[50] _6cm array, extract the maximum value as the second echo peak-to-peak value of the chip under test, and store it in the MAX_VALUE_final_6cm variable. Correspondingly, store the peak corresponding to the second echo peak-to-peak value and the time point when the peak appears in MAX_VALUE3_6cm and MAX_TIME3_6cm respectively, and store the trough corresponding to the second echo peak-to-peak value and the time point when the trough appears in MAX_VALUE4_6cm and MAX_TIME_6cm4 respectively.

[0084] In the technical solution provided in this embodiment, when measuring the second echo peak-to-peak value of the chip under test, since the echo of the chip under test at the 6-cm detachable baffle is relatively unstable, the frequency of the echo of the chip under test to the sine wave is measured 50 times, which improves the accuracy of determining the second echo peak-to-peak value of the chip under test.

[0085] Figure 5 FIG. is a schematic flowchart of another method for testing a wafer-level ultrasonic chip provided in an embodiment of the present application. In combination with Figure 5 As shown, before measuring the first echo peak-to-peak value of the chip under test, the method further includes:

[0086] Performing DC characteristic parameter testing on the chip under test, where the DC characteristic parameter testing includes open / short circuit testing and static current testing;

[0087] When the DC characteristic parameter testing of the chip under test passes, perform the operation of measuring the first echo peak-to-peak value or the second echo peak-to-peak value of the chip under test.

[0088] In a specific implementation, first use a PPMU to perform DC parameter testing such as open / short circuit testing and static current testing on the chip under test. If the DC parameter testing of the chip under test fails, stop the testing; after the DC parameter testing of the chip under test passes, then perform echo peak-to-peak value testing, that is, perform the operation of measuring the first echo peak-to-peak value or the second echo peak-to-peak value of the chip under test. If the echo peak-to-peak value testing of the chip under test passes, the chip under test is qualified; if the echo peak-to-peak value testing of the chip under test fails, the chip under test is unqualified.

[0089] The technical solution provided in this embodiment first performs DC parameter testing on the chip under test and then performs echo peak-to-peak value testing after the DC parameter testing passes, which can detect defective chips as early as possible and terminate the testing in time, shortening the testing time and improving the efficiency of chip testing.

[0090] Based on the above embodiment, this embodiment further explains and optimizes the technical solution. Specifically, in this embodiment, performing DC characteristic parameter testing on the chip under test includes:

[0091] When the voltages of other pins except the pin under test in the chip under test are at a first voltage value, use a pin precise measurement unit to provide a preset intensity of current for the pin under test, where the pin under test is the pin in the chip under test that is connected to the probe;

[0092] Use the pin precise measurement unit to measure the target voltage value of the pin under test;

[0093] Based on the target voltage value, determine the open / short circuit test result of the chip under test, where the open / short circuit test result is used to indicate the connectivity of the pin under test.

[0094] Specifically, the OS test is used to confirm that all signal pins are electrically connected to the corresponding channels of the test system during the test of the chip under test, and no signal pin is short-circuited to other signal pins, power supply or ground. The OS test performs an open-short circuit check on the input / output (IO) pins of the chip under test without powering on the chip under test.

[0095] In a possible implementation, the first voltage value is 0 volts (V), the preset intensity is -100 microamperes (uA), and the connectivity between the pin under test and ground or other pins is tested.

[0096] In a specific implementation, as Figure 6 shown, use the PPMU to set the voltages of other pins in the chip under test except the pin under test to 0V; provide a current of -100 uA for the pin under test; measure the target voltage value on the pin under test; when the target voltage value is about -0.7V or within the range of (-1.5V, -0.2V), it is determined that the pin under test is in good contact with the tester and the probe card, and the pin under test itself has no open circuit or short circuit to the power supply pin, ground pin or other IO pin; if the target voltage value is a large negative voltage, such as less than -1.5V, it indicates that the pin under test has an open circuit fault to ground; if the target voltage value is close to 0V or greater than -0.2V, it indicates that the pin under test has a short circuit to the power supply pin, ground pin or other IO pins.

[0097] In another possible implementation, the first voltage value is 0V, the preset intensity is +100 uA, and the connectivity between the chip under test and the VDD pin or other pins is tested.

[0098] In a specific implementation, as Figure 7 shown, use the PPMU to set the voltages of other pins in the chip under test except the pin under test to 0V; provide a current of +100 uA for the pin under test; measure the target voltage value on the pin under test; when the target voltage value is about 0.7V or within the range of (0.2V, 1.5V), it is determined that the pin under test is in good contact with the tester and the probe card, and the pin under test itself has no open circuit or short circuit to the power supply pin, ground pin or other IO pin; if the target voltage value is a large positive voltage, such as greater than 1.5V, it indicates that the pin under test has an open circuit fault to the corresponding power supply pin; if the target voltage value is close to 0V or less than 0.2V, it indicates that the pin under test has a short circuit to the power supply pin, ground pin or other IO pins.

[0099] The technical solution provided in this embodiment uses a pin precision measurement unit to complete the open - short test in the DC parameter test, tests the connectivity of the pins to be measured, and improves the accuracy of chip detection.

[0100] Based on the above - mentioned embodiment, this embodiment further explains and optimizes the technical solution. Specifically, in this embodiment, when performing DC characteristic parameter tests on the chip to be measured, it includes:

[0101] Using the pin precision measurement unit to control the chip to be measured to enter the low - power mode;

[0102] When the chip to be measured enters the low - power mode, measure the target current value flowing into the drain power supply voltage VDD pin;

[0103] Based on the target current value, determine the static current test result of the chip to be measured, and the static current test result is used to indicate the static power consumption situation of the chip to be measured.

[0104] Specifically, in the static current test, the chip to be measured is usually preset to a specific state, such as the low - power mode or the sleep mode, then the current flowing into the VDD pin is measured, and the measured value is compared with the preset parameters to determine whether the chip to be measured is normal.

[0105] In a specific implementation, use the PPMU to provide 3.3V voltage for the VDD pin of the chip to be measured to make the chip to be measured enter the low - power mode; measure the target current value flowing into the VDD pin; the preset range of the static current is set to (-0.5uA, 10uA). When the target current value is within the preset range of the static current, the static current test result of the chip to be measured is passed; when the target current value is not within the preset range of the static current, the static current test result of the chip to be measured is failed.

[0106] The technical solution provided in this embodiment uses the PPMU to complete the static current test in the DC parameter test, tests the static power consumption situation of the chip to be measured, and improves the accuracy of chip detection.

[0107] Figure 8 The following is a structural block diagram of a test device for a wafer - level ultrasonic chip provided in an embodiment of the present application. For the sake of convenience of description, only the parts related to the embodiments of the present application are shown. Refer to Figure 8 , the wafer - level ultrasonic chip test device 800 may include a measurement module 801 and a determination module 802.

[0108] The measurement module 801 is used to measure the first echo peak - to - peak value of the chip to be measured when there is no detachable baffle set at a preset distance from the tip plane of the probe on the probe card. The first echo peak - to - peak value is the peak - to - peak value of the echo to the air of the chip to be measured. The probe is connected to the chip to be measured, and the probe card is connected to the tester through a cable.

[0109] The measurement module 801 is further configured to measure the second echo peak-to-peak value at the detachable baffle when a detachable baffle is provided on the probe card at a preset distance from the tip plane of the probe;

[0110] The determination module 802 is configured to determine the echo peak-to-peak value test result of the chip under test according to the second echo peak-to-peak value, the first echo peak-to-peak value, and the preset peak-to-peak value design parameter.

[0111] The wafer-level ultrasonic chip testing device provided by the embodiment of the present application has the same beneficial effects as the above-mentioned testing method for a wafer-level ultrasonic chip.

[0112] In one embodiment, the determination module 802 includes:

[0113] The first determination sub-module is configured to subtract the second echo peak-to-peak value from the first echo peak-to-peak value to obtain the target echo peak-to-peak value;

[0114] The second determination sub-module is configured to determine the echo peak-to-peak value test result of the chip under test based on the target echo peak-to-peak value and the preset peak-to-peak value design parameter.

[0115] In one embodiment, the measurement module 801 includes:

[0116] The first main frequency determination sub-module is configured to send a sine wave with a preset frequency to the chip under test to determine the first main frequency of the chip under test;

[0117] The first waveform single-cycle time determination sub-module is configured to determine the first waveform single-cycle time based on the first main frequency of the chip under test;

[0118] The first frequency acquisition sub-module is configured to perform frequency acquisition on the echo of the chip under test for a first preset number of times based on the first waveform single-cycle time, and obtain a plurality of first frequency measurement values corresponding to the first preset number of times;

[0119] The first data screening sub-module is configured to screen out a first target frequency measurement value set from the plurality of first frequency measurement values, and the first target frequency measurement value set includes the first frequency measurement values corresponding to the echoes at a preset distance among the plurality of first frequency measurement values;

[0120] The first peak value determination sub-module is configured to determine the first peak value and the first valley value based on the first target frequency measurement value set;

[0121] The first echo peak-to-peak value determination sub-module is configured to determine the first echo peak-to-peak value based on the first peak value and the first valley value.

[0122] In one embodiment, the measurement module 801 includes:

[0123] A second main frequency determination sub-module, configured to send a sine wave with a preset frequency to the chip under test to determine the second main frequency of the chip under test;

[0124] A second waveform single-cycle time determination sub-module, configured to determine the second waveform single-cycle time based on the second main frequency of the chip under test;

[0125] A second frequency acquisition sub-module, configured to perform frequency acquisition on the echo of the chip under test for a second preset number of acquisitions based on the second waveform single-cycle time, and obtain a plurality of second frequency measurement values corresponding to the second preset number of acquisitions;

[0126] A second data screening sub-module, configured to screen out a second target frequency measurement value set from the plurality of second frequency measurement values, where the second target frequency measurement value set includes the second frequency measurement values corresponding to the echoes at the detachable baffle among the plurality of second frequency measurement values;

[0127] A second peak value determination sub-module, configured to determine a second wave peak value and a second wave trough value based on the second target frequency measurement value set;

[0128] A second echo peak-to-peak value determination sub-module, configured to determine a second echo peak-to-peak value based on the second wave peak value and the second wave trough value.

[0129] In one embodiment, the wafer-level ultrasonic chip testing device 800 further includes:

[0130] A DC characteristic parameter testing module, configured to perform DC characteristic parameter testing on the chip under test, and the DC characteristic parameter testing includes open / short circuit testing and static current testing.

[0131] In one embodiment, the DC characteristic parameter testing module includes:

[0132] A current providing sub-module, configured to provide a preset-intensity current for the pin under test by using the pin precise measurement unit when the voltages of other pins except the pin under test in the chip under test are at a first voltage value, where the pin under test is the pin of the chip under test connected to the probe;

[0133] A target voltage value measurement sub-module, configured to measure the target voltage value of the pin under test by using the pin precise measurement unit;

[0134] An open / short circuit testing sub-module, configured to determine the open / short circuit testing result of the chip under test based on the target voltage value, and the open / short circuit testing result is used to indicate the connectivity of the pin under test.

[0135] In one embodiment, the DC characteristic parameter testing module includes:

[0136] A control sub-module, configured to use a pin precise measurement unit to control a chip under test to enter a low-power mode;

[0137] A target current value measurement sub-module, configured to measure a target current value flowing into a drain power supply voltage VDD pin when the chip under test enters the low-power mode;

[0138] A static current test sub-module, configured to determine a static current test result of the chip under test based on the target current value, and the static current test result is used to indicate the static power consumption condition of the chip under test.

[0139] It should be noted that for the information interaction, execution process, etc. between the above-mentioned devices / units, since they are based on the same concept as the method embodiment of the present application, for their specific functions and the technical effects brought, reference can be specifically made to the method embodiment part, and details are not described herein again.

[0140] Those skilled in the art can clearly understand that for the convenience and conciseness of description, only the above-mentioned division of each functional unit and module is used as an example for illustration. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in a processing unit, or each unit exists physically alone, or two or more units are integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction and do not limit the protection scope of the present application. The specific working processes of the units and modules in the above system can refer to the corresponding processes in the foregoing method embodiment, and details are not described herein again.

[0141] Figure 9 It is a schematic structural diagram of a tester provided in an embodiment of the present application. As Figure 9 shown, the tester 9 in this embodiment includes: at least one processor 90 ( Figure 9 only one is shown in the figure), a memory 91, and a computer program 92 stored in the memory 91 and executable on at least one processor 90. When the processor 90 executes the computer program 92, it implements the above Figure 4 or Figure 5 steps in the method embodiment, or implements the functions of each module / unit in the above Figure 8 device embodiment.

[0142] As an example, the tester 9 can be the Figure 1 tester 120 in

[0143] The tester 9 may include, but is not limited to, a processor 90 and a memory 91. Those skilled in the art can understand that Figure 9 merely examples of the tester 9, which do not constitute a limitation on the tester 9, may include more or fewer components than shown in the figure, or combine certain components, or different components. For example, it may also include input / output devices, network access devices, etc.

[0144] The processor 90 may be a central processing unit (CPU), and the processor 90 may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0145] In some embodiments, the memory 91 may be an internal storage unit of the tester 9, such as the hard disk or memory of the tester 9. In other embodiments, the memory 91 may also be an external storage device of the tester 9, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the tester 9. Further, the memory 91 may also include both the internal storage unit and the external storage device of the tester 9. The memory 91 is used to store an operating system, application programs, a boot loader, data, and other programs, such as the program code of a computer program. The memory 91 may also be used to temporarily store data that has been output or is to be output.

[0146] The embodiments of the present application also provide a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments can be implemented.

[0147] When an integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above method embodiments of this application, a computer program can be used to instruct relevant hardware to complete. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the tester, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal, and software distribution medium. For example, USB flash drive, mobile hard disk, magnetic disk or optical disc, etc.

[0148] A computer-readable storage medium provided by an embodiment of this application has the same beneficial effects as the above-mentioned method for testing a wafer-level ultrasonic chip.

[0149] An embodiment of this application provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments can be implemented.

[0150] A computer program product provided by an embodiment of this application has the same beneficial effects as the above-mentioned method for testing a wafer-level ultrasonic chip.

[0151] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0152] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0153] In the embodiments provided in the present application, it should be understood that the disclosed device / tester and method can be implemented in other ways. For example, the device / tester embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in electrical, mechanical or other forms.

[0154] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0155] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for testing a wafer-level ultrasonic chip, characterized in that: The method comprises: In the case where no detachable baffle is provided at a preset distance from the needle tip plane of the probe on the probe card, measuring the first echo peak-to-peak value of the chip to be tested, wherein the first echo peak-to-peak value is the peak-to-peak value of the air echo of the chip to be tested, the probe is connected to the chip to be tested, and the probe card is connected to the tester through a flat cable; In a case where a detachable baffle plate which is at a preset distance from the needle tip plane of the probe is provided on the probe card, measuring the peak value of the second echo of the chip to be tested at the detachable baffle plate; Determine an echo peak-to-peak value test result of the chip to be tested according to the second echo peak-to-peak value and the first echo peak-to-peak value, as well as preset peak-to-peak value design parameters, wherein the echo peak-to-peak value test result is used to indicate the ranging capability of the chip to be tested; The step of determining the echo peak-to-peak value test result of the chip to be tested according to the second echo peak-to-peak value and the first echo peak-to-peak value, as well as preset peak-to-peak value design parameters, comprises: Subtracting the peak-to-peak value of the second echo from the peak-to-peak value of the first echo to obtain the peak-to-peak value of the target echo; Based on the target echo peak-to-peak value and the preset peak-to-peak value design parameter, an echo peak-to-peak value test result of the chip to be tested is determined.

2. The method according to claim 1, characterized in that: The method of measuring the peak-to-peak value of the first echo of the chip to be tested when no detachable baffle is provided at a preset distance from the needle tip plane of the probe on the probe card comprises: Sending a sine wave of a preset frequency to the chip under test to determine a first main frequency of the chip under test; Determine a single cycle time of a first waveform based on a first main frequency of the chip to be tested; Based on a single cycle time of the first waveform, frequency acquisition is performed on the echo of the chip to be tested for a first preset acquisition number of times, to obtain a plurality of first frequency measurement values ​​corresponding to the first preset acquisition number of times; Filtering out a first target frequency measurement value set from the plurality of first frequency measurement values, wherein the first target frequency measurement value set includes first frequency measurement values ​​corresponding to the echo at the preset distance among the plurality of first frequency measurement values; determining a first wave peak value and a first wave valley value based on the first target frequency measurement value set; The first echo peak-to-peak value is determined based on the first echo peak value and the first echo trough value.

3. The method according to claim 1, characterized in that In the case where a detachable baffle plate which is at a preset distance from the needle tip plane of the probe is provided on the probe card, measuring the peak value of the second echo of the chip to be tested at the detachable baffle plate comprises: Sending a sine wave of a preset frequency to the chip under test to determine a second main frequency of the chip under test; Determine a single cycle time of a second waveform based on a second main frequency of the chip to be tested; Based on a single cycle time of the second waveform, frequency acquisition is performed on the echo of the chip to be tested for a second preset acquisition number of times, to obtain a plurality of second frequency measurement values ​​corresponding to the second preset acquisition number of times; Filtering out a second target frequency measurement value set from the plurality of second frequency measurement values, the second target frequency measurement value set including second frequency measurement values ​​corresponding to the echo at the detachable baffle among the plurality of second frequency measurement values; determining a second wave peak value and a second wave trough value based on the second target frequency measurement value set; The second echo peak-to-peak value is determined based on the second echo peak value and the second echo trough value.

4. The method according to any one of claims 1 to 3, characterized in that: Before measuring the peak-to-peak value of the first echo of the chip to be tested, the method further includes: Performing a DC characteristic parameter test on the chip to be tested, wherein the DC characteristic parameter test includes an open-short circuit test and a static current test; When the DC characteristic parameter test of the chip under test passes, the operation of measuring the first echo peak-to-peak value or the second echo peak-to-peak value of the chip under test is performed.

5. The method according to claim 4, characterized in that The DC characteristic parameter test of the chip to be tested includes: When the voltage of other pins of the chip under test except the pin under test is a first voltage value, a pin precision measurement unit is used to provide a current of a preset intensity to the pin under test, wherein the pin under test is a pin of the chip under test connected to the probe; Measuring the target voltage value of the pin to be tested by using the pin precision measurement unit; Based on the target voltage value, an open-short circuit test result of the chip to be tested is determined, and the open-short circuit test result is used to indicate the connectivity of the pin to be tested.

6. The method according to claim 4, characterized in that The DC characteristic parameter test of the chip to be tested includes: Using the pin precision measurement unit to control the chip under test to enter a low power consumption mode; When the chip under test enters a low power consumption mode, measuring a target current value flowing into a drain power supply voltage VDD pin; Based on the target current value, a static current test result of the chip under test is determined, and the static current test result is used to indicate the static power consumption of the chip under test.

7. The method according to any one of claims 1 to 3, characterized in that: The preset distance is 6 cm.

8. A wafer-level ultrasonic chip testing device, characterized in that: The device comprises: A measuring module, for measuring a first echo peak-to-peak value of a chip to be tested when no detachable baffle is provided at a preset distance from a needle tip plane of the probe on the probe card, wherein the first echo peak-to-peak value is an air echo peak-to-peak value of the chip to be tested, the probe is connected to the chip to be tested, and the probe card is connected to a tester via a flat cable; The measuring module is further used for measuring the peak value of the second echo of the chip to be tested at the detachable baffle plate when a detachable baffle plate with a preset distance from the needle tip plane of the probe is provided on the probe card; A determination module, used to determine the echo peak-to-peak value test result of the chip to be tested according to the second echo peak-to-peak value and the first echo peak-to-peak value, and preset peak-to-peak value design parameters; The determining module comprises: A first determination submodule is used to subtract the peak-to-peak value of the second echo from the peak-to-peak value of the first echo to obtain the peak-to-peak value of the target echo; The second determination submodule is used to determine the echo peak-to-peak value test result of the chip to be tested based on the target echo peak-to-peak value and the preset peak-to-peak value design parameters.

9. A wafer-level ultrasonic chip testing system, characterized in that: The system comprises a probe card and a tester, wherein the probe card is provided with a probe and a detachable baffle plate arranged at a preset distance from a needle tip plane of the probe; The tester is used to perform the method according to any one of claims 1 to 7.

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