Current limiting circuit, method and chip of LDO (low dropout regulator)
By adding the current limiting circuit to the LDO current limiting circuit and multiplexing the current limiting device of the stable current limiting circuit, the current sampling ratio is improved, and the problem of excessive current in the LDO start-up stage is solved, avoiding damage, and does not affect normal operation during the stable operation stage. Work.
Patent Information
- Application Number
- CN202411363691.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-28
- Publication Date
- 2024-12-10
AI Technical Summary
The current flowing through the power tube during the LDO is too large during startup, and the current limiting circuit cannot respond in time, resulting in possible damage.
Design an LDO current limiting circuit including starting current limiting circuit and stable current limiting circuit. By increasing the current sampling ratio during the startup phase, the actual current limiting value is reduced, so that it is less than or equal to the current limiting value during stable operation, and in a stable manner. The working stage does not affect normal work.
It effectively reduces the actual current limit value in the LDO startup stage to avoid damage, and at the same time, it does not affect the current limit during the stable working stage, achieving low-cost current limit.
Smart Images
Figure CN119105606A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit design, and in particular to a current limiting circuit, method and chip of a low dropout regulator (LDO). Background Art
[0002] In order to prevent excessive current from flowing through the power tube of the LDO and causing damage to the chip, a current limiting circuit is usually designed in the LDO to limit the current flowing through the power tube. However, during the startup of the LDO output voltage, since the current limiting circuit has just been established and requires a certain response time, the current limiting value in the startup phase is usually higher than the preset current limiting value, causing the current flowing through the power tube during the startup process to exceed the preset current limiting value upper limit, which can easily cause damage to the LDO. Summary of the invention
[0003] The present invention provides a current limiting circuit, method and chip of an LDO, which solves the problem that the current flowing through a power tube during the startup of the LDO is too large and the current limiting circuit cannot respond in time.
[0004] In order to achieve the above object, the present invention adopts the following technical scheme: In a first aspect, the present invention provides a current limiting circuit of an LDO, comprising: A power tube connected to the voltage output terminal for providing an output voltage to an external load; A startup current limiting circuit is connected to the power tube and is used to generate a first current greater than zero according to a load current flowing through the power tube when the LDO is started, and is also used to generate a second current when the LDO is working stably, and the second current is equal to zero; A stable current limiting circuit is connected to the starting current limiting circuit and the power tube, and is used to limit the load current to a first current limiting value according to the first current, and is also used to limit the load current to a second current limiting value according to the second current, and the first current limiting value is less than or equal to the second current limiting value.
[0005] In a possible implementation, starting the current limiting circuit includes: starting a sampling circuit and a conversion circuit; A sampling circuit is started, connected to the power tube, and used to generate a first current according to the load current; The conversion circuit is connected to the startup sampling circuit and the stable current limiting circuit, and is used for mirroring the first current and outputting it to the stable current limiting circuit.
[0006] In a possible implementation, the startup sampling circuit includes: a first NMOS, a second NMOS and a delay circuit; The gate of the first NMOS is connected to the first end of the delay circuit and the drain of the first NMOS, and the drain of the first NMOS is used to input a first sampling current, and the first sampling current is generated according to the load current sampling; The gate of the second NMOS is connected to the second end of the delay circuit, the drain of the second NMOS is used to input the second sampling current, and is also connected to the conversion circuit, and the second sampling current is generated according to the load current sampling; The source of the first NMOS, the source of the second NMOS, and the third terminal of the delay circuit are grounded.
[0007] In a possible implementation, a current ratio of the first sampling current to the second sampling current is a first ratio; The width-to-length ratio of the first NMOS to the second NMOS is a second ratio; The first ratio is greater than the second ratio.
[0008] In a possible implementation, the conversion circuit includes: a third NMOS and a fourth NMOS; The gate of the third NMOS is connected to the drain of the third NMOS and the gate of the fourth NMOS, and the drain of the third NMOS is also connected to the output end of the startup sampling circuit; A source of the third NMOS and a source of the fourth NMOS are grounded; The drain of the fourth NMOS is connected to the stable current limiting circuit.
[0009] In a possible implementation, the startup sampling circuit further includes a first PMOS and a second PMOS; The gate of the first PMOS is connected to the gate of the second PMOS and the gate of the power tube; The drain of the first PMOS is connected to the drain of the first NMOS; The drain of the second PMOS is connected to the drain of the second NMOS; The source of the first PMOS and the source of the second PMOS are connected to the power supply voltage.
[0010] In a possible implementation, the delay circuit includes: a resistor and a capacitor; One end of the resistor is connected to the gate of the first NMOS and the drain of the first NMOS, and the other end of the resistor is connected to the gate of the second NMOS and one end of the capacitor; The other end of the capacitor is grounded.
[0011] In a second aspect, the present invention provides a current limiting method of an LDO, which is applied to a current limiting circuit of an LDO according to the first aspect and any possible implementation thereof, and the current limiting method includes: A starting current limiting circuit generates a first current according to a load current flowing through the power tube when the LDO is started, and the first current is greater than zero; a stable current limiting circuit, which limits the load current to a first current limiting value according to the first current; The current limiting circuit is started to generate a second current when the LDO is working stably, and the second current is equal to zero; The stable current limiting circuit limits the load current to a second current limiting value according to the second current, and the first current limiting value is less than or equal to the second current limiting value.
[0012] In a third aspect, the present invention provides a chip, which may include the current limiting circuit of the LDO according to the first aspect and any possible implementation thereof.
[0013] The current limiting circuit of the LDO provided by the present invention adds a startup current limiting circuit to the original current limiting circuit, and reuses the current limiting device of the stable current limiting circuit to increase the current sampling ratio of the LDO in the startup phase, thereby reducing the theoretical current limiting value in the startup phase of the LDO, and further making the actual current limiting value in the startup phase of the LDO (i.e., the first current limiting value, since the current limiting circuit in the startup phase has just been established, the actual current limiting value is greater than the theoretical current limiting value) less than or equal to the set current limiting value when the LDO is working stably (i.e., the second current limiting value). In this way, compared with the prior art in which the actual current limiting value in the startup phase of the LDO is higher than the set current limiting value in the stable operation, the present invention reduces the actual current limiting value in the startup phase of the LDO by adding a startup current limiting circuit, realizes the limitation of the load current of the LDO in the startup phase in a low-cost manner, solves the problem that the current flowing through the power tube of the LDO is too large during the startup process and the current limiting circuit cannot respond in time, and avoids damage to the LDO in the startup phase.
[0014] Moreover, in the stable working stage of the LDO, since the second current generated by the startup current limiting circuit is equal to zero, the second current will not affect the stable current limiting circuit, so the stable current limiting circuit can limit the load current to the set current limiting value, that is, the second current limiting value. In other words, the startup current limiting circuit will not affect the normal operation of the LDO in the stable working stage of the LDO. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 A circuit principle block diagram of a current limiting circuit of an LDO provided by an embodiment of the present invention; Figure 2 A circuit schematic diagram of a current limiting circuit of an LDO provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0017] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "multiple" means two or more. In addition, the use of "based on" or "according to" means openness and inclusiveness, because the process, steps, calculations or other actions "based on" or "according to" one or more of the conditions or values may be based on additional conditions or values beyond the described values in practice.
[0018] Figure 1 The circuit principle block diagram of a current limiting circuit of an LDO provided by an embodiment of the present invention. Figure 1 As shown, the current limiting circuit of the LDO may include: a power tube 11 , a startup current limiting circuit 12 and a stable current limiting circuit 13 .
[0019] The power tube 11 is connected to the voltage output terminal and is used to provide an output voltage to an external load.
[0020] The startup current limiting circuit 12 is connected to the power tube 11 and is used to generate a first current greater than zero according to the load current flowing through the power tube 11 when the LDO is started; and is also used to generate a second current equal to zero when the LDO is working stably.
[0021] The stable current limiting circuit 13 is connected to the startup current limiting circuit 12 and the power tube 11, and is used to limit the load current to a first current limiting value according to the first current, and is also used to limit the load current to a second current limiting value according to the second current, and the first current limiting value is less than or equal to the second current limiting value. In a specific implementation, during the startup process of the LDO, the stable current limiting circuit 13 itself will also sample the load current. When sampling, the stable current limiting circuit 13 can generate a final sampling current according to the first current, and when the sampling current is higher than the first current limiting value, the load current is limited.
[0022] It can be understood that the first current limiting value is the actual current limiting value in the startup phase of the LDO, and the second current limiting value is the actual current limiting value in the stable working phase of the LDO. Since the current limiting circuit of the LDO is just established and needs response time during the startup phase, the actual current limiting value in the startup phase will be higher than the set current limiting value. The embodiment of the present invention increases the startup current limiting circuit and combines the original stable current limiting circuit to limit the load current, so that the actual current limiting value in the startup phase of the LDO is less than or equal to the set current limiting value, thereby avoiding damage to the LDO during the startup phase.
[0023] The current limiting circuit of the LDO provided by the present invention adds a startup current limiting circuit to the original current limiting circuit, and reuses the current limiting device of the stable current limiting circuit to increase the current sampling ratio of the LDO in the startup phase, thereby reducing the theoretical current limiting value in the startup phase of the LDO, and further making the actual current limiting value (i.e., the first current limiting value) of the LDO startup phase less than or equal to the set current limiting value (i.e., the second current limiting value) when the LDO is working stably. In this way, compared with the prior art in which the actual current limiting value of the LDO startup phase is higher than the set current limiting value when working stably, the present invention reduces the actual current limiting value of the LDO startup phase by adding a startup current limiting circuit, realizes the load current limitation of the LDO in the startup phase in a low-cost manner, solves the problem that the current flowing through the power tube of the LDO is too large during the startup process and the current limiting circuit cannot respond in time, and avoids damage to the LDO in the startup phase.
[0024] Moreover, in the stable working stage of the LDO, since the second current generated by the startup current limiting circuit is equal to zero, the second current will not affect the stable current limiting circuit, so the stable current limiting circuit can limit the load current to the set current limiting value, that is, the second current limiting value. In other words, the startup current limiting circuit will not affect the normal operation of the LDO in the stable working stage of the LDO.
[0025] For example, assuming that the set current limit value of the LDO, that is, the second current limit value, is 300mA. In the prior art, the actual current limit value of the LDO during the startup phase may reach 600mA, causing damage to the LDO. In an embodiment of the present invention, after adding a startup current limiting circuit to increase the current sampling ratio, assuming that the theoretical current limit value of the LDO startup phase is 100mA, which is less than the set current limit value of 300mA, then the actual current limit value of the LDO during the startup phase may be 290mA, which is less than the set current limit value of 300mA, so that damage to the LDO during the startup phase can be avoided.
[0026] Optional, Figure 2 The circuit schematic diagram of a current limiting circuit of an LDO provided by an embodiment of the present invention. Figure 2 As shown, the startup current limiting circuit 12 may include: a startup sampling circuit 121 and a conversion circuit 122 .
[0027] The start sampling circuit 121 is connected to the power tube 11 and is used to generate a first current according to the load current.
[0028] The conversion circuit 122 is connected to the startup sampling circuit 121 and the stable current limiting circuit 13 , and is used for mirroring the first current and outputting it to the stable current limiting circuit 13 .
[0029] Optional, such as Figure 2 As shown, the startup sampling circuit 121 may include: a first NMOS NM1, a second NMOS NM2 and a delay circuit.
[0030] The gate of NM1 is connected to the first end of the delay circuit and the drain of NM1. The drain of NM1 is used to input a first sampling current. The first sampling current is generated according to load current sampling.
[0031] The gate of NM2 is connected to the second end of the delay circuit, the drain of NM2 is used to input the second sampling current, and is also connected to the conversion circuit 122. The second sampling current is generated according to the load current sampling. The first sampling current and the second sampling current are different and are in a certain ratio.
[0032] The source of NM1, the source of NM2, and the third terminal of the delay circuit are grounded.
[0033] It can be understood that, in the embodiment of the present invention, the delay circuit is used to make the rising speed of the gate voltage of NM2 slower than the rising speed of the gate voltage of NM1 during the LDO startup phase.
[0034] It can be understood that, in the embodiment of the present invention, the startup sampling circuit 121 is specifically used to generate a first sampling current and a second sampling current according to the load current, and to generate a first current in the startup phase according to the first sampling current and the second sampling current, or to generate a second current in the stable working phase.
[0035] In a possible implementation, if the current ratio of the first sampling current to the second sampling current is a first ratio, and the width-to-length ratio of NM1 to NM2 is a second ratio, then the first ratio is greater than the second ratio.
[0036] For example, the first ratio may be 1:X, the second ratio may be 1:Y, and (1:X) is greater than (1:Y). That is, the value of X is less than the value of Y.
[0037] Thus, in the LDO startup phase, the gate voltage of NM2 rises slower than the gate voltage of NM1 due to the delay circuit. According to the current formula (1) of the NMOS tube working in the linear region and the current formula (2) of the NMOS tube working in the saturation region, when the gate-source voltage V GSWhen the overcurrent capability of NM2 decreases, part of the current I1 will flow out, that is, the startup sampling circuit 121 will output the first current. After that, the first current is mirrored by the conversion circuit 122 and output to the stable current limiting circuit 13. The stable current limiting circuit 13 limits the load current according to the first current. In this way, by increasing the sampling current in the startup phase of the LDO and improving the current sampling ratio, the current limit value in the startup phase is reduced, and the function of LDO startup current limiting is achieved in a low-cost manner.
[0038] I D =μ n *C OX (W / L)[(V GS –V TH )V DS –0.5*V DS 2 ] (1) I D =0.5*μ n *C OX (W / L)(V GS –V TH ) 2 (2) Among them, μ n is the electron mobility of NM2, C OX is the gate oxide capacitance per unit area of NM2, (W / L) is the width-to-length ratio of NM2, V GS is the gate-source voltage of NM2, V TH is the threshold voltage, V DS is the source-drain voltage of NM2.
[0039] In the stable operation stage of the LDO, assuming that the width-to-length ratio of NM1 to NM2 is 1:Y, and the first sampling current is Isense1, then the overcurrent capability of NM2 is Y*Isense1. Since the first ratio of the first sampling current to the second sampling current is 1:X, and (1:X) is greater than (1:Y), X*Isense1 is less than Y*Isense1, that is, the second sampling current Isense2 is less than the overcurrent capability of NM2. In other words, the second sampling current Isense2 will all flow through NM2, and the second current output by the startup sampling circuit 121 is zero, and the second current has no effect on the normal operation of the LDO.
[0040] It should be noted that the first current limiting value is related to parameters such as the first ratio, the second ratio, and the startup duration, and the parameter sizes can be adjusted in advance according to actual needs.
[0041] Optional, such as Figure 2 As shown, the delay circuit may include: a resistor R and a capacitor C.
[0042] One end of the resistor R is connected to the gate of NM1 and the drain of NM1 , and the other end of the resistor is connected to the gate of NM2 and one end of the capacitor C.
[0043] The other end of capacitor C is grounded.
[0044] The embodiment of the present invention improves the current sampling ratio in the LDO startup phase by using an RC delay circuit, and the current sampling ratio changes linearly during the startup process. Compared with the prior art of directly using switch switching to improve the current sampling ratio, the use of the RC delay circuit has less impact on the LDO loop.
[0045] Optional, such as Figure 2 As shown, the startup sampling circuit 121 may further include: a first PMOS PM1 and a second PMOS PM2.
[0046] The gate of PM1 is connected to the gate of PM2 and the gate of the power tube 11 .
[0047] The drain of PM1 is connected to the drain of NM1 and is used to input the first sampling current to NM1.
[0048] The drain of PM2 is connected to the drain of NM2 and is used to input the second sampling current to NM2.
[0049] The source of PM1 and the source of PM2 are connected to the power supply voltage.
[0050] In this way, the load current is sampled by using PM1 and PM2.
[0051] Optional, such as Figure 2 As shown, the conversion circuit 122 may include: a third NMOS NM3 and a fourth NMOS NM4.
[0052] The gate of NM3 is connected to the drain of NM3 and the gate of NM4 . The drain of NM3 is also connected to the output end of the startup sampling circuit 121 .
[0053] The source of NM3 and the source of NM4 are grounded.
[0054] The drain of NM4 is connected to the stable current limiting circuit 13 .
[0055] In this way, through the current mirror units NM3 and NM4, the first current mirror can be input to the stable current limiting circuit.
[0056] The embodiment of the present invention further provides a chip, which may include Figure 1-Figure 2 The current limit circuit of any LDO in the
[0057] In a possible implementation, the chip may be an LDO chip, or other chips including an LDO, which is not specifically limited here.
[0058] The embodiment of the present invention also provides a current limiting method of an LDO, which is applied to the above Figure 1-Figure 2 In any one of the LDO current limiting circuits, the current limiting method may include: The current limiting circuit is started, and when the LDO is started, a first current is generated according to the load current flowing through the power tube, and the first current is greater than zero.
[0059] The stable current limiting circuit limits the load current to a first current limiting value according to the first current.
[0060] The current limiting circuit is started to generate a second current when the LDO operates stably, and the second current is equal to zero.
[0061] The stable current limiting circuit limits the load current to a second current limiting value according to the second current, and the first current limiting value is less than or equal to the second current limiting value.
[0062] It can be understood that the first current limiting value is the actual current limiting value in the startup phase of the LDO, and the second current limiting value is the actual current limiting value in the stable working phase of the LDO. Since the current limiting circuit of the LDO is just established and needs response time during the startup phase, the actual current limiting value in the startup phase will be higher than the set current limiting value. The embodiment of the present invention increases the startup current limiting circuit and combines the original stable current limiting circuit to limit the load current, so that the actual current limiting value in the startup phase of the LDO is less than or equal to the set current limiting value, thereby avoiding damage to the LDO during the startup phase.
[0063] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
Claims
1. A current limiting circuit for LDO, It is characterized in that include: A power tube connected to the voltage output terminal for providing an output voltage to an external load; A startup current limiting circuit, connected to the power tube, used to generate a first current greater than zero according to a load current flowing through the power tube when the LDO is started, and also used to generate a second current when the LDO is working stably, and the second current is equal to zero; A stable current limiting circuit is connected to the startup current limiting circuit and the power tube, and is used to limit the load current to a first current limiting value according to the first current, and is also used to limit the load current to a second current limiting value according to the second current, and the first current limiting value is less than or equal to the second current limiting value.
2. The current limiting circuit of the LDO according to claim 1, It is characterized in that The startup current limiting circuit comprises: a startup sampling circuit and a conversion circuit; The startup sampling circuit is connected to the power tube and is used to generate the first current according to the load current; The conversion circuit is connected to the startup sampling circuit and the stable current limiting circuit, and is used for mirroring the first current and outputting it to the stable current limiting circuit.
3. The current limiting circuit of the LDO according to claim 2, It is characterized in that The startup sampling circuit comprises: a first NMOS, a second NMOS and a delay circuit; The gate of the first NMOS is connected to the first end of the delay circuit and the drain of the first NMOS, and the drain of the first NMOS is used to input a first sampling current, where the first sampling current is generated according to the load current sampling; The gate of the second NMOS is connected to the second end of the delay circuit, the drain of the second NMOS is used to input a second sampling current and is also connected to the conversion circuit, and the second sampling current is generated according to the load current sampling; A source of the first NMOS, a source of the second NMOS, and a third terminal of the delay circuit are grounded.
4. The current limiting circuit of the LDO according to claim 3, It is characterized in that A current ratio of the first sampling current to the second sampling current is a first ratio; The width-to-length ratio of the first NMOS to the second NMOS is a second ratio; The first ratio is greater than the second ratio.
5. The current limiting circuit of the LDO according to any one of claims 2 to 4, It is characterized in that The conversion circuit comprises: a third NMOS and a fourth NMOS; The gate of the third NMOS is connected to the drain of the third NMOS and the gate of the fourth NMOS, and the drain of the third NMOS is also connected to the output end of the startup sampling circuit; The source of the third NMOS and the source of the fourth NMOS are grounded; The drain of the fourth NMOS is connected to the stable current limiting circuit.
6. The current limiting circuit of the LDO according to claim 3 or 4, It is characterized in that The startup sampling circuit also includes a first PMOS and a second PMOS; The gate of the first PMOS is connected to the gate of the second PMOS and the gate of the power tube; The drain of the first PMOS is connected to the drain of the first NMOS; The drain of the second PMOS is connected to the drain of the second NMOS; A source of the first PMOS and a source of the second PMOS are connected to a power supply voltage.
7. The current limiting circuit of the LDO according to claim 3 or 4, It is characterized in that The delay circuit comprises: a resistor and a capacitor; One end of the resistor is connected to the gate of the first NMOS and the drain of the first NMOS, and the other end of the resistor is connected to the gate of the second NMOS and one end of the capacitor; The other end of the capacitor is grounded.
8. A current limiting method for LDO, It is characterized in that The current limiting circuit of the LDO according to any one of claims 1 to 7, wherein the current limiting method comprises: A starting current limiting circuit generates a first current according to a load current flowing through the power tube when the LDO is started, wherein the first current is greater than zero; a stable current limiting circuit, which limits the load current to a first current limiting value according to the first current; The startup current limiting circuit generates a second current when the LDO is working stably, and the second current is equal to zero; The stable current limiting circuit limits the load current to a second current limiting value according to the second current, and the first current limiting value is less than or equal to the second current limiting value.
9. A chip, It is characterized in that The chip includes the current limiting circuit of the LDO according to any one of claims 1 to 7.