Low-voltage closed-loop self-starting LDO circuit suitable for high-voltage system

Abstract

The invention provides a low-voltage closed-loop self-starting LDO circuit suitable for a high-voltage system. The low-voltage closed-loop self-starting LDO circuit comprises a power voltage end; a ground terminal; the starting circuit is electrically connected between a power supply voltage end and a grounding end and is configured to generate an initial starting voltage; the LDO circuit is electrically connected between a power supply voltage end and a ground end and receives the initial starting voltage so as to generate a pre-power supply voltage at the output end of the LDO circuit; and a reference voltage providing circuit electrically connected to an output terminal of the LDO circuit, the reference voltage providing circuit configured to generate a reference voltage and an electrical signal, where the voltage is output to the LDO circuit as the reference voltage of the LDO circuit and the LDO circuit generates a new pre-supply voltage based on the reference voltage of the LDO circuit, and the electric signal is output to the self-starting circuit to close the self-starting circuit, so that the low-voltage closed-loop self-starting LDO circuit enters a stable working state.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a low-voltage closed-loop self-starting LDO circuit and chip suitable for high-voltage systems. Background Art

[0002] In current high-voltage applications of integrated circuits, considering the large power supply variation and the influence of high-voltage tube leakage, the reference voltage providing circuit (e.g., high-precision BandGap (BG)) is usually not implemented under high voltage, but rather implemented in a stable voltage domain. However, at this time, the reference voltage required by the Low Dropout Regulator (LDO) cannot be provided stably. Summary of the invention

[0003] It would be advantageous to provide a mechanism that alleviates, mitigates, or even eliminates one or more of the above-mentioned problems.

[0004] According to one aspect of the present disclosure, a low-voltage closed-loop self-starting LDO circuit suitable for a high-voltage system is provided, comprising: a power supply voltage terminal; a ground terminal; a startup circuit, electrically connected between the power supply voltage terminal and the ground terminal, the startup circuit being configured to generate a first initial startup voltage at a first output terminal of the startup circuit and a second initial startup voltage at a second output terminal of the startup circuit; an LDO circuit, electrically connected between the power supply voltage terminal and the ground terminal and electrically connected to the first output terminal and the first output terminal of the startup circuit, the LDO circuit comprising a self-starting circuit and an operational amplifier circuit, wherein the LDO circuit is configured to generate a first initial startup voltage at a first output terminal of the startup circuit and a second initial startup voltage at a second output terminal of the startup circuit; After the threshold voltage, the self-starting circuit is started to generate a pre-power supply voltage at the output end of the LDO circuit; and a reference voltage providing circuit is electrically connected to the output end of the LDO circuit, and the reference voltage providing circuit is configured to generate a reference voltage at a first output end of the reference voltage providing circuit and generate an electrical signal at a second output end of the reference voltage providing circuit after the pre-power supply voltage is generated at the output end of the LDO circuit, wherein the reference voltage is output to the LDO circuit as a reference voltage of the LDO circuit and the LDO circuit generates a new pre-power supply voltage based on the reference voltage of the LDO circuit, and the electrical signal is output to the self-starting circuit to turn off the self-starting circuit, so that the low-voltage closed-loop self-starting LDO circuit enters a stable working state.

[0005] According to another aspect of the present disclosure, a chip is provided, comprising the above-mentioned low-voltage closed-loop self-starting LDO circuit.

[0006] These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a modular circuit schematic diagram illustrating a low voltage closed loop self-starting LDO circuit according to an exemplary embodiment of the present disclosure;

[0009] Figure 2 is a specific circuit diagram illustrating a low voltage closed loop self-starting LDO circuit according to an exemplary embodiment of the present disclosure; and

[0010] Figure 3 1 is a diagram illustrating various voltage waveforms of a low voltage closed-loop self-starting LDO circuit according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part without departing from the teaching of the present disclosure.

[0012] Spatially relative terms such as "below," "beneath," "lower," "below," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figure. It will be understood that these spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is flipped, the element described as "below other elements or features" or "below other elements or features" or "below other elements or features" will be oriented to "above other elements or features." Therefore, the exemplary terms "below" and "below" can cover both orientations above and below. Terms such as "before" or "before" and "after" or "followed by" can be similarly used, for example, to indicate the order in which light passes through the elements. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used in this article are interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between two layers,” it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0013] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one", "one" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprise" specify the existence of the features, integral bodies, steps, operations, elements and / or parts when used in this specification, but do not exclude the existence of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups or add one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of A and B" includes only A, only B, and both A and B.

[0014] It will be understood that when an element or layer is referred to as being "on another element or layer," "connected to another element or layer," "coupled to another element or layer," or "adjacent to another element or layer," it may be directly on another element or layer, directly connected to another element or layer, directly coupled to another element or layer, or directly adjacent to another element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly on another element or layer," "directly connected to another element or layer," "directly coupled to another element or layer," or "directly adjacent to another element or layer," there are no intermediate elements or layers. However, in no case should "on..." or "directly on..." be interpreted as requiring that one layer completely cover the layer below.

[0015] Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. As such, variations in the illustrated shapes, for example as a result of manufacturing techniques and / or tolerances, should be expected. Therefore, embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the zones illustrated herein, but should include shape deviations, for example, due to manufacturing. Therefore, the zones illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the zones of the device and are not intended to limit the scope of the present disclosure.

[0016] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0017] Exemplary embodiments of the present disclosure are described in detail below and may be used to advantage for a number of reasons, for example, to mitigate or alleviate these undesirable side effects.

[0018] Figure 1 is a modular circuit diagram illustrating a low voltage closed loop self-starting LDO circuit 100 according to an exemplary embodiment of the present disclosure. Figure 2 2 is a specific circuit diagram illustrating a low voltage closed loop self-starting LDO circuit 200 according to an exemplary embodiment of the present disclosure. Figure 1 and Figure 2 To illustrate, the low-voltage closed-loop self-starting LDO circuit 200 may include: a power supply voltage terminal VDDH; a ground terminal GND; a startup circuit, electrically connected between the power supply voltage terminal VDDH and the ground terminal GND, the startup circuit may be configured to generate a first initial startup voltage VA at a first output terminal of the startup circuit and a second initial startup voltage VB at a second output terminal of the startup circuit; an LDO circuit, electrically connected between the power supply voltage terminal VDDH and the ground terminal GND and electrically connected to a first output terminal and a first output terminal of the startup circuit, the LDO circuit may include a self-starting circuit and an operational amplifier circuit, wherein the LDO circuit is configured to start the self-starting circuit to generate a pre-power supply voltage PERVDD at an output terminal of the LDO circuit after the first initial startup voltage VA exceeds a first threshold voltage and the second initial startup voltage VB exceeds a second threshold voltage; and a reference voltage providing circuit, electrically connected to the output terminal of the LDO circuit, in some examples, the reference voltage providing circuit may be a BandGap circuit (such as Figure 2 As shown), the reference voltage providing circuit is configured to generate a pre-power supply voltage PERVDD at the output terminal of the LDO circuit, and then generate a reference voltage (that is, a bandgap voltage VBG) at the first output terminal of the reference voltage providing circuit and generate an electrical signal BG-OK at the second output terminal of the reference voltage providing circuit, wherein VBG is output to the LDO circuit as a reference voltage REF of the operational amplifier circuit of the LDO circuit and the operational amplifier circuit can generate a new pre-power supply voltage PERVDD based on the reference voltage REF, and the electrical signal BG-OK is output to the self-starting circuit to turn off the self-starting circuit, so that the low-voltage closed-loop self-starting LDO circuit 200 enters a stable working state. In the example, the power supply voltage terminal VDDH provides a high voltage power supply for the low-voltage closed-loop self-starting LDO circuit 200.

[0019] In some examples, the startup circuit provides a first initial startup voltage VA to the operational amplifier circuit of the LDO circuit and provides a second initial startup voltage VB to the self-starting circuit.

[0020] Therefore, after the low-voltage closed-loop self-starting LDO circuit is started for the first time by the starting circuit, the reference voltage generated by the mounted reference voltage providing circuit can be continuously provided to the operational amplifier circuit of the LDO circuit as the reference voltage REF, and the electrical signal generated by the reference voltage providing circuit can turn off the self-starting circuit of the LDO circuit, thereby providing a stable reference voltage for the LDO circuit in high-voltage applications.

[0021] Continue to refer Figure 2 In the low-voltage closed-loop self-starting LDO circuit 200, the self-starting circuit of the LDO circuit may include: a first N-type transistor NM1, including a drain electrically connected to the operational amplifier circuit, a source electrically connected to the ground terminal GND, and a gate electrically connected to the second output terminal of the startup circuit; and a second N-type transistor NM2, including a drain electrically connected to the second output terminal of the startup circuit, a source electrically connected to the ground terminal GND, and a gate electrically connected to the second output terminal of the reference voltage providing circuit. In some examples, NM1 and NM2 may both be low-voltage transistors.

[0022] It should be understood that Figure 2 "NM1" or "NM2" in the figure can be a MOS field effect transistor, but they are just an example of a "first N-type transistor" and a "second N-type transistor". In other embodiments, the first N-type transistor and the second N-type transistor can be other types of field effect transistors or transistors, such as junction field effect transistors, bipolar junction transistors, etc. The same applies to NM3 to NM9 and PM1 to PM5 below, which will not be repeated. In addition, the transistors with "(HV)" in the figure are high-voltage transistors, and the remaining transistors are low-voltage transistors by default.

[0023] Continue to refer Figure 2In the low-voltage closed-loop self-starting LDO circuit 200, the operational amplifier circuit may include: a current source IB, including an input terminal and an output terminal, the output terminal being electrically connected to the ground terminal GND; a first P-type transistor PM1, including a gate and a drain electrically connected to each other and a source electrically connected to the power supply voltage terminal VDDH; a second P-type transistor PM2, including a drain, a source electrically connected to the power supply voltage terminal VDDH, and a gate electrically connected to the gate of the first P-type transistor PM1; a third N-type transistor NM3, including a source, a drain electrically connected to the drain of the first P-type transistor PM1, and a gate electrically connected to the drain of the first P-type transistor PM1 and the first output terminal of the startup circuit; a fourth N-type transistor NM4, including a source, a drain electrically connected to the drain of the second P-type transistor PM2, a gate electrically connected to the drain of the first P-type transistor PM1 and the first output terminal of the startup circuit; a fifth N-type transistor NM5, including a source electrically connected to the first P-type transistor PM1; a drain electrically connected to the drain of the second P-type transistor PM2, a drain electrically connected to the drain of the first P-type transistor PM1 and the first output terminal of the startup circuit; a fifth N-type transistor NM6, including a source electrically connected to the drain of the second P-type transistor PM2, a drain electrically connected to the drain of the first P-type transistor PM1 and the first output terminal of the startup circuit; a fifth N-type transistor NM7, including a source electrically connected to the drain of the second P-type transistor PM2, a drain electrically connected to the drain of the first P-type transistor PM1 and the first output terminal of the startup circuit; a fifth N-type transistor NM8, including a source electrically connected to the drain of the second P-type transistor PM2, a drain electrically connected to the drain of the first P-type transistor PM8, and a gate electrically connected to the drain of the first P-type transistor PM8. a drain, a gate and a source electrically connected to the input terminal of the first current source IB of the third N-type transistor NM3; a sixth N-type transistor NM6, including a drain electrically connected to the source of the fourth N-type transistor NM4 and the drain of the first N-type transistor NM1, a gate electrically connected to the first output terminal of the reference voltage providing circuit and a source electrically connected to the input terminal of the first current source IB; a third P-type transistor PM3, including a drain as the output terminal of the LDO circuit, a source electrically connected to the power supply voltage terminal VDDH and a gate electrically connected to the drain of the second P-type transistor PM2; a second resistor R2, electrically connected between the gate of the fifth N-type transistor NM5 and the ground terminal GND; a third resistor R3, electrically connected between the drain of the third P-type transistor PM3 and the gate of the fifth N-type transistor NM5; and a diode D, including a positive electrode electrically connected to the ground terminal GND and a negative electrode electrically connected to the drain of the third P-type transistor PM3.

[0024] In some examples, the resistance values ​​of R2 and R3 can be adjusted. After the low voltage closed-loop self-starting LDO circuit 200 reaches a stable working state, the pre-power supply voltage PERVDD=V BG (1+R3 / R2), therefore, by adjusting the ratio of R2 and R3, flexible adjustment of PREVDD can be achieved.

[0025] Continue to refer Figure 2In the low-voltage closed-loop self-starting LDO circuit 200, the startup circuit may include: a fourth P-type transistor PM4, including a gate, a drain, and a source electrically connected to the power supply voltage terminal VDDH; a fourth resistor R4, electrically connected between the power supply voltage terminal VDDH and the gate of the fourth P-type transistor PM4; a fifth P-type transistor PM5, including a drain as a first output terminal of the startup circuit, a source electrically connected to the gate of the fourth P-type transistor PM4, and a gate electrically connected to the drain of the fourth P-type transistor PM4; a first resistor R1, including a first terminal and a source electrically connected to the gate of the fourth P-type transistor PM4; a fifth P-type transistor PM5, including a drain as a first output terminal of the startup circuit, a source electrically connected to the gate of the fourth P-type transistor PM4, and a gate electrically connected to the drain ... Two terminals, a first terminal electrically connected to the drain of the fifth P-type transistor PM5, and a second terminal electrically connected to the drain of the second N-type transistor NM2 as the second output terminal of the startup circuit; a fifth resistor R5, electrically connected between the ground terminal GND and the gate of the fifth P-type transistor PM5; a seventh N-type transistor NM7, including a source and a drain and a gate electrically connected to the drain of the fifth P-type transistor PM5; and an eighth N-type transistor NM8, including a source electrically connected to the ground terminal GND and a drain and a gate electrically connected to the source of the seventh N-type transistor NM7.

[0026] In some examples, the startup circuit may also be a combination of a current source and a Zener diode.

[0027] In some examples, the low voltage closed loop self-starting LDO circuit 200 can also be mounted with other circuits for driving, for example Figure 2 The operational amplifier OP1 shown in FIG.

[0028] refer to Figure 3 , Figure 3 It shows that after the power supply voltage terminal VDDH is powered on, as the magnitude of VDDH increases with time T, the first initial startup voltage V A、 The waveform diagram of the second initial startup voltage VB, the reference voltage VBG (the reference voltage providing circuit still takes the BandGap circuit as an example) and the pre-power supply voltage PREVDD. Figure 2 right Figure 3 The first initial startup voltage VA is finally stabilized at the threshold voltage V of the seventh N-type transistor NM7 after the voltage VDDH at the power supply voltage terminal increases. NMTH7 and the threshold voltage V NMTH8 The sum of VA = V NMTH7 +V NMTH8 When the first initial startup voltage VA exceeds the threshold voltage V of the fourth N-type transistor NM4 NMTH4 The second initial startup voltage VB exceeds the conduction threshold value V of the first N-type transistor NM1 (low voltage tube) NMTH1 After that, the pre-supply voltage PREVDD will be pulled to the voltage VDDH and V BG(1+R3 / R2) is the lower value. Therefore, if the reference voltage providing circuit starts normal operation upon receiving the pre-power supply voltage PREVDD of 2V, the voltage VDDH at the power supply voltage end can generate the reference voltage VBG at 2V. The reference voltage providing circuit can also generate an electrical signal BG-OK to turn off the self-starting circuit. At this time, the voltage VDDH at the power supply voltage end only needs to be higher than the Vdropout of the third P-type transistor PM3 to provide a continuous and stable reference voltage REF for the low-voltage closed-loop self-starting LDO circuit 200. After the VBG as the reference voltage of the operational amplifier circuit is output stably, PREVDD=V BG (1+R3 / R2) continuously provides circuit power for the reference voltage, and the low-voltage closed-loop self-starting LDO circuit achieves steady state under closed-loop control.

[0029] In some examples, VBG needs the pre-power supply voltage PREVDD to be started at 2V, so the LDO can be started at the voltage VDDH=2V+Vdropout≈2.3V at the power supply voltage terminal, thereby achieving low-voltage closed-loop operation with controllable PREVDD output voltage.

[0030] In some examples, due to the closed-loop control of the pre-power supply voltage PREVDD, the value of the pre-power supply voltage PREVDD can be flexibly set through the second resistor R2 and the third resistor R3. If the pre-power supply voltage PREVDD is set below 2.3V, after the 2.3V pre-power supply voltage PREVDD is started, the power supply voltage changes, and the closed-loop controlled pre-power supply voltage PREVDD can be stabilized at 2.3V and changes very little, thereby achieving good DC power supply suppression DC PSR at low voltage.

[0031] According to one aspect of the present disclosure, a chip is provided, comprising any low-voltage closed-loop self-starting LDO circuit described above.

[0032] Although the present disclosure has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description should be considered illustrative and schematic, not restrictive; the present disclosure is not limited to the disclosed embodiments. By studying the drawings, the disclosure and the appended claims, those skilled in the art will be able to understand and implement variations to the disclosed embodiments when practicing the claimed subject matter. In the claims, the word "comprising" does not exclude other elements or steps that are not listed, the indefinite article "a" or "an" does not exclude a plurality, the term "plurality" means two or more, and the term "based on" should be interpreted as "based at least in part on". The mere fact that certain measures are recorded in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A low voltage closed loop self-starting LDO circuit suitable for a high voltage system, comprising: Power supply voltage terminal; Ground terminal; a startup circuit electrically connected between the power supply voltage terminal and the ground terminal, the startup circuit being configured to generate a first initial startup voltage at a first output terminal of the startup circuit and a second initial startup voltage at a second output terminal of the startup circuit; an LDO circuit electrically connected between the power supply voltage terminal and the ground terminal and electrically connected to the first output terminal and the first output terminal of the startup circuit, the LDO circuit comprising a self-starting circuit and an operational amplifier circuit, wherein the LDO circuit is configured to start the self-starting circuit to generate a pre-power supply voltage at an output terminal of the LDO circuit after the first initial startup voltage exceeds a first threshold voltage and the second initial startup voltage exceeds a second threshold voltage; and A reference voltage providing circuit is electrically connected to the output terminal of the LDO circuit, and the reference voltage providing circuit is configured to generate a reference voltage at a first output terminal of the reference voltage providing circuit and generate an electrical signal at a second output terminal of the reference voltage providing circuit after generating a pre-power supply voltage at the output terminal of the LDO circuit, wherein the reference voltage is output to the LDO circuit as a reference voltage of the operational amplifier circuit of the LDO circuit and the operational amplifier circuit generates a new pre-power supply voltage based on the reference voltage, and the electrical signal is output to the self-starting circuit to shut down the self-starting circuit, so that the low-voltage closed-loop self-starting LDO circuit enters a stable working state.

2. The low voltage closed loop self-starting LDO circuit according to claim 1, wherein the self-starting circuit of the LDO circuit comprises: a first N-type transistor including a drain electrically connected to the operational amplifier circuit, a source electrically connected to the ground terminal, and a gate electrically connected to the second output terminal of the startup circuit; as well as The second N-type transistor includes a drain electrically connected to the second output terminal of the startup circuit, a source electrically connected to the ground terminal, and a gate electrically connected to the second output terminal of the reference voltage providing circuit.

3. The low voltage closed loop self-starting LDO circuit according to claim 2, wherein the operational amplifier circuit comprises: a current source, comprising an input terminal and an output terminal, wherein the output terminal is electrically connected to the ground terminal; A first P-type transistor, comprising a gate and a drain electrically connected to each other and a source electrically connected to the power supply voltage terminal; a second P-type transistor comprising a drain, a source electrically connected to the power supply voltage terminal, and a gate electrically connected to the gate of the first P-type transistor; a third N-type transistor including a source, a drain electrically connected to the drain of the first P-type transistor, and a gate electrically connected to the drain of the first P-type transistor and the first output terminal of the startup circuit; a fourth N-type transistor, comprising a source, a drain electrically connected to the drain of the second P-type transistor, and a gate electrically connected to the drain of the first P-type transistor and the first output terminal of the startup circuit; a fifth N-type transistor, comprising a drain electrode electrically connected to the source electrode of the third N-type transistor, a gate electrode, and a source electrode electrically connected to the input terminal of the first current source; a sixth N-type transistor, comprising a drain electrically connected to the source of the fourth N-type transistor and the drain of the first N-type transistor, a gate electrically connected to the first output terminal of the reference voltage providing circuit, and a source electrically connected to the input terminal of the first current source; a third P-type transistor including a drain electrode serving as an output terminal of the LDO circuit, a source electrode electrically connected to the power supply voltage terminal, and a gate electrode electrically connected to the drain electrode of the second P-type transistor; a second resistor, electrically connected between the gate of the fifth N-type transistor and the ground terminal; a third resistor, electrically connected between the drain of the third P-type transistor and the gate of the fifth N-type transistor; as well as A diode includes an anode electrically connected to the ground terminal and a cathode electrically connected to the drain of the third P-type transistor.

4. The low voltage closed loop self-starting LDO circuit according to claim 3, wherein the starting circuit comprises: a fourth P-type transistor, comprising a gate, a drain, and a source electrically connected to the power supply voltage terminal; a fourth resistor, electrically connected between the power supply voltage terminal and the gate of the fourth P-type transistor; a fifth P-type transistor, comprising a drain electrode serving as a first output terminal of the startup circuit, a source electrode electrically connected to the gate electrode of the fourth P-type transistor, and a gate electrode electrically connected to the drain electrode of the fourth P-type transistor; a first resistor, comprising a first end and a second end, wherein the first end is electrically connected to the drain of the fifth P-type transistor, and the second end is electrically connected to the drain of the second N-type transistor as a second output end of the startup circuit; a fifth resistor, electrically connected between the ground terminal and the gate of the fifth P-type transistor; a seventh N-type transistor including a source, a drain electrically connected to the drain of the fifth P-type transistor, and a gate; as well as The eighth N-type transistor includes a source electrically connected to the ground terminal and a drain and a gate electrically connected to the source of the seventh N-type transistor.

5. The low voltage closed loop self-starting LDO circuit as claimed in claim 4, wherein: The first threshold voltage is a threshold voltage of the fourth N-type transistor, and the second threshold voltage is a threshold voltage of the first N-type transistor.

6. A chip comprising the low-voltage closed-loop self-starting LDO circuit according to any one of claims 1 to 5.

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