Apparatus and method for write data preprocessing using neural network

Abstract

The invention relates to an apparatus and method for write data preprocessing using a neural network. The memory includes: a receiver circuit configured to receive write data via a data terminal; and a neural network-based pre-processing circuit configured to receive a write data signal in accordance with the write data. A neural network of the pre-processing circuit is configured to pre-process the write data signal based on characteristics of a write data path to provide a modified write data signal. The memory further includes a memory array configured to store the write data based on the modified write data signal.

Description

Technical Field

[0001] The present application relates generally to memory devices, and in particular, to apparatus and methods for write data pre-processing using neural networks. Background Art

[0002] Digital systems (e.g., memory devices) continue to operate at higher and higher speeds. Various signal lines carrying digital signals may exhibit low pass filter (LPF) characteristics due to channel loss increasing with frequency or through capacitive filtering. In addition, process and temperature variations may also affect the speed at which the circuit system can operate. Therefore, the maximum data rate supported by the channel becomes limited. Existing solutions for compensating for channel data rate limitations may include various equalization techniques that have been used, including added complex circuit systems that cannot effectively increase the channel data rate in many cases. Summary of the invention

[0003] According to aspects of the present disclosure, an apparatus is provided. The apparatus includes: a receiver circuit configured to receive write data via a data terminal coupled to a data bus; a preprocessing circuit configured to receive a write data signal based on the write data, wherein a neural network of the preprocessing circuit is configured to preprocess the write data signal based on characteristics of a write data path to provide a modified write data signal, the write data path including a propagation path of the write data from the data terminal all the way to a storage device at a memory cell; and a memory array configured to store the write data at the memory cell based on the modified write data signal.

[0004] According to another aspect of the present disclosure, a method is provided, comprising: generating a write data training data set based on characteristics of a write data channel of a memory, wherein the training data set comprises correlations between the write data for the channel and the characteristics of the write data channel; and training a neural network of a write data preprocessing circuit of the memory using the write data training data set to determine the channel characteristics of the write data channel based on the write data of the write data channel.

[0005] According to another aspect of the present disclosure, a method is provided. The method includes: receiving write data via a data terminal at a receiver circuit of a memory; preprocessing a write data signal corresponding to the write data based on characteristics of a write data path via a neural network of a preprocessing circuit of the memory to provide a modified write data signal; and storing the write data at a memory array based on the modified write data signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1is a schematic diagram of a semiconductor device according to various embodiments.

[0007] Figure 2 A schematic block diagram illustrates a system for pre-processing a write data signal in a memory device according to various embodiments.

[0008] Figure 3 A schematic block diagram illustrating a neural network based system for pre-processing a write data signal in a memory device according to various embodiments.

[0009] Figure 4 is a block diagram illustrating a processing unit arranged in a computing system according to various embodiments.

[0010] Figure 5 is a flow chart illustrating a method for training a neural network to pre-process a write data signal at a memory according to various embodiments.

[0011] Figure 6 is a flow chart illustrating a method for pre-processing a write data signal at a memory using a neural network according to various embodiments. DETAILED DESCRIPTION

[0012] The present disclosure describes examples of apparatus and methods for preprocessing transmitted write data signals using a neural network during a write or programming operation. Preprocessing may include modifying the shape of the transmitted signal so that the properties of the signal line (e.g., capacitance, circuit switching speed, etc.) cause the transmitted signal to be received and stored at the memory cell array in a desired shape. Preprocessing may include pre-emphasis or de-emphasis of the signal shape. Pre-emphasis refers to increasing the amplitude of a digital signal by providing an overshoot filtered by the capacitive effects of the signal line at each bit transition. De-emphasis refers to a complementary process of reducing the amplitude of a digital signal, wherein a full rail-to-rail swing between a high power supply voltage (VDDQ, VDD) and a low power supply voltage (VSSQ, VSS) is provided at each bit transition.

[0013] One conventional way to implement de-emphasis / pre-emphasis is to use delay chains to sequentially turn on or off branches of the pull-up and / or pull-down circuits of a voltage driver. This results in dynamic changes in the driver output impedance, which can degrade signal integrity. In addition, de-emphasis / pre-emphasis is typically asymmetric, either emphasizing the pull-up from VSSQ or the pull-down from VDDQ. The use of neural networks can mitigate the negative effects of these conventional approaches.

[0014] The following detailed description describes several exemplary embodiments in more detail to enable those skilled in the art to practice such embodiments. The described examples are provided for illustrative purposes and are not intended to limit the scope of the present invention. In the following description, for the purpose of explanation, many specific details are stated in order to provide a thorough understanding of the described embodiments. However, it should be understood by those skilled in the art that other embodiments of the present invention may be practiced without some of these specific details.

[0015] Figure 1 1 is a schematic diagram of a semiconductor device 100 according to various embodiments. The semiconductor device 100 includes a memory die. The memory die may include an address / command input circuit 105, an address decoder 110, a command decoder 115, a clock input circuit 120, an internal clock generator 130, a timing generator 135, a row decoder 140, a column decoder 145, a memory array 150, a read / write amplifier 155, a pre-processing control circuit 125, an I / O circuit 160, a ZQ calibration circuit 165, and a voltage generator 170.

[0016] In some embodiments, the semiconductor device 100 may include, without limitation, a DRAM device, such as a DDR3 or DDR4 device integrated into a single semiconductor chip. The die may be mounted on an external substrate, such as a memory module substrate, a motherboard, or the like. The semiconductor device 100 may further include a memory array 150. The memory array 150 includes a plurality of memory banks, each memory bank including a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word lines WL is performed by a row decoder 140 and the selection of the bit lines BL is performed by a column decoder 145. The sense amplifier (SA) is positioned for its corresponding bit line BL and is connected to at least one corresponding local I / O line, which in turn may be coupled to a corresponding one of at least two main I / O line pairs via a transfer gate (TG) used as a switch.

[0017] The semiconductor device 100 may employ a plurality of external terminals, including an address and command terminal coupled to a command / address bus (C / A), clock terminals CK and / CK, a data terminal DQ (e.g., a pad or pin coupling the semiconductor device 100 to a data bus), a data select signal terminal DQS (e.g., a pad or pin coupling the semiconductor device 100 to a data select signal line), and a data mask signal terminal DM (e.g., a pad or pin coupling the semiconductor device 100 to a data mask signal line), power supply terminals a high voltage power supply VDD, a low voltage power supply VSS, a high voltage power supply for an input / output signal VDDQ, and a low voltage power supply for an input / output signal VSSQ, and an output impedance control ZQ calibration terminal (ZQ).

[0018] The address signal and the memory bank address signal can be supplied from the outside to the command / address terminal. The address signal and the memory bank address signal supplied to the address terminal are transmitted to the address decoder 110 via the address / command input circuit 105. The address decoder 110 receives the address signal and supplies the decoded row address signal to the row decoder 140, and supplies the decoded column address signal to the column decoder 145. The address decoder 110 also receives the memory bank address signal and supplies the memory bank address signal to the row decoder 140 and the column decoder 145.

[0019] The command / address terminal may be further supplied with a command signal from the outside (e.g., for example, a memory controller). The command signal may be provided to the command decoder 115 via the C / A bus via the address / command input circuit 105. The command decoder 115 decodes the command signal to generate various internal commands, including a row command signal for selecting a word line and a column command signal for selecting a bit line (e.g., a read command or a write command).

[0020] Therefore, when a read command is issued and a row address and a column address are supplied in time with the read command, read data is read from the memory cells specified by these row addresses and column addresses in the memory array 150. The read data DQ is output to the outside from the data terminals DQ, DQS, and DM via the read / write amplifier 155 and the input / output circuit 160. Similarly, when a write command is issued and a row address and a column address are supplied in time with this command and then write data is supplied to the data terminals DQ, DQS, and DM, the write data is received by the data receiver of the input / output circuit 160 and supplied to the memory array 150 via the input / output circuit 160 and the read / write amplifier 155 and is written in the memory cells specified by the row address and the column address.

[0021] When the write data DQ is received at the receiver of the input / output circuit 160, it will usually be passed to the read / write amplifier 155 to be written into the memory array 150. However, in order to increase the channel data rate for transmitting data to the read / write amplifier 155 to be written into the memory array 150, the write data signal may be processed by the neural network of the pre-processing control circuit 125 to modify the shape of the write data signal so that the properties of the write data channel (e.g., capacitance, circuit switching speed, etc.) cause the write data signal to be received in a desired shape at the memory cell array 150. The pre-processing may include pre-emphasis or de-emphasis of the signal shape.

[0022] The neural network can be trained to set coefficients applied to the write data signal to compensate for the channel characteristics of the write data channel and the corresponding circuit system. For example, using the following equation:

[0023] y i(k) = x i (k)+f i (k)

[0024] where y i (k) is the real voltage at the ith cell and its kth level (K levels in total), x i (k) is the target voltage at the i-th cell and its k-level, and f i (k) is the offset voltage caused by programming noise, inter-cell interference and leakage. To train the neural network, the cell x in the codeword i (k)(i=1,,...L) can be programmed, and then the real voltage y can be measured i (k). The pre-processing control signal may be used during training to train the neural network by adjusting the coefficients used by the neural network to modify the write data signal. During training, the input of the neural network may be y i (k)(KxL) and the target output can be x i (k). Real voltage y i (k) can be compared with the target output x i (k) is compared. During training, the input of the neural network can be y i (k)(KxL) to determine the convergence error estimate f i (k) (e.g., target input x i (k) minus the output of the neural network equals f i (k)). The coefficients can be modified until the target output x is met. i (k) and the converged difference and coefficients can be stored in the coefficient data memory. During the write or programming operation, the neural network of the pre-processing control circuit 125 can receive the write data signal x i (k) and the neural network can use the stored coefficients to modify x i (k) to provide a new programming voltage for the write data signal (for example, it should be x i (k)-f i (k) or equal to the input of the neural network minus f i (k)). Therefore, due to the channel characteristics after the write data signal is transmitted to the read / write amplifier 155, the resulting voltage of the write data signal is x i (k).

[0025] Turning to the explanation of the external terminals included in the semiconductor device 100, the clock terminals CK and / CK are supplied with an external clock signal and a complementary external clock signal, respectively. The external clock signal (including the complementary external clock signal) may be supplied to the clock input circuit 120. The clock input circuit 120 may receive the external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK is supplied to the internal clock generator 130, and thus a phase-controlled internal clock signal LCLK is generated based on the internal clock signal ICLK and the clock enable signal CKE received from the address / command input circuit 105. Although not limited thereto, the DLL circuit may be used as the internal clock generator 130. The phase-controlled internal clock signal LCLK is supplied to the input / output circuit 160, and is used as a timing signal for determining the output timing of the read data. The internal clock signal ICLK is also supplied to the timing generator 135 and thus various internal clock signals may be generated.

[0026] The power supply terminals are supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 170. The internal voltage generating circuit 170 generates various internal potentials VPP, VOD, VARY, VPERI and the like and a reference potential ZQVREF based on the power supply potentials VDD and VSS. The internal potential VPP is mainly used in the row decoder 140, the internal potentials VOD and VARY are mainly used in the sense amplifier included in the memory array 150, and the internal potential VPERI is used in many other circuit blocks. The reference potential ZQVREF is used in the ZQ calibration circuit 165.

[0027] The power supply terminal is also supplied with power supply potentials VDDQ and VSSQ. These power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 160. The power supply potentials VDDQ and VSSQ are the same potentials as the power supply potentials VDD and VSS, respectively. However, the dedicated power supply potentials VDDQ and VSSQ are used for the input / output circuit 160 so that the power supply noise generated by the input / output circuit 160 does not propagate to other circuit blocks.

[0028] The calibration terminal ZQ is connected to the ZQ calibration circuit 165. When activated by the ZQ calibration command signal (ZQ_com), the ZQ calibration circuit 165 performs a calibration operation with reference to the impedance of RZQ and the reference potential ZQVREF. The impedance code ZQCODE obtained by the calibration operation is supplied to the input / output circuit 160, and thus specifies the impedance of the output buffer (not shown) included in the input / output circuit 160.

[0029] Figure 2A schematic block diagram of a system 200 for preprocessing write data signals in a memory device according to various embodiments is illustrated. The system 200 may include a memory controller 205 coupled to a system memory 215. The memory controller 205 may include preprocessing control logic 210. The system memory 215 may include a preprocessing control circuit 220 configured to receive a preprocessing control signal from the preprocessing control logic 210. The preprocessing control circuit 220 may be further configured to receive write data (DQ) from the memory controller 205 during a write or programming operation. The DQ may include digital data preprocessed by the preprocessing control circuit 220 before being stored at the memory array 230. The preprocessing control circuit 220 may be coupled to a data receiver 225. In some embodiments, the data receiver 225 may include a data buffer.

[0030] In some examples, the pre-processing time used to modify the shape of the write data DQ may be controlled via external control signals, such as those generated by the pre-processing control logic 210. This may include adjusting the pre-processing time as well as the pre-processing amplitude adjustment amount. The memory controller 205 may include an external controller, such as a processor, to control the pre-processing operations.

[0031] In some embodiments, the memory controller 205 may optionally include a training circuit 235. The training circuit 235 may be configured to train the neural network of the pre-processing control circuit 220 to pre-process the write data signal before storing the write data signal at the memory array 230 based on, but not limited to, data eye optimization, reference voltage (amplitude) calibration, and write data training. In some embodiments, the training circuit 235 may also be optionally connected to the pre-processing control logic 210. Thus, in some embodiments, such as in data eye optimization, the pre-processing control signal may be adjusted based on input from the training circuit 235 to adjust the coefficients of the neural network. In further embodiments, data eye optimization may include first identifying the pre-processing amplitude adjustment direction (e.g., de-emphasis or pre-emphasis) and amplitude that provides the best data eye for a given channel (e.g., but not limited to, a data path for data in the memory array 230). To perform training, the cells in the codeword may be programmed, and then the real voltage may be measured. During training, the input to the neural network may be the expected output, and the target output may be the write data signal. The training circuit 235 may compare the actual voltage to the target output to determine a convergence difference estimate (e.g., the target input minus the output of the neural network). The training circuit 235 may modify the coefficients of the neural network until the target output is met, and may store the convergence difference and the coefficients in a coefficient data memory.

[0032] Figure 3A schematic block diagram of a system 300 for preprocessing a write data signal in a memory device according to various embodiments is illustrated. The system 300 may include a neural network based preprocessing circuit 310, a read / write amplifier 320, and a memory array 330. The neural network based preprocessing circuit 310 may be configured to receive data from an input / output circuit (e.g., Figure 1 The receiver of the input / output circuit 160 of the memory array 330 receives the write data signal, and the neural network of the neural network based pre-processing circuit 310 may be configured to pre-process the write data signal using the stored coefficients before providing the write data signal to the read / write amplifier 320. The read / write amplifier 320 may be configured to process the write data signal for storage at the memory array 330 at the location specified by the row address and the column address.

[0033] In some examples, the pre-processing time used to modify the shape of the write data DQ may be controlled via an external control signal. This may include adjusting the pre-processing time by changing the coefficients applied to the write data signal by the neural network and making pre-processing amplitude adjustments.

[0034] Figure 4 4 is a block diagram illustrating a processing unit 405 arranged in a computing system 400 according to various embodiments. The system 400 may include Figure 1 The semiconductor device 100, Figure 2 System 200, Figure 3 The processing unit 405 may be configured to implement a neural network, such as a neural network trained to pre-process the write data signal based on channel characteristics of the memory device.

[0035] The processing unit 405 may receive input data (e.g., X_1 / 2 / N(n)) 410a-c from a computing system (e.g., a host computing device). In some examples, the input data 410a-c may be write data associated with a write or programming operation at a memory. The processing unit 405 may include multiplication units / accumulation units 412a-c, 416a-c and memory lookup units 414a-c, 418a-c, which when mixed with coefficient data retrieved from the memory 430 may generate output data (e.g., Y_1 / 2 / N(n)) 420a-c. In some examples, the output data 420a-c may be used as input data or output data for another processing stage, such as one or more channel characteristics associated with a channel within a memory. In other words, the processing unit 405 may include one or more stages of a neural network such that the processing unit 405 receives input data 410a-c including data associated with a write or programming operation and generates output data 420a-c including one or more channels through which the write or programming operation is performed.

[0036] When implementing one or more processing units 405, the computer-readable medium at the electronic device may execute corresponding control instructions to perform operations within the processing unit 405 through the executable pre-processing control instructions 415. For example, the control instructions provide instructions to the processing unit 405, which, when executed by the electronic device, cause the processing unit 405 to configure the multiplication units 412a to c to multiply the input data 410a to c with the coefficient data, and configure the accumulation units 416a to c to accumulate the processing results to generate the output data 420a to c.

[0037] The multiplication units / accumulation units 412a-c, 416a-c multiply two operands from the input data 410a-c to produce a multiplication processing result that is accumulated by the accumulation unit portion of the multiplication units / accumulation units 412a-c, 416a-c. The multiplication units / accumulation units 412a-c, 416a-c add the multiplication processing results to update the processing results stored in the accumulation unit portion, thereby accumulating the multiplication processing results. For example, the multiplication units / accumulation units 412a-c, 416a-c can perform a multiplication-accumulation operation such that two operands M and N are multiplied and then added with P to produce a new version of P stored in its corresponding multiplication unit / accumulation unit. The memory lookup unit 414a-c, 418a-c retrieves the coefficient data stored in the memory 430. For example, the memory lookup unit can be a lookup table that retrieves a specific coefficient. The output of the memory lookup unit 414a-c, 418a-c is provided to the multiplication unit / accumulation unit 412a-c, 416a-c, which can be used as a multiplication operand in the multiplication unit portion of the multiplication unit / accumulation unit 412a-c, 416a-c. Using this circuit system arrangement, output data (e.g., Y_1 / 2 / N(n)) 420a-c can be generated based on the input data (e.g., X_1 / 2 / N(n)) 410a-c.

[0038] In some examples, coefficient data, such as from memory 430 , may be mixed with input data X_1 / 2 / N(n) 410 a - c to produce output data Y_1 / 2 / N(n) 420 a - c .

[0039] As described above, the memory lookup units 414a to c, 418a to c retrieve coefficients to mix with the input data. Thus, the output data can be provided by manipulating the input data with a set of coefficients stored in the memory and associated with the write data channel at the memory using a multiplication / accumulation unit. The resulting mapping data can be manipulated by an additional multiplication / accumulation unit using an additional coefficient group associated with the characteristics of the channel stored in the memory. The coefficient group multiplied at each level of the processing unit 405 can represent or provide an estimate of the processing of the input data in specially designed hardware (e.g., FPGA). In addition, it can be shown that in some examples, the system 400 can approximate any nonlinear mapping with arbitrarily small errors, and the mapping of the system 400 is determined by the coefficients. For example, if this coefficient data is specified, any mapping and processing between the input data X_1 / 2 / N(n) 410a to c and the output data Y_1 / 2 / N(n) 420a to c can be completed by the system 400. This relationship, as derived from the circuitry arrangement depicted in system 400, may be used to train entities of computing system 400 to generate coefficient data. For example, entities of computing system 400 may compare input data and output data to generate coefficient data.

[0040] In the example of system 400, processing unit 405 mixes coefficient data with input data X_1 / 2 / N(n) 410a-c using memory lookup units 414a-c, 418a-c. In some examples, memory lookup units 414a-c, 418a-c may be referred to as table lookup units. Coefficient data may be associated with a mapping relationship of input data X_1 / 2 / N(n) 410a-c to output data Y_1 / 2 / N(n) 420a-c. For example, coefficient data may represent a nonlinear mapping of input data X_1 / 2 / N(n) 410a-c to output data Y_1 / 2 / N(n) 420a-c. In some examples, the nonlinear mapping of coefficient data may represent a Gaussian function, a piecewise linear function, a sigmoid function, a thin plate spline function, a complex quadratic function, a cubic approximation, an inverse complex quadratic function, or a combination thereof. In some examples, some or all of the memory lookup units 414a-c, 418a-c may be deactivated. For example, one or more of the memory lookup units 414a-c, 418a-c may be operated as gain units with unity gain. In this case, instructions (e.g., executable instructions 415) may be executed to facilitate selecting a unity gain processing mode for some or all of the memory lookup units 414a-c, 418a-c.

[0041] Each of the multiplication units / accumulation units 412a-c, 416a-c may include multiple multipliers, multiple accumulation units, and / or multiple adders. Any of the multiplication units / accumulation units 412a-c, 416a-c may be implemented using an arithmetic logic unit (ALU). In some examples, any of the multiplication units / accumulation units 412a-c, 416a-c may include one multiplier and one adder that each perform multiple multiplications and multiple additions, respectively. The input-output relationship of the multiplication / accumulation units 412, 416 may be expressed as:

[0042]

[0043] where "I" represents the number of multiplications performed in the unit, C i represents a coefficient accessible from a memory such as memory 430, and B in (i) represents a factor from the input data X_1 / 2 / N(n) 410a to c or from the output of the multiplication unit / accumulation unit 412a to c, 416a to c. In the example, the output B of a group of multiplication units / accumulation units out Equal to coefficient data C i Multiply by the output B of another set of multiplication unit / accumulation unit in The sum of (i). in (i) It is also possible to make the output B of a set of multiplication units / accumulation units for input data out Equal to coefficient data C i Multiplies the sum of the input data.

[0044] Figure 5 is a flow chart illustrating a method 500 for training a neural network to pre-process a write data signal at a memory according to various embodiments. Figure 1 At least a portion of the semiconductor device 100 (eg, the pre-processing control circuit 125) and / or Figure 2 at least a portion of the system 200 (e.g., the training circuit 235, the pre-processing control circuit 220 and / or the pre-processing control logic 210), Figure 3 The neural network based preprocessing circuit 310 and / or Figure 4 The method 500 may be performed by the processing unit 405 of the embodiment of the present invention. In some examples, the pre-processing circuit, the memory cell array, and the input / output circuit (e.g., a receiver) may be part of a single semiconductor device (e.g., such as a memory or a processor) or a common (integrated) circuit. In other examples, the pre-processing circuit, the memory cell array, and the input / output circuit (e.g., a receiver) may be formed on separate devices or integrated circuits.

[0045] The method 500 includes, at 502 , generating a write data training data set based on characteristics of a write data channel of a memory, wherein the training data set includes a correlation between the write data for the channel and the characteristics of the write data channel.

[0046] Method 500 further includes, at 504, training a neural network of a write data pre-processing circuit of a memory using the write data training data set to determine a channel characteristic of the write data channel based on the write data of the write data channel. In some examples, the write data training data set is associated with a codeword of a memory. In some examples, method 500 further includes applying the trained neural network to determine the characteristic of the write data channel based on the write data, and modifying one or more coefficient values ​​of the neural network associated with the write data channel based on the determined channel characteristic.

[0047] In some examples, method 500 further includes generating a write data training data set using the write data, testing the trained neural network using the write data training data set, and retraining the trained neural network using a different training data set when the trained neural network does not exceed a threshold accuracy level.

[0048] Figure 6 is a flow chart illustrating a method 600 for preprocessing a write data signal at a memory using a neural network according to various embodiments. Figure 1 At least a portion of the semiconductor device 100 (eg, the pre-processing control circuit 125) and / or Figure 2 at least a portion of the system 200 (e.g., the pre-processing control circuit 220 and / or the pre-processing control logic 210), Figure 3 The neural network based preprocessing circuit 310 and / or Figure 4 The processing unit 405 executes the method 500.

[0049] The method 600 includes, at 602 , receiving write data at a receiver circuit of a memory via a data terminal.

[0050] The method 600 further includes, at 604, preprocessing a write data signal corresponding to the write data via a neural network of a preprocessing circuit of the memory based on a characteristic of a write data path to provide a modified write data signal. The write data path includes at least a propagation path of the write data as the write data travels from a data terminal receiving the write data through the semiconductor device to a physical storage device at the memory cell array (including input / output circuitry (e.g., buffers), read / write circuitry, sense amplifiers, transfer gates, etc.). In some examples, the method 600 further includes modifying the write data signal based on one or more coefficient values ​​selected according to the characteristic of the write data path. In some examples, the one or more coefficient values ​​are determined by writing test write data to the memory array during training of the neural network. In some examples, the method 600 further includes increasing the amplitude of the write data signal via the neural network to provide the modified write data signal. In some examples, the method 600 further includes decreasing the amplitude of the write data signal via the neural network to provide the modified write data signal. In some examples, the characteristic of the write data path includes capacitance, process variations of circuit components of the memory array, or any combination thereof.

[0051] The method 600 further includes, at 606, storing the write data at the memory array based on the modified write data signal.

[0052] Although certain features and aspects have been described with respect to exemplary embodiments, it will be appreciated by those skilled in the art that various modifications and additions may be made to the embodiments discussed without departing from the scope of the present disclosure. Although the embodiments described above relate to features, the scope of the present invention also includes embodiments with different combinations of features and embodiments that do not include all of the features described above. For example, the methods and processes described herein may be implemented using hardware components, software components, and / or any combination thereof. In addition, although the various methods and processes described herein may be described with respect to specific structural and / or functional components for ease of description, the methods provided by the various embodiments are not limited to any specific structural and / or functional architecture, but may be implemented in any suitable hardware, firmware, and / or software configuration. Similarly, although certain functionality is assigned to certain system components, unless the context otherwise dictates, this functionality may be distributed among various other system components according to several embodiments.

[0053] In addition, although the procedures of the methods and processes described herein are described in a particular order for ease of description, various procedures may be reordered, added, and / or omitted according to various embodiments. The procedures described with respect to a method or process may be incorporated into other described methods or processes; similarly, hardware components described according to a particular structural architecture and / or with respect to one system may be organized in an alternative structural architecture and / or incorporated into other described systems. Therefore, although various embodiments with or without certain features are described for ease of description, various components and / or features described herein with respect to specific embodiments may be combined, replaced, added, and / or subtracted from other described embodiments. Therefore, although several exemplary embodiments are described above, it should be understood that the present invention is intended to cover all modifications and equivalents within the scope of the following claims.

Claims

1. A device comprising: a receiver circuit configured to receive write data via a data terminal coupled to the data bus; a pre-processing circuit configured to receive a write data signal based on the write data, wherein a neural network of the pre-processing circuit is configured to pre-process the write data signal to provide a modified write data signal based on characteristics of a write data path including a propagation path of the write data from the data terminal through to the storage device at the memory cell; and A memory array is configured to store the write data at the memory cell based on the modified write data signal.

2. The apparatus of claim 1 , wherein the neural network is configured to modify the write-data signal based on one or more coefficient values ​​selected according to the characteristics of the write-data path.

3. The apparatus of claim 2, wherein the one or more coefficient values ​​are determined during training of the neural network by writing test write data to the memory array.

4. The apparatus of claim 2, wherein the neural network comprises a multiplication and accumulation unit configured to combine the write data signal and the one or more coefficient values.

5. The apparatus of claim 1, wherein the neural network is configured to cause an amplitude of the write-data signal to be adjusted to provide the modified write-data signal.

6. The apparatus of claim 1, wherein the neural network is configured to increase an amplitude of the write-data signal to provide the modified write-data signal.

7. The apparatus of claim 1, wherein the neural network is configured to reduce an amplitude of the write-data signal to provide the modified write-data signal.

8. The apparatus of claim 1, wherein the characteristic of the write data path comprises capacitance.

9. The apparatus of claim 1, wherein the characteristics of the write data path include process variations of circuit components of the memory array.

10. A method comprising: generating a write data training data set based on characteristics of a write data channel of a memory, wherein the training data set includes correlations between the write data for the channel and the characteristics of the write data channel; and A neural network of a write data preprocessing circuit of a memory is trained using the write data training data set to determine a channel characteristic of the write data channel based on the write data of the write data channel. The method of claim 10 , wherein the write data training data set is associated with a codeword of the memory.

12. The method according to claim 10, further comprising: applying the trained neural network to determine the characteristics of the write data channel based on the write data; and One or more coefficient values ​​of the neural network associated with the write data channel are modified based on the determined channel characteristics.

13. The method according to claim 10, further comprising: Using the written data to generate a written data training data set; testing the trained neural network using the written data training data set; and When the trained neural network does not exceed a threshold accuracy level, the trained neural network is retrained using a different training data set.

14. A method comprising: receiving write data at a receiver circuit of the memory via a data terminal; preprocessing, via a neural network of a preprocessing circuit of the memory, a write data signal corresponding to the write data based on characteristics of a write data path to provide a modified write data signal; and The write data is stored at a memory array based on the modified write data signal.

15. The method of claim 14, further comprising modifying the write data signal based on one or more coefficient values ​​selected according to the characteristics of the write data path.

16. The method of claim 15, wherein the one or more coefficient values ​​are determined during training of the neural network by writing test write data to the memory array.

17. The method of claim 14, further comprising increasing an amplitude of the write data signal via the neural network to provide the modified write data signal.

18. The method of claim 14, further comprising reducing an amplitude of the write data signal via the neural network to provide the modified write data signal.

19. The method of claim 14, wherein the characteristic of the write data path comprises capacitance.

20. The method of claim 14, wherein the characteristics of the write data path include process variations of circuit components of the memory array.

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