A method and apparatus for determining a quantum circuit cutpoint

Abstract

The application discloses a quantum circuit cutting point determination method and device. The method comprises the following steps: obtaining a quantum circuit to be cut, and generating a graph corresponding to the quantum circuit, wherein a vertex of the graph represents a quantum logic gate in the quantum circuit, and an edge of the graph represents a quantum bit segment connecting corresponding quantum logic gates in the quantum circuit; obtaining a Laplacian matrix corresponding to the graph; determining a sample to be clustered corresponding to the quantum circuit according to the Laplacian matrix; performing spectral clustering on the sample to be clustered to obtain a cutting point of the quantum circuit. According to the embodiment of the application, the quantum circuit to be cut is processed, the processing result is subjected to spectral clustering, and the cutting point is accurately and quickly determined based on the characteristics of spectral clustering.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of quantum circuit splitting, and particularly relates to a method and device for determining a quantum circuit cutting point. BACKGROUND

[0002] At present, although several hundred quantum bits of NISQ (Noisy Intermediate Scale Quantum) computers have been designed, due to the high noise level, the large-bit quantum circuit cannot be directly run. Meanwhile, for the future mature large-scale fault-tolerant quantum computers, the large-scale integration of quantum bits is affected by inherent problems such as control systems, bit arrangement modes and bit-to-bit crosstalk, and cannot be simply improved like classical integrated circuit chips. The quantum circuit splitting technology provides a feasible idea for solving the above problems. It splits the circuit into multiple small-bit and low-depth sub-circuits, each of which is independently run on a NISQ computer, and finally the output information of these sub-circuits is recombined to obtain the target information, achieving the purpose of simulating a large-scale quantum circuit using a small-scale quantum computer.

[0003] The key to the splitting of the quantum circuit lies in the determination of the cutting point. The determination method of the cutting point determines the accuracy and efficiency of the splitting of the quantum circuit, and is an important factor affecting the development of large-scale quantum circuits. Therefore, how to accurately and quickly determine the cutting point is a problem to be solved at present. SUMMARY

[0004] The purpose of the application is to provide a method and device for determining a quantum circuit cutting point. The quantum circuit to be cut is processed, the processing result is subjected to spectral clustering, and the cutting point is accurately and quickly determined based on the characteristics of spectral clustering.

[0005] One embodiment of the application provides a method for determining a quantum circuit cutting point, which comprises the following steps.

[0006] A quantum circuit to be cut is obtained, and a graph corresponding to the quantum circuit is generated, wherein a vertex of the graph represents a quantum logic gate in the quantum circuit, and an edge of the graph represents a quantum bit segment connecting corresponding quantum logic gates in the quantum circuit.

[0007] A Laplacian matrix corresponding to the graph is obtained.

[0008] According to the Laplacian matrix, a sample to be clustered corresponding to the quantum circuit is determined.

[0009] The sample to be clustered is subjected to spectral clustering to obtain a cutting point of the quantum circuit.

[0010] Optionally, the generation of the graph corresponding to the quantum circuit comprises:

[0011] numbering the quantum logic gates according to an execution sequence of the quantum logic gates in the quantum circuit;

[0012] generating a graph corresponding to the quantum circuit based on the numbering of the quantum logic gates and a relationship between the quantum logic gates, wherein the relationship is determined by quantum bits on which the corresponding quantum logic gates act.

[0013] Optionally, the obtaining the Laplacian matrix corresponding to the graph comprises:

[0014] generating an adjacency matrix corresponding to the graph by using the graph, wherein the adjacency matrix is composed of weights of edges in the graph;

[0015] obtaining the Laplacian matrix corresponding to the graph based on the adjacency matrix.

[0016] Optionally, the obtaining the Laplacian matrix corresponding to the graph based on the adjacency matrix comprises:

[0017] determining weights to be processed in the adjacency matrix based on a target transmission direction, wherein the target transmission direction comprises a transmission direction of quantum states in the quantum circuit;

[0018] adjusting the weights to be processed to obtain an adjusted adjacency matrix;

[0019] generating the Laplacian matrix corresponding to the graph by using the obtained adjusted adjacency matrix.

[0020] Optionally, the determining the weights to be processed in the adjacency matrix based on the obtained target transmission direction comprises:

[0021] determining edges of a potential cut in the graph by using the obtained target transmission direction, and taking weights corresponding to the edges as the weights to be processed in the adjacency matrix.

[0022] Optionally, the performing spectral clustering on the samples to be clustered to obtain the cut point of the quantum circuit comprises:

[0023] determining a target number according to a jump point determined by the samples to be clustered, wherein the target number is a number of clusters of spectral clustering;

[0024] performing spectral clustering on the samples to be clustered to obtain a clustering result composed of the target number of clusters;

[0025] determining the cut point of the quantum circuit based on the clustering result.

[0026] Yet another embodiment of the present application provides a device for determining a cut point of a quantum circuit, the device comprising:

[0027] a generating module configured to obtain a quantum circuit to be cut and generate a graph corresponding to the quantum circuit, wherein a vertex of the graph represents a quantum logic gate in the quantum circuit and an edge of the graph represents a quantum bit segment connecting corresponding quantum logic gates in the quantum circuit;

[0028] a first obtaining module configured to obtain a Laplacian matrix corresponding to the graph;

[0029] a determining module configured to determine a sample to be clustered corresponding to the quantum circuit according to the Laplacian matrix;

[0030] a second obtaining module configured to perform spectral clustering on the sample to be clustered to obtain a cut point of the quantum circuit.

[0031] Yet another embodiment of the present application provides a quantum super-collaborative operating system, which determines a quantum circuit cut point according to the method in any of the above.

[0032] Yet another embodiment of the present application provides a storage medium having a computer program stored therein, wherein the computer program is configured to implement the method in any of the above when executed.

[0033] Yet another embodiment of the present application provides an electronic device comprising a memory and a processor, wherein the memory has a computer program stored therein and the processor is configured to execute the computer program to implement the method in any of the above.

[0034] Compared with the prior art, the present application first obtains a quantum circuit to be cut and generates a graph corresponding to the quantum circuit, then obtains a Laplacian matrix corresponding to the graph, and then determines a sample to be clustered corresponding to the quantum circuit according to the Laplacian matrix, and finally performs spectral clustering on the sample to be clustered to obtain a cut point of the quantum circuit. By processing the quantum circuit to be cut and performing spectral clustering on the processing result, the cut point is accurately and quickly determined based on the characteristics of spectral clustering. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 is a network block diagram of a quantum circuit cut point determination system provided by an embodiment of the present application;

[0036] Figure 2 is a flowchart of a quantum circuit cut point determination method provided by an embodiment of the present application;

[0037] Figure 3 is a structural diagram of a quantum circuit provided by an embodiment of the present application;

[0038] Figure 4 A schematic diagram of a quantum circuit according to an embodiment of the present application is provided;

[0039] Figure 5 A schematic diagram of a graph corresponding to a quantum circuit according to an embodiment of the present application is provided;

[0040] Figure 6 A schematic diagram of a target transmission direction according to an embodiment of the present application is provided;

[0041] Figure 7 A schematic diagram of a graph corresponding to a quantum circuit according to an embodiment of the present application is provided;

[0042] Figure 8 A schematic diagram of a quantum circuit with a cutting point according to an embodiment of the present application is provided;

[0043] Figure 9 A schematic diagram of a quantum circuit cutting point determination device according to an embodiment of the present application is provided. DETAILED DESCRIPTION

[0044] The embodiments described below are exemplary and are intended to explain the present application, but should not be interpreted as limiting the present application.

[0045] Figure 1 A network block diagram of a quantum circuit cutting point determination system according to an embodiment of the present application is provided. The quantum circuit cutting point determination system can include a network 110, a server 120, a wireless device 130, a client 140, a storage unit 150, a classical processing system 160, a quantum processing system 170, and can also include additional storage, classical processors, quantum processors and other devices not shown.

[0046] The network 110 is a medium for providing communication links between various devices and computers connected together in the quantum circuit cutting point determination system, including but not limited to the Internet, an intranet, a local area network, a mobile communication network and combinations thereof, and the connection can be made by wired, wireless communication links or optical fiber cables, etc.

[0047] The server 120 and the client 140 are conventional data processing systems that can contain data and have applications or software tools that perform conventional computing processes. The client 140 can be a personal computer or a network computer, so the data can also be provided by the server 120. The wireless device 130 can be a smartphone, a tablet, a notebook computer, a smart wearable device, etc. The storage unit 150 can include a database 151, which can be configured to store quantum bit parameters, quantum logic gate parameters, quantum circuits, quantum programs, etc.

[0048] The classical processing system 160 (quantum processing system 170) can include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 163 (memory 172) for storing classical data (quantum data), which can be a boot file, an operating system image, and an application program 162 (application program 173), which can be used to implement a quantum algorithm compiled by the method for determining a quantum circuit cutting point provided by the embodiments of the present application.

[0049] Any data or information stored or generated in the classical processing system 160 (quantum processing system 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application program executed by it can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0050] It should be noted that a real quantum computer is a hybrid structure, which at least includes Figure 1 two parts: a classical processing system 160 responsible for performing classical computation and control; and a quantum processing system 170 responsible for running a quantum program to implement quantum computation.

[0051] The classical processing system 160 and the quantum processing system 170 described above can be integrated in one device or distributed in two different devices. For example, a first device including the classical processing system 160 runs a classical computer operating system, on which quantum application development tools and services are provided, and storage and network services required by quantum application programs are also provided. A user develops a quantum application program through the quantum application development tools and services thereon, and sends the quantum program to a second device including the quantum processing system 170 through the network services thereon. The second device runs a quantum computer operating system, which parses the code of the quantum program and compiles it into instructions that can be recognized and executed by the quantum computer control system, and the quantum processor 170 implements the quantum algorithm corresponding to the quantum program according to the instructions.

[0052] In a classical processing system 160 based on a silicon chip, the unit of the classical processor 161 is a CMOS tube, and such a computing unit is not limited by time and coherence, i.e., such a computing unit is not limited by the length of use and is available at any time. In addition, in a silicon chip, the number of such computing units is also sufficient, and the number of computing units in a classical processor is currently in the thousands. The number of computing units is sufficient and the computing logic of the CMOS tube is fixed, such as AND logic. When operating with CMOS tubes, a large number of CMOS tubes are combined with limited logic functions to achieve the effect of operation.

[0053] Unlike the logical units in the classical processing system 160, the basic computing unit of the quantum processor 171 in the quantum processing system 170 is a quantum bit, and the input of the quantum bit is limited by coherence and coherence time, that is, the quantum bit is limited by the use time and is not available at any time. It is a key problem of quantum computing to fully use the quantum bit within the available use time of the quantum bit. In addition, the number of quantum bits in a quantum computer is one of the representative indicators of the performance of the quantum computer, and each quantum bit realizes a computing function through a logically configured function, and given the limited number of quantum bits and the diversified logical functions in the field of quantum computing, such as: Hadamard gate (H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), X gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, Toffoli gate, and the like. In quantum computing, the operation effect is realized by combining the limited quantum bits with the diversified logical functions.

[0054] A quantum program corresponds to a total quantum circuit as a whole, and the total number of quantum bits in the quantum circuit is the same as the total number of quantum bits of the quantum program. A quantum circuit can include quantum bits and tens, hundreds, or even thousands of quantum logic gates. The operation of a quantum circuit is a process in which all quantum logic gates evolve quantum states according to a certain execution time sequence. It should be noted that the execution time sequence is the time sequence in which the quantum logic gates are executed.

[0055] Based on these differences, the design of the logical function acting on the quantum bit (including the design of whether to use the quantum bit and the design of the use efficiency of each quantum bit) is the key to improving the operation performance of the quantum computer, and special design is required. The above design for quantum bits is a technical problem that ordinary computing devices do not need to consider and face. Based on this, in order to determine the cutting point of the quantum circuit in quantum computing and improve the accuracy and efficiency of quantum circuit splitting, the present application provides a method for determining the cutting point of a quantum circuit, which aims to process the quantum circuit to be cut and determine the cutting point by spectral clustering of the processing result, thereby improving the accuracy and efficiency of quantum circuit splitting.

[0056] Referring to Figure 2 , Figure 2 A flowchart of a method for determining a cutting point of a quantum circuit provided by an embodiment of the present application can include the following steps:

[0057] S201: Obtain a quantum circuit to be cut, and generate a graph corresponding to the quantum circuit to be cut, wherein the vertices of the graph represent quantum logic gates in the quantum circuit, and the edges of the graph represent quantum bit segments connecting corresponding quantum logic gates in the quantum circuit.

[0058] The quantum circuit to be cut can be obtained by quantum application development tools and services provided by a classical processing system, or can be received from other devices. The quantum circuit to be cut is processed so that the quantum circuit is converted into a corresponding graph, which can be a graph for spectral clustering, and specifically can be an undirected graph or a directed acyclic graph. If two quantum logic gates are adjacent in the execution time sequence in the quantum circuit to be cut, and there is a common quantum bit, there is an edge between the two vertices.

[0059] The quantum circuit includes quantum bits, timelines, and quantum logic gates. One timeline corresponds to one quantum bit, and one timeline is divided into multiple segments due to the action of quantum logic gates. These segments are referred to as quantum bit segments. A quantum bit segment includes a timeline corresponding to a quantum bit acted on by two quantum logic gates, a timeline between the input end of a quantum bit and a quantum logic gate, and a timeline between a quantum logic gate and the output end of a quantum bit. For example, as shown in FIG. 1, one quantum bit corresponds to multiple quantum bit segments, q0 corresponds to quantum bit segment A and quantum bit segment B, q1 corresponds to quantum bit segment C, quantum bit segment D, and quantum bit segment E, and q2 corresponds to quantum bit segment F and quantum bit segment G. Figure 3

[0060] In actual splitting, only quantum bit segments connected to two-bit quantum logic gates at both ends can be of interest. The quantum bit segment corresponds to an edge in the graph, that is, the edge in the graph corresponds to a timeline of a quantum bit acted on by two quantum logic gates. For example, as shown in FIG. 2, only quantum bit segment D has a corresponding edge in the graph. If there are other quantum logic gates acting after quantum logic gate U2, the edges in the generated graph can include one or more of quantum bit segments B, E, and G, and specifically are determined by the quantum bits acted on by quantum logic gate U2. The cutting point of the quantum circuit is located on the quantum bit segment. When a quantum bit segment has a cutting point, the quantum bit segment is cut into two quantum bit segments. Figure 3

[0061] S202: Obtain a Laplacian matrix corresponding to the graph.

[0062] The graph is converted into a corresponding matrix, the rows and columns of the matrix represent the vertices of the graph, and the elements in the matrix are determined by the edges of the graph. Further processing of the matrix can obtain a Laplacian matrix.

[0063] S203: Determine the samples to be clustered corresponding to the quantum circuit according to the Laplacian matrix.

[0064] ​​The eigenvectors of the Laplacian matrix are calculated, and the eigenvectors can be calculated in a manner using standard linear algebra methods, for example, the Lanczos algorithm (an algorithm named after the Hungarian mathematician Lanczos, which transforms a symmetric matrix into a symmetric tridiagonal matrix through orthogonal similarity transformation) can be used to achieve fast solution, and the final eigenvectors can be used as the samples to be clustered. It should be noted that the Laplacian matrix can be a normalized Laplacian matrix.

[0065] S204: performing spectral clustering on the samples to be clustered to obtain the cut point of the quantum circuit.

[0066] The spectral clustering is performed on the samples to be clustered to obtain a clustering result, and the cut point of the quantum circuit can be obtained based on the clustering result.

[0067] As can be seen, the quantum circuit to be cut is obtained first, and a graph corresponding to the quantum circuit is generated; then a Laplacian matrix corresponding to the graph is obtained; then the samples to be clustered corresponding to the quantum circuit are determined according to the Laplacian matrix; finally, the spectral clustering is performed on the samples to be clustered to obtain the cut point of the quantum circuit. By processing the quantum circuit to be cut and performing spectral clustering on the processing result, the cut point is accurately and quickly determined based on the characteristics of the spectral clustering.

[0068] In some possible embodiments of the present application, the graph corresponding to the quantum circuit is generated by:

[0069] The quantum logic gates are numbered according to the execution time sequence of the quantum logic gates in the quantum circuit;

[0070] The graph corresponding to the quantum circuit is generated based on the numbering of the quantum logic gates and the relationship between the quantum logic gates, wherein the relationship is determined by the quantum bits acted on by the corresponding quantum logic gates.

[0071] The execution time sequence of the quantum logic gates in the quantum circuit can be predetermined or divided according to a preset rule. The quantum logic gates in one execution time sequence are numbered first, and then the quantum logic gates in the next execution time sequence are numbered. For the same execution time sequence, the quantum logic gates can be numbered from the quantum logic gate acting on the low-order quantum bit, or from the quantum logic gate acting on the high-order quantum bit, as long as the numbering is performed according to a certain rule. For example, the quantum circuit numbered according to the execution time sequence can be as shown in Figure 4 The quantum circuit is a random Clifford circuit, and only quantum bits and two-bit U gates exist in the quantum circuit at this time. The dashed line in the graph represents the division of the execution time sequence.

[0072] The relationship between quantum logic gates can be a sequential dependence relationship of the quantum logic gates. When quantum logic gates of adjacent execution sequences have common quantum bits, it indicates that the execution of the two quantum logic gates has a dependence relationship, and the next quantum logic gate needs to be executed after the execution of the previous quantum logic gate. Therefore, there is an edge between the vertices corresponding to the two quantum logic gates in the graph. According to this rule, the generated Figure 3 The graph corresponding to the quantum circuit shown in FIG. 6 can be as shown in FIG. 7. Figure 5 The dashed line indicates that the corresponding quantum logic gate acts on the highest bit quantum bit or the lowest bit quantum bit.

[0073] In some possible embodiments of the present application, the obtaining of the Laplacian matrix corresponding to the graph comprises:

[0074] The graph is used to generate an adjacency matrix corresponding to the graph, wherein the adjacency matrix is composed of the weights of the edges in the graph.

[0075] The Laplacian matrix corresponding to the graph is obtained based on the adjacency matrix.

[0076] The adjacency matrix, which can also be referred to as a weight matrix, is an n x n symmetric matrix composed of vertices and weights between vertices. The weight between vertices is the weight of the edge connecting the vertices, and the weight of the edge is determined according to a preset rule. The generated Figure 4 The corresponding adjacency matrix W can be an upper triangular matrix as shown below:

[0077]

[0078] The Laplacian matrix is constructed based on the adjacency matrix and the degree matrix. The degree matrix is a diagonal matrix, and the diagonal elements of the degree matrix can be where w ij is the element in the i-th row and the j-th column of the adjacency matrix. Of course, the diagonal elements of the adjacency matrix can also be directly used as the elements in the degree matrix. The relationship between the Laplacian matrix and the adjacency matrix and the degree matrix can be L = D-W, where L is the Laplacian matrix, and D is the degree matrix.

[0079] In some possible embodiments of the present application, the obtaining of the Laplacian matrix corresponding to the graph based on the adjacency matrix comprises:

[0080] Based on the target transmission direction, the weight to be processed in the adjacency matrix is determined, wherein the target transmission direction includes the transmission direction of the quantum state in the quantum circuit.

[0081] The weight to be processed is adjusted to obtain an adjacency matrix after the weight adjustment.

[0082] A Laplacian matrix corresponding to the graph is generated by using the obtained adjusted adjacency matrix.

[0083] The target transmission direction can be determined according to the transmission direction of the quantum information flow. For the quantum circuit to be cut in the present application, there can be only one target transmission direction. In this case, the quantum circuit can be an original quantum circuit or a quantum circuit obtained after cutting the original quantum circuit and needing further cutting. When the quantum circuit to be cut has multiple transmission directions, the quantum circuit to be cut can be segmented, and the target transmission direction of each segmented quantum circuit can be determined.

[0084] When the target transmission direction is determined, the edges whose weights are to be reduced or to be increased can be determined from the graph, and then the weights to be processed in the adjacency matrix, i.e., the elements to be processed in the adjacency matrix, can be determined. By a preset rule, the weights to be processed are adjusted to obtain an adjusted adjacency matrix. Each weight to be processed can be reduced by the same proportion or by the same value. Of course, different adjustment rules can be set for different weights to be processed. Based on the above example, when each weight to be processed is reduced by the same proportion, the adjusted adjacency matrix W' can be as follows:

[0085]

[0086] In the present application, by selectively changing the weights of the quantum bit segments (edges) connected to any U gate in the quantum circuit, the accuracy and efficiency of quantum circuit splitting can be improved, and the balance of the number of quantum bits and two-bit quantum logic gates in quantum circuit splitting can be improved, thereby improving the splitting effect and promoting the application of quantum circuit splitting technology.

[0087] In some possible embodiments of the present application, the determination of the weights to be processed in the adjacency matrix based on the target transmission direction comprises:

[0088] The edges to be potentially cut are determined from the graph by using the target transmission direction, and the weights of the edges are taken as the weights to be processed in the adjacency matrix.

[0089] For example, a target transmission direction can be as shown in Figure 6 The direction of the arrow in the graph is the target transmission direction, A, B, C, and D are four quantum bit segments, and the corresponding Figure 5 may become as shown in Figure 7 The edges pointing in the same direction as the target transmission direction are the edges to be potentially cut, i.e. Figure 7The edges with arrows are potential cutting edges, and the edges corresponding to the dashed lines are also potential cutting edges. The non-potential cutting edge is an edge opposite to the target transmission direction, and increasing the weight of the non-potential cutting edge is equivalent to reducing the weight of the potential cutting edge. By reducing the weight of the potential cutting edge or increasing the weight of the non-potential cutting edge, the nested circuit splitting mode can be effectively avoided, and the number of split sub-circuits can be more easily determined.

[0090] In some possible embodiments of the present application, the spectrum clustering of the to-be-clustered sample is performed to obtain the cutting point of the quantum circuit, including:

[0091] The target number is determined according to the jumping point determined by the to-be-clustered sample, wherein the target number is the number of clusters of the spectrum clustering;

[0092] The spectrum clustering of the to-be-clustered sample is performed to obtain a clustering result composed of target number of clusters;

[0093] The cutting point of the quantum circuit is determined based on the clustering result.

[0094] Because the connection degrees between two-bit quantum logic gates of different types of quantum circuits are different, the number of cutting points is also different. However, quantum circuit splitting is to simulate and combine quantum channels with classical channels, and too many cutting points have a great impact on the efficiency of quantum circuit execution, so before quantum circuit splitting, it is necessary to determine the number of sub-circuits that the quantum circuit can be split into and the splitting difficulty, that is, the number of cutting points. The number of sub-circuits can be determined by the to-be-clustered sample, and the first jump of the to-be-clustered sample arranged from small to large is specifically determined, and the number of to-be-clustered samples before the jump is determined as the target number, that is, the number k of sub-circuits obtained by splitting. The more the jump, the better the sub-circuit is split, and therefore, adjusting the weight of the adjacency matrix can help to find a more explicit k value.

[0095] The value of k determines the number of clusters, and the obtained clustering result includes k clusters. The k clusters are processed to determine the cutting point. For example, the clustering result of the quantum circuit shown in Figure 3 is (1, 2, 4, 6) and (3, 5, 7, 8), and two cutting points can be as shown in Figure 8 The cutting points are represented by crosses in the figure.

[0096] Referring to Figure 9 , Figure 9 A structure diagram of a quantum circuit cutting point determination device provided by an embodiment of the present application, and Figure 2 corresponding to the flow shown in

[0097] The generating module 901 is configured to obtain a quantum circuit to be cut and generate a graph corresponding to the quantum circuit, wherein a vertex of the graph represents a quantum logic gate in the quantum circuit, and an edge of the graph represents a quantum bit segment connecting corresponding quantum logic gates in the quantum circuit.

[0098] The first obtaining module 902 is configured to obtain a Laplacian matrix corresponding to the graph.

[0099] The determining module 903 is configured to determine a sample to be clustered corresponding to the quantum circuit according to the Laplacian matrix.

[0100] The second obtaining module 904 is configured to perform spectral clustering on the sample to be clustered to obtain a cut point of the quantum circuit.

[0101] In some possible implementation manners of the present application, the generating module 901 can be specifically configured to:

[0102] number the quantum logic gates according to an execution time sequence of the quantum logic gates in the quantum circuit;

[0103] generate the graph corresponding to the quantum circuit based on the numbers of the quantum logic gates and a relationship between the quantum logic gates, wherein the relationship is determined by quantum bits acted on by the corresponding quantum logic gates.

[0104] In some possible implementation manners of the present application, the first obtaining module 902 can include:

[0105] A generating unit is configured to generate an adjacency matrix corresponding to the graph by using the graph, wherein the adjacency matrix is composed of weights of edges in the graph.

[0106] An obtaining unit is configured to obtain the Laplacian matrix corresponding to the graph based on the adjacency matrix.

[0107] In some possible implementation manners of the present application, the obtaining unit can be specifically configured to:

[0108] determine a weight to be processed in the adjacency matrix based on a target transmission direction, wherein the target transmission direction includes a transmission direction of a quantum state in the quantum circuit.

[0109] adjust the weight to be processed to obtain an adjacency matrix with adjusted weights.

[0110] generate the Laplacian matrix corresponding to the graph by using the obtained adjacency matrix with adjusted weights.

[0111] In some possible implementation manners of the present application, the obtaining unit can be specifically configured to:

[0112] Determine edges of potential cuts from the graph using the target transmission direction, and take the weights corresponding to the edges as weights to be processed in the adjacency matrix.

[0113] In some possible embodiments of the present application, the second obtaining module 904 can be specifically configured to:

[0114] Determine a target number according to the jump point determined by the samples to be clustered, wherein the target number is the number of clusters of spectral clustering;

[0115] Perform spectral clustering on the samples to be clustered to obtain a clustering result composed of target-number clusters;

[0116] Determine the cut point of the quantum circuit based on the clustering result.

[0117] It can be seen that the present application first obtains a quantum circuit to be cut and generates a graph corresponding to the quantum circuit; then obtains a Laplacian matrix corresponding to the graph; then determines samples to be clustered corresponding to the quantum circuit according to the Laplacian matrix; and finally performs spectral clustering on the samples to be clustered to obtain a cut point of the quantum circuit. By processing the quantum circuit to be cut and performing spectral clustering on the processing result, the cut point is accurately and quickly determined based on the characteristics of spectral clustering.

[0118] The present application also provides a quantum super-collaborative operating system, which runs on a quantum computer including a quantum processor and / or a supercomputer including a classical processor, and is used to determine a cut point of a quantum circuit according to the method of the method embodiment of the present application.

[0119] The present application also provides a storage medium in which a computer program is stored, wherein the computer program is configured to implement the steps in any of the method embodiments when running.

[0120] Specifically, in the present embodiment, the above storage medium can be configured to store a computer program for implementing the following steps:

[0121] S201: Obtain a quantum circuit to be cut and generate a graph corresponding to the quantum circuit, wherein a vertex of the graph represents a quantum logic gate in the quantum circuit, and an edge of the graph represents a quantum bit segment connecting corresponding quantum logic gates in the quantum circuit;

[0122] S202: Obtain a Laplacian matrix corresponding to the graph;

[0123] S203: Determine samples to be clustered corresponding to the quantum circuit according to the Laplacian matrix;

[0124] S204: performing spectral clustering on the to-be-clustered sample to obtain a cut point of the quantum circuit.

[0125] The embodiment of the present application further provides an electronic device, including a memory and a processor, the memory stores a computer program, and the processor is arranged to run the computer program to realize the steps in any one of the method embodiments.

[0126] Specifically, the electronic device can further include a transmission device and an input and output device, wherein the transmission device is connected with the processor, and the input and output device is connected with the processor.

[0127] Specifically, in the embodiment, the processor can be arranged to realize the following steps through the computer program:

[0128] S201: obtaining a quantum circuit to be cut and generating a graph corresponding to the quantum circuit, wherein a vertex of the graph represents a quantum logic gate in the quantum circuit, and an edge of the graph represents a quantum bit segment connecting corresponding quantum logic gates in the quantum circuit;

[0129] S202: obtaining a Laplacian matrix corresponding to the graph;

[0130] S203: determining a to-be-clustered sample corresponding to the quantum circuit according to the Laplacian matrix;

[0131] S204: performing spectral clustering on the to-be-clustered sample to obtain a cut point of the quantum circuit.

[0132] The embodiment of the present application further provides a computer program product including instructions, which are executed by a computer to make the computer execute the determination of the cut point of the quantum circuit in any one of the embodiments.

[0133] It can be understood that, in various embodiments of the present application, the size of the serial number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0134] It can be understood that the various embodiments described in the present application can be implemented alone or in combination, and the embodiments of the present application do not limit this.

[0135] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this specification belongs. The terminology used in the specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. As used in this specification, the terms "may" and "can" include any one of, or a combination of, the corresponding inexcitables. As used in this specification and the appended claims, the singular forms "a," "an" and "the" include plural referents unless the context clearly dictates otherwise.

[0136] It can be understood that the processor in the embodiments of the present specification can be an integrated circuit chip with processing capability of signals. In the implementation process, each step of the method embodiments described above can be completed by integrated logic circuits or instructions in the form of software in the processor. The processor described above can be a general processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. Each method, step and logic block diagram disclosed in the embodiments of the present specification can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor or the like. The steps of the method disclosed in combination with the embodiments of the present specification can be directly embodied as a hardware coding processor to execute, or a combination of hardware and software modules in the coding processor. The software module can be located in a storage medium in the art such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, register, etc. The storage medium is located in the storage, and the processor reads the information in the storage, and combines the hardware to complete the steps of the above method.

[0137] It can be understood that the memory in the embodiments of the present specification can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) or flash memory. The volatile memory can be random access memory (RAM). It should be noted that the memory of the system and method described herein is intended to include but not limited to these and any other suitable type of memory.

[0138] Those skilled in the art can clearly understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present specification.

[0139] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0140] In several embodiments provided in the present specification, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are merely schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0141] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, i.e. can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the present embodiment.

[0142] In addition, each functional unit in each embodiment of the present specification can be integrated into one processing unit, or each unit can exist physically independently, or two or more units can be integrated into one unit.

[0143] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present specification or the parts of the technical solutions that essentially contribute to the prior art or the parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present specification. The aforementioned storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0144] The above is only a specific embodiment of the present specification, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present specification, which should be covered within the protection scope of the present specification. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for determining the cutting point of a quantum circuit, characterized in that, The method comprises: obtaining a quantum circuit to be cut, and generating a graph corresponding to the quantum circuit, wherein a vertex of the graph represents a quantum logic gate in the quantum circuit, and an edge of the graph represents a quantum bit segment connecting corresponding quantum logic gates in the quantum circuit; using the graph, generating an adjacency matrix corresponding to the graph, wherein the adjacency matrix is composed of weights of edges in the graph; based on a target transmission direction, determining weights to be processed in the adjacency matrix; adjusting the weights to be processed to obtain an adjusted adjacency matrix; using the obtained adjusted adjacency matrix, generating a Laplacian matrix corresponding to the graph; wherein the target transmission direction includes a transmission direction of a quantum state in the quantum circuit; determining, according to the Laplacian matrix, a sample to be clustered corresponding to the quantum circuit; determining a target number according to a jump point determined by the sample to be clustered; performing spectral clustering on the sample to be clustered to obtain a clustering result composed of a target number of clusters; and determining a cutting point of the quantum circuit based on the clustering result, wherein the target number is the number of clusters of spectral clustering.

2. The method of claim 1, wherein, The method for generating the graph corresponding to the quantum circuit comprises: numbering the quantum logic gates according to an execution time sequence of the quantum logic gates in the quantum circuit; based on the numbering of the quantum logic gates and a relationship between the quantum logic gates, generating a graph corresponding to the quantum circuit, wherein the relationship is determined by quantum bits acted on by corresponding quantum logic gates.

3. The method of claim 1, wherein, The method for determining the weights to be processed in the adjacency matrix based on the target transmission direction comprises: using the target transmission direction to determine edges of potential cuts in the graph, and taking weights corresponding to the edges as the weights to be processed in the adjacency matrix.

4. A device for determining the cutting point of a quantum circuit, characterized in that, The device comprises: a generating module configured to obtain a quantum circuit to be cut, and generate a graph corresponding to the quantum circuit, wherein a vertex of the graph represents a quantum logic gate in the quantum circuit, and an edge of the graph represents a quantum bit segment connecting corresponding quantum logic gates in the quantum circuit; a first obtaining module configured to use the graph to generate an adjacency matrix corresponding to the graph, wherein the adjacency matrix is composed of weights of edges in the graph; based on a target transmission direction, determine weights to be processed in the adjacency matrix; adjust the weights to be processed to obtain an adjusted adjacency matrix; and use the obtained adjusted adjacency matrix to generate a Laplacian matrix corresponding to the graph; wherein the target transmission direction includes a transmission direction of a quantum state in the quantum circuit; a determining module configured to determine, according to the Laplacian matrix, a sample to be clustered corresponding to the quantum circuit; a second obtaining module configured to determine a target number according to a jump point determined by the sample to be clustered; perform spectral clustering on the sample to be clustered to obtain a clustering result composed of a target number of clusters; and determine a cutting point of the quantum circuit based on the clustering result, wherein the target number is the number of clusters of spectral clustering.

5. A quantity super-synergetic operating system, characterized in that, The super-collaborative operating system determines the cutting point of the quantum circuit according to the method in any one of claims 1 to 3.

6. A storage medium, characterized by The storage medium stores a computer program, and the computer program is configured to implement the method in any one of claims 1 to 3 when executed. 7.An electronic device comprising a memory and a processor, the electronic device characterized by, The memory stores a computer program, and the processor is configured to execute the computer program to implement the method in any one of claims 1 to 3.

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