Display panel, driving method thereof and display device

Abstract

The invention provides a display panel, a driving method thereof and a display device, and belongs to the technical field of display. The display panel comprises the shift register unit and the compensation circuit which are located on the two sides of the substrate in the pixel row direction, the shift register unit can output the light emitting driving signal to one row of pixels, and the compensation circuit can output the driving compensation signal to the same row of pixels. Therefore, the light-emitting driving signal received by the far-end pixel which is far away from the shift register unit can be compensated through the driving compensation signal. And far-end pixels far from the shift register unit and near-end pixels close to the shift register unit in the row of pixels can emit light under the driving of the same or similar driving signals. Furthermore, the uniformity of the luminance of each pixel in a row of pixels can be ensured to be relatively good, so that the display uniformity of the display panel is ensured to be relatively good.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a driving method thereof, and a display device. Background Art

[0002] In a display panel, a gate driving circuit is usually used to transmit a gate driving signal to a plurality of rows of pixels to drive the plurality of rows of pixels to emit light.

[0003] In the related art, the gate drive circuit is mostly integrated into the display panel using the gate drive on array (GOA) technology to facilitate the design of narrow frame. Correspondingly, the gate drive circuit is also called the GOA circuit. The GOA circuit generally includes a plurality of cascaded shift register units (also called GOA units). In addition, the plurality of GOA units are all located on the same side of the multiple rows of pixels, and are connected to the multiple rows of pixels through a plurality of gate lines to transmit gate drive signals to the multiple rows of pixels. That is, currently, single-sided gate drive is mostly used.

[0004] However, due to the RC delay (i.e., signal delay caused by resistance and capacitance) on the gate line, the potential of the gate drive signal transmitted to the pixel close to the GOA unit is different from the potential of the gate drive signal transmitted to the pixel far away from the GOA unit, which leads to poor display uniformity of the display panel. Summary of the invention

[0005] Provided are a display panel and a driving method thereof, and a display device, which can solve the problem of poor display uniformity of the display panel in the related art. The technical solution is as follows:

[0006] In one aspect, a display panel is provided, the display panel comprising:

[0007] a substrate having a display area and a peripheral area at least partially surrounding the display area;

[0008] A plurality of pixels arranged in an array are located in the display area;

[0009] A plurality of cascaded shift register units are located in the peripheral area and connected to a plurality of rows of pixels, and each of the shift register units is connected to at least one row of pixels in the plurality of rows of pixels, and each of the shift register units is also respectively connected to a plurality of first control lines and a first clock line, and is used to control the on-off of the first clock line and the at least one row of pixels connected thereto in response to a first control signal provided by the plurality of first control lines, so as to output a light-emitting drive signal to the at least one row of pixels connected thereto;

[0010] A plurality of compensation circuits, located in the peripheral area, connected to the plurality of rows of pixels, each of the compensation circuits being connected to at least one row of pixels in the plurality of rows of pixels, and each of the compensation circuits being connected to a second control line and a second clock line, respectively, and being used to control the on-off of the second clock line and the at least one row of pixels connected thereto in response to a second control signal provided by the second control line, so as to output a driving compensation signal to the at least one row of pixels connected thereto;

[0011] Among them, at least one shift register unit among the multiple shift register units and at least one compensation circuit among the multiple compensation circuits are respectively located on both sides of the substrate in the pixel row direction, and a shift register unit and a compensation circuit connected to the same row of pixels are respectively located on the two sides.

[0012] Optionally, each of the shift register units and each of the compensation circuits are connected to at least one row of pixels in the plurality of rows of pixels via a gate line, and a shift register unit and a compensation circuit connected to the same row of pixels share the gate line;

[0013] The light-emitting driving signal is a gate driving signal transmitted via the gate line, and the driving compensation signal is a gate driving compensation signal transmitted via the gate line.

[0014] Optionally, the plurality of shift register units are connected to the plurality of rows of pixels in a one-to-one correspondence; and the plurality of compensation circuits are connected to the plurality of rows of pixels in a one-to-one correspondence.

[0015] Optionally, the second control line connected to the nth compensation circuit is connected to the n+ith shift register unit, and the second control signal is a light-emitting driving signal output by the n+ith shift register unit;

[0016] wherein the effective potential transition edge of the first clock signal provided by the first clock line connected to the n+i-th shift register unit is aligned with the effective potential transition edge of the second clock signal provided by the second clock line connected to the n-th compensation circuit, and the effective potential of the second clock signal provided by the second clock line connected to the n-th compensation circuit is within the effective potential of the first clock signal provided by the first clock line connected to the n+i-th shift register unit, and is within the effective potential of the first clock signal provided by the first clock line connected to the n-th shift register unit;

[0017] Furthermore, the nth compensation circuit refers to a compensation circuit connected to the nth row of pixels, the n+ith shift register unit refers to a shift register unit connected to the n+ith row of pixels, the nth shift register unit refers to a shift register unit connected to the nth row of pixels, n is an integer greater than 0, and i is an integer greater than or equal to 0; and the potential of the first clock signal is a valid potential and the potential of the second clock signal is a valid potential for driving the pixel to emit light, the potential of the first clock signal is an invalid potential and the potential of the second clock signal is an invalid potential for stopping driving the pixel to emit light, and the effective potential transition edge is a transition edge from an invalid potential to a valid potential.

[0018] Optionally, i is 2.

[0019] Optionally, among the plurality of shift register units, a portion of the shift register units are located on a first side of the two sides, and the remaining shift register units except the portion of the shift register units are located on a second side of the two sides;

[0020] Among the plurality of compensation circuits, a portion of the compensation circuits are located on a first side of the two sides, and the remaining compensation circuits except the portion of the compensation circuits are located on a second side of the two sides.

[0021] Optionally, among the plurality of shift register units, each shift register unit connected to pixels in odd rows is located on the first side, and each shift register unit connected to pixels in even rows is located on the second side;

[0022] Among the plurality of compensation circuits, the compensation circuits connected to the pixels in even rows are located on the first side, and the compensation circuits connected to the pixels in odd rows are located on the second side.

[0023] Optionally, the shift register units and the compensation circuits located on the first side are arranged alternately in the order of one shift register unit and one compensation circuit in the direction of the pixel column;

[0024] The shift register units and the compensation circuits located on the second side are arranged alternately in the order of one compensation circuit and one shift register unit in the direction of the pixel columns.

[0025] Optionally, the plurality of shift register units are all located on a first side of the two sides, and the plurality of compensation circuits are all located on a second side of the two sides.

[0026] Optionally, the compensation circuit comprises: a compensation transistor;

[0027] A gate of the compensation transistor is connected to the second control line, a first electrode of the compensation transistor is connected to the second clock line, and a second electrode of the compensation transistor is connected to the at least one row of pixels.

[0028] Optionally, the shift register unit is a shift register unit of a 22T1C architecture, where the 22T1C architecture refers to an architecture including 22 transistors and 1 capacitor.

[0029] Optionally, among the multiple shift register units, each shift register unit located on the same side is alternately connected to at least two first clock lines; among the multiple compensation circuits, each compensation circuit located on the same side is alternately connected to at least two second clock lines; and the number of the at least two second clock lines is less than the number of the at least two first clock lines.

[0030] Optionally, among the plurality of shift register units, each shift register unit located on the same side is alternately connected to four first clock lines;

[0031] Among the plurality of compensation circuits, each compensation circuit located on the same side is alternately connected to two second clock lines.

[0032] In another aspect, a method for driving a display panel is provided, for driving the display panel as described in the above aspect; the method comprises:

[0033] During the display period, each shift register unit controls a first clock line connected to at least one row of pixels in response to a first control signal provided by the plurality of first control lines connected thereto to conduct light emission driving signals to the at least one row of pixels connected thereto;

[0034] During the display period, each compensation circuit controls a second clock line to be connected to at least one row of pixels in response to a second control signal provided by a second control line, so as to output a driving compensation signal to the at least one row of pixels.

[0035] In yet another aspect, a display device is provided, the display device comprising: a driving circuit, and the display panel as described in the above aspect;

[0036] The driving circuit is connected to each signal line in the display panel and is used to provide signals to each signal line.

[0037] In summary, the beneficial effects brought about by the technical solution provided by this application may at least include:

[0038] A display panel and a driving method thereof, and a display device are provided. Since the display panel includes a shift register unit and a compensation circuit located on both sides of a substrate in a pixel row direction, the shift register unit can output a light-emitting driving signal to a row of pixels, and the compensation circuit can output a driving compensation signal to the same row of pixels, so that the light-emitting driving signal received by the remote pixels far from the shift register unit can be compensated by the driving compensation signal, so that the remote pixels far from the shift register unit and the near pixels near the shift register unit in the row of pixels can both emit light under the drive of the same or similar driving signals. Furthermore, it can ensure that the light-emitting brightness uniformity of each pixel in a row of pixels is good, thereby ensuring that the display uniformity of the display panel is good. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 is a structural schematic diagram of a display panel provided in an embodiment of the present application;

[0041] Figure 2 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0042] Figure 3 is a structural schematic diagram of another display panel provided in an embodiment of the present application;

[0043] Figure 4 is a timing diagram of a clock signal provided in an embodiment of the present application;

[0044] Figure 5 is a circuit structure diagram of a compensation circuit provided in an embodiment of the present application;

[0045] Figure 6 is a schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present application;

[0046] Figure 7 is a schematic flow chart of a method for driving a display panel provided in an embodiment of the present application;

[0047] Figure 8 It is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0049] It should be noted that the transistors used in all embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present application are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiment of the present application, the source is referred to as the first pole and the drain is referred to as the second pole. According to the form in the accompanying drawings, the middle end of the transistor is defined as the control pole, which can also be referred to as the gate, the signal input end is the source, and the signal output end is the drain. In addition, the switching transistor used in the embodiment of the present application may include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level, and the N-type switching transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level.

[0050] In recent years, with the rapid development of displays, considering the aesthetic requirements, major manufacturers are compressing the borders of display panels to form displays with narrow borders or even extremely narrow borders. For example, the gate drive circuit is integrated into the display panel using GOA technology. The display can be, for example, a liquid crystal display (LCD). In addition, as recorded in the background, currently, a single-sided gate is used to drive the pixels in the display to emit light. That is, along the direction of the pixel row, a GOA circuit is set on one side of multiple rows of pixels, and the GOA circuit is connected to the multiple rows of pixels through multiple gate lines to transmit gate drive signals to the multiple rows of pixels, thereby driving the multiple rows of pixels to emit light. However, under this driving mode, for medium to large-sized (e.g., larger than 20 inches) and high-resolution displays, due to the influence of the RC delay on the gate line, the far-end signal will have a larger signal distortion problem than the near-end signal, and both Tr and Tf will be larger. The larger Tf will cause mischarging, resulting in inconsistent potentials of the near-end signal and the far-end signal, that is, the potentials of the gate drive signals received by the near-end pixels and the far-end pixels are different, resulting in different luminous brightness of the near-end pixels and the far-end pixels, that is, causing the display to have an abnormal uneven display.

[0051] Among them, taking a row of pixels as an example, the near-end pixel refers to the pixel in a row of pixels that is close to the GOA circuit set on one side; the far-end pixel refers to the pixel in a row of pixels that is far away from the GOA circuit set on one side. Correspondingly, the near-end signal refers to the gate drive signal transmitted by the GOA circuit to the near-end pixel; the far-end signal refers to the gate drive signal transmitted by the GOA circuit to the far-end pixel. Tr refers to the rise time or turn-on time, that is, the time required for the potential of the gate drive signal to rise from a low potential to a high potential to turn on the pixel, that is, the time required to light up the pixel; Tf refers to the fall time or turn-off time, that is, the time required for the potential of the gate drive signal to fall from a high potential to a low potential to turn off the pixel. Larger Tr and Tf will cause the pixel response speed to slow down, thereby affecting the display performance of dynamic pictures. In addition, a longer Tf time will also cause the pixel to not be turned off when it should be turned off, that is, the pixel still maintains a certain brightness when it should not be lit, resulting in the so-called mischarging.

[0052] Based on this, in some embodiments, it is also considered to adopt bilateral gate drive, that is, along the pixel row direction, GOA circuits are respectively arranged on both sides of multiple rows of pixels and connected to multiple rows of pixels. Although this will improve the problem of uneven display, at the same time, the area occupied by the GOA circuit on the display panel will increase, the difficulty of the preparation process will increase, and the working power consumption of the circuit will increase. Therefore, the embodiment of the present application provides a display panel to solve the problems existing in the above solution. Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figure 1 As shown, the display panel includes:

[0053] The substrate 01 has a display area AA and a peripheral area BB at least partially surrounding the display area AA. Figure 1 In the substrate 01 shown therein, the peripheral area BB partially surrounds the display area AA and is located on the left and right sides of the display area AA. Of course, in some other embodiments, the peripheral area BB may also be located on the upper side and / or the lower side of the display area AA. Alternatively, the peripheral area BB may also surround the display area AA, that is, the display area AA is surrounded by the GOA area. The embodiment of the present application does not limit the positional relationship between the peripheral area BB and the display area AA.

[0054] The plurality of pixels 02 are arranged in an array, and the plurality of pixels 02 are located in the display area AA. The array arrangement may refer to the plurality of pixels 02 being arranged in an array according to the following Figure 1 The pixels are arranged in the row direction X1 and the column direction Y1 as shown, that is, the display panel may include the following Figure 1 Of course, in some other embodiments, the plurality of pixels 02 may also be arranged in other ways other than array arrangement.

[0055] A plurality of cascaded shift register units 03, and the plurality of shift register units 03 are located in the peripheral area BB and connected to a plurality of rows of pixels 02, and each shift register unit 03 is connected to at least one row of pixels 02 in the plurality of rows of pixels 02, and each shift register unit 03 is also connected to a plurality of first control lines Con1 and a first clock line CK1, respectively, and is used to control the on and off of a first clock line CK1 and at least one row of pixels 02 connected in response to a first control signal provided by the plurality of first control lines Con1, so as to output a light-emitting drive signal to the at least one row of pixels 02 connected. The shift register unit 03 is also a GOA unit, hereinafter referred to as GOA.

[0056] A plurality of compensation circuits 04 are provided, and the plurality of compensation circuits 04 are located in the peripheral area BB and connected to a plurality of rows of pixels 02, and each compensation circuit 04 is connected to at least one row of pixels 02 among the plurality of rows of pixels 02, and each compensation circuit 04 is also respectively connected to a second control line Con2 and a second clock line CK2, and is used for controlling the on and off of a second clock line CK2 and at least one row of pixels 02 connected thereto in response to a second control signal provided by a second control line Con2, so as to output a driving compensation signal to the at least one row of pixels 02 connected thereto.

[0057] Optionally, refer to Figure 1 , the multiple GOAs 03 shown therein are connected to the multiple rows of pixels 02 in one-to-one correspondence, and the multiple compensation circuits 04 are connected to the multiple rows of pixels 02 in one-to-one correspondence. That is, each GOA 03 and each compensation circuit 04 are connected to the same row of pixels 02, and each GOA 03 and each compensation circuit 04 are connected to different rows of pixels 02, respectively.

[0058] exist Figure 1 On this basis, for example, each GOA 03 can control the connected first clock line CK1 and a row of pixels 02 to be turned on under the control of the first control signal provided by the connected multiple first control lines Con1, so that the first clock line CK1 can transmit the first clock signal to the row of pixels 02, and the transmitted first clock signal can be used as a light-emitting drive signal to drive the row of pixels 02 to emit light; and the connected first clock line CK1 can also be controlled to be disconnected from the row of pixels 02.

[0059] Similarly, each compensation circuit 04 can control the connected second clock line CK2 and a row of pixels 02 to be turned on under the control of a second control signal provided by a connected second control line Con2, so that the second clock line CK2 can transmit a second clock signal to the row of pixels 02, and the transmitted second clock signal can be used as a driving compensation signal of the light-emitting driving signal to drive the row of pixels 02 to emit light; and the connected second clock line CK2 can also be controlled to be disconnected from the row of pixels 02.

[0060] Optionally, the light emitting driving signal may be, for example, a gate driving signal transmitted through the gate line Gate; correspondingly, the driving compensation signal may be a gate driving compensation signal of the gate driving signal transmitted through the gate line Gate.

[0061] It can be understood that the effective potential light-emitting driving signal (i.e., the first clock signal of the effective potential) and the driving compensation signal (i.e., the second clock signal of the effective potential) can drive the pixel 02 to emit light. The invalid potential light-emitting driving signal and the driving compensation signal can stop driving the pixel 02 to emit light. In addition, as described above, for an N-type transistor, the effective potential can be a high potential relative to the invalid potential; for a P-type transistor, the effective potential can be a low potential relative to the invalid potential.

[0062] It can also be understood that the potential of the driving compensation signal can be the same as the potential of the light-emitting driving signal, and the effective potential of the driving compensation signal can be within the effective potential duration of the light-emitting driving signal. In this way, under the drive of the light-emitting driving signal and the driving compensation signal, a row of pixels 02 can emit light at the same time, and the light-emitting brightness of each pixel 02 in a row of pixels 02 can be kept as consistent as possible.

[0063] And, continue to refer to Figure 1 It can be seen that in the embodiment of the present application, at least one shift register unit GOA 03 among the multiple shift register units GOA 03 and at least one compensation circuit 04 among the multiple compensation circuits 04 are respectively located on both sides of the substrate 01 in the pixel row direction X1, and a shift register unit GOA 03 and a compensation circuit 04 connected to the same row of pixels can be respectively located on the two sides. That is, there are one or more GOA 03 and compensation circuit 04 respectively located on the left and right sides of the display area AA, and for the same row of pixels 02, a GOA 03 and a compensation circuit 04 connected to the row of pixels 02 are respectively located on the left and right sides of the display area AA.

[0064] For example, refer to Figure 1 , the multiple GOAs 03 shown are all located in the peripheral area BB on the left side of the display area AA, and the multiple compensation circuits 04 are all located in the peripheral area BB on the right side of the display area AA. That is, for the same row of pixels 02, a GOA 03 connected to the row of pixels 02 is located on the left side of the display area AA, and a compensation circuit 04 connected to the row of pixels 02 is located on the right side of the display area AA. Of course, the layout here is only a schematic description.

[0065] In this way, by arranging GOA 03 and compensation circuit 04 on the left and right sides of a row of pixels 02, respectively, to transmit a light-emitting drive signal and a drive compensation signal to the row of pixels 02 to drive the row of pixels 02 to emit light, the light-emitting drive signal transmitted to the far-end pixel far from GOA 03 can be compensated by the drive compensation signal, so that the far-end pixel far from GOA 03 and the near-end pixel near GOA 03 can receive the same or similar potential drive signal. Furthermore, the luminous brightness of the far-end pixel and the near-end pixel can be kept consistent as much as possible. That is, the luminous brightness of each pixel 02 in a row of pixels 02 can be made relatively uniform, so as to ensure that the display uniformity of the display panel is better. In addition, because the compensation circuit 04 is a non-GOA unit different from GOA03, the number of control lines required to be connected to the compensation circuit 04 is less than the number of control lines required to be connected to GOA03, so it can be known that the number of devices included in the compensation circuit 04 should also be less than the number of devices included in GOA03. That is, the circuit structure of the compensation circuit 04 is simpler than that of the GOA 03, and the required area is smaller. In this way, while ensuring better display uniformity, compared with the double-sided gate driving method, it not only simplifies the difficulty of the manufacturing process, but also can better facilitate the narrow frame design of the display panel and reduce the overall working power consumption of the circuit.

[0066] In summary, the embodiment of the present application provides a display panel. Since the display panel includes a shift register unit and a compensation circuit located on both sides of the substrate in the direction of the pixel row, the shift register unit can output a light-emitting drive signal to a row of pixels, and the compensation circuit can output a drive compensation signal to the same row of pixels, so the light-emitting drive signal transmitted to the remote pixels far from the shift register unit can be compensated by the drive compensation signal, so that the remote pixels far from the shift register unit and the near pixels close to the shift register unit in the row of pixels can emit light under the drive of the same or similar drive signal. Furthermore, it can ensure that the light-emitting brightness uniformity of each pixel in a row of pixels is good, thereby ensuring that the display uniformity of the display panel is good.

[0067] Optionally, continue to refer to Figure 1 It can be seen that each shift register unit GOA03 and each compensation circuit 04 can be connected to at least one row of pixels 02 in the multiple rows of pixels 02 through the gate line Gate, and a shift register unit GOA03 and a compensation circuit 04 connected to the same row of pixels 02 share the gate line Gate. That is, a shift register unit GOA03 and a compensation circuit 04 can be connected to the same row of pixels 02 through the same gate line Gate.

[0068] Accordingly, as described above, the light-emitting driving signal may be a gate driving signal transmitted via the gate line Gate, and the driving compensation signal may be a gate driving compensation signal transmitted via the gate line Gate. Of course, in some other embodiments, the light-emitting driving signal may also be a light-emitting control signal transmitted via the light-emitting control line EM.

[0069] Optionally, continue to refer to Figure 1 It can be seen that, as described above, multiple shift register units GOA 03 can be connected to multiple rows of pixels 02 in a one-to-one correspondence, and multiple compensation circuits 04 can be connected to multiple rows of pixels 02 in a one-to-one correspondence. In this way, a good compensation driving effect can be achieved for each row of pixels 02, so that the uniformity of the luminous brightness of each row of pixels 02 is good. Of course, in some other embodiments, it is not limited to a one-to-one correspondence connection. For example, each GOA03 can be connected to 2 or more rows of pixels 02.

[0070] Optionally, as an optional implementation: Figure 1 As shown, the multiple shift register units GOA 03 can be located on the first side of the two sides, and the multiple compensation circuits 04 can be located on the second side of the two sides. That is, on the two sides in the pixel row direction X1, one side can include multiple cascaded GOA 03, and the other side can include multiple compensation circuits 04. In this way, cascading and layout can be facilitated, thereby saving manufacturing costs.

[0071] For example, refer to Figure 1 , the first side shown may refer to the left side of the display area AA, and the second side may refer to the right side of the display area AA. Of course, in some other embodiments, the first side may also refer to the right side of the display area AA, and correspondingly, the second side may refer to the left side of the display area AA. The same applies to the following embodiments.

[0072] Alternatively, as another optional implementation: Figure 2 As shown, multiple shift registers with a single GOA

[0073] In the embodiment of the present invention, a part of the shift register unit GOA03 may be located on the first side of the two sides, and the remaining shift register units GOA03 except a part of the shift register unit GOA03 may be located on the second side of the two sides. In the plurality of compensation circuits 04, a part of the compensation circuits 04 may be located on the first side of the two sides, and the remaining compensation circuits 04 except a part of the compensation circuits 04 may be located on the second side of the two sides. In this way, the same compensation effect can be achieved for the light emitting drive signals received by the remote pixels located in the left and right parts of the display area AA along the pixel row direction X1, thereby ensuring better display uniformity of the left and right parts.

[0074] For example, refer to Figure 2, the first side shown may also refer to the left side of the display area AA, and the second side may also refer to the right side of the display area AA. In addition, the multiple shift register units GOA 03 shown are divided equally between the first side and the second side in a half-half ratio, and the multiple compensation circuits 04 are also divided equally between the first side and the second side in a half-half ratio. And, for each row of pixels 02, the GOA 03 and the compensation circuit 04 connected to the row of pixels 02 are located on the first side and the second side, respectively. Such equal division can further ensure that the overall display uniformity of the left and right parts of the display area AA is good.

[0075] Optionally, continue to refer to Figure 2 , among the multiple shift register units GOA 03, each shift register unit GOA 03 connected to the odd-numbered rows of pixels 02 (i.e., the 1st row of pixels 02, the 3rd row of pixels 02, the 5th row of pixels 02...) can be located on the first side (e.g., the left side), and each shift register unit GOA 03 connected to the even-numbered rows of pixels 02 (i.e., the 2nd row of pixels, the 4th row of pixels, the 6th row of pixels...) can be located on the second side (e.g., the right side). Similarly, among the multiple compensation circuits 04, each compensation circuit 04 connected to the even-numbered rows of pixels 02 can be located on the first side, and each compensation circuit 04 connected to the odd-numbered rows of pixels 02 can be located on the second side. In the figure, the GOA 03 and the compensation circuit 04 connected to the 1st row of pixels 02 are respectively identified as GOA (1) and compensation circuit 04 (1), and the circuits connected to other rows of pixels 02 are identified similarly.

[0076] That is, each GOA 03 connected to the odd-numbered rows of pixels 02 and each GOA 03 connected to the even-numbered rows of pixels can be alternately arranged on the left and right sides of the pixel row direction X1. And, each compensation circuit 04 connected to the odd-numbered rows of pixels 02 and each compensation circuit 04 connected to the even-numbered rows of pixels 02 can be alternately arranged on both sides of the pixel row direction X1. Moreover, each GOA 03 connected to the odd-numbered rows of pixels 02 and each compensation circuit 04 connected to the even-numbered rows of pixels 02 can be located on the same side (e.g., the left side); each GOA 03 connected to the even-numbered rows of pixels 02 and each compensation circuit 04 connected to the odd-numbered rows of pixels 02 can be located on the same side (e.g., the right side). The GOA 03 and the compensation circuit 04 connected to each row of pixels 02 can be located on the left and right sides, respectively.

[0077] Accordingly, on this basis, continue to refer to Figure 2It can be seen that the shift register units GOA03 and the compensation circuits 04 located on the first side can be arranged alternately in the order of one shift register unit GOA03 and one compensation circuit 04 in the pixel column direction Y1. The shift register units GOA03 and the compensation circuits 04 located on the second side can be arranged alternately in the order of one compensation circuit 04 and one shift register unit GOA03 in the pixel column direction Y1. In this way, the layout can be facilitated, the wiring can be simplified, and the manufacturing cost can be saved.

[0078] Of course, in some other embodiments, each adjacent row of pixels 02 may be a group, and the GOAs 03 connected to the same group may be arranged on the same side, and the GOAs 03 connected to adjacent groups may be arranged on the left and right sides respectively. The layout of the compensation circuit 04 is similar. That is, the embodiments of the present application are not limited to Figure 1 and Figure 2 Two layouts are shown.

[0079] Optionally, in Figure 2 Based on this, continue to refer to Figure 3 It can be seen that among the multiple shift register units GOA 03, each shift register unit GOA 03 located on the same side can be alternately connected to at least two first clock lines CK1. Among the multiple compensation circuits 04, each compensation circuit 04 located on the same side can be alternately connected to at least two second clock lines CK2. Moreover, the number of the at least two second clock lines CK2 can be less than the number of the at least two first clock lines CK1.

[0080] For example, Figure 3 In the multiple shift register units GOA 03 shown, each shift register unit GOA 03 located on the same side can be alternately connected to the four first clock lines CK1. In the multiple compensation circuits 04, each compensation circuit 04 located on the same side can be alternately connected to the two second clock lines CK2.

[0081] Combination Figure 3 It can be understood that the alternating connection between each shift register unit GOA 03 located on the same side and at least two first clock lines CK1 can mean that: each GOA 03 located on the same side can be divided into multiple groups of GOA 03, and each group of GOA 03 can include two or more cascaded GOA 03. On this basis, each group of GOA 03 can be connected to the same at least two first clock lines CK1, and each GOA 03 in each group of GOA 03 can be alternately connected to the at least two first clock lines CK1. Correspondingly, the number of first clock lines CK1 to be set can be the same as the number of GOA 03 included in each group of GOA 03.

[0082] For example, refer to Figure 3 , among the multiple cascaded shift register units GOA 03 shown therein, each GOA 03 on the left and right sides can be divided into multiple groups of GOA 03, with each group of 4 adjacent and cascaded GOA 03. Moreover, the 4 GOA 03 in each group can be alternately connected to the same 4 first clock lines CK1. For distinction, the 4 first clock lines CK1 connected to the GOA 03 located on the left side of the display area AA and connected to the odd-numbered rows of pixels 02 are respectively identified as CK11, CK13, CK15 and CK17; the 4 first clock lines CK1 connected to the GOA 03 located on the right side of the display area AA and connected to the even-numbered rows of pixels 02 are respectively identified as CK12, CK14, CK16 and CK18. Continue to refer to Figure 3 , alternately connected, that is, along the pixel column direction Y1 from top to bottom, the 1st GOA03 is connected to the 1st first clock line CK1 (such as CK11 or CK12), the 2nd GOA 03 is connected to the 2nd first clock line CK1 (such as CK13 or CK14), the 3rd GOA 03 is connected to the 3rd first clock line CK1 (such as CK15 or CK16), and the 4th GOA03 is connected to the 4th first clock line CK1 (such as CK17 or CK18).

[0083] Similarly, combined Figure 3 It can also be understood that the compensation circuits 04 located on the same side are alternately connected to at least two second clock lines CK2, which can mean that the compensation circuits 04 located on the same side can be divided into multiple groups of compensation circuits 04, and each group of compensation circuits 04 can include two or more compensation circuits 04. On this basis, each group of compensation circuits 04 can be connected to the same at least two second clock lines CK2, and each compensation circuit 04 in each group of compensation circuits 04 can be alternately connected to the at least two second clock lines CK2. Accordingly, the number of second clock lines CK2 to be set can be the same as the number of compensation circuits 04 included in each group of compensation circuits 04.

[0084] For example, refer to Figure 3 Among the multiple compensation circuits 04 shown, each compensation circuit 04 on the left and right sides can be divided into multiple groups of compensation circuits 04, with each two adjacent compensation circuits 04 as a group. Moreover, the two compensation circuits 04 in each group can be alternately connected to the same two second clock lines CK2. For distinction, the two second clock lines CK2 connected to the compensation circuit 04 located on the left side of the display area AA and connected to the even-numbered rows of pixels 02 are marked as CK22 and CK24, respectively; the two second clock lines CK2 connected to the compensation circuit 04 located on the right side of the display area AA and connected to the odd-numbered rows of pixels 02 are marked as CK21 and CK23, respectively. Continue to refer to Figure 3, alternately connected, that is, along the pixel column direction Y1 from top to bottom, the first compensation circuit 04 is connected to the first second clock line CK2 (such as CK21 or CK22), and the second compensation circuit 04 is connected to the second second clock line CK2 (such as CK23 or CK24).

[0085] Based on the above records, it can be known that for the cascaded multiple GOA03, a total of 8 first clock lines CK11 to CK18 need to be set for the multiple GOA 03 to connect. On this basis, if multiple GOA 03 are set on both the left and right sides of the display area AA, that is, a bilateral gate drive method is adopted to drive multiple rows of pixels to emit light, then 8 first clock lines CK11 to CK18 need to be set on both the left and right sides respectively. In the embodiment of the present application, by setting a compensation circuit 04 instead of the bilateral gate drive method, the potential of the clock signal can be flexibly designed so that the number of the second clock lines CK2 set is less than the number of the first clock lines CK1, thereby reducing the total number of clock lines required to be set for the display panel. For example, Figure 3 In the structure shown, only two second clock lines CK2 are required on the left and right sides for connection with the compensation circuit 04, and four first clock lines CK1 are required for connection with the GOA 03. That is, only six clock lines are required on each side. In this way, compared with the bilateral gate driving method, two clock lines can be reduced on both sides, which can better facilitate the design of narrow frame.

[0086] Optionally, refer to Figure 3 It can also be seen that the pixel 02 may be a pixel including a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Of course, the structure is not limited to this.

[0087] Optionally, Figure 3 Take the structure shown as an example, Figure 4 A timing diagram is also schematically shown. Figure 4 It can be seen that the timing relationship satisfied by the four first clock lines CK1 (including CK11 to CK18 ) and the two second clock lines CK2 (including CK21 to CK24 ) arranged on the left and right sides respectively.

[0088] Taking the GOA03 and compensation circuit 04 connected to the first row of pixels 02, where the effective potential is a high potential and the invalid potential is a low potential as an example, the first clock line CK11 and the second clock line CK21 respectively connected thereto can satisfy: the duration of the high potential of the first clock signal provided by the first clock line CK11 is 4H, the duration of the high potential of the second clock signal provided by the second clock line CK21 is 2H, and the falling edge of the high potential of the second clock signal provided by the second clock line CK21 is aligned with the falling edge of the high potential of the first clock signal provided by the first clock line CK11. In this way, as described in the above embodiment, for multiple GOA03, each GOA 03 located on the same side is alternately connected to the four first clock lines CK1. For multiple compensation circuits 04, each compensation circuit 04 located on the same side is alternately connected to the two second clock lines. Of course, the clock timing is not limited to Figure 4 Example shown.

[0089] Optionally, in the embodiment of the present application, combined with Figure 3 and Figure 4 It can be known that the second control line Con2 connected to the nth compensation circuit 04 can be connected to the n+ith shift register unit GOA03. Correspondingly, the second control signal can be the light-emitting drive signal output by the n+ith shift register unit GOA03. Here, it means that the second control line Con2 is connected to the output terminal Gn+i of the n+ith GOA03 connected to the pixel 02 to receive the light-emitting drive signal output by the n+ith GOA03. In this way, the wiring can be simplified, thereby saving costs and facilitating the design of a narrow frame.

[0090] Among them, the effective potential transition edge of the first clock signal provided by the first clock line CK1 connected to the n+i-th shift register unit GOA 03 is aligned with the effective potential transition edge of the second clock signal provided by the second clock line CK2 connected to the n-th compensation circuit 04, and the effective potential of the second clock signal provided by the second clock line CK2 connected to the n-th compensation circuit 04 is within the effective potential of the first clock signal provided by the first clock line CK1 connected to the n+i-th shift register unit GOA 03, and is within the effective potential of the first clock signal provided by the first clock line CK1 connected to the n-th shift register unit GOA03.

[0091] Furthermore, the nth compensation circuit 04 may refer to the compensation circuit 04 connected to the nth row of pixels 02, the n+ith shift register unit GOA03 may refer to the shift register unit GOA03 connected to the n+ith row of pixels 02, the nth shift register unit GOA03 may refer to the shift register unit 03 connected to the nth row of pixels 02, n may be an integer greater than 0, and i may be an integer greater than or equal to 0.

[0092] Also, as described above, the potential of the first clock signal is an effective potential and the potential of the second clock signal is an effective potential, which can be used to drive the pixel 02 to emit light, the potential of the first clock signal is an invalid potential and the potential of the second clock signal is an invalid potential, which can be used to stop driving the pixel 02 to emit light, and the effective potential jump edge can be a jump edge from the invalid potential to the effective potential. For example, on the basis that the effective potential is a high potential and the invalid potential is a low potential, the jump edge can refer to a rising edge from a low potential to a high potential.

[0093] For example, in Figure 4 Based on the timing sequence shown, i can be 2. That is, the second control line Con2 connected to the nth compensation circuit 04 can be connected to the output terminal Gn+2 of the n+2th GOA03. For example, the second control line Con2 connected to the first compensation circuit 04 connected to the first row of pixels 02 can be connected to the output terminal G3 of the third GOA03 connected to the third row of pixels 03. The light-emitting drive signal output by the output terminal G3 of the third GOA03 is also the first clock signal provided by the first clock line CK13 connected to it. Figure 4 It can be seen that the rising edge of the first clock signal provided by the first clock line CK13 is aligned with the rising edge of the second clock signal provided by the second clock line CK21 connected to the first compensation circuit 04 .

[0094] Optionally, refer to Figure 5 , which shows a schematic diagram of the circuit structure of a compensation circuit 04. Figure 5 As shown, the compensation circuit 04 may include: a compensation transistor TFTX.

[0095] The gate of the compensation transistor TFTX can be connected to the second control line Con2 (e.g., Gn+2), the first electrode of the compensation transistor TFTX can be connected to the second clock line CK2, and the second electrode of the compensation transistor TFTX can be connected to at least one row of pixels 02. For example, the second electrode of the compensation transistor TFTX can be connected to a row of pixels 02 through the gate line Gate. Compared with GOA03, the structure is simple.

[0096] Optionally, refer to Figure 6 , which shows a schematic diagram of the circuit structure of a shift register unit GOA 03. Figure 6 As shown, the shift register unit GOA03 may be a shift register unit GOA03 of a 22T1C architecture. The 22T1C architecture may refer to an architecture including 22 transistors and 1 capacitor. Of course, in some other embodiments, GOA03 is not limited to Figure 6 The structure shown.

[0097] Optionally, combined Figure 6It can also be seen that the plurality of first control lines Con1 connected to GOA03 may include: power lines VGH and VGL, control lines LC1, LC2 and CLR, and the like.

[0098] Based on the foregoing description, it can be seen that the solution provided by the embodiment of the present application can reduce the number of clock lines required to be set while ensuring display uniformity, simplify the circuit structure, and thus better facilitate the design of a narrow frame.

[0099] In summary, the embodiment of the present application provides a display panel. Since the display panel includes a shift register unit and a compensation circuit located on both sides of the substrate in the direction of the pixel row, the shift register unit can output a light-emitting drive signal to a row of pixels, and the compensation circuit can output a drive compensation signal to the same row of pixels, so the light-emitting drive signal transmitted to the remote pixels far from the shift register unit can be compensated by the drive compensation signal, so that the remote pixels far from the shift register unit and the near pixels close to the shift register unit in the row of pixels can emit light under the drive of the same or similar drive signal. Furthermore, it can ensure that the light-emitting brightness uniformity of each pixel in a row of pixels is good, thereby ensuring that the display uniformity of the display panel is good.

[0100] The present application also provides a method for driving a display panel, which can be used to drive the display panel described in the above embodiment. Figure 7 As shown, the method includes:

[0101] Step 701: During a display period, each shift register unit controls a first clock line to be turned on with at least one row of pixels in response to a first control signal provided by a plurality of first control lines, so as to output a light-emitting drive signal to the at least one row of pixels.

[0102] Step 702: During the display period, each compensation circuit controls a connected second clock line to be turned on with at least one row of pixels in response to a second control signal provided by a connected second control line, so as to output a driving compensation signal to the connected at least one row of pixels.

[0103] As described above, at least one of the multiple shift register units and at least one of the multiple compensation circuits are located on both sides of the substrate in the direction of the pixel row, and a shift register unit and a compensation circuit connected to the same row of pixels are located on both sides. In this way, the light-emitting drive signal transmitted to the far-end pixel far from the shift register unit can be compensated by driving the compensation signal, so that the far-end pixel and the near-end pixel close to the shift register unit can receive the same or similar potential drive signal. Furthermore, the light-emitting brightness of the far-end pixel and the near-end pixel can be kept as consistent as possible. That is, the light-emitting brightness of each pixel in a row of pixels can be made more uniform, thereby ensuring that the display uniformity of the display panel is better.

[0104] It can be understood that since the driving method of the display panel can have basically the same implementation method and technical effect as the display panel described in the previous embodiment, for the purpose of brevity, the implementation method and technical effect of the driving method of the display panel will not be repeated here.

[0105] The present application also provides a display device. Figure 8 As shown, the display device includes: a driving circuit 10, and a display panel 00 as described in the above embodiment.

[0106] The driving circuit 10 is connected to each signal line in the display panel 00 and is used to provide signals to each signal line. The signal lines may be, for example, a first control line Con1, a second control line Con2, a first clock line CK1, and a second clock line CK2. The driving circuit 10 may be, for example, a timing controller (TCON). Optionally, in combination with Figure 2 It can also be seen that the driving circuit 10 can be disposed on a printed circuit board (PCB).

[0107] Optionally, the display panel 100 may be an LCD display panel, and the display device may be an LCD display device. Also, the display device may be any appropriate display device, including but not limited to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and an e-book.

[0108] It can be understood that, since the display device can have substantially the same technical effects as the display panel described in the previous embodiment, for the purpose of brevity, the technical effects of the display device will not be repeatedly described herein.

[0109] The terms used in the embodiments of this application are only used to explain the embodiments of this application, and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this application should be the common meanings understood by people with general skills in the field to which this application belongs.

[0110] The terms used in the implementation mode of the present application are only used to explain the embodiments of the present application, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the implementation mode of the present application should be the common meanings understood by people with ordinary skills in the field to which the present application belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limit, but indicate that there is at least one. Words such as "include" or "include" and similar words mean that the elements or objects appearing in front of "include" or "include" include the elements or objects listed after "include" or "include" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. "And / or" indicates that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship.

[0111] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, It is characterized in that The display panel comprises: A substrate having a display area and a peripheral area at least partially surrounding the display area; A plurality of pixels arranged in an array are located in the display area; A plurality of cascaded shift register units are located in the peripheral area and connected to a plurality of rows of pixels, and each of the shift register units is connected to at least one row of pixels in the plurality of rows of pixels, and each of the shift register units is also respectively connected to a plurality of first control lines and a first clock line, and is used to control the on-off of the first clock line and the at least one row of pixels connected thereto in response to a first control signal provided by the plurality of first control lines, so as to output a light-emitting drive signal to the at least one row of pixels connected thereto; A plurality of compensation circuits, located in the peripheral area and connected to the plurality of rows of pixels, each of the compensation circuits being connected to at least one row of pixels in the plurality of rows of pixels, and each of the compensation circuits being connected to a second control line and a second clock line, respectively, and being used to control the on-off of the second clock line and the at least one row of pixels connected thereto in response to a second control signal provided by the second control line, so as to output a driving compensation signal to the at least one row of pixels connected thereto; Among them, at least one shift register unit among the multiple shift register units and at least one compensation circuit among the multiple compensation circuits are respectively located on both sides of the substrate in the pixel row direction, and a shift register unit and a compensation circuit connected to the same row of pixels are respectively located on the two sides.

2. The display panel according to claim 1, It is characterized in that Each of the shift register units and each of the compensation circuits are connected to at least one row of pixels in the plurality of rows of pixels through a gate line, and a shift register unit and a compensation circuit connected to the same row of pixels share the gate line; The light-emitting driving signal is a gate driving signal transmitted via the gate line, and the driving compensation signal is a gate driving compensation signal transmitted via the gate line.

3. The display panel according to claim 1, It is characterized in that The plurality of shift register units are connected to the plurality of rows of pixels in a one-to-one correspondence; The plurality of compensation circuits are connected to the plurality of rows of pixels in a one-to-one correspondence.

4. The display panel according to any one of claims 1 to 3, It is characterized in that The second control line connected to the nth compensation circuit is connected to the n+ith shift register unit, and the second control signal is a light-emitting driving signal output by the n+ith shift register unit; wherein the effective potential transition edge of the first clock signal provided by the first clock line connected to the n+i-th shift register unit is aligned with the effective potential transition edge of the second clock signal provided by the second clock line connected to the n-th compensation circuit, and the effective potential of the second clock signal provided by the second clock line connected to the n-th compensation circuit is within the effective potential of the first clock signal provided by the first clock line connected to the n+i-th shift register unit, and is within the effective potential of the first clock signal provided by the first clock line connected to the n-th shift register unit; Furthermore, the nth compensation circuit refers to a compensation circuit connected to the nth row of pixels, the n+ith shift register unit refers to a shift register unit connected to the n+ith row of pixels, the nth shift register unit refers to a shift register unit connected to the nth row of pixels, n is an integer greater than 0, and i is an integer greater than or equal to 0; and the potential of the first clock signal is a valid potential and the potential of the second clock signal is a valid potential for driving the pixel to emit light, the potential of the first clock signal is an invalid potential and the potential of the second clock signal is an invalid potential for stopping driving the pixel to emit light, and the effective potential transition edge is a transition edge from an invalid potential to a valid potential.

5. The display panel according to claim 4, It is characterized in that The i is 2.

6. The display panel according to any one of claims 1 to 3, It is characterized in that Among the plurality of shift register units, a portion of the shift register units are located on a first side of the two sides, and the remaining shift register units except the portion of the shift register units are located on a second side of the two sides; Among the plurality of compensation circuits, a portion of the compensation circuits are located on a first side of the two sides, and the remaining compensation circuits except the portion of the compensation circuits are located on a second side of the two sides.

7. The display panel according to claim 6, It is characterized in that Among the plurality of shift register units, each shift register unit connected to pixels in odd rows is located on the first side, and each shift register unit connected to pixels in even rows is located on the second side; Among the plurality of compensation circuits, the compensation circuits connected to the pixels in even rows are located on the first side, and the compensation circuits connected to the pixels in odd rows are located on the second side.

8. The display panel according to claim 7, It is characterized in that The shift register units and the compensation circuits located on the first side are arranged alternately in the order of one shift register unit and one compensation circuit in the direction of the pixel columns; The shift register units and the compensation circuits located on the second side are arranged alternately in the order of one compensation circuit and one shift register unit in the direction of the pixel columns.

9. The display panel according to any one of claims 1 to 3, It is characterized in that The plurality of shift register units are all located on a first side of the two sides, and the plurality of compensation circuits are all located on a second side of the two sides.

10. The display panel according to any one of claims 1 to 3, It is characterized in that The compensation circuit comprises: a compensation transistor; A gate of the compensation transistor is connected to the second control line, a first electrode of the compensation transistor is connected to the second clock line, and a second electrode of the compensation transistor is connected to the at least one row of pixels.

11. The display panel according to any one of claims 1 to 3, It is characterized in that The shift register unit is a shift register unit of a 22T1C architecture, and the 22T1C architecture refers to an architecture including 22 transistors and 1 capacitor.

12. The display panel according to any one of claims 1 to 3, It is characterized in that Among the multiple shift register units, each shift register unit located on the same side is alternately connected to at least two first clock lines; among the multiple compensation circuits, each compensation circuit located on the same side is alternately connected to at least two second clock lines; and the number of the at least two second clock lines is less than the number of the at least two first clock lines.

13. The display panel according to claim 12, It is characterized in that Among the plurality of shift register units, each shift register unit located on the same side is alternately connected to four first clock lines; Among the plurality of compensation circuits, each compensation circuit located on the same side is alternately connected to two second clock lines.

14. A method for driving a display panel, It is characterized in that Used to drive the display panel according to any one of claims 1 to 13; the method comprises: During the display period, each shift register unit controls a first clock line connected to at least one row of pixels in response to a first control signal provided by the plurality of first control lines connected thereto to conduct light emission driving signals to the at least one row of pixels connected thereto; During the display period, each compensation circuit controls a second clock line to be connected to at least one row of pixels in response to a second control signal provided by a second control line, so as to output a driving compensation signal to the at least one row of pixels.

15. A display device, It is characterized in that The display device comprises: a driving circuit, and a display panel according to any one of claims 1 to 13; The driving circuit is connected to each signal line in the display panel and is used to provide signals to each signal line.

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