Semiconductor device

Abstract

The present disclosure relates to semiconductor device structures and methods of manufacturing semiconductor devices. The method includes providing a first semiconductor substrate having a first major surface and an opposing second major surface, the first major surface having a first metal layer formed thereon; providing a second semiconductor substrate having a first major surface and an opposing second major surface, wherein the second semiconductor substrate includes a plurality of active device regions formed therein and a second metal layer formed on the first major surface connecting each of the plurality of active device regions; bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate; and forming a device contact on the second major surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions.

Description

[0001] This application is a divisional application of patent application No. 2019101045464, filed on February 1, 2019, entitled “Semiconductor Device”. TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor device structure and a manufacturing method. In particular, the present disclosure relates to a semiconductor device structure comprising a donor substrate and a bonded carrier substrate. BACKGROUND

[0003] Chip-scale semiconductor packages (CSPs) are characterized as packages that are directly surface mountable. CSPs are arranged to have all external contacts on one surface of the package, enabling the package to be mounted on a carrier, such as a printed circuit board. CSPs typically contain diode and / or transistor device structures arranged vertically within the package, such that the dominant current flow within the device structure is inherently vertical. However, because the CSP is arranged to have contacts on one surface, the current must flow to another contact on the same side, and thus the vertical current flow through the active region of the device structure must change direction to lateral, through the substrate, and then change direction back to vertical to reach the second contact. Due to the limited conductivity of the bulk semiconductor material, the current density in the bulk and in the device structure and the contacts will be non-uniform. The current density in portions of the device structure closer to the second contact can be higher. In addition, current crowding occurs at the edges of the contacts of the device structures. Thus, the maximum allowed total current through the device structures and the contacts will be less than if the second contact were placed on the other surface of the semiconductor crystal; and the current through the bulk is always vertical; and thus the current density within the device structures is, in principle, the same for the entire area of the device structure.

[0004] In addition, parasitic current paths can occur between the device structures, which can affect performance. These issues are also particularly relevant for transient voltage suppression devices, where localized heating can cause device failure. SUMMARY

[0005] According to one embodiment, a method of fabricating a semiconductor device is provided, the method comprising: providing a first semiconductor substrate having a first major surface and an opposing second major surface, the first major surface having a first metal layer formed thereon; providing a second semiconductor substrate having a first major surface and an opposing second major surface, wherein the second semiconductor substrate includes a plurality of active device regions formed therein and a second metal layer formed on the first major surface connecting each of the plurality of active device regions; bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate; and forming a device contact on the second major surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions.

[0006] Optionally, the method can include bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate to form a metal layer disposed between the two semiconductor layers. Optionally, the first metal layer and the second metal layer can be gold or aluminum.

[0007] Optionally, the method can further include thinning the opposing second major surface of the second semiconductor substrate prior to bonding the first metal layer to the second metal layer.

[0008] Optionally, the method can further include forming one or more trench regions extending from the first major surface to the opposing second major surface of the second semiconductor substrate. The method can further include filling the trench regions with an insulating material.

[0009] Optionally, the second semiconductor substrate can be a silicon-on-insulator substrate. Optionally, the plurality of active device regions are bidirectional active device regions.

[0010] According to one embodiment, a semiconductor device is also provided, comprising: a first semiconductor substrate having a first major surface and an opposing second major surface, the first major surface having a first metal layer formed thereon; and a second semiconductor substrate having a first major surface and an opposing second major surface, wherein the second semiconductor substrate includes a plurality of active device regions formed therein and a second metal layer formed on the first major surface connecting each of the plurality of active device regions; wherein the first metal layer of the first semiconductor substrate is bonded to the second metal layer of the second semiconductor substrate; and a device contact disposed on the second major surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions.

[0011] The first metal layer of the first semiconductor substrate can be bonded to the second metal layer of the second semiconductor substrate to form a metal layer disposed between the two semiconductor layers. BRIEF DESCRIPTION OF DRAWINGS

[0012] Accordingly, in an implementation, one or more portions of the subject matter described herein can be implemented as a computer program product, i.e., a computer program tangibly embodied in a machine-readable medium, for execution by a computer processor. The machine-readable medium can include, but is not limited to, a floppy disk, a CD-ROM, and a hard disk. The computer program can be written in any of various styles, including code contained in a stand-alone file, code contained in a file that uses a library, code contained in a file that uses a class hierarchy, and code contained in a file that uses an object hierarchy. In an implementation, the computer program can be written in object-oriented code, which has at least some portions that are object code.

[0013] Figure 1 A carrier substrate or wafer is shown that includes a metal contact layer formed thereon.

[0014] Figure 2 A donor substrate or wafer is shown that includes an active region connected to a metal contact layer formed thereon;

[0015] Figure 3a An active region structure for a back-to-back diode is shown according to an example of an embodiment;

[0016] Figure 3b An active region structure for an open base transistor is shown according to an example of an embodiment;

[0017] Figure 4 A donor substrate is shown that is bonded to a carrier substrate prior to thinning the wafer;

[0018] Figure 5 A donor substrate is shown that is bonded to a carrier substrate after thinning the wafer;

[0019] Figure 6 A semiconductor device formed from a donor substrate and a carrier substrate according to an embodiment;

[0020] and

[0021] Figure 7 A semiconductor device formed from a donor substrate and a carrier substrate according to an embodiment is shown. DETAILED DESCRIPTION

[0022] Reference is made to Figures 1 to 6 An example method of forming a semiconductor device according to an embodiment is described. The process can begin with Figure 1The carrier wafer or first substrate 100 is shown. A first metal conductive layer 102 can be formed on a first major surface of the carrier wafer or first substrate 100. The first metal layer 102 can be deposited on the first substrate 100 by any suitable process, such as evaporation or sputtering. The first metal layer 102 can be formed of, for example, aluminum, gold, titanium, tungsten, platinum, or alloys thereof. The first substrate 100 can be a semiconductor substrate, such as a silicon substrate, and can be a doped substrate or an undoped substrate. Preferably, the first metal layer 102 forms an ohmic contact with the first substrate 100.

[0023] As shown in Figure 2 , a donor wafer or second substrate 104 is provided. One or more active semiconductor device regions 106 can be formed in the second substrate 104. A second metal conductive layer 108 can be formed on a first major surface of the second substrate 104, and the second metal layer 108 can be electrically connected to contact regions of the one or more semiconductor device regions 106 formed in the second substrate 104. The semiconductor device regions 106 can be formed in the second substrate 104 by diffusion and / or implantation, and some examples of semiconductor device region structures are discussed below with reference to Figure 3a and Figure 3b .

[0024] Referring to Figure 3a , a back-to-back diode structure is shown. In this example, the active regions 106 are formed in a lightly doped p- second substrate 104. In this example, each cathode of the active regions 106 is formed by a buried highly doped n-type region (BN) followed by a deep highly doped n-type (DN) region, thereby forming the cathode region of each diode. The anode region is formed in the substrate of the highly doped p+ region, and the anode contact is formed to the highly doped p+ region of the active regions 106 using the second metal layer 108.

[0025] To this end, the back-to-back diode structure is an anode-anode connection structure, and the formation and arrangement of the cathode contact is discussed in more detail below with reference to Figure 6 .

[0026] Figure 3b Another example of an example active structure 106 is shown. In this case, the active structure 106 is a so-called open base transistor formed in a lightly doped p- second substrate 104. In this example, the active regions 106 are formed by a buried highly doped n-type region (BN) forming the emitter region, followed by a p- well base region, in turn followed by a highly doped n+ collector region. The collector contact is formed to the highly doped n+ region of the active regions 106 using the second metal layer 108. Since the open base device is a bidirectional type device, the roles of the emitter and collector will change depending on the polarity, and only the (floating) base will remain the base when the polarity is reversed.

[0027] Embodiments of the present disclosure are not limited to the device structure as shown in Figure 3a or Figure 3b The skilled person will appreciate that any suitable device structure, combination of structures or structures can be arranged and implemented without departing from the concept of the present disclosure. In all embodiments, the metal layer 108 can be connected to a plurality of device structures.

[0028] After forming the first metal layer 102 on the first substrate 100 and the active regions 106 in the second substrate 104 and the second metal layer 108, the first substrate 100 and the second substrate 104 are bonded together. As shown in Figure 4 the first metal layer 102 is bonded to the second metal layer 108.

[0029] In this regard, from an electrical point of view, the bonded first metal layer 102 and the second metal 108 can be considered as one multi-layered layer structure. In this way, the first metal layer 102 bonded to the second metal layer 108 can be considered as a buried metal layer, i.e. buried between the first substrate 100 and the second substrate 104.

[0030] Examples of bonding techniques can include thermal compression bonding. By simultaneously applying heat and force, the first metal layer 102 and the second metal layer 108 are brought into atomic contact. Atoms from the lattice of the first metal layer migrate to the lattice of the second metal layer based on lattice vibrations and this atomic interaction results in the first metal layer being bonded to the second metal layer. Alternatively, an intermetallic bonding layer such as a eutectic alloy layer can be formed as a bonding material. Other alternatives for the bonding layer can include simultaneous adhesive-metal bonding or simultaneous fusion-metal bonding.

[0031] As shown in Figure 5 after bonding the first substrate 100 and the second substrate 104 together, the second substrate 104 on the main side opposite the second metal layer 108 can be thinned to expose portions of the active regions 106. For example, the following examples are presented in Figure 3a or Figure 3b The second substrate 104 can be thinned by any suitable etching or grinding process to remove a portion of the second substrate 104 to expose the highly doped n+ region (BN) after the following examples are presented in

[0032] A finished semiconductor device 120 is shown in Figure 6 which shows suitable contacts 110 formed on the active regions 106. Prior to forming the contacts 110, an optional isolation layer 112 can be formed on the side of the second substrate 104 opposite the second metal layer 108.

[0033] Before bonding the first substrate 100 to the second substrate 104, an active region 106 is formed in the second substrate 104. Therefore, all the high-temperature diffusion processes required to form the active region 106 are performed on the second substrate 104 prior to bonding. As a result, low-melting-point metals such as gold or aluminum can be used in the bonding process because the bonding metal does not diffuse outwards. Furthermore, high-temperature processing of the device (i.e., for forming various diffusion regions) after bonding of the first and second metal layers that form the buried metal layer is difficult. This would require metals with high melting points to withstand the temperatures required to form various diffusion regions and could lead to serious mechanical problems such as wafer bending or metal layer degradation. Therefore, it is advantageous to perform all high-temperature processes, such as diffusion processes, prior to wafer bonding.

[0034] Furthermore, the resistance of the bonded metal layers 102 and 108 can be controlled by appropriately selecting the metal and / or the metal thickness.

[0035] In Figure 5 In an alternative process, before bonding the first metal layer 102 to the second metal layer 108, the second substrate 104 on the main side opposite to the second metal layer 108 can be thinned to expose portions of each active region 106. Furthermore, depending on the thickness or depth at which the active regions 106 are formed in the second substrate 104, the second substrate 104 may not need to be thinned or may be partially thinned to expose each active region 106, allowing suitable contacts 110 to be formed.

[0036] Optionally, the first substrate 100 may be thinned before further processing of the finished device 120. This may include partially thinning the first substrate 100 to reduce its thickness and / or locally thinning it to facilitate segmentation of the device from an array of such devices.

[0037] Figure 7 A semiconductor device 120 according to one embodiment is shown. A donor wafer or second substrate 104 may include at least one trench 116 extending from a first main surface of the second substrate 104 to an opposing second main surface and located between active regions 106. At least one trench 116 may be filled with an electrically insulating material (e.g., oxide) to isolate the respective active regions 106 to prevent parasitic currents from flowing between the active regions through the second substrate 104.

[0038] At least one trench 116 can be formed in the second substrate 104, simultaneously forming an active region 106. As shown, the trench 116 can also be arranged at the edge of the device 120 to prevent parasitic currents (e.g., leakage current) from the edge of the device 120. In cases where the second device structure is not an active structure but has simple contact with the bulk semiconductor material, the contact can be connected to the buried metal layer via conductive trenches to reduce the resistance between the contact and the buried metal layer. This can effectively reduce the on-resistance of the device.

[0039] In terms of operation and reference Figure 6 Its manifestation Figure 3a Back-to-back diode arrangement or Figure 3b In the open-type base transistor arrangement, current can flow from one contact 110 through one of the active regions 106 and into a multilayer metal layer formed by a first metal layer 102 and a second metal layer 108. The current then flows through the multilayer metal and another active region 106 until it reaches another contact 110.

[0040] Because the multilayer metal structure is formed by a first metal layer 102 and a second metal layer 108, the current distribution perpendicular to the surface is substantially uniform. In other words, the current density is essentially the same in each region across the entire device structure. Compared to the current path of a bulk semiconductor with a sheet resistance of 200-1000 mΩ, the resistance of the multilayer metal structure is very small, with a sheet resistance of 1-20 mΩ. As a result, unlike known arrangements, the current density at the inner and outer edges of the device will be substantially uniform.

[0041] Furthermore, for the same reason, the differential on-resistance is very small. The buried metal layer effectively reduces the bulk that is typically part of the current path. Therefore, the on-resistance of the device according to the embodiment is reduced by 180-990 mOhm. Additionally, because the silicon portion of the current path (i.e., the vertical path) is very small, current will only be transmitted from the top contact to the buried metal layer in the vertical direction, due to the very low silicon resistance of this path.

[0042] Furthermore, the introduction of the multilayer metal structure 114 provides improved heat dissipation from the active region 106 of the device 120 during operation. Specifically, heat generated during operation of the device 120 will be conducted away from the active region 106 through the multilayer metal structure, thereby increasing the current robustness of the device 120.

[0043] In an alternative to the above embodiment, the donor wafer or second substrate 104 may be an SOI (silicon-on-insulator) wafer. After forming the active region 106 in the SOI wafer and forming the second metal conductive layer 108 on the first main surface, as described above... Figure 4The SOI wafer can be bonded to the first substrate 100. The oxide layer of the SOI wafer can be used as the optional isolation layer 112 with appropriate contacts 110 formed therethrough to contact the active region 106, as described above with reference to Figure 6 as discussed above.

[0044] If the oxide layer of the SOI wafer is a buried oxide, the SOI wafer on the main surface opposite the second metal layer 108 can be thinned to expose the buried oxide. As described above, the buried oxide can be used as the optional isolation layer 112 and appropriate contacts can be formed therethrough to connect to the active region 106. As discussed above with reference to Figure 7 The trench 116 can also be formed in the SOI wafer, as discussed above.

[0045] As mentioned above with reference to Figure 3a and 3b The skilled person will appreciate that the arrangement of the active layer is not limited to the examples of back-to-back diodes or open-base transistors. Based on the above teachings, the skilled person will appreciate that the concept of a buried metal layer is applicable to different types of semiconductor device structures. For example, devices such as vertical MOS diodes, trench MOS transistors, insulated gate bipolar transistors (IGBTs) and / or vertical bipolar transistors or any combination of devices can be arranged as the active region 106.

[0046] The above-described embodiments are particularly suitable for semiconductor devices for transient voltage suppression (TVS), which can be required to shunt overcurrents during operation when a transient voltage exceeds the avalanche breakdown potential of the device. A TVS device typically suppresses all transient voltages higher than the breakdown voltage of the device and because these transient voltages generate heat in the device, the buried metal layer formed by the first metal layer 102 and the second metal layer 108 improves the heat dissipation capability of the device while also reducing the on-resistance of the device. The device is improved due to the inclusion of an additional thermal conduction path and current conduction path.

[0047] Particular aspects and preferred aspects of the present application are set out in the accompanying independent claims. Combinations of features from the dependent claims and / or the independent claims can also be made as appropriate, not just as described in the claims.

[0048] The scope of the disclosure encompasses any novel feature or combination of features disclosed herein or any generalisation thereof, whether or not it mitigates any of the same problems as those disclosed by the application. The applicant makes no intention to relinquish any features of the application, and the intent includes the disclosure of alternative aspects to the extent that they present distinct innovations over the prior art. In particular, it is intended to require protection of novel subject matter or the application thereof, in any combination, per se, or in

[0049] Features described in the context of separate embodiments can also be provided in combination, in a single embodiment. Conversely, various features described in the context of a single embodiment can also be provided separately or in any appropriate

[0050] The term "comprising" does not exclude other elements or steps, the term "a" or "an" does not exclude a plurality, and the term "one" or "only one" does not exclude there being more than one. A single unit can fulfil the functions of several features recited. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures can not be used to advantage. The references signs in the claims shall not be construed as limiting the scope of the claims.

Claims

1. A method of fabricating a semiconductor device, the method comprising: providing a first semiconductor substrate having a first major surface and an opposing second major surface, the first major surface having a first metal layer formed directly thereon; providing a second semiconductor substrate having a first major surface and an opposing second major surface, wherein the second semiconductor substrate includes a plurality of active device regions formed therein and a continuous second metal layer formed directly on the first major surface and laterally across an entire width of the semiconductor device to connect each of the plurality of active device regions; directly bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate to form a buried metal layer disposed between the two semiconductor layers, the buried metal layer configured such that a current distribution perpendicular to the surface is uniform and the current density is the same for each region across the entire area of the device; and forming a plurality of device contacts on the second major surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions such that current input from any one of the plurality of device contacts will flow through a corresponding one of the plurality of active device regions, into the buried metal layer and laterally along the buried metal layer, out of the buried metal layer, and then through another one of the plurality of active device regions to reach another one of the plurality of device contacts corresponding to the other active device region.

2. The method of claim 1, further comprising bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate using a gold or aluminum bonding layer.

3. The method of claim 1, further comprising thinning the opposing second major surface of the second semiconductor substrate prior to bonding the first metal layer to the second metal layer.

4. The method of claim 1, further comprising forming one or more trench regions extending from the first major surface to the opposing second major surface of the second semiconductor substrate.

5. The method of claim 4, further comprising filling the trench regions with an insulating material.

6. The method of claim 1, wherein, the second semiconductor substrate is a silicon-on-insulator substrate.

7. The method of claim 1, wherein, the plurality of active device regions are bidirectional active device regions.

8. A semiconductor device comprising: a first semiconductor substrate having a first major surface and an opposing second major surface, the first major surface having a first metal layer formed directly thereon; a second semiconductor substrate having a first major surface and an opposing second major surface, wherein the second semiconductor substrate includes a plurality of active device regions formed therein and a continuous second metal layer formed directly on the first major surface and laterally across an entire width of the semiconductor device to connect each of the plurality of active device regions; a buried metal layer disposed between the two semiconductor layers, the buried metal layer configured such that a current distribution perpendicular to the surface is uniform and the current density is the same for each region across the entire area of the device. wherein the first metal layer of the first semiconductor substrate is directly bonded to the second metal layer of the second semiconductor substrate to form a buried metal layer disposed between the two semiconductor layers, the buried metal layer being configured such that a current distribution perpendicular to the surface is uniform and the current density is the same for each region over the entire area of the device; and a plurality of device contacts disposed on a second major surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions; and the semiconductor device is configured such that current input from any one of the plurality of device contacts will flow through a respective one of the plurality of active device regions, into the buried metal layer and flow laterally along the buried metal layer, out of the buried metal layer, and then through another one of the plurality of active device regions to reach another one of the plurality of device contacts corresponding to the other active device region.

9. The semiconductor device of claim 8, wherein, the first and second metal layers are gold or aluminum.

10. The semiconductor device of claim 8, further comprising one or more trench regions extending from a first major surface to an opposing second major surface of the second semiconductor substrate.

11. The semiconductor device of claim 10, wherein, the trench regions are filled with an insulating material.

12. The semiconductor device of claim 8, wherein, the second semiconductor substrate is a silicon-on-insulator substrate.

13. The semiconductor device of claim 8, wherein, the active device regions are bidirectional active device regions.

14. The semiconductor device of claim 8, wherein, the buried metal layer has a sheet resistance of 1-20 mΩ.

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