Package structure and method of forming the same

Abstract

A method of forming a package structure includes bonding a device die to a package assembly. The device die includes a semiconductor substrate and a through-via extending into the semiconductor substrate. The method further includes depositing a dielectric liner to liner a sidewall of the device die; depositing a dielectric layer on the dielectric liner; and planarizing the dielectric layer and the first device die. Remaining portions of the dielectric liner and the dielectric layer form a gap filling region and expose a top end of the through hole. An implantation process is performed to introduce a stress modulating dopant into at least one of the dielectric liner and the dielectric layer. A redistribution line is formed over the through hole, and the redistribution line is electrically connected to the through hole. The embodiment of the invention also relates to a packaging structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to package structures and methods of forming package structures. Background Art

[0002] Integrated circuit packages may have multiple package components, such as device dies and package substrates, bonded together to increase functionality and integration levels. Warping may occur due to differences between the different materials of the multiple package components. Warping may cause misjoining issues and misjoining of some conductive components that are intended to be bonded to each other, resulting in circuit failure. Summary of the invention

[0003] An embodiment of the present disclosure provides a method for forming a packaging structure, the method comprising: bonding a first device die to a packaging assembly, wherein the first device die comprises a semiconductor substrate; depositing a dielectric liner to line the sidewalls of the first device die; depositing a dielectric layer on the dielectric liner; planarizing the dielectric layer and the first device die, wherein the dielectric liner and the remaining portion of the dielectric layer form a gap-filling region; performing a first implantation process to introduce a stress-modulated dopant into at least one of the dielectric liner and the dielectric layer; and forming a redistribution line above the first device die, and the redistribution line is electrically connected to the first device die.

[0004] Another embodiment of the present disclosure provides a packaging structure, which includes: a packaging component, the packaging component includes a top dielectric layer, wherein the top dielectric layer includes a first portion and a second portion; a device die, located above the second portion of the top dielectric layer and bonded to the second portion of the top dielectric layer; and a gap-fill dielectric region, the gap-fill dielectric region includes a dielectric liner, the dielectric liner includes a first portion lining the sidewall of the device die, and a second portion located above the first portion of the top dielectric layer and contacting the first portion of the top dielectric layer, wherein the second portion of the dielectric liner includes a dopant having a first concentration, and wherein the second concentration of the dopant in the second portion of the top dielectric layer is lower than the first concentration.

[0005] Another embodiment of the present disclosure provides a packaging structure, which includes: a first device die; a second device die, the second device die is located above the first device die and bonded to the first device die, wherein the first device die extends laterally beyond the sidewall of the second device die; and a gap-filling dielectric region, the gap-filling dielectric region includes a dielectric liner, the dielectric liner includes a first portion located on the sidewall of the second device die, the dielectric liner also includes a second portion, the second portion is located above the first device die and contacts the first device die to form a horizontal interface, wherein the second portion includes a dopant, and the dopant has a first peak concentration in the second portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, aspects of the present disclosure are best understood from the following detailed description. It is noteworthy that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 13 A cross-sectional view of an intermediate stage in forming a multi-layer package is shown in accordance with some embodiments.

[0008] Figures 14 to 19 A cross-sectional view of an intermediate stage in forming a multi-layer package is shown in accordance with an alternative embodiment.

[0009] Figure 20 to Figure 23 Shown are patterns and locations of stress modulated regions in a wafer according to some embodiments.

[0010] Fig.24A and Fig. 24B A vertical stress dopant distribution profile and a horizontal stress dopant distribution profile are shown, respectively, in accordance with some embodiments.

[0011] Fig.25 A process flow for forming a package including stress modulating dopants is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing the different components of the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the individual embodiments and / or configurations discussed.

[0013] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0014] Methods of implanting stress modulating dopants into a dielectric layer to form stress modulating regions are provided. The warpage profile of the implanted wafer can be improved, and the warpage can be reduced. The embodiments discussed herein are intended to provide examples of how the subject matter of the present disclosure can be made or used, and one of ordinary skill in the art will readily appreciate the modifications that can be made while remaining within the intended scope of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may also be performed in any logical order.

[0015] Figures 1 to 13 1 shows a cross-sectional view of an intermediate stage of forming a package according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in the following Fig.25 The process flow shown.

[0016] Figure 1 A release film 22 is shown formed on the carrier 20. The carrier 20 may be a glass carrier, a silicon wafer, an organic carrier, etc. The release film 22 may be formed of a polymer-based material and / or an epoxy-based thermal release material (such as a light-to-heat conversion (LTHC) material) that can be decomposed under radiation such as a laser beam, so that the carrier 20 can be separated from the upper structure to be formed in a subsequent process. According to some embodiments, the release film 22 is applied to the carrier 20 by coating.

[0017] Figure 1 It is further shown that a redistribution structure including a redistribution line (RDL) is formed by a first RDL process. The corresponding process is shown as follows Fig.25 The process flow 200 is shown as process 202. According to an alternative embodiment, the redistribution structure 24 including a plurality of dielectric layers 26 and a plurality of RDLs 28 is formed over the release film 22.

[0018] According to some embodiments, dielectric layer 26 may be formed of or include an inorganic dielectric material, which may be a silicon-containing dielectric material, such as SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc., or a combination thereof. According to an optional embodiment, dielectric layer 26 may be formed of or include an organic dielectric material, which may be a polymer. For example, dielectric layer 26 may be formed of or include polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc., or dielectric layer 26 may include polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc.

[0019] In an exemplary embodiment, the formation of the bottom layer of RDL 28 may include forming a metal seed layer (not shown) over the underlying dielectric layer 26, forming a patterned mask (not shown), such as a photoresist, over the metal seed layer, and then performing a metal plating process to deposit a metal material on the exposed metal seed layer. The patterned mask and the portion of the metal seed layer covered by the patterned mask are then removed, leaving a metal layer such as Figure 1 The bottom RDL 28 is shown. According to some embodiments, the metal seed layer includes a titanium layer and a copper layer above the titanium layer. The metal seed layer may be formed using a process such as physical vapor deposition (PVD). Plating may be performed using an electrochemical plating process, for example.

[0020] The formation of the upper RDL 28 may include depositing a dielectric layer 26 over the bottom RDL 28, patterning the dielectric layer 26 to form a via opening and exposing the RDL 28 below, depositing a blanket metal seed layer extending into the via opening, and forming and patterning a plating mask (such as a photoresist), with an opening formed in the plating mask and located directly above the via opening. A plating process is then performed to plate a metal material that fills the via opening and has some portions that are higher than the top surface of the dielectric layer 26. The plating mask is then removed, followed by an etching process to remove the exposed portions of the metal seed layer previously covered by the plating mask. The remaining portions of the metal seed layer and the plated metal material are the RDL 28. The RDL 28 includes an RDL line (also referred to as a trace or trace portion) and a via portion (also referred to as a via). The trace portion is located above the corresponding dielectric layer 26, and the via portion is located in the corresponding dielectric layer 26.

[0021] The bonding layer 32 and the bonding pad 30 are formed as the top of the redistribution structure 24. The bonding layer 32 may be formed of a silicon-containing dielectric material, which may be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc. or a combination thereof. The bonding pad 30 may include copper, and the bonding pad 30 may be formed by a damascene process. The bonding layer 32 and the bonding pad 30 are planarized so that their top surfaces are coplanar, which may be due to a chemical mechanical polishing (CMP) process performed when forming the bonding pad 30.

[0022] refer to Figure 2 , the device die 36 is bonded to the wafer 2. The corresponding process is shown as follows Fig.25 Process 204 in process flow 200 is shown. According to some embodiments, each device die 36 may be a logic die, which may be a central processing unit (CPU) die, a microcontroller (MCU) die, an input output (IO) die, a baseband die, etc. Device die 36 may also include a memory die.

[0023] Device die 36 may include semiconductor substrate 38, which may be a silicon substrate. Through silicon vias (TSVs) 40, sometimes referred to as through substrate vias, through semiconductor vias, or through vias, are formed to extend into semiconductor substrate 38. TSVs 40 are used to connect devices and metal lines formed on the front side (bottom side shown) of semiconductor substrate 38 to the back side. Furthermore, device die 36 includes an interconnect structure 42 for connecting to active devices and passive devices in device die 36. Interconnect structure 42 includes metal lines and vias.

[0024] Each device die 36 includes a bonding pad 44 and a bonding layer 46 (also referred to as a bonding film) at the bottom surface of the device die 36 as shown. The bottom surface of the bonding pad 44 can be coplanar with the bottom surface of the bonding layer 46. According to some embodiments, the bonding layer 46 can be formed of a silicon-containing dielectric material, which can be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc. or a combination thereof. The bonding pad 44 may include copper and the bonding pad 44 may be formed by a damascene process. The bonding layer 46 and the bonding pad 44 are planarized so that their surfaces are coplanar, which may be due to CMP in forming the bonding pad 44.

[0025] The bonding can be achieved by bumpless stacking technology, wafer-to-wafer bonding, die-to-wafer bonding, or die-to-die bonding technology. For example, the bonding pad 44 is bonded to the bonding pad 30 by metal-to-metal direct bonding. According to some embodiments, the metal-to-metal direct bonding is copper-to-copper direct bonding. In addition, the bonding layer 46 is bonded to the bonding layer 32 by, for example, fusion bonding, while generating Si-O-Si bonds. Figure 2 The structure shown is referred to as a reconstructed wafer 50 , and more components will be formed in subsequent processes to further expand the reconstructed wafer 50 .

[0026] Figure 2 FIG. 4 shows an implantation process 48 for forming a stress modulation region in the bonding layer 32 according to some embodiments. The corresponding process is shown as follows Fig.25 Process 205 in process flow 200 is shown. Throughout the description, multiple implant processes are discussed. This does not mean that all implant processes discussed are performed. Instead, forming a package may include one or more of the implant processes discussed, while other implant processes discussed may be skipped. At least one, or more, or all of the implant processes discussed may be performed in any combination.

[0027] Prior to performing the implantation process 48, the portion of the bonding layer 32 to be implanted is determined. All or some portions of the wafer-level structure shown may be implanted. For example, Figure 20 to Figure 23The portion to be implanted in the implant process in question (as will be discussed in subsequent paragraphs) is shown. According to some embodiments, in order to determine which portions of the reconstructed wafer 50 will be implanted, a sample reconstructed wafer may be formed, for example, such as having Figure 7 or Fig.19 The same structure as shown in . The warpage of the sample reconstructed wafer is measured. The measurement results include the warpage profile of the sample structure, such as which parts have warpage, and the degree of warpage.

[0028] Based on the warpage profile, the portion of the reconstructed wafer 50 to be implanted is determined. According to some embodiments, a blanket implant is performed. According to an alternative embodiment, a selective implant process is performed on some but not all of the reconstructed wafer 50. When performing the selective implant process, an implant mask such as a patterned photoresist may be formed to mask portions of the reconstructed wafer 50 that are not implanted.

[0029] According to some embodiments, the implanted ions (hereinafter also referred to as stress modulation dopants) may include Ge, B, P, As, Ga, etc., or combinations thereof. The implanted ions may also include H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb, or combinations thereof, and / or combinations having Ge, B, P, As, and / or Ga.

[0030] According to some embodiments, the implantation process 48 is controlled so that the peak concentration of the implanted stress modulating dopant is located inside the bonding layer 32. Throughout the description, when a layer is discussed as being implanted with a stress modulating dopant, the implantation process is controlled so that the peak concentration of the stress modulating dopant will be inside the implanted layer and the concentration will decrease when entering adjacent layers. According to some embodiments, the peak concentration of the stress modulating dopant in the implanted layer may be greater than about 10 16 / cm 3 , and according to some embodiments, the peak concentration of the stress modulation dopant in the implanted layer may be about 10 16 / cm 3 and about 10 22 / cm 3 in the range between.

[0031] Throughout the description, the letter "I" (for "implanted") is used to indicate regions implanted with stress-modulating dopants, and the implanted portion of bonding layer 32 is indicated as implanted portion (or region) 32-I. The symbol "UI" (for "unimplanted") is used to indicate regions not implanted with stress-modulating dopants, and the unimplanted portion of bonding layer 32 is therefore indicated as portion (or region) 32-UI. The unimplanted region (portion) may have a lower concentration of stress-modulating dopants than the implanted region, or may be free of stress-modulating dopants.

[0032] like Figure 2 As shown, device die 36 acts as an implant mask to mask underlying portions of bonding layer 32, such that these portions are unimplanted portions 32-UI. Some other portions are not covered by device die 36, and are implanted to form implanted portions 32-I.

[0033] By the implantation process 48, the material of the bonding layer 32 is modified. In addition, the density of the implanted portion is increased. Therefore, the warpage of the reconstructed wafer 50 is reduced, and the warpage profile is also modified. For example, the implantation process 48 and / or subsequent implantation processes performed separately or together can produce a modified warpage profile, and the warpage is reduced.

[0034] According to some embodiments, a backside grinding process may be performed to thin device die 36. By thinning device die 36, the aspect ratio of the gaps between adjacent device dies 36 is reduced so that gap filling can be performed. Otherwise, gap filling may be difficult due to the high aspect ratio of the gaps. After backside grinding, TSVs 40 may be exposed. Optionally, TSVs 40 are not exposed at this time, and backside grinding is stopped when there is a thin layer of substrate covering TSVs 40. According to these embodiments, the backside grinding process may be performed to thin the ... Figure 5 The TSV 40 is exposed in the step shown.

[0035] Figure 3 and Figure 4 The formation of multiple gap-fill layers is shown. In accordance with some embodiments, the gap-fill layers include a dielectric liner 54 and a dielectric layer 56 over and contacting the dielectric liner 54 .

[0036] refer to Figure 3 , depositing dielectric liner 54. The corresponding process is shown as Fig.25Process 206 in process flow 200 is shown. Dielectric liner 54 may be deposited using a conformal deposition method such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Dielectric liner 54 is formed of a dielectric material that has good adhesion to the sidewalls of device die 36 and the top surfaces of bonding layer 32 and bonding pad 30. According to some embodiments, dielectric liner 54 is formed of a nitride-containing material such as silicon nitride, SiON, SiCN, etc. Dielectric liner 54 extends over and contacts the sidewalls of device die 36.

[0037] According to some embodiments, an implantation process 58 is performed to implant stress modulation dopants into the dielectric liner 54. The corresponding process is shown as follows. Fig.25 Process 208 in process flow 200 is shown. According to an optional embodiment, implantation process 58 is skipped. According to some embodiments, implantation process 58 includes an inclined implantation so that the stress modulation dopant can be implanted into a sidewall portion 54-SW of dielectric liner 54, which is located on the sidewall of device die 36. Therefore, according to some embodiments, sidewall portion 54-SW is also represented as 54-I. Implantation process conditions, such as the tilt angle and implantation energy, are controlled so that the peak concentration of the stress modulation dopant is located in the sidewall portion of dielectric liner 54. According to some embodiments, depending on the implantation energy and the tilt angle, the peak concentration of the stress modulation dopant can also be in the horizontal portion of dielectric liner 54, or can be in the underlying bonding layer 32.

[0038] The implant process 58 may also include a vertical implant process, which may be performed in addition to or without the tilted implant. The vertical implant process is controlled to have a peak concentration of the stress-modulating dopant in the horizontal portion of the dielectric liner 54 .

[0039] When the implantation process 58 includes a vertical implantation process but does not include a tilted implantation process, the lower portion of the sidewall portion 54-SW may be free of stress-modulation dopants and is also represented as 54-UI according to an optional embodiment, while the horizontal portion and some upper portions of the sidewall portion are doped and are marked as 54-I.

[0040] The stress modulation dopant introduced by implantation process 58 may be selected from the same as implantation process 48 ( Figure 2 ) and may be the same or different from the stress-modulating dopants introduced by implantation process 48.

[0041] Figure 4 The formation of a dielectric layer 56 over and in contact with the dielectric liner 54 is shown. The corresponding process is shown as follows Fig.25Process 210 in process flow 200 is shown. Dielectric layer 56 is formed of a material different from the material of dielectric liner 54. According to some embodiments, dielectric layer 56 is formed of silicon oxide, while other dielectric materials such as silicon carbide, silicon oxynitride, silicon oxycarbonitride, etc. may also be used when there is a sufficient etching selectivity (e.g., greater than about 50) between dielectric layer 56 and dielectric liner 54. Etching selectivity is the ratio of the etching rate of dielectric layer 56 to the etching rate of dielectric liner 54 when dielectric layer 56 is etched in a subsequent process. Dielectric layer 56 can be deposited as a conformal layer, in which the thickness of the horizontal portion and the vertical portion are substantially equal to each other, or deposited as a non-conformal dielectric layer.

[0042] refer to Figure 5 , a planarization process such as a CMP process or a mechanical grinding process is performed to remove the excess portion of the dielectric layer 56 and the dielectric liner 54, thereby exposing the device die 36. The corresponding process is shown as follows Fig.25 The process flow 200 is shown as process 212. In addition, the through-hole 40 is also exposed. The dielectric liner 54 and the remaining portion of the dielectric layer 56 are collectively referred to as the (gap-fill) isolation region 62.

[0043] According to some embodiments, an implantation process 64 is performed to implant stress modulation dopants into the isolation region 62. The corresponding process is shown as follows Fig.25 According to an alternative embodiment, the implantation process 64 is skipped. According to another alternative embodiment, as shown in FIG. Figure 6 As shown, the implantation process 64 is performed after forming the through via 66. The peak concentration of the stress-modulating dopant may be inside the isolation region 62 and may also be in the semiconductor substrate 38.

[0044] In the implantation process 64, some top portions of the semiconductor substrate 38 and the through-vias 40 are also implanted. Since the density of the through-vias 40 (which include metal) is high, the stress-modulating dopants are concentrated at the tops of the through-vias 40. For example, Figure 5 The top portion 40 -I containing stress modulation dopants and the lower portion 40 -UI without stress modulation dopants are schematically shown. Due to the blocking of the through hole 40, the stress modulation dopants are enriched at the top portion 40 -I of the through hole 40, wherein the concentration of the stress modulation dopants in the top portion 40 -I is higher than the concentration of the stress modulation dopants in the dielectric liner 54 and the dielectric region 56.

[0045] According to some embodiments, the peak concentration of the stress-modulation dopant is at or above an intermediate level of the isolation region 62, which is located between the top surface and the bottom surface of the isolation region 62. The stress-modulation dopant introduced by the implantation process 64 may extend to the bottom of the isolation region 62, or may be limited to the upper portion of the isolation region 62, with the bottom of the isolation region 62 being free of the stress-modulation dopant.

[0046] The stress-modulating dopant introduced by implant process 64 may be selected from the same set of candidate dopants as the stress-modulating dopant introduced by implant process 48 and / or implant process 58 , and may be the same as or different from the stress-modulating dopant introduced by implant process 48 and / or implant process 58 .

[0047] Figure 6 The formation of a through hole 66 penetrating the isolation region 62 is shown. The corresponding process is shown as follows Fig.25 Process 216 in process flow 200 is shown. According to some embodiments, a patterned etch mask such as photoresist is formed (not shown), and the patterned photoresist is used as an etch mask to etch dielectric layer 56. An opening is thereby formed (occupied by through hole 66), and the opening extends down to dielectric liner 54, which acts as an etch stop layer. Another etching process is then performed to etch through dielectric liner 54, thereby exposing the underlying metal pad, which is also labeled with reference numeral 30.

[0048] Next, a dielectric liner (not shown) is formed to line the sidewalls of the opening to isolate the semiconductor substrate 38 from the subsequently formed through-hole 66. In a subsequent process, a conductive material is filled into the opening, followed by a planarization process to remove excess conductive material, thereby forming the through-hole 66.

[0049] According to an alternative embodiment, the through-hole 66 is not formed. Accordingly, the through-hole 66 is shown as a dotted line to indicate that the through-hole 66 may or may not be formed.

[0050] refer to Figure 7 , forming a (backside) interconnect structure 72 on the back side of the device die 36. The corresponding process is shown as Fig.25 Process 218 in process flow 200 is shown. Interconnect structure 72 includes redistribution line (RDL) 70 (which also includes bonding pads) and dielectric layer 68 (which also includes a bonding layer). According to some embodiments, dielectric layer 68 is formed of an oxide such as silicon oxide, a nitride such as silicon nitride, etc. RDL 70 can be formed using a damascene process, which includes etching dielectric layer 68 to form an opening, depositing a conductive barrier layer into the opening, plating a metal material such as copper or a copper alloy, and performing a planarization process to remove excess portions of RDL 70.

[0051] According to some embodiments, an implantation process 74 is performed to implant stress modulation dopants into the dielectric layer 68. The corresponding process is shown as follows. Fig.25 220 in the process flow 200 shown. According to an alternative embodiment, the implantation process 74 is skipped. The peak concentration of the stress modulation dopant can be inside the dielectric layer 68. The stress modulation dopant introduced by the implantation process 74 can be selected from the same as the implantation process 48 ( Figure 2 ), injection process 58( Figure 3 ) and / or implantation process 64 ( Figure 5 ) of the same group of candidate dopants.

[0052] According to some embodiments, the packaging process includes a multi-layer packaging process, wherein the device die 36 is a layer 1 die. In a subsequent process, a layer 2 die will be bonded. The process of forming the layer 2 die can be similar to the process associated with the layer 1 die, and the process of forming the layer 2 die is briefly discussed below.

[0053] refer to Figure 8 , the device die 76 (layer 2 die) is bonded to the bonding pads in the interconnect structure 72. The corresponding process is shown as follows Fig.25 Process 222 in process flow 200 is shown. Device die 76 may include semiconductor substrate 78, through via 80, interconnect structure 82, bonding pad 84, and bonding layer 86. In some embodiments, bonding pad 84 is bonded to bonding pad in RDL 70 by metal-to-metal direct bonding, and bonding layer 86 is bonded to bonding layer in dielectric layer 68 by fusion bonding.

[0054] According to some embodiments, an implantation process 88 is performed to implant stress-modulating dopants into selected portions of dielectric layer 68 that are not covered by device die 76 and are referred to as stress-modulating regions 68-I. The corresponding process is shown as Fig.25 224 in process flow 200 is shown. According to an alternative embodiment, implant process 88 is skipped. The portion of dielectric layer 68 directly below device die 76 is not implanted and is referred to as unimplanted portion 68-UI. The peak concentration of stress-modulating dopants may be within dielectric layer 68. The stress-modulating dopants introduced by implant process 88 may be selected from the same group as the stress-modulating dopants introduced by implant processes 48, 58, 64, and / or 74, and may be the same as or different from the stress-modulating dopants introduced by implant processes 48, 58, 64, and / or 74.

[0055] Fig. 9 The formation of a dielectric liner 94 and an optional implantation process 98 according to some embodiments are shown. The corresponding process is shown as Fig.25The process 226 in the process flow 200 is shown. The details of the dielectric liner 94 and the implant process 98 can be described in detail. Figure 3 The dielectric liner 54 and implant process 58 shown are substantially the same, and the details will not be repeated here.

[0056] Fig.10 The formation of dielectric layer 96, a planarization process to form isolation region 102, and the optional formation of through-hole 106 are shown. The corresponding process is shown as Fig.25 The process flow 200 is shown as processes 228, 230, 232, and 234. The optional implant process 104 may (or may not) be performed. The details of the dielectric layer 96, the through hole 106, and the implant process 104 may be different from those of FIG. Figures 4 to 6 The dielectric layer 56, through-via 66, and implant process 64 shown are substantially the same, and the details will not be repeated here.

[0057] Fig.11 The formation of a redistribution structure 112 including a dielectric layer 108 and an RDL 110 and an optional implantation process 114 are shown in accordance with some embodiments. The corresponding process is shown as follows Fig.25 The process 236 and 238 in the process flow 200 are shown. The details of the dielectric layer 108, the RDL 110 and the implant process 114 can be described in detail. Figure 7 The dielectric layer 68, RDL 70 and implant process 74 shown are substantially the same and the details will not be repeated here. The formation of the reconstructed wafer 50 is thus completed.

[0058] In subsequent processes, such as Fig.12 As shown, the wafer 120 is bonded to the reconstructed wafer 50 by a wafer-on-wafer bonding process. The corresponding process is shown as follows Fig.25 Process 240 in process flow 200 is shown. According to an optional embodiment, more layers of device dies may be further bonded to the second layer device die 76 before bonding wafer 120 to further expand reconstructed wafer 50. Due to the implantation process performed during the formation of reconstructed wafer 50, the warpage profile of reconstructed wafer 50 is improved and / or the warpage of reconstructed wafer 50 is reduced. Accordingly, the bonding of wafer 120 and reconstructed wafer 50 may be free of unbonding problems.

[0059] According to some embodiments, wafer 120 is a device wafer including a semiconductor substrate 122 , integrated circuit devices 124 , interconnect structures 126 , bonding pads 130 , and bonding layers 132 .

[0060] Next, the reconstructed wafer 50 is separated from the carrier 20, for example, by projecting a laser beam onto the LTHC coating material 22, thereby decomposing the LTHC coating material 22. The corresponding process is shown as follows: Fig.25 The process 242 in the process flow 200 is shown. The resulting structure is as Fig.13 In a subsequent process, electrical connections 134 (which may be, for example, solder regions) are formed to connect to the front side redistribution structures 24, thereby forming a reconstructed wafer 136. The corresponding process is shown as follows Fig.25 Process 244 in the process flow 200 shown. Figure 1 In an alternative embodiment in which the redistribution structure 24 has not yet been formed in the illustrated process, the redistribution structure 24 may be formed after the carrier 20 is separated.

[0061] In a subsequent process, the reconstructed wafer 136 is singulated in a sawing process to form discrete packages 136'. The discrete packages 136' include the device dies 120' sawn from the device wafer 120, and also include the device dies 36 and the device dies 76. The corresponding process is shown as follows Fig.25 Process 246 in process flow 200 is shown.

[0062] The process discussed above shows a facing-back bonding process, where the front side (front side) of device die 120 ′ faces the back side of device die 76 . The front side of device die 76 also faces the back side of device die 36 . Figures 14 to 19 The formation of a package according to an optional embodiment is shown, wherein face-to-face bonding is performed. Unless otherwise specified, the materials, structures, and formation processes of the components in these embodiments are substantially the same as similar components represented by similar reference numerals in the aforementioned embodiments. The details of materials, structures, and formation processes provided in each embodiment of the entire description can be applied to any other embodiment as long as it is applicable.

[0063] refer to Fig.14 , forming a device wafer 120. According to some embodiments, the wafer 120 is a device wafer including a semiconductor substrate 122, an integrated circuit device 124, and an interconnect structure 126. The interconnect structure 126 further includes a bonding pad 130 and a bonding layer 132. The device wafer 120 further includes a device die 120' therein.

[0064] refer to Fig.15 , device die 36 is bonded to device wafer 120 by a die-on-wafer bonding process. Next, according to some embodiments, implantation process 48 may or may not be performed. Thus, implanted regions 132-I and unimplanted regions 132-UI are generated.

[0065] according to Figures 16 to 18 The details of the implantation process can be found in reference Figures 3 to 7 The process is briefly mentioned below, and the details can be found in the previous embodiments.

[0066] Reference Fig.16 , the dielectric liner 54 is deposited as a conformal layer by a conformal deposition process. According to some embodiments, the implantation process 58 may or may not be performed.

[0067] Fig.17 The formation of dielectric layer 56, isolation region 62, and optional through-via 66 is shown in accordance with some embodiments. Implantation process 64 may be performed or may be skipped. When implantation process 64 is performed, implantation process 64 is performed after forming isolation region 62, and implantation process 64 may be performed before or after forming through-via 66.

[0068] Fig.18 The redistribution structure 112 ( Fig.19 ), which includes the dielectric layer 108 and the redistribution lines 110 therein. The implantation process 114 may be performed or may be skipped.

[0069] Fig.19 Further formation of a redistribution structure 112 is shown, which includes more dielectric layers 108 and redistribution lines 110 therein. Electrical connectors 121 are then formed on the redistribution lines 110. According to some embodiments, the electrical connectors 121 may include solder regions. Thus, a reconstructed wafer 136 is formed. In a subsequent process, a singulation process is performed to saw the reconstructed wafer 136 into a plurality of discrete packages 136'.

[0070] exist Fig.13 or Fig.19In the discrete package 136' shown, the region implanted with stress modulation dopants may have a stress modulation dopant concentration DC-I that is higher than the stress modulation dopant concentration DC-UI of the undoped portion of the package. For example, the implanted region may include region 32-I, dielectric liner 54, dielectric region 56, dielectric layer 68-I, dielectric liner 94, and / or dielectric layer 108. Depending on which implant process is performed or skipped, at least one or more or all (in any combination) of these regions / layers may be implanted and have a stress modulation dopant concentration DC-I. The unimplanted region may include bonding layer 46 of device die 36, bonding layer 86 of device die 76, bonding layer 132 of device die 120', unimplanted region 32-UI and / or 68-I (when implant process 74 is skipped), and the like. According to some embodiments, the ratio DC-I / DC-UI may be greater than about 10, greater than about 100, or even greater. The concentration DC-UI may be equal to 0 (no stress modulation dopant) or greater than 0 / cm 3 .

[0071] Figure 20 to Figure 23 The implanted portion of wafer 120 and reconstructed wafer 50 (hereinafter referred to as wafer 120 / 50) according to some embodiments is shown. The corresponding implantation process is discussed with reference to the previous embodiments, and the corresponding implantation process may include any combination of one, more or all of the implantation processes 48, 58, 64, 74, 88, 98, 104 and 114. Fig. 20 As shown, the entire wafer 50 / 120 is implanted, and the implanted portion is indicated as 50-I / 120-I.

[0072] exist Fig.21 In the embodiment, some strip portions 50-I / 120-I of the wafer 50 / 120 are implanted, while the rest of the wafer 50 / 120 is not implanted. The overlapping area of ​​the implanted strips 50-I / 120-I having a length direction in the X direction and the implanted strips having a length direction in the Y direction may overlap with the area of ​​the carrier wafer 50 / 120 having the highest warpage value. Fig. 22 An embodiment is shown in which the implant region 50 -I / 120 -I is a circular region or may include a plurality of circular regions. Fig.23 An embodiment is shown in which selected and isolated regions 50 -I / 120 -I are implanted.

[0073] Furthermore, the implanted portion of one of the implant processes 48 , 58 , 64 , 74 , 88 , 98 , 104 , and 114 may be the same as or different from the implanted regions of the other implant processes to achieve better results.

[0074] Fig.24AA distribution profile of stress modulation dopants in a stress modulation region / layer 140 is shown, which distribution profile represents any of the stress modulation layers / regions 32-I, 56, 68 / 68-I, 96, 108, etc. described above. Fig.24A and Fig. 24B The Y direction in represents the direction perpendicular to the main surface of the implanted region / layer. Accordingly, for all implanted regions / layers except the sidewall portions of the dielectric liners 54 and 94, Fig.24A and Fig. 24B The Y direction in Fig.13 and Fig.19 For the implanted sidewall portions of dielectric liners 54 and 94, Fig.24A and Fig. 24B The Y direction in Fig.13 and Fig.19 Horizontal direction in .

[0075] exist Fig.24A , layers 142 and 144 represent dielectric layers above (if any) and below stress modulation region / layer 140. The concentration of stress modulation dopants is shown on the right side of the figure. According to some embodiments, the peak concentration of the stress modulation dopant is in the stress modulation region / layer 140 (and may be at or near the middle level of the stress modulation region / layer 140). The concentration of the stress modulation dopant may gradually decrease in the direction away from the location where the peak concentration occurs.

[0076] Fig. 24B Distribution profiles of stress modulation dopants in implanted regions 140-I (implanted regions 140-I may be implanted regions 32-I, 68-I, and / or 132-I) and unimplanted regions 140-UI (unimplanted regions 140-UI may be unimplanted regions 32-UI, 68-UI, and / or 132-UI) in dielectric layer 140 are shown. Dielectric layer 140 may represent any of the selectively implanted stress modulation layers / regions described above. According to some embodiments, the peak concentration of stress modulation dopants is in implanted regions 140-I (and may be at or near the middle of implanted regions 140-I). The concentration of stress modulation dopants may gradually decrease as one moves into adjacent unimplanted regions 140-UI. Some portions of unimplanted regions 140-UI may be free of stress modulation dopants.

[0077] In the embodiments shown above, some processes and components are discussed according to some embodiments of the present disclosure. Other components and processes may also be included. For example, a test structure may be included to assist in verification testing of 3D packages or 3DIC devices. For example, the test structure may include a test pad formed in a redistribution layer or on a substrate, the test pad allowing testing of 3D packages or 3DICs, the use of probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that combines intermediate verification of known good dies to increase yield and reduce costs.

[0078] Embodiments of the present disclosure have some advantageous features. By forming stress modulation regions in the die and / or wafer through an ion implantation process, the warpage of the device die and / or wafer can be reduced, and the warpage profile can be modified. This can improve bonding and reduce unbonding issues. For example, when the top wafer and the bottom wafer have reduced warpage and / or their warpage profiles are similar to each other, the wafers are more easily mated to each other and improved bonding.

[0079] According to some embodiments, a method includes bonding a first device die to a packaging assembly, wherein the first device die includes a semiconductor substrate; and a through hole extending into the semiconductor substrate; depositing a dielectric liner to line the sidewalls of the first device die; depositing a dielectric layer on the dielectric liner; planarizing the dielectric layer and the first device die, wherein the dielectric liner and the remaining portion of the dielectric layer form a gap-filling region and expose a top end of the through hole; performing a first implantation process to introduce a stress-modulating dopant into at least one of the dielectric liner and the dielectric layer; and forming a redistribution line above the through hole, and the redistribution line is electrically connected to the through hole.

[0080] In an embodiment, a first implant process is performed on the dielectric liner and the first implant process is performed before depositing the dielectric layer. In an embodiment, the first implant process includes a tilted implant process. In an embodiment, the first implant process includes a vertical implant process. In an embodiment, the first implant process is performed after planarizing the dielectric layer and the first device die. In an embodiment, the method further includes, after bonding the first device die to the package assembly and before depositing the dielectric liner, performing a second implant process to implant the top dielectric layer of the package assembly.

[0081] In an embodiment, the method also includes bonding a second device die over the first device die; depositing an additional dielectric liner to line the sidewalls of the second device die; depositing an additional dielectric layer on the additional dielectric liner; planarizing the additional dielectric layer and the second device die, wherein the additional dielectric liner and a remaining portion of the additional dielectric layer form an additional gap fill region; and performing a second implantation process to introduce additional stress modulation dopants into at least one of the additional dielectric liner and the additional dielectric layer.

[0082] In an embodiment, the stress modulation dopant is the same as the additional stress modulation dopant. In an embodiment, the first implant process comprises implanting an element selected from the group consisting of Ge, B, P, As, Ga, H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb, and combinations thereof. In an embodiment, implanting the stress modulation dopant comprises implanting an element selected from the group consisting of Ge, B, P, As, Ga, and combinations thereof. In an embodiment, the peak concentration of the stress modulation dopant is located in the dielectric liner.

[0083] According to some embodiments, a structure includes a package component, the package component including a top dielectric layer, wherein the top dielectric layer includes a first portion and a second portion; a device die located above and bonded to the second portion of the top dielectric layer; and a gap-fill dielectric region, the gap-fill dielectric region including a dielectric liner, the dielectric liner including a vertical portion lining a sidewall of the device die and a horizontal portion located above and contacting the first portion of the top dielectric layer, wherein the horizontal portion of the dielectric liner includes a stress-modulation dopant having a first concentration, and wherein a second concentration of the stress-modulation dopant in the second portion of the top dielectric layer is lower than the first concentration; and a dielectric region located on the dielectric liner.

[0084] In an embodiment, the device die comprises a bottom dielectric layer bonded to a second portion of the top dielectric layer, wherein the bottom dielectric layer is free of stress-modulating dopants. In an embodiment, the device die comprises a semiconductor substrate; and a through-hole penetrating the semiconductor substrate, wherein a third concentration of the stress-modulating dopant in a top portion of the through-hole is higher than both the first concentration and the second concentration. In an embodiment, the stress-modulating dopant comprises an element selected from the group consisting of Ge, B, P, As, Ga, H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb, and combinations thereof. In an embodiment, the element is selected from the group consisting of Ge, B, P, As, Ga, and combinations thereof.

[0085] According to some embodiments, a structure includes a first device die; a second device die located above and bonded to the first device die, wherein the first device die extends laterally beyond a sidewall of the second device die; and a gap-fill dielectric region, the gap-fill dielectric region including a dielectric liner including a vertical portion located on the sidewall of the second device die, and a horizontal portion located above and contacting the first device die to form a horizontal interface, wherein the horizontal portion includes a stress-modulation dopant and the stress-modulation dopant has a first peak concentration in the horizontal portion.

[0086] In an embodiment, the concentration of the stress modulation dopant gradually decreases in an upward direction and a downward direction from the location of the first peak concentration. In an embodiment, the stress modulation dopant is included in the vertical portion, and the stress modulation dopant has a second peak concentration in the vertical portion. In an embodiment, the concentration of the stress modulation dopant gradually decreases in an opposite horizontal direction from the location of the second peak concentration.

[0087] According to some embodiments, the present disclosure provides a method for forming a package structure, the method comprising: bonding a first device die to a package assembly, wherein the first device die comprises a semiconductor substrate; depositing a dielectric liner to line the sidewalls of the first device die; depositing a dielectric layer on the dielectric liner; planarizing the dielectric layer and the first device die, wherein the dielectric liner and the remaining portion of the dielectric layer form a gap filling region; performing a first implantation process to introduce a stress modulation dopant into at least one of the dielectric liner and the dielectric layer; and forming a redistribution line above the first device die, and the redistribution line is electrically connected to the first device die. In some embodiments, the first implantation process is performed on the dielectric liner, and the first implantation process is performed before the dielectric layer is deposited. In some embodiments, the first implantation process comprises a tilted implantation process. In some embodiments, the first implantation process comprises a vertical implantation process. In some embodiments, the first device die comprises a through hole extending into the semiconductor substrate, and wherein the top of the through hole is exposed after the dielectric layer is planarized. In some embodiments, the method further comprises: performing a second implant process to implant a top dielectric layer of the package assembly after bonding the first device die to the package assembly and before depositing the dielectric liner. In some embodiments, the method further comprises: bonding a second device die over the first device die; depositing an additional dielectric liner to line the sidewalls of the second device die; depositing an additional dielectric layer on the additional dielectric liner; planarizing the additional dielectric layer and the second device die, wherein the additional dielectric liner and the remaining portion of the additional dielectric layer form an additional gap fill region; and performing a second implant process to introduce an additional stress modulation dopant into at least one of the additional dielectric liner and the additional dielectric layer. In some embodiments, the stress modulation dopant is the same as the additional stress modulation dopant. In some embodiments, the first implant process comprises implanting an element selected from the group consisting of Ge, B, P, As, Ga, H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb, and combinations thereof. In some embodiments, implanting the stress-modulation dopant includes implanting an element selected from the group consisting of Ge, B, P, As, Ga, and combinations thereof. In some embodiments, a peak concentration of the stress-modulation dopant is located in the dielectric liner.

[0088] According to some embodiments, the present disclosure provides a package structure, the package structure comprising: a package assembly, the package assembly comprising a top dielectric layer, wherein the top dielectric layer comprises a first portion and a second portion; a device die, located above the second portion of the top dielectric layer and bonded to the second portion of the top dielectric layer; and a gap-fill dielectric region, the gap-fill dielectric region comprising a dielectric liner, the dielectric liner comprising a first portion lining the sidewall of the device die, and a second portion located above the first portion of the top dielectric layer and contacting the first portion of the top dielectric layer, wherein the second portion of the dielectric liner comprises a dopant having a first concentration, and wherein the second concentration of the dopant in the second portion of the top dielectric layer is lower than the first concentration. In some embodiments, the device die comprises: a bottom dielectric layer, the bottom dielectric layer bonded to the second portion of the top dielectric layer, wherein the bottom dielectric layer is free of dopants. In some embodiments, the device die comprises: a semiconductor substrate and a through-hole, the through-hole penetrating the semiconductor substrate, wherein a third concentration of the dopant in the top of the through-hole is higher than both the first concentration and the second concentration. In some embodiments, the dopant comprises an element selected from the group consisting of Ge, B, P, As, Ga, H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb, and combinations thereof. In some embodiments, the element is selected from the group consisting of Ge, B, P, As, Ga, and combinations thereof.

[0089] According to some embodiments, a package structure includes: a first device die; a second device die located above the first device die and bonded to the first device die, wherein the first device die extends laterally beyond the sidewall of the second device die; and a gap-filling dielectric region, the gap-filling dielectric region including a dielectric liner, the dielectric liner including a first portion located on the sidewall of the second device die, and a second portion located above the first device die and contacting the first device die to form a horizontal interface, wherein the second portion includes a dopant, and the dopant has a first peak concentration in the second portion. In some embodiments, the concentration of the dopant gradually decreases in an upward direction and a downward direction from the position of the first peak concentration. In some embodiments, the first portion includes a dopant, and the dopant has a second peak concentration in the first portion. In some embodiments, the concentration of the dopant gradually decreases in an opposite horizontal direction from the position of the second peak concentration.

[0090] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a packaging structure, comprising: bonding a first device die to a package assembly, wherein the first device die comprises a semiconductor substrate; depositing a dielectric liner to line the sidewalls of the first device die; depositing a dielectric layer on the dielectric liner; planarizing the dielectric layer and the first device die, wherein the dielectric liner and a remaining portion of the dielectric layer form a gap-fill region; performing a first implantation process to introduce a stress modulation dopant into at least one of the dielectric liner and the dielectric layer; and Redistribution lines are formed over the first device die and are electrically connected to the first device die.

2. The method for forming a packaging structure according to claim 1, wherein: The first implant process is performed on the dielectric liner and is performed before depositing the dielectric layer.

3. The method for forming a packaging structure according to claim 2, wherein: The first implantation process includes a tilted implantation process.

4. The method for forming a packaging structure according to claim 2, wherein: The first implantation process includes a vertical implantation process.

5. The method for forming a package structure according to claim 1, wherein: The first device die includes a through-via extending into the semiconductor substrate, and wherein a top end of the through-via is exposed after planarizing the dielectric layer.

6. The method for forming a package structure according to claim 1, further comprising: After bonding the first device die to the package assembly and before depositing the dielectric liner, a second implant process is performed to implant a top dielectric layer of the package assembly.

7. The method for forming a package structure according to claim 1, further comprising: bonding a second device die over the first device die; depositing an additional dielectric liner to line the sidewalls of the second device die; depositing an additional dielectric layer on the additional dielectric liner; planarizing the additional dielectric layer and the second device die, wherein the additional dielectric liner and a remaining portion of the additional dielectric layer form an additional gap fill region; as well as A second implantation process is performed to introduce an additional stress-modulating dopant into at least one of the additional dielectric liner and the additional dielectric layer.

8. The method for forming a package structure according to claim 7, wherein: The stress-modulating dopant is the same as the additional stress-modulating dopant.

9. A packaging structure, comprising: A package assembly, the package assembly comprising a top dielectric layer, wherein the top dielectric layer comprises: Part I; and Part II; a device die over and bonded to the second portion of the top dielectric layer; and A gap-fill dielectric region, the gap-fill dielectric region comprising: A dielectric liner, the dielectric liner comprising: A first portion lining a sidewall of the device die; and A second portion is located above and contacts the first portion of the top dielectric layer, wherein the second portion of the dielectric liner includes a dopant having a first concentration, and wherein a second concentration of the dopant in the second portion of the top dielectric layer is lower than the first concentration.

10. A packaging structure, comprising: a first device die; a second device die overlying and bonded to the first device die, wherein the first device die laterally extends beyond a sidewall of the second device die; and A gap-fill dielectric region, the gap-fill dielectric region comprising: A dielectric liner, the dielectric liner comprising: A first portion located on the sidewall of the second device die; and A second portion is located above the first device die and contacts the first device die to form a horizontal interface, wherein the second portion includes a dopant and the dopant has a first peak concentration in the second portion.

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