A BiCMOS integration method based on standard bipolar devices

Abstract

The application discloses a BiCMOS integration method based on standard bipolar devices, which comprises the following steps: 1) forming A buried layer regions and a plurality of isolation regions on a substrate; 2) forming a field region; 3) forming a first base region and a second base region; 4) etching a first gate oxide layer by using a mask pattern, and then growing a second gate oxide layer and a third gate oxide layer by oxidation to form thick and thin gate oxides; 5) forming a gate oxide polycrystal of a MOS tube; 6) forming a first emitter region, a first base heavy contact region, a first CMOS source-drain region and a second DMOS source-drain region; 7) forming a second emitter region, a second base heavy contact region, a second CMOS source-drain region and a third DMOS source-drain region; 8) forming a first dielectric layer; 9) etching a CT hole by using a mask; performing metal deposition, etching a metal end by using a mask pattern, and forming BJT, CMOS and DMOS devices. The application realizes complementary bipolar technology without increasing the number of photolithography layers, and enriches the selectable types of devices to meet more extensive and higher demand application technical fields.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and particularly relates to a BiCMOS integration method based on standard bipolar devices. BACKGROUND

[0002] Bipolar process and CMOS process are mainstream silicon integrated circuit processes today, the Bipolar process has advantages of large driving capability and high cutoff frequency, and the CMOS process has advantages of low power consumption and high integration degree. BiCMOS (Bipolar Junction Transistor and Complementary Metal Oxide Semiconductor) integrates the two processes in a set of processes, so that the device performance and adaptability exceed that of a single process.

[0003] The complementary bipolar process can integrate high-performance vertical NPN tubes and vertical PNP tubes on a chip, and the conventional lateral PNP tube has low characteristic frequency and driving capability, so the use scene is limited. The use of the vertical PNP tube in the complementary bipolar process enables many analog integrated circuits to work normally without sacrificing key parameters, thereby expanding the application range.

[0004] The current BiCMOS process is mainly based on the CMOS process. In order to obtain higher speed of the MOS device, the epitaxial layer and the base width selection of this type of BiCMOS are limited, and the breakdown and gain of the triode produced are mostly not comparable to that of the triode produced by the standard bipolar process.

[0005] The standard bipolar process flow mainly includes the following steps: using a buried layer to reduce the collector area resistance, epitaxial growth, using a deep N+ collector area to improve the speed and reduce the saturation voltage drop, forming a field area through a LOCOS process, and forming two PN junctions of the triode through implantation and annealing of the base area and the emitter area. The main parameters of the triode, such as the cutoff frequency and the breakdown, are determined by the epitaxial thickness, and the gain is mainly determined by the base width and the base doping concentration. The BiCMOS process based on the CMOS cannot freely select the epitaxial thickness and the base width. In the analog system components involving high voltage and large gain, it is difficult to use such a process. Therefore, it is necessary to research a BiCMOS that can reach the standard bipolar process level while maintaining the MOS function. SUMMARY

[0006] The present application aims to provide a BiCMOS integration method based on standard bipolar devices, which comprises the following steps:

[0007] 1) Forming A buried layer areas and a plurality of isolation areas on a substrate. The A buried layer areas include B first buried layer areas, C second buried layer areas, D third buried layer areas and E fourth buried layer areas, and A=B+C+D+E. Each buried layer area includes a left and right arranged N-type heavily doped buried layer and a P-type heavily doped buried layer; and the isolation area is a P-type heavily doped area.

[0008] 2) On a substrate containing buried and isolation regions, epitaxial and oxidative growth of sacrificial oxide layers are performed to form B first deep collector contact regions, C first CMOS substrate well regions, D first DMOS source / drain regions and D first DMOS substrate well regions, E second deep collector contact regions and E P-type WELL well regions, while forming multiple PN junction isolations.

[0009] 3) Perform LOCOS oxidation isolation to form a field area.

[0010] 4) Etch the sacrificial oxide layer, oxidize and grow the first gate oxide layer, and form the first base region and the second base region.

[0011] 5) Adjust the channels in the CMOS and DMOS regions using mask patterns.

[0012] 6) The first gate oxide layer is etched using a mask pattern, and the second and third gate oxide layers are grown by oxidation again to form thick and thin gate oxide layers.

[0013] 7) Perform polysilicon deposition, implant and etch using a mask to form gate polysilicon, and perform SPACER oxidation etching on the polysilicon to form the gate oxide polysilicon of the MOS transistor.

[0014] 8) Ion implantation is performed using mask patterns and polygate self-alignment to simultaneously form the first emitter region, the first base heavy contact region, the first CMOS source / drain region, and the second DMOS source / drain region.

[0015] 9) Ion implantation is performed using mask patterns and polygate self-alignment to simultaneously form a second emitter region, a second base heavy contact, a second CMOS source / drain region, and a third DMOS source / drain region.

[0016] 10) Form the first dielectric layer.

[0017] 11) Use a mask to etch CT holes. Perform metal deposition and use the mask pattern to etch metal ends to form BJT, CMOS, and DMOS devices.

[0018] Furthermore, the method for forming A buried regions and multiple isolation regions includes: using a mask pattern to form them by ion implantation and annealing.

[0019] The method for forming B first deep collector contact regions (20), C first CMOS substrate well regions (22), D first DMOS source / drain regions (23) and D first DMOS substrate well regions (24), E second deep collector contact regions (25) and E P-type WELL well regions (26) includes: forming by ion implantation and annealing using a mask pattern.

[0020] The method for forming the first and second base regions is as follows: using a mask pattern, ion implantation and annealing are employed.

[0021] Furthermore, the first buried layer region is an N-type bipolar buried layer, the second buried layer region is a CMOS buried layer, the third buried layer region is a DMOS buried layer, and the fourth buried layer region is a P-type bipolar buried layer.

[0022] Furthermore, the B first deep collector electrode contact regions are N-type and are connected to the first buried layer region through ion implantation annealing or diffusion via a mask pattern.

[0023] The E second deep collector electrode contact areas 25 are P-type and are connected through the mask pattern via the fourth buried layer area after ion implantation annealing.

[0024] The injection menu conditions for the second deep collector electrode contact region and the isolation region are the same as those for the isolation region.

[0025] The conditions for P-type WELL injection and NMOS region well injection are the same.

[0026] When the MOS types are the same, the injection menu conditions of the source-drain region of the first DMOS and the well region of the first DMOS substrate are the same.

[0027] Furthermore, the C first CMOS substrate well regions, D first DMOS source / drain regions, D first DMOS substrate well regions, and E P-type WELL well regions are formed by mask pattern ion implantation annealing, and the implanted ion type is related to the device type.

[0028] If the BiCMOS device is an N-type CMOS, then the doping type of the first CMOS substrate well region is P-type.

[0029] If the BiCMOS device is a P-type CMOS, then the doping type of the first CMOS substrate well region is N-type.

[0030] The doping energy of the first CMOS substrate well region is determined by the epitaxial thickness, and the doping depth after annealing is 70% of the epitaxial layer thickness.

[0031] Furthermore, the isolation region uses high-concentration BORON doping.

[0032] To prevent parasitic PNP tubes from passing through and to improve breakdown, the minimum distance between the isolation region and the first deep collector contact region is 1.2 times the epitaxial thickness, and the minimum distance between the isolation region and the second deep collector contact region is 1.5 times the epitaxial thickness.

[0033] Furthermore, the thickness of the first gate oxide layer falls between the thicknesses of the second and third gate oxide layers. The second gate oxide layer is a thin gate oxide region, the thickness of which is determined by the CMOS gate breakdown, while the third gate oxide layer is a thick gate oxide region. The second gate oxide layer encompasses the CMOS region and the low-threshold DMOS device region, while the third gate oxide layer encompasses the remaining region excluding that encompassed by the second gate oxide layer.

[0034] Furthermore, the first emitter region is an N-type bipolar emitter region, the first base heavy contact region is a P-type bipolar base heavy contact region, the first CMOS source / drain region is an N-type CMOS source / drain region, and the second DMOS source / drain region is an N-type DMOS source / drain region. The first emitter region, the first base heavy contact region, the first CMOS source / drain region, and the second DMOS source / drain region are formed simultaneously by arsenic ion implantation and annealing.

[0035] Furthermore, the second emitter region is a P-type bipolar emitter region, the second base heavy contact region is an N-type bipolar base heavy contact region, the second CMOS source / drain region is a P-type CMOS source / drain region, and the third DMOS source / drain region is a P-type DMOS source / drain region.

[0036] The second emitter region, the second base heavy contact region, the second CMOS source / drain region, and the third DMOS source / drain region are all formed simultaneously by BF2 injection annealing.

[0037] Furthermore, when the BiCMOS device is a VPNP high-breakdown device, the P-type Well region in the MOS region is formed by doping implantation, and the P-type Well region is connected to the fourth buried layer region.

[0038] When a BiCMOS device is used as a VPNP high-speed device, a P-type Well region of the MOS region is formed by undoped off-fire implantation, and the P-type Well region is not connected to the fourth buried layer region.

[0039] The technical effects of this invention are undeniable, and its beneficial effects are as follows:

[0040] Complementary bipolar technology was achieved without adding a photolithography layer. By utilizing N-type MOS well injection and P-type buried layer flipping, the VPNP device was transformed from N-type epitaxy to P-type epitaxy, thus improving the gain of the VPNP transistor. Optionally, to meet the requirements of high-voltage standard bipolar devices, the PWELL layer can be removed from the layout to widen the VPNP base region. In this way, high-voltage and high-speed VPNP devices can be fabricated simultaneously in the same process without increasing the process budget.

[0041] In this invention, BF2 is used for ion doping during the formation of the P-type bipolar emitter region and N-type bipolar base. The diffusion depth of BF2 is slower compared to Boron implantation. Using BF2 allows for better control of the emitter junction depth of the VPNP and the lateral diffusion of the source and drain regions of the P-type MOS. Furthermore, unlike traditional BiCMOS, where the NPN emitter region and heavily doped base are completed in a single annealing process, this invention first performs N-type annealing to complete the N-type doping diffusion in the bipolar and MOS regions, followed by P-type annealing to complete the N-type doping diffusion in both regions. By using BF2 for ion doping and segmented annealing, the VPNP gain is controlled and short-channel effects are avoided.

[0042] This invention employs a method of first growing a first gate oxide layer as a sacrificial oxide layer for base region implantation, and then selectively etching the first gate oxide layer using a mask pattern, followed by oxidation to generate gate oxide layers of varying thicknesses. The advantage of this method is that the thickness of the first gate oxide layer can be very close to the thickness of the sacrificial oxide layer in a standard bipolar process, thereby improving the electron channel quality during base region implantation in traditional BiCMOS and more closely resembling the base region implantation situation in standard bipolar processes.

[0043] In summary, by using the manufacturing method of this invention, high-performance high-voltage VPNP transistors and high-speed VPNP transistors can be produced without increasing costs on the basis of traditional BICMOS, and a set of Bipolar device integration technology comparable to standard bipolar devices can be manufactured. Attached Figure Description

[0044] Figure 1 This is a schematic diagram illustrating the steps of a BiCMOS integration method based on standard bipolar devices.

[0045] Figures 2-11 This is a process flow diagram of the BiCMOS integration method based on standard bipolar devices.

[0046] Figures 12-13 This is a parameter diagram of the actual device fabricated using the BiCMOS integration method based on standard bipolar devices.

[0047] Explanation of icon numbers:

[0048] 10 – First buried layer region, 11 – Second buried layer region, 12 – Isolation region, 13 – Third isolation region, 14 – Fourth buried layer region, 20 – First deep collector contact region, 21 – Isolation region, 22 – First CMOS substrate well region, 23 – First DMOS source / drain region, 24 – First DMOS substrate well region, 25 – Second deep collector contact region, 26 – P-type Well region, 30 – LOCOS oxide isolation, 40 – First base region, 41 – Second base region, 50 – First gate oxide layer, 51 – MOS tuning trench, 60 – Second gate oxide layer, 61 – Third gate oxide layer, 70 – Gate oxide polysilicon, 80 – First emitter region, 81 – Second base heavy contact region, 82 – CMOS source / drain region, 83 – DMOS source / drain region, 84 – First base heavy contact region, 85 – Second emitter region, 91 – Metal port. Detailed Implementation

[0049] The present invention will be further described below with reference to embodiments, but it should not be construed that the scope of the present invention is limited to the following embodiments. Various substitutions and modifications made based on ordinary technical knowledge and common practices in the art without departing from the above-described technical concept of the present invention should be included within the scope of protection of the present invention.

[0050] Example 1:

[0051] See Figures 1 to 13 A BiCMOS integration method based on standard bipolar devices includes the following steps:

[0052] 1) A buried layer region and multiple isolation regions 12 are formed on the substrate. The A buried layer region includes B first buried layer region 10, C second buried layer region 11, D third buried layer region 13 and E fourth buried layer region 14, where A = B + C + D + E. Each buried layer region includes N-type heavily doped buried layers and P-type heavily doped buried layers arranged on the left and right sides. The isolation regions 12 are P-type heavily doped regions.

[0053] 2) Epitaxial and oxidative growth of sacrificial oxide layers are performed on a substrate containing buried layer and isolation region (12) to form B first deep collector contact regions (20), C first CMOS substrate well regions (22), D first DMOS source and drain regions (23) and D first DMOS substrate well regions (24), E second deep collector contact regions (25) and E P-type WELL well regions (26), while forming multiple PN junction isolations;

[0054] 3) Perform LOCOS oxidation isolation 30 to form the field area.

[0055] 4) Etch the sacrificial oxide layer, oxidize and grow the first gate oxide layer 50, and form the first base region 40 and the second base region 41.

[0056] 5) Adjust the channels of the CMOS region and DMOS region using mask patterns 51.

[0057] 6) The first gate oxide layer 50 is etched using a mask pattern, and the second gate oxide layer 60 and the third gate oxide layer 61 are grown by oxidation again to form a thick and thin gate oxide layer.

[0058] 7) Perform polysilicon deposition, implant and etch using a mask to form gate polysilicon, and perform SPACER oxidation etching on the polysilicon to form the gate oxide polysilicon 70 of the MOS transistor.

[0059] 8) Ion implantation is performed using mask patterning and polygate self-alignment to simultaneously form a first emitter region 80, a first base heavy contact region 84, a first CMOS source / drain region 82, and a second DMOS source / drain region 83.

[0060] 9) Ion implantation is performed using mask patterning and polygate self-alignment to simultaneously form a second emitter region 85, a second base heavy contact 81, a second CMOS source / drain region 82, and a third DMOS source / drain region 83.

[0061] 10) Form the first dielectric layer.

[0062] 11) Use a mask to etch out the CT holes. Perform metal deposition and use the mask pattern to etch out the metal terminals 91 to form BJT, CMOS, and DMOS devices.

[0063] Methods for forming A buried regions and multiple isolation regions include: using mask patterns, forming by ion implantation and annealing.

[0064] The method for forming B first deep collector contact regions (20), C first CMOS substrate well regions (22), D first DMOS source / drain regions (23) and D first DMOS substrate well regions (24), E second deep collector contact regions (25) and E P-type WELL well regions (26) includes: forming by ion implantation and annealing using a mask pattern.

[0065] The method for forming the first base region 40 and the second base region 41 is as follows: using a mask pattern, the base regions are formed by ion implantation and annealing.

[0066] The first buried layer region is an N-type bipolar buried layer, the second buried layer region is a CMOS buried layer, the third buried layer region is a DMOS buried layer, and the fourth buried layer region is a P-type bipolar buried layer.

[0067] The B first deep collector electrode contact areas are N-type and are connected to the first buried layer area through ion implantation annealing or diffusion via a mask pattern.

[0068] The E second deep collector electrode contact areas 25 are P-type and are connected through the mask pattern via the fourth buried layer area after ion implantation annealing.

[0069] The injection menu conditions for the second deep collector electrode contact region and the isolation region are the same as those for the isolation region.

[0070] The conditions for P-type WELL injection and NMOS region well injection are the same.

[0071] When the MOS types are the same, the injection menu conditions of the source-drain region of the first DMOS and the well region of the first DMOS substrate are the same.

[0072] The C first CMOS substrate well regions, D first DMOS source / drain regions, D first DMOS substrate well regions, and E P-type WELL well regions are formed by mask pattern ion implantation annealing, and the implanted ion type is related to the device type.

[0073] If the BiCMOS device is an N-type CMOS, then the doping type of the first CMOS substrate well region is P-type.

[0074] If the BiCMOS device is a P-type CMOS, then the doping type of the first CMOS substrate well region is N-type.

[0075] The doping energy of the first CMOS substrate well region is determined by the epitaxial thickness, and the doping depth after annealing is 70% of the epitaxial layer thickness.

[0076] The isolation region uses high-concentration BORON doping.

[0077] To prevent parasitic PNP tubes from passing through and to improve breakdown, the minimum distance between the isolation region and the first deep collector contact region is 1.2 times the epitaxial thickness, and the minimum distance between the isolation region and the second deep collector contact region is 1.5 times the epitaxial thickness.

[0078] The thickness of the first gate oxide layer falls between the thicknesses of the second and third gate oxide layers. The second gate oxide layer is a thin gate oxide region, the thickness of which is determined by the CMOS gate breakdown. The third gate oxide layer is a thick gate oxide region. The second gate oxide layer includes the CMOS region and the low-threshold DMOS device region, while the third gate oxide layer includes the remaining region excluding the region included by the second gate oxide layer.

[0079] The first emitter region is an N-type bipolar emitter region, the first base heavy contact region is a P-type bipolar base heavy contact region, the first CMOS source / drain region is an N-type CMOS source / drain region, and the second DMOS source / drain region is an N-type DMOS source / drain region. The first emitter region, the first base heavy contact region, the first CMOS source / drain region, and the second DMOS source / drain region are formed simultaneously by arsenic ion implantation and annealing.

[0080] The second emitter region is a P-type bipolar emitter region, the second base heavy contact region is an N-type bipolar base heavy contact region, the second CMOS source / drain region is a P-type CMOS source / drain region, and the third DMOS source / drain region is a P-type DMOS source / drain region.

[0081] The second emitter region, the second base heavy contact region, the second CMOS source / drain region, and the third DMOS source / drain region are all formed simultaneously by BF2 injection annealing.

[0082] When the BiCMOS device is a VPNP high-breakdown device, the P-type Well region 26 in the MOS region is formed by doping implantation, and the P-type Well region 26 is connected to the fourth buried layer region 14.

[0083] When a BiCMOS device is used as a VPNP high-speed device, a P-type Well region 26 of the MOS region is formed by undoped off-fire injection, and the P-type Well region 26 is not connected to the fourth buried layer region 14.

[0084] Example 2:

[0085] A BiCMOS integration method based on standard bipolar devices includes the following steps:

[0086] 1. A buried layer region and multiple isolation regions 12 are formed on the substrate. The A buried layer regions include B first buried layer regions 10, C second buried layer regions 11, D third buried layer regions 13, and E fourth buried layer regions 14, where A = B + C + D + E. Each buried layer region includes an N-type heavily doped buried layer and a P-type heavily doped buried layer. The isolation regions 12 are P-type heavily doped regions.

[0087] 2. On a substrate containing a buried layer region and an isolation region (12), an epitaxial and oxidative growth of a sacrificial oxide layer is performed to form B first deep collector contact regions (20), C first CMOS substrate well regions (22), D first DMOS source / drain regions (23) and D first DMOS substrate well regions (24), E second deep collector contact regions (25) and E P-type WELL well regions (26), while forming multiple PN junction isolations.

[0088] 3. Perform LOCOS oxidation isolation 30 to form a field area.

[0089] 4. Etch the sacrificial oxide layer, oxidize and grow the first gate oxide layer 50, and form the first base region 40 and the second base region 41.

[0090] 5. Trenching of CMOS and DMOS regions using mask patterns 51.

[0091] 6. The first gate oxide layer 50 is etched using a mask pattern, and the second gate oxide layer 60 and the third gate oxide layer 61 are grown by oxidation again to form a thick and thin gate oxide layer.

[0092] 7. Perform polysilicon deposition, implant and etch using a mask to form gate polysilicon, and perform SPACER oxidation etching on the polysilicon to form gate oxide polysilicon 70 of the MOS transistor.

[0093] 8. Ion implantation is performed using mask patterning and polygate self-alignment to simultaneously form a first emitter region 80, a first base heavy contact region 84, a first CMOS source / drain region 82, and a second DMOS source / drain region 83.

[0094] 9. Ion implantation is performed using mask patterning and polygate self-alignment to simultaneously form a second emitter region 85, a second base heavy contact 81, a second CMOS source / drain region 82, and a third DMOS source / drain region 83.

[0095] 10. The first dielectric layer is formed.

[0096] 11) Use a mask to etch out the CT holes. Perform metal deposition and use the mask pattern to etch out the metal terminals 91 to form BJT, CMOS, and DMOS devices.

[0097] Example 3:

[0098] A BiCMOS integration method based on standard bipolar devices, with the same technical content as in Embodiment 2, further comprising the method of forming A buried layer regions and multiple isolation regions by using a mask pattern and forming them by ion implantation and annealing.

[0099] The method for forming B first deep collector contact regions (20), C first CMOS substrate well regions (22), D first DMOS source / drain regions (23) and D first DMOS substrate well regions (24), E second deep collector contact regions (25) and E P-type WELL well regions (26) includes: forming by ion implantation and annealing using a mask pattern.

[0100] The method for forming the first base region 40 and the second base region 41 is as follows: using a mask pattern, the base regions are formed by ion implantation and annealing.

[0101] Example 4:

[0102] A BiCMOS integration method based on standard bipolar devices, with the same technical content as any one of embodiments 2-3, further wherein the first buried layer region is an N-type Bipolar buried layer, the second buried layer region is a CMOS buried layer, the third buried layer region is a DMOS buried layer, and the fourth buried layer region is a P-type Bipolar buried layer.

[0103] Example 5:

[0104] A BiCMOS integration method based on standard bipolar devices, with the same technical content as any one of embodiments 2-4, further wherein the B first deep collector electrode contact regions are N-type and are connected to the first buried layer region through ion implantation annealing or diffusion via a mask pattern.

[0105] The E second deep collector electrode contact areas 25 are P-type and are connected through the mask pattern via the fourth buried layer area after ion implantation annealing.

[0106] The injection menu conditions for the second deep collector electrode contact region and the isolation region are the same as those for the isolation region.

[0107] The conditions for P-type WELL injection and NMOS region well injection are the same.

[0108] When the MOS types are the same, the injection menu conditions of the source-drain region of the first DMOS and the well region of the first DMOS substrate are the same.

[0109] Example 6:

[0110] A BiCMOS integration method based on standard bipolar devices, with the same technical content as any one of embodiments 2-5, further wherein the D first CMOS substrate well regions, E first DMOS source / drain regions, E first DMOS substrate well regions, and P-type WELL well regions are formed by mask pattern ion implantation annealing, and the implanted ion type is related to the device type.

[0111] If the BiCMOS device is an N-type CMOS, then the doping type of the first CMOS substrate well region is P-type.

[0112] If the BiCMOS device is a P-type CMOS, then the doping type of the first CMOS substrate well region is N-type.

[0113] The doping energy of the first CMOS substrate well region is determined by the epitaxial thickness, and the doping depth after annealing is 70% of the epitaxial layer thickness.

[0114] Example 7:

[0115] A BiCMOS integration method based on standard bipolar devices, with the same technical content as any one of Examples 2-6, further wherein the isolation region is doped with a high concentration of BORON.

[0116] To prevent parasitic PNP tubes from passing through and to improve breakdown, the minimum distance between the isolation region and the first deep collector contact region is 1.2 times the epitaxial thickness, and the minimum distance between the isolation region and the second deep collector contact region is 1.5 times the epitaxial thickness.

[0117] Example 8:

[0118] A BiCMOS integration method based on standard bipolar devices, with the same technical content as any one of embodiments 2-7, further wherein the thickness of the first gate oxide layer is between the thickness of the second gate oxide layer and the thickness of the third gate oxide layer. The second gate oxide layer is a thin gate oxide region, the thickness of which is determined according to the CMOS gate breakdown, and the third gate oxide layer is a thick gate oxide region. The second gate oxide layer includes the CMOS region and the low-threshold DMOS device region, and the third gate oxide layer includes the remaining region excluding the region included by the second gate oxide layer.

[0119] Example 9:

[0120] A BiCMOS integration method based on standard bipolar devices, with the same technical content as any one of embodiments 2-8, further wherein the first emitter region is an N-type bipolar emitter region, the first base heavy contact region is a P-type bipolar base heavy contact region, the first CMOS source / drain region is an N-type CMOS source / drain region, and the second DMOS source / drain region is an N-type DMOS source / drain region. The first emitter region, the first base heavy contact region, the first CMOS source / drain region, and the second DMOS source / drain region are formed simultaneously by arsenic ion implantation annealing.

[0121] Example 10:

[0122] A BiCMOS integration method based on standard bipolar devices, with the same technical content as any one of embodiments 2-9, further wherein the second emitter region is a P-type Bipolar emitter region, the second base heavy contact region is an N-type Bipolar base heavy contact region, the second CMOS source / drain region is a P-type CMOS source / drain region, and the third DMOS source / drain region is a P-type DMOS source / drain region.

[0123] The second emitter region, the second base heavy contact region, the second CMOS source / drain region, and the third DMOS source / drain region are all formed simultaneously by BF2 injection annealing.

[0124] Example 11:

[0125] A BiCMOS integration method based on standard bipolar devices, with the same technical content as any one of embodiments 2-10, further wherein when the BiCMOS device is a VPNP high breakdown device, the P-type WELL well region 26 of the MOS region is formed by doping implantation, and the P-type WELL well region 26 is connected to the fourth buried layer region 14.

[0126] When a BiCMOS device is used as a VPNP high-speed device, a P-type Well region 26 of the MOS region is formed by undoped off-fire injection, and the P-type Well region 26 is not connected to the fourth buried layer region 14.

[0127] Example 12:

[0128] A BiCMOS integration method based on standard bipolar devices, comprising the following steps:

[0129] 1) such as Figure 2 As shown, a P-type silicon substrate is provided. Using a mask pattern, ion implantation and annealing are used to form A buried layer regions and multiple isolation regions. The A buried layer regions contain B first buried layer regions 10, C second buried layer regions 11, D third buried layer regions 13 and E fourth buried layer regions 14, where A = B + C + D + E. The buried layer regions contain N-type heavily doped buried layers and P-type heavily doped buried layers. The isolation region 12 is P-type heavily doped.

[0130] 2) such as Figure 3 As shown, epitaxial growth and oxidation of sacrificial oxide layers are performed on a substrate containing buried regions and isolation regions (12) to form B first deep collector contact regions (20), C first CMOS substrate well regions (22), D first DMOS source / drain regions (23) and D first DMOS substrate well regions (24), E second deep collector contact regions (25) and E P-type WELL well regions (26), while forming multiple PN junction isolations. The injection menu conditions for the second deep collector contact regions 2 and the isolation regions 21 are consistent. Optionally, the injection conditions for P-type WELL and NMOS region well regions are the same. Depending on the required P-type bipolar, the VPNP can achieve either high breakdown or high speed by adding or not adding PWELL doping to the MOS region. When using PWELL doping, the PWELL should be connected to the fourth buried region. Figure 3 The image shows a high-speed VPNP pipe;

[0131] 3) such as Figure 4 As shown, LOCOS oxidation isolation 30 is performed to form a field area;

[0132] 4) such as Figure 5 As shown, the sacrificial oxide layer is etched, and the first gate oxide layer 50 is grown by oxidation. Ion implantation and annealing are performed using a mask pattern to form the first base region 40 and the second base region 41.

[0133] 5) such as Figure 6 As shown, the channels in the CMOS region and DMOS region are tuned using a mask pattern 51;

[0134] 6) such as Figure 7 As shown, the first gate oxide layer is etched using a mask pattern, and the second gate oxide layer 60 and the third gate oxide layer 61 are grown by oxidation again to form a thick and thin gate oxide layer.

[0135] 7) such as Figure 8 As shown, polysilicon deposition is performed, and a gate polysilicon is formed by implantation and etching using a mask. The polysilicon is then subjected to SPACER oxidation etching to form the gate oxide polysilicon 70 of the MOS transistor.

[0136] 8) such as Figure 9 As shown, ion implantation is performed using mask patterning and polygate self-alignment to simultaneously form a first emitter region 80, a first base heavy contact region 84, a first CMOS source / drain region 82, and a second DMOS source / drain region 83.

[0137] 9) such as Figure 9 As shown, ion implantation is performed using mask patterning and polygate self-alignment to simultaneously form a second emitter region 85, a second base heavy contact 81, a second CMOS source / drain region 82, and a third DMOS source / drain region 83.

[0138] 10) such as Figure 10 As shown, a first dielectric layer is formed;

[0139] 11) such as Figure 11 CT holes are etched using a mask; metal deposition is performed, and metal tips 91 are etched using the mask pattern to form BJT, CMOS, and DMOS devices.

[0140] Example 13:

[0141] The manufacturing method of BiCMOS based on standard bipolar devices is the same as in Example 12. Further, the first buried layer region is an N-type bipolar buried layer, the second buried layer region is a CMOS buried layer, the third buried layer region is a DMOS buried layer, and the fourth buried layer region is a P-type bipolar buried layer. The type of buried layer in the MOS region is determined according to the type of MOS; if it is PMOS, then the buried layer type is N-type.

[0142] Example 14:

[0143] The manufacturing method of BiCMOS based on standard bipolar devices is the same as any one of Embodiments 12-13. Further, the B first deep collector electrode contact regions are N-type and are connected to the first buried layer region through ion implantation annealing or diffusion via mask pattern. The E second deep collector electrode contact regions 25 are P-type and are connected to the fourth buried layer region through ion implantation annealing via mask pattern. The implantation menu conditions of the second deep collector electrode contact regions and the isolation region are the same as the implantation menu conditions of the isolation region.

[0144] Example 15:

[0145] The manufacturing method of BiCMOS based on standard bipolar devices is the same as any one of embodiments 12-14. Further, the C first CMOS substrate well regions, D first DMOS source / drain regions, D first DMOS substrate well regions, and E P-type Well well regions are formed by mask pattern ion implantation annealing. The implanted ion type is related to the device type itself. If it is an N-type CMOS, the doping type of the first CMOS substrate well region is P-type. The doping energy of the above well regions is determined according to the epitaxial thickness. After annealing, the doping depth is 70% of the epitaxial layer thickness. The well region implantation menu for P-type Well implantation is the same as that for the NMOS region. The implantation menus for the first CMOS substrate well regions, first DMOS source / drain regions, and first DMOS substrate well regions are all divided into N-type implantation and P-type implantation. When the MOS types of the above three well regions are the same (such as N-type CMOS and N-type DMOS), their implantation menu conditions are consistent.

[0146] Example 16:

[0147] The manufacturing method of BiCMOS based on standard bipolar devices is the same as any one of Examples 12-15. Furthermore, the present invention uses PN junction isolation, and its isolation region is doped with a high concentration of BORON. In order to prevent parasitic PNP tubes from passing through and to improve breakdown, the minimum distance between its isolation region and the first deep collector contact region should be 1.2 times the epitaxial thickness, and the minimum distance between its isolation region and the second deep collector contact region should be 1.5 times the epitaxial thickness.

[0148] Example 17:

[0149] The manufacturing method of BiCMOS based on standard bipolar devices is the same as any one of embodiments 12-16. Further, by selectively etching the grown gate oxide through a mask pattern, DMOS devices can be fabricated with varying gate oxide thicknesses to produce high and low threshold DMOS devices. The thickness of the first gate oxide layer is between the thickness of the second and third gate oxide layers, with the specific thickness determined by the thickness of the second gate oxide layer. The second gate oxide layer is a thin gate oxide region, with its specific thickness determined by the CMOS gate breakdown. The third gate oxide layer is a thick gate oxide region. The second gate oxide layer includes the CMOS region and the low threshold DMOS device region, while the third gate oxide layer includes the remaining region excluding the region included by the second gate oxide layer.

[0150] Example 18:

[0151] The manufacturing method of BiCMOS based on standard bipolar devices is the same as any one of Examples 12-17. Further, the first emitter region is an N-type Bipolar emitter region, the first base heavy contact region is a P-type Bipolar base heavy contact region, the first CMOS source / drain region is an N-type CMOS source / drain region, and the second DMOS source / drain region is an N-type DMOS source / drain region. All four regions are formed simultaneously by arsenic ion implantation and annealing.

[0152] Example 19:

[0153] The fabrication method of BiCMOS based on standard bipolar devices is the same as any one of Examples 12-18, and further...

[0154] The second emitter region is a P-type bipolar emitter region, the second base heavy contact region is an N-type bipolar base heavy contact region, the second CMOS source / drain region is a P-type CMOS source / drain region, and the third DMOS source / drain region is a P-type DMOS source / drain region. All four regions are formed simultaneously by BF2 injection and annealing.

[0155] Example 20:

[0156] The manufacturing method of BiCMOS based on standard bipolar devices is the same as any one of Examples 12-19. Furthermore, when using a high-speed VPNP device, theoretically, except for cases where excessive epitaxial thickness prevents the PWELL from connecting to the fourth buried layer region, PWELL injection can be achieved through normal injection or high-energy injection to connect to the fourth buried layer region. The conditions for P-type WELL injection and well injection in the NMOS region are the same. Depending on the required P-type Bipolar, the choice between high-breakdown or high-speed VPNP can be achieved by whether or not PWELL doping is used. When using a high-speed VPNP, its PWELL should be connected to the upturned fourth buried layer region.

[0157] Example 21:

[0158] The manufacturing method of BiCMOS based on standard bipolar devices can theoretically meet the requirements of most standard bipolar devices. Taking the standard bipolar 40V process as an example, this standard 40V process includes: 10 – first buried layer region, 11 – second buried layer region, 12 – isolation region, 13 – third buried layer region, 14 – fourth buried layer region, 20 – first deep collector contact region, 21 – first deep collector contact region, 22 – first CMOS substrate well region, 23 – first DMOS source / drain region, 24 – first DMOS substrate well region. 25 – Second deep collector contact region, 26 – P-type Well region, 30 – LOCOS oxide isolation, 40 – First base region, 41 – Second base region, 50 – First gate oxide layer, 51 – MOS tuning trench, 60 – Second gate oxide layer, 61 – Third gate oxide layer, 70 – Gate oxide polysilicon, 80 – First emitter region, 81 – Second deep base contact region, 82 – CMOS source / drain region, 83 – DMOS source / drain region, 84 – First deep base contact region, 85 – Second emitter region, 91 – Metal port. The steps are as follows:

[0159] Step 1: Provide a P-type silicon substrate. Using a mask pattern, ion implantation and annealing are performed to form A buried layer regions and multiple isolation regions. The A buried layer regions contain B (first buried layer region 10), C (second buried layer region 11), D (third buried layer region 13), and E (fourth buried layer region 14), where A = B + C + D + E. The buried layer regions contain both heavily N-type and heavily P-type doped buried layers. Isolation region 12 is heavily P-type doped. The silicon substrate crystal orientation mentioned earlier should be 100°. Isolation region 12 is formed by homo-implantation, specifically boron (B) impurity doping, with a peak concentration typically around 10%. 18 cm-3~10 19 In the cm⁻³ range, its N-type heavily doped buried layer is formed by AS (arsenic) impurity doping, with a peak concentration typically around 10. 19 cm-3~10 20 The range is cm-3;

[0160] 2) such as Figure 3 As shown, epitaxial growth and oxidation of a sacrificial oxide layer are performed on a substrate containing a buried region and an isolation region (12) to form B first deep collector contact regions (20), C first CMOS substrate well regions (22), D first DMOS source / drain regions (23) and D first DMOS substrate well regions (24), E second deep collector contact regions (25) and E P-type WELL well regions (26), while simultaneously forming multiple PN junction isolations. The epitaxial conditions described above match the epitaxial conditions of a 40V standard bipolar process, and the concentration peaks of the N-type and P-type substrate well regions in the MOS region are generally around 10. 16 cm-3~10 17Between cm-3, a well region is formed through high-energy implantation. In this process, the VPNP region uses a high-speed type VPVP, and PWELL25 is implanted through a mask pattern to connect with the flipped-up fourth buried layer. Its PWELL25 is consistent with the well region implantation menu of the P-type MOS region substrate.

[0161] 3) such as Figure 4 As shown, LOCOS oxidation isolation 30 is performed to form a field area;

[0162] 4) such as Figure 5 As shown, the sacrificial oxide layer is etched, and the first gate oxide layer 50 is grown by oxidation. Ion implantation and annealing are performed using the mask pattern to form the first base region 40 and the second base region 41. The first base region 40 is achieved by Boron implantation, and the second base region 41 is achieved by PHOS implantation. The second base region 41 should be annealed first, followed by the first base region 40.

[0163] 5) such as Figure 6 As shown, the channels in the CMOS and DMOS regions are tuned using a mask pattern 51, and the tuning concentration is determined according to the actual threshold requirements.

[0164] 6) such as Figure 7 As shown, the first gate oxide layer is etched using a mask pattern, and the second gate oxide layer 60 and the third gate oxide layer 61 are grown by oxidation again to form a thick and thin gate oxide layer.

[0165] 7) such as Figure 8 As shown, polysilicon deposition is performed, and the gate polysilicon is fully implanted and etched using a mask to form the gate polysilicon. SPACER oxidation etching is then performed on the polysilicon to form the gate oxide polysilicon 70 of the MOS transistor.

[0166] 8) such as Figure 9 As shown, ion implantation is performed using a mask pattern and polygate self-alignment to simultaneously form a first emitter region 80, a first base heavy contact region 84, a first CMOS source / drain region, and a second DMOS source / drain region. All ion implantations use arsenic (AS) ions with a peak concentration of 10. 20 cm-3~10 21 Between cm-3;

[0167] 9) such as Figure 9 As shown, ion implantation is performed using a mask pattern and polygate self-alignment to simultaneously form a second emitter region, a second base heavy contact region, a second CMOS source / drain region, and a third DMOS source / drain region. All ion implantations are performed using BF2 (boron difluoride), with a peak concentration of 10. 20 cm-3~10 21 Between cm-3;

[0168] 10) such as Figure 10As shown, the first dielectric layer is formed. Taking the standard bipolar 40V process as an example, the first dielectric layer formed is an ILD TEOS oxide layer.

[0169] 11) such as Figure 11 CT holes are etched using a mask; metal deposition is performed, and metal ends are etched using the mask pattern to form BJT, CMOS, and DMOS devices.

[0170] 12) such as Figure 12 and Figure 13 As shown, the final NPN output curve and NMOS threshold voltage curve obtained by this manufacturing process are normal and meet the requirements of the standard 40V bipolar process.

Claims

1. A BiCMOS integration method based on standard bipolar devices, characterized in that, Includes the following steps: 1) A buried layer regions and multiple isolation regions (12) are formed on the substrate; A buried layer regions include B first buried layer regions (10), C second buried layer regions (11), D third buried layer regions (13) and E fourth buried layer regions (14), A = B + C + D + E; each buried layer region includes N-type heavily doped buried layers and P-type heavily doped buried layers arranged on the left and right; the isolation region (12) is a P-type heavily doped region; 2) Epitaxial and oxidative growth of sacrificial oxide layers are performed on a substrate containing buried layer and isolation region (12) to form B first deep collector contact regions (20), C first CMOS substrate well regions (22), D first DMOS source and drain regions (23) and D first DMOS substrate well regions (24), E second deep collector contact regions (25) and E P-type WELL well regions (26), while forming multiple PN junction isolations; 3) Perform LOCOS oxidation isolation (30) to form a field area; 4) Etch the sacrificial oxide layer, oxidize and grow the first gate oxide layer (50), and form the first base region (40) and the second base region (41); 5) Adjust the channels in the CMOS and DMOS regions using mask patterns (51); 6) The first gate oxide layer (50) is etched using a mask pattern, and the second gate oxide layer (60) and the third gate oxide layer (61) are grown by oxidation again to form a thick and thin gate oxide layer; 7) Perform polysilicon deposition, implant and etch using a mask to form gate polysilicon, and perform SPACER oxidation etching on the polysilicon to form the gate oxide polysilicon of the MOS transistor (70); 8) Ion implantation is performed using mask pattern and polygate self-alignment to simultaneously form a first emitter region (80), a first base heavy contact region (84), a first CMOS source / drain region (82), and a second DMOS source / drain region (83); 9) Ion implantation is performed using mask pattern and polygate self-alignment to simultaneously form a second emitter region (85), a second base heavy contact region (81), a second CMOS source / drain region (82), and a third DMOS source / drain region (83); 10) Formation of the first dielectric layer; 11) Use a mask to etch out CT holes; perform metal deposition, use the mask pattern to etch out metal ends (91) to form BJT, CMOS, and DMOS devices; The first emitter region is an N-type bipolar emitter region, the first base heavy contact region is a P-type bipolar base heavy contact region, the first CMOS source / drain region is an N-type CMOS source / drain region, and the second DMOS source / drain region is an N-type DMOS source / drain region; the first emitter region, the first base heavy contact region, the first CMOS source / drain region, and the second DMOS source / drain region are formed simultaneously by arsenic ion implantation annealing; The second emitter region is a P-type bipolar emitter region, the second base heavy contact region is an N-type bipolar base heavy contact region, the second CMOS source / drain region is a P-type CMOS source / drain region, and the third DMOS source / drain region is a P-type DMOS source / drain region. The second emitter region, the second base heavy contact region, the second CMOS source / drain region, and the third DMOS source / drain region are all formed simultaneously by BF2 injection annealing. During BiCMOS integration, N-type annealing is performed first to complete the N-type doping diffusion in the Bipolar and MOS regions, and then P-type annealing is performed to complete the N-type doping diffusion in the Bipolar and MOS regions. The first buried layer region is an N-type bipolar buried layer, the second buried layer region is a CMOS buried layer, the third buried layer region is a DMOS buried layer, and the fourth buried layer region is a P-type bipolar buried layer.

2. The BiCMOS integration method based on standard bipolar devices according to claim 1, characterized in that, The method for forming A buried layer regions and multiple isolation regions includes: using a mask pattern, forming them by ion implantation and annealing; The method for forming B first deep collector contact regions (20), C first CMOS substrate well regions (22), D first DMOS source / drain regions (23) and D first DMOS substrate well regions (24), E second deep collector contact regions (25) and E P-type WELL well regions (26) includes: forming by ion implantation and annealing using a mask pattern; The method for forming the first base region (40) and the second base region (41) is as follows: using a mask pattern, the base regions are formed by ion implantation and annealing.

3. The BiCMOS integration method based on standard bipolar devices according to claim 1, characterized in that, The B first deep collector electrode contact areas are N-type and are connected to the first buried layer area through mask patterning, ion implantation annealing or diffusion. The E second deep collector electrode contact areas (25) are P-type and are connected through the mask pattern via the fourth buried layer area after ion implantation annealing; The injection menu conditions for the second deep collector electrode contact region and the isolation region are the same as those for the isolation region. The conditions for P-type WELL injection and NMOS region well injection are the same; When the MOS types are the same, the injection menu conditions of the source-drain region of the first DMOS and the well region of the first DMOS substrate are the same.

4. The BiCMOS integration method based on standard bipolar devices according to claim 1, characterized in that, The C first CMOS substrate well regions, D first DMOS source and drain regions, D first DMOS substrate well regions and E P-type WELL well regions are formed by mask pattern ion implantation annealing, and the implanted ion type is related to the device type. If the BiCMOS device is an N-type CMOS, then the doping type of the well region of the first CMOS substrate is P-type; If the BiCMOS device is a P-type CMOS, then the doping type of the well region of the first CMOS substrate is N-type; The doping energy of the first CMOS substrate well region is determined by the epitaxial thickness, and the doping depth after annealing is 70% of the epitaxial layer thickness.

5. The BiCMOS integration method based on standard bipolar devices according to claim 1, characterized in that, The isolation region uses high-concentration BORON doping; To prevent parasitic PNP tubes from passing through and to improve breakdown, the minimum distance between the isolation region and the first deep collector contact region is 1.2 times the epitaxial thickness, and the minimum distance between the isolation region and the second deep collector contact region is 1.5 times the epitaxial thickness.

6. The BiCMOS integration method based on standard bipolar devices according to claim 1, characterized in that, The thickness of the first gate oxide layer is between the thickness of the second gate oxide layer and the thickness of the third gate oxide layer; the second gate oxide layer is a thin gate oxide region, the thickness of which is determined by the CMOS gate breakdown, and the third gate oxide layer is a thick gate oxide region; the area included by the second gate oxide layer is the CMOS region and the low threshold DMOS device region, and the area included by the third gate oxide layer is the remaining area excluding the area included by the second gate oxide layer.

7. The BiCMOS integration method based on standard bipolar devices according to claim 1, characterized in that, When the BiCMOS device is a VPNP high breakdown device, the P-type WELL well region (26) in the MOS region is formed by doping implantation, and the P-type WELL well region (26) is connected to the fourth buried layer region (14). When a BiCMOS device is used as a VPNP high-speed device, a P-type Well region (26) of the MOS region is formed by undoped off-fire injection, and the P-type Well region (26) is not connected to the fourth buried layer region (14).

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