Display panel preparation method and display panel

Abstract

The invention relates to a display panel preparation method and a display panel, and the display panel preparation method comprises the steps: firstly arranging a patterned sacrificial layer on a growth substrate, and then carrying out the epitaxial growth through the patterned sacrificial layer, so that after the patterned sacrificial layer is removed subsequently, the epitaxial growth of the patterned sacrificial layer is carried out; according to the invention, a plurality of independent epitaxial layers can be obtained without etching the epitaxial layers, so that the influence of etching damage on radiation recombination efficiency in the epitaxial layers is avoided, the brightness of a light-emitting chip and a display panel prepared based on the epitaxial layers is improved, and the display performance of the display panel is enhanced; and after the epitaxial layer is grown and before the chip electrode is arranged on the epitaxial layer, the whole surface of the epitaxial layer on the growth substrate is bound to the driving backboard, and then the preparation of the light-emitting chip is completed, so that the process of the chip electrode of the light-emitting chip and the backboard electrode on the driving backboard is avoided, the alignment difficulty is reduced, and the production efficiency is improved. The preparation yield of the display panel is improved, and the production cost of the display panel is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a method for preparing a display panel and a display panel. Background Art

[0002] Due to the outstanding advantages of Micro-LED (micrometer-level light-emitting diode) in high brightness, high resolution and high contrast, it has great market potential in the fields of VR (Virtual Reality) and AR (Augmented Reality). At present, the use of Micro-LED to prepare high-resolution display devices is mainly based on the technical route of chip bonding. This technology first obtains the Mesa table by dry etching the epitaxial layer, and then makes separate Micro-LED arrays, and makes welding bumps on the driving backplane. Finally, through precise alignment, the integration of Micro-LED and the driving backplane is realized, and then a high-resolution Micro-LED display panel is produced. However, on the one hand, the dry etching used in chip bonding technology will cause etching damage to the side walls of the Mesa, which will lead to a decrease in the radiation recombination ratio, affecting the display brightness of the Micro-LED display panel. On the other hand, the pixel size of Micro-LED display panels prepared using the chip bonding technology route is 5 microns and above. As the chip size is further reduced to below 5 microns, the chip bonding technology route has problems such as high cost and low yield due to the influence of alignment accuracy and bump electrical characteristics, which limits the application of Micro-LED in higher resolution display panels.

[0003] Therefore, how to improve the display brightness and manufacturing yield of display panels is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of the deficiencies of the above-mentioned related technologies, the purpose of the present application is to provide a display panel manufacturing method and a display panel, aiming to solve the problems of insufficient brightness of existing display panels and high manufacturing yield and low cost.

[0005] The present application first provides a method for preparing a display panel, which is characterized by comprising:

[0006] A patterned sacrificial layer is provided on the growth substrate, wherein the patterned sacrificial layer includes a plurality of through holes;

[0007] Growing an epitaxial layer of the light-emitting chip in the plurality of through holes, wherein the thickness of the epitaxial layer is less than or equal to the depth of the through holes, and the epitaxial layer comprises a first semiconductor layer, an active layer, and a second semiconductor layer, the distances between which and the growth substrate increase in sequence;

[0008] Providing a driving backplane provided with a first backplane electrode and a second backplane electrode, and bonding the epitaxial layer on the growth substrate to the driving backplane so that the second semiconductor layer is electrically connected to the second backplane electrode;

[0009] removing the growth substrate and the patterned sacrificial layer;

[0010] A first chip electrode electrically connecting the first semiconductor layer and the first backplane electrode is prepared.

[0011] The above-mentioned display panel preparation method first sets a patterned sacrificial layer on the growth substrate, and then performs epitaxial growth through the patterned sacrificial layer. In this way, after the patterned sacrificial layer is subsequently removed, multiple independent epitaxial layers can be obtained without etching the epitaxial layer, thereby avoiding the influence of etching damage on the radiation recombination efficiency in the epitaxial layer, improving the brightness of the light-emitting chip and display panel made based on the epitaxial layer, and enhancing the display performance of the display panel; and after the epitaxial layer growth is completed, before the chip electrode is set on the epitaxial layer, the entire surface of the epitaxial layer on the growth substrate is first bound to the driving backplane, and then the preparation of the light-emitting chip is completed, thereby avoiding the process of the chip electrode of the light-emitting chip and the backplane electrode on the driving backplane, reducing the difficulty of alignment, improving the preparation yield of the display panel, and reducing the production cost of the display panel.

[0012] Optionally, providing a patterned sacrificial layer on the growth substrate includes:

[0013] providing a growth substrate;

[0014] Disposing a sacrificial material on the surface of the growth substrate to form a sacrificial layer;

[0015] The sacrificial layer is patterned to form a plurality of through holes, wherein radial dimensions of the through holes gradually increase from a side close to the growth substrate to a side far from the growth substrate.

[0016] In the above-mentioned display panel preparation method, the radial size of the through hole in the patterned sacrificial layer gradually increases from the side close to the growth substrate to the side far from the growth substrate. Therefore, after the epitaxial layer formed in the through hole is bound to the driving backplane, the closer to the driving backplane, the larger the cross-sectional area. This facilitates the attachment of other materials to the side of the epitaxial layer and facilitates the setting of other layer structures and the first chip electrode.

[0017] Optionally, bonding the epitaxial layer on the growth substrate to the driving backplane includes:

[0018] A first bonding metal layer is arranged on a side of the epitaxial layer away from the growth substrate, and a second bonding metal layer is arranged on a bonding surface of the driving backplane, wherein the first bonding metal layer and the second bonding metal layer are electrically connected to the second semiconductor layer and the second backplane electrode respectively, and the second bonding metal layer is electrically isolated from the first backplane electrode;

[0019] The side of the first bonding metal layer away from the epitaxial layer is bonded to the side of the second bonding metal layer away from the driving back plate to form a conductive layer including the first bonding metal layer and the second bonding metal layer.

[0020] In the above-mentioned display panel preparation method, when the epitaxial layer is bonded to the driving backplane, a first bonding metal layer is set on the side of the epitaxial layer away from the growth substrate, and a second bonding metal layer is set on the bonding surface of the driving backplane. The first bonding metal layer and the second bonding metal layer are bonded together to form a conductive layer, thereby achieving fixation of the epitaxial layer on the driving backplane, and achieving electrical connection between the second semiconductor layer and the second backplane electrode on the driving backplane. The bonding method is simple and easy, thereby reducing the preparation cost of the display panel.

[0021] Optionally, the conductive layer further includes a current spreading layer, and a first bonding metal layer is arranged on a side of the epitaxial layer away from the growth substrate, including:

[0022] A current spreading layer is provided on a side of the epitaxial layer away from the growth substrate;

[0023] A first bonding metal layer is disposed on a surface of the current spreading layer away from the growth substrate.

[0024] In the above display panel manufacturing method, a current spreading layer is further provided between the epitaxial layer and the first bonding metal layer. After the first bonding metal layer and the second bonding metal layer are bonded, the current spreading layer, the first bonding metal layer and the second bonding metal layer together form a conductive layer. The current spreading layer can achieve uniform diffusion of current and improve the light extraction efficiency of the epitaxial layer.

[0025] Optionally, after the plurality of second backplane electrodes on the driving backplane are arranged in an array, after the growth substrate and the patterned sacrificial layer are removed, and before the first chip electrode electrically connected to the first semiconductor layer and the first backplane electrode is prepared, the method further includes:

[0026] The conductive layer is patterned to form a plurality of independent conductive blocks, and the conductive blocks correspond to the second back plate electrodes one by one.

[0027] After removing the growth substrate and the patterned sacrificial layer in the above-mentioned display panel preparation method, the conductive layer will be patterned to form a plurality of independent conductive blocks, and the conductive blocks correspond to the epitaxial layers one by one. The epitaxial layer realizes the electrical connection between the second semiconductor layer and the corresponding second backplane electrode on the driving backplane through the corresponding conductive blocks. The first bonding metal layer and the second bonding metal layer in the conductive blocks jointly form the second chip electrode of the light-emitting chip.

[0028] Optionally, after removing the growth substrate and the patterned sacrificial layer and before preparing the first chip electrode electrically connecting the first semiconductor layer and the first backplane electrode, the method further includes:

[0029] Disposing a passivation layer at least covering the epitaxial layer;

[0030] An insulating first reflective layer is arranged on a side of the passivation layer away from the epitaxial layer, and an insulating light absorbing layer is arranged in the gap between adjacent conductive blocks, the first reflective layer at least covers the side of the epitaxial layer, and the distance between the side of the light absorbing layer away from the driving backplane and the driving backplane is less than or equal to the distance between the side of the active layer facing the driving backplane and the driving backplane;

[0031] A first chip electrode is arranged along a surface of the first reflective layer away from the passivation layer and a surface of the light absorbing layer away from the driving backplane, and the first chip electrode is electrically connected to a first backplane electrode on the driving backplane.

[0032] In the above display panel preparation method, the side of the epitaxial layer is covered with a first reflective layer, and a light absorbing layer is arranged in the gap between adjacent conductive blocks. Through the joint action of the first reflective layer and the light absorbing layer, light isolation is achieved, and light crosstalk between adjacent light-emitting chips is reduced. Moreover, the distance between the side of the light absorbing layer away from the driving backplane and the driving backplane is less than or equal to the distance between the side of the active layer facing the driving backplane and the driving backplane. In the orientation where the driving backplane is at the bottom and the epitaxial layer is at the top, the top surface of the light absorbing layer is not higher than the bottom surface of the active layer. In this way, the light isolation effect can be ensured while avoiding the light absorbing layer affecting the light output efficiency of the light-emitting chip. Moreover, the light absorbing layer is filled in the gap between adjacent conductive blocks, and to a certain extent, the role of a "flat layer" is achieved, which can facilitate the setting of the first chip electrode, reduce the probability of the first chip electrode being broken, and improve the quality of the display panel.

[0033] Optionally, the number of the first backplane electrodes on the driving backplane is less than the number of the first backplane electrodes, and at least two epitaxial layers share one first chip electrode.

[0034] In the display panel prepared by the above-mentioned display panel preparation method, each epitaxial layer has an independent second chip electrode, but at least two epitaxial layers share one first chip electrode. This simplifies the setting of the first chip electrode while ensuring that the light-emitting chip corresponding to each epitaxial layer can be lit independently, thereby improving the preparation efficiency of the display panel.

[0035] Optionally, the first chip electrode includes at least one of a nano-metal material and a transparent conductive material.

[0036] Optionally, after preparing the first chip electrode electrically connecting the first semiconductor layer and the first backplane electrode, the method further includes:

[0037] Depositing cavity material on one side of the driving back plate provided with the epitaxial layer to form a cavity material layer;

[0038] Etching the cavity material layer to form a plurality of reflective cavities at positions corresponding to the epitaxial layer, so that the light emitted by the epitaxial layer can be emitted into the reflective cavity from the cavity bottom of the reflective cavity;

[0039] Disposing a reflective material on the side wall of the reflective cavity to form a second reflective layer;

[0040] A light conversion material is arranged in the reflective cavity to form a light conversion layer.

[0041] In the above display panel preparation method, after the first chip electrode is set, a cavity material layer is also set to form a plurality of reflective cavities corresponding to the epitaxial layer in the cavity material, and a second reflective layer is formed by setting a reflective material on the side wall of the reflective cavity. At the same time, a light conversion layer is also set in the reflective cavity, and the light conversion layer can be used to achieve the conversion of light wavelength, thereby achieving full-color display of the display panel. The second reflective layer can prevent light from the side wall of the reflective cavity from emitting to the adjacent reflective cavity, and together with the first reflective layer and the light absorption layer, reduce light crosstalk and improve the display effect of the display panel.

[0042] Optionally, after the light conversion material is arranged in the reflective cavity, at least one of the following processes is further performed:

[0043] A water-oxygen isolation layer covering the light conversion layer is arranged in the reflection cavity;

[0044] A filter film layer is arranged on the light output side of the light conversion layer, wherein the filter film layer includes a plurality of filter units corresponding to the epitaxial layers one by one;

[0045] A lens array layer is arranged on a side of the cavity material layer away from the driving back plate, and the lens array layer includes a plurality of micro lenses corresponding to the epitaxial layers one by one.

[0046] In the above-mentioned display panel preparation method, a water-oxygen isolation layer is set in the reflective cavity, and the water-oxygen isolation layer is used to protect the light conversion layer, thereby avoiding the problem of the reliability of the light conversion material being affected by external water and oxygen erosion, and enhancing the reliability of the light conversion layer; by setting a filter film layer on the light-emitting side of the light conversion layer, the purity of the light emitted by each light-emitting chip in the display panel can be improved, and the display effect can be enhanced; by setting a lens array layer on the side of the cavity material layer away from the driving backplane, the light type of the light-emitting chip can be modified by using a microlens, the light emission angle of each light-emitting chip is unified, and the quality of the display panel is enhanced.

[0047] Based on the same inventive concept, the present application also provides a display panel, which is manufactured by any of the above-mentioned display panel manufacturing methods, and the display panel includes:

[0048] A driving back plate, wherein a first back plate electrode and a plurality of second back plate electrodes are arranged on a bonding surface of the driving back plate;

[0049] A plurality of mutually independent conductive blocks are arranged on the bonding surface, and the conductive blocks correspond to the second back plate electrodes one by one;

[0050] A plurality of epitaxial layers corresponding to the conductive blocks one by one, the epitaxial layers comprising a second semiconductor layer, an active layer and a first semiconductor layer, the distances between the epitaxial layers and the driving back plate increasing in sequence, the second semiconductor layer being electrically connected to the second back plate electrode through the conductive blocks corresponding thereto;

[0051] A light absorbing layer filled between adjacent conductive blocks, wherein the distance between the side of the light absorbing layer away from the driving backplane and the driving backplane is less than or equal to the distance between the side of the active layer facing the driving backplane and the driving backplane;

[0052] A first reflective layer covering the side surfaces of the epitaxial layer; and

[0053] The first chip electrode is arranged along the surface of the first reflective layer away from the epitaxial layer and the surface of the light absorbing layer away from the driving backplane, and is configured to electrically connect the first backplane electrode and the first semiconductor layer.

[0054] The above display panel can obtain multiple independent epitaxial layers without etching the epitaxial layer during preparation, thus avoiding the influence of etching damage on the radiation recombination efficiency in the epitaxial layer, improving the brightness of the light-emitting chip and the display panel made based on the epitaxial layer, and enhancing the display performance of the display panel; and after the epitaxial layer is grown, before the chip electrode is set on the epitaxial layer, the entire surface of the epitaxial layer on the growth substrate is first bound to the driving backplane, and then the preparation of the light-emitting chip is completed, thus avoiding the process of the chip electrode of the light-emitting chip and the backplane electrode on the driving backplane, reducing the difficulty of alignment, improving the preparation yield of the display panel, and reducing the production cost of the display panel. Moreover, the side of the epitaxial layer is covered with a first reflective layer, and a light absorbing layer is set in the gap between adjacent conductive blocks. Through the joint action of the first reflective layer and the light absorbing layer, light isolation is achieved, and light crosstalk between adjacent light-emitting chips is reduced. Moreover, the distance between the side of the light-absorbing layer away from the driving backplane and the driving backplane is less than or equal to the distance between the side of the active layer facing the driving backplane and the driving backplane. In the case where the driving backplane is at the bottom and the epitaxial layer is at the top, the top surface of the light-absorbing layer is not higher than the bottom surface of the active layer, so that the light-absorbing layer can be prevented from affecting the light-emitting efficiency of the light-emitting chip while ensuring the light isolation effect. Moreover, the light-absorbing layer is filled in the gap between adjacent conductive blocks, and to a certain extent, it has achieved the role of a "flat layer", which can facilitate the setting of the first chip electrode, reduce the probability of the first chip electrode being broken, and improve the quality of the display panel.

[0055] Optionally, the conductive block includes a stacked bonding metal layer and a current spreading layer, the current spreading layer is located between the bonding metal layer and the epitaxial layer; the number of first backplane electrodes on the driving backplane is less than the number of second backplane electrodes, and at least two epitaxial layers share one first backplane electrode.

[0056] In the above display panel, each epitaxial layer has an independent second chip electrode, but at least two epitaxial layers share one first chip electrode. This simplifies the setting of the first chip electrode while ensuring that the light-emitting chip corresponding to each epitaxial layer can be lit independently, thereby improving the preparation efficiency of the display panel.

[0057] Optionally, in a direction away from the driving back plate, a cross-sectional area of ​​at least one of the conductive block and the epitaxial layer gradually decreases, and the cross section is parallel to the bonding surface of the driving back plate.

[0058] Optionally, the display panel further includes:

[0059] A cavity material layer, in which a plurality of reflective cavities are arranged at positions corresponding to the epitaxial layer, and light emitted by the epitaxial layer can be emitted into the reflective cavity from the cavity bottom of the reflective cavity;

[0060] A second reflective layer disposed on a side wall of the reflective cavity;

[0061] A light conversion layer disposed in the reflective cavity;

[0062] A water-oxygen isolation layer disposed in the reflection cavity and covering the light conversion layer;

[0063] A filter film layer is arranged on the light output side of the light conversion layer, and the filter film layer includes a plurality of filter units corresponding to the epitaxial layers one by one;

[0064] The lens array layer is arranged on the side of the cavity material layer away from the driving back plate, and the lens array layer includes a plurality of micro lenses corresponding to the epitaxial layers one by one.

[0065] In the above display panel, a plurality of reflective cavities corresponding to the epitaxial layers are provided, and a second reflective layer is formed by providing a reflective material on the side wall of the reflective cavity, and a light conversion layer is also provided in the reflective cavity, and the light wavelength conversion can be realized by using the light conversion layer, so as to realize the full-color display of the display panel. The second reflective layer can prevent the light from the side wall of the reflective cavity from emitting to the adjacent reflective cavity, and together with the first reflective layer and the light absorption layer, reduce the light crosstalk, and improve the display effect of the display panel. Moreover, by providing a water-oxygen isolation layer in the reflective cavity, the water-oxygen isolation layer is used to protect the light conversion layer, and the problem of affecting the reliability of the light conversion material due to external water-oxygen erosion is avoided, and the reliability of the light conversion layer is enhanced; by providing a filter film layer on the light-emitting side of the light conversion layer, the purity of the light emitted by each light-emitting chip in the display panel can be improved, and the display effect can be enhanced; by providing a lens array layer on the side of the cavity material layer away from the driving backplane, the light type of the light-emitting chip can be modified by using a microlens, and the light-emitting angle of each light-emitting chip can be unified, thereby enhancing the quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1A schematic diagram of a process of manufacturing a display panel provided in an optional embodiment of the present application;

[0067] Figure 2 for Figure 1 A schematic diagram of a manufacturing process of a display panel;

[0068] Figure 3 A schematic diagram of a selectively grown epitaxial layer provided in an optional embodiment of the present application;

[0069] Figure 4 A schematic diagram of a backplane electrode on a driving backplane provided in an optional embodiment of the present application;

[0070] Figure 5 A schematic diagram of bonding between an epitaxial layer and a driving backplane provided in an optional embodiment of the present application;

[0071] Figure 6 A schematic diagram of an epitaxial layer and a driving backplane bonded together in an optional embodiment of the present application;

[0072] Figure 7 A schematic diagram of the structure of a display panel shown in an optional embodiment of the present application;

[0073] Figure 8 A schematic diagram of a manufacturing process of a display panel in the first stage provided in another optional embodiment of the present application;

[0074] Fig. 9 A schematic diagram of a second-stage manufacturing process of a display panel provided in another optional embodiment of the present application;

[0075] Fig.10 A schematic diagram of the structure of a display panel provided in another optional embodiment of the present application.

[0076] Description of reference numerals:

[0077] 10-display panel; 21-growth substrate; 22-patterned sacrificial layer; 220-through hole; 31-epitaxial layer; 32-first chip electrode; 33-passivation layer; 34-light absorption layer; 35-first reflective layer; 36-mask layer; 40-driving backplane; 41-first backplane electrode; 42-second backplane electrode; 51-first bonding metal layer; 52-second bonding metal layer; 53-current spreading layer; 54-conductive block; 60-cavity material layer; 600-reflective cavity; 61-second reflective layer; 62-light conversion layer; 63-water-oxygen isolation layer; 64-filter film layer; 65-lens array layer; 650-microlens. DETAILED DESCRIPTION

[0078] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0079] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0080] In the relevant display panel preparation scheme, the preparation of the light-emitting chip inevitably needs to undergo dry etching, and the epitaxial layer will be damaged during the dry etching process, affecting the radiation recombination ratio of electrons and holes, thereby reducing the light-emitting efficiency of the light-emitting chip and affecting the display performance of the display panel. At the same time, it is difficult to align the light-emitting chip with the driving backplane when bonding, especially when the light-emitting chip is a small chip such as Micro-LED, the display panel preparation yield is low, resulting in high display panel preparation costs, which restricts the application and development of Micro-LED.

[0081] Based on this, the present application hopes to provide a solution that can solve the above-mentioned technical problems, the details of which will be described in the subsequent embodiments.

[0082] An optional embodiment of the present application:

[0083] This embodiment provides a method for preparing a display panel. Figure 1 and Figure 2 ,in Figure 1 is a schematic diagram of the process of manufacturing a display panel provided in this embodiment, and Figure 2 1 is a schematic diagram of a manufacturing process of the display panel 10:

[0084] S102: Disposing a patterned sacrificial layer on the growth substrate, wherein the patterned sacrificial layer includes a plurality of through holes.

[0085] First, a growth substrate 21 is provided. Figure 2As shown in (a), in this embodiment, the epitaxial layer 31 to be grown on the growth substrate 21 is GaN (gallium nitride)-based blue-green light epitaxy. In this case, the growth substrate 21 can be a sapphire substrate, or any one of a silicon substrate, a SiC (silicon carbide) substrate, and a GaN substrate. In some other examples of this embodiment, the epitaxial layer 31 to be grown on the growth substrate 21 can also be other types of materials, such as red light epitaxy. In this case, the growth substrate 21 can be a GaAs (gallium arsenide) substrate. In addition to blue light epitaxy and red light epitaxy, in some other examples of this embodiment, the epitaxial layer 31 can also be purple light epitaxy or ultraviolet light epitaxy.

[0086] Then, a patterned sacrificial layer 22 is disposed on the growth substrate 21. The patterned sacrificial layer 22 includes a plurality of through holes 220. Figure 2 As shown in (b), a part of the growth substrate 21 is exposed from the bottom of the through hole 220. In some examples of this embodiment, the patterned sacrificial layer 22 is set according to the following process: first, a sacrificial material is deposited on the growth substrate 21 to form a sacrificial layer, the sacrificial layer is stacked with the growth substrate 21, and then the sacrificial layer is etched to form a plurality of through holes 220, thereby obtaining a patterned sacrificial layer 22. In some examples of this embodiment, the sacrificial material may include at least one of oxide materials such as SiO2 (silicon dioxide) and Si3N4 (silicon nitride), and may also include a high temperature resistant polymer or AlAs (aluminum arsenide) and other compounds. It can be understood that in the above examples, the patterned sacrificial layer 22 is directly formed on the growth substrate 21, and in some other examples of this embodiment, the patterned sacrificial layer 22 may also be prepared on another substrate first and then transferred to the growth substrate 21.

[0087] S104: growing an epitaxial layer of the light-emitting chip in the plurality of through holes, wherein the thickness of the epitaxial layer is less than or equal to the depth of the through holes.

[0088] In this embodiment, after the patterned sacrificial layer 22 is set on the growth substrate 21, an epitaxial layer 31 will be grown on the growth substrate 21. The epitaxial layer 31 grows in the through hole 220, and includes a first semiconductor layer, an active layer and a second semiconductor layer whose distances from the growth substrate 21 increase successively. One of the first semiconductor layer and the second semiconductor layer is an N-type doped semiconductor layer, for example, the doping element is Si (silicon), and the other is a P-type doped semiconductor layer, for example, the doping element is Mg (magnesium).

[0089] In this embodiment, one side of the grown epitaxial layer 31 is attached to the surface of the growth substrate 21, and the other side is not higher than the surface of the patterned sacrificial layer 22 away from the growth substrate 21, that is, the thickness of the epitaxial layer 31 is less than or equal to the depth of the through hole 220. Figure 2(c) in the figure can ensure that the epitaxial layers 31 grown in each through hole 220 are independent of each other and will not be connected into a whole.

[0090] It is undoubted that the spatial shape of the through hole 220 determines the shape of the grown epitaxial layer 31. In some examples of this embodiment, the inner wall of the through hole 220 is perpendicular to the surface of the growth substrate 21, see Figure 3 Schematic diagram of the structure of an epitaxial layer 31 on a growth substrate 21. In some examples of this embodiment, the inner wall of the through hole 220 is inclined. For example, in one example, the radial dimension of the through hole 220 gradually increases from the side close to the growth substrate 21 to the side far from the growth substrate 21. Figure 2 As shown in (c) in FIG. 2 . It should be noted that the “radial dimension” is used here to describe the shape of the through hole 220, but this does not mean that the cross section of the through hole 220 must be circular. In some examples of the present embodiment, the epitaxial layer 31 grown in the through hole 220 is in the shape of an inverted truncated cone, and in other examples, the epitaxial layer 31 is in the shape of an inverted terrace. The cross section of the through hole 220 can be a regular geometric shape such as a circle, an ellipse, a triangle, a rectangle, a pentagon, a hexagon or a trapezoid. In some examples, the cross section of the through hole 220 can also be an irregular geometric shape.

[0091] S106: providing a driving backplane having a first backplane electrode and a second backplane electrode, and bonding the epitaxial layer on the growth substrate to the driving backplane, so that the second semiconductor layer is electrically connected to the second backplane electrode.

[0092] After the epitaxial layer 31 is grown, the source chip with the epitaxial layer 31 can be bonded to the driving backplane 40, such as Figure 2 As shown in (d) in .

[0093] It can be understood that the driving backplane 40 includes a driving circuit, and a plurality of first backplane electrodes 41 and a plurality of second backplane electrodes 42 are also provided on the driving backplane 40. The first backplane electrodes 41 and the second backplane electrodes 42 are electrically connected to the driving circuit on the driving backplane 40, respectively, but the first backplane electrodes 41 and the second backplane electrodes 42 are electrically isolated. The first backplane electrode 41 is configured to be electrically connected to the first semiconductor layer in the epitaxial layer 31, and the second backplane electrode 42 is configured to be electrically connected to the second semiconductor layer in the epitaxial layer 31. In some examples of the present embodiment, the number of the first backplane electrodes 41 and the second backplane electrodes 42 on the driving backplane 40 is the same, and in other examples, the number of the first backplane electrodes 41 is less than the number of the second backplane electrodes 42, for example, see Figure 4A schematic diagram of the distribution of backplane electrodes on a driving backplane 40 is shown: a plurality of second backplane electrodes 42 are arranged in an array on the driving backplane 40, while only one first backplane electrode 41 is provided on the driving backplane 40, and the first backplane electrode 41 is located at the edge region of the driving backplane 40. In some other examples, although the number of the first backplane electrodes 41 is less than the number of the second backplane electrodes 42, the number of the first backplane electrodes 41 is more than one.

[0094] When the aforementioned chip source is bonded to the driving backplane 40, the side of the epitaxial layer 31 away from the growth substrate 21 faces the driving backplane 40. After the bonding is completed, the second semiconductor layer in the epitaxial layer 31 will be electrically connected to the second backplane electrode 42 on the driving backplane 40. In some examples of this embodiment, each epitaxial layer 31 in the chip source uniquely corresponds to one second backplane electrode 42.

[0095] Due to the relationship between the materials of the epitaxial layer 31 and the second back plate electrode 42, the second semiconductor layer cannot usually be directly bonded to the second back plate electrode 42. In some examples of this embodiment, the epitaxial layer 31 can be bonded to the second back plate electrode 42 through a conductive adhesive layer. The conductive adhesive layer can achieve a fixed connection between the epitaxial layer 31 and the second back plate electrode 42 on the one hand, and also achieve an electrical connection between the two on the other hand. In some other examples, it can be Figure 5 The schematic diagram shown is for bonding the chip source to the driving backplane 40:

[0096] First, see Figure 5 In (a) and (b), a first bonding metal layer 51 is provided on one side of the epitaxial layer 31 away from the growth substrate 21, and on the other hand, Figure 5 As shown in (c) and (d) in the figure, a second bonding metal layer 52 is provided on the bonding surface of the driving backplane 40. The bonding surface here refers to the surface of the driving backplane 40 configured to bond with the light-emitting chip, so the bonding surface is the surface where the first backplane electrode 41 and the second backplane electrode 42 are located on the driving backplane 40. The second bonding metal layer 52 is electrically connected to each second backplane electrode 42 on the driving backplane 40, but is electrically isolated from the first backplane electrode 41. It can be understood that although Figure 5 In the figure, the second bonding metal layer 52 is formed later than the first bonding metal layer 51. However, in practical applications, there is no strict timing restriction for setting the first bonding metal layer 51 and the second bonding metal layer 52. The two can be performed simultaneously, or the second bonding metal layer 52 can be set first and then the first bonding metal layer 51.

[0097] Then, the first bonding metal layer 51 is bonded to the second bonding metal layer 52 to form a conductive layer. Figure 5As shown in (e) in the figure. The conductive layer formed includes a first bonding metal layer 51 and a second bonding metal layer 52. In some examples of the present embodiment, in order to facilitate the bonding between the first bonding metal layer 51 and the second bonding metal layer 52, the bonding surface of the first bonding metal layer 51 (i.e., the side facing the second bonding metal layer 52 after the bonding of the first bonding metal layer 51 is completed) and the bonding surface of the second bonding metal layer 52 (i.e., the side facing the first bonding metal layer 51 after the bonding of the second bonding metal layer 52 is completed) can be subjected to surface activation treatment before bonding. When the first bonding metal layer 51 and the second bonding metal layer 52 after the activation treatment are in contact with each other at room temperature, atomic diffusion will occur, and they will adhere to each other to achieve bonding.

[0098] It can be understood that the conductive layer not only realizes the combination of the epitaxial layer 31 and the driving backplane 40, but also completes the electrical connection between the second semiconductor layer and the second backplane electrode 42, so the first bonding metal layer 51 and the second bonding metal layer 52 can be regarded as the second chip electrode arranged on the second semiconductor layer. In some examples of this embodiment, before the first bonding metal layer 51 is arranged on the side of the epitaxial layer 31 away from the growth substrate 21, a current spreading layer 53 is also arranged first, and then the first bonding metal layer 51 is arranged on the side of the current spreading layer 53 away from the growth substrate 21. In these cases, the conductive layer formed by bonding the first bonding metal layer 51 and the second bonding metal layer 52 also includes the current spreading layer 53, such as Figure 6 shown.

[0099] In some examples of this embodiment, at least one of the first bonding metal layer 51 and the second bonding metal layer 52 may include at least one of the following metals: Ti (titanium), Al (aluminum), Au (gold), Cr (chromium), Pt (platinum), In (indium), Sn (tin), Ag (silver). In some examples of this embodiment, the bonding metal layer is a single layer, which is composed of one metal element; in other examples, the bonding metal layer is a composite layer structure, each layer structure includes one or more of the aforementioned metal elements; in some other examples, the bonding metal layer is an alloy layer including at least two metal elements. The current spreading layer 53 is a metal layer, and in other examples, the current spreading layer 53 may be a metal oxide layer, such as ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide).

[0100] S108: removing the growth substrate and the patterned sacrificial layer.

[0101] After the epitaxial layer 31 is bonded to the driving backplane 40, the growth substrate 21 and the patterned sacrificial layer 22 can be removed. The epitaxial layer 31 and the growth substrate 21 can be separated by laser. For example, in some examples of the present embodiment, a solid laser can be used to irradiate the interface between the epitaxial layer 31 and the growth substrate 21, so as to peel off the growth substrate 21. Figure 2 As shown in (e) in .

[0102] exist Figure 2 After the growth substrate 21 is peeled off, the patterned sacrificial layer 22 may be removed by a wet method, such as Figure 2 In some examples of this embodiment, the patterned sacrificial layer 22 is formed of SiO2, and BOE (Buffered Oxide Etch) or hydrofluoric acid can be used for wet removal.

[0103] It is understandable that, in some examples of this embodiment, the patterned sacrificial layer 22 may be removed first, and then the growth substrate 21 may be lifted off by laser.

[0104] S110: preparing a first chip electrode electrically connecting the first semiconductor layer and the first backplane electrode.

[0105] After removing the growth substrate 21 and the patterned sacrificial layer 22, a first chip electrode 32 may be provided, and the first chip electrode 32 is configured to electrically connect the first semiconductor layer in the epitaxial layer 31 and the first backplane electrode 41 on the driving backplane 40. In some examples of the present embodiment, each epitaxial layer 31 has a separate first chip electrode 32, in which case the number of first backplane electrodes 41 on the driving backplane 40 is equal to the number of epitaxial layers 31. In some other examples, multiple epitaxial layers 31 may share a first chip electrode 32, in which case the number of first backplane electrodes 41 on the driving backplane 40 is less than the number of epitaxial layers 31. In some examples of the present embodiment, the lighting of each epitaxial layer 31 on the driving backplane 40 can be independently controlled, so there is no epitaxial layer 31 on the driving backplane 40 that shares both the first backplane electrode 41 and the second backplane electrode 42. For example, in some examples, each epitaxial layer 31 shares the first backplane electrode 41, but the corresponding second backplane electrodes 42 are independent of each other; in other examples, each epitaxial layer 31 shares the second backplane electrode 42, but the first backplane electrodes 41 of these epitaxial layers 31 are independent of each other. In some other examples, the light emission of each epitaxial layer 31 on the driving backplane 40 does not need to be independently controlled, for example, the epitaxial layer 31 on the driving backplane 40 is used as the light source of the backlight module. In this case, the epitaxial layer 31 may share the first backplane electrode 41 and the second backplane electrode 42 at the same time.

[0106] In some examples of this embodiment, the first chip electrode 32 is a bonding wire, such as a bonding gold wire. It is understandable that the bonding wire can be electrically connected to the first semiconductor layer at one end and connected to the first backplane electrode 41 at the other end. At the same time, the bonding wire is suspended in the middle and does not contact the epitaxial layer 31, so as to ensure that the normal electrical performance of the epitaxial layer 31 is not affected. However, in more examples of this embodiment, in order to ensure that the electrical function of the epitaxial layer 31 is not affected by other components, a layer structure with an insulating function is also provided on the epitaxial layer 31. For example, in some examples of this embodiment, before the first chip electrode 32 is provided, a passivation layer 33 covering the epitaxial layer 31 can also be provided. See Figure 2 As shown in (g) in FIG. 3 . The passivation layer 33 may include at least one of SiO2 and Al2O3 (aluminum oxide). After the passivation layer 33 is provided, the passivation layer 33 may be etched so that the first semiconductor layer in the epitaxial layer 31 is at least partially exposed to the passivation layer 33, and then the first chip electrode 32 is provided. When the passivation layer 33 is provided, the first chip electrode 32 may be provided along the surface of the passivation layer 33 in a winding manner.

[0107] In some examples of the present embodiment, each epitaxial layer 31 on the driving backplane 40 has its own independent second chip electrode and shares the first chip electrode 32. Correspondingly, a plurality of second backplane electrodes 42 and a first backplane electrode 41 are provided on the driving backplane 40. The array arrangement of the plurality of second backplane electrodes 42 on the driving backplane 40 is the same as the array arrangement of the plurality of epitaxial layers 31, so that the position of each second backplane electrode 42 corresponds exactly to one epitaxial layer 31; the first backplane electrode 41 is provided at the periphery of the array formed by the second backplane electrodes 42, for example, at the edge area of ​​the driving backplane 40. The epitaxial layer 31 is bonded to the driving backplane 40 through a conductive layer including a first bonding metal layer 51 and a second bonding metal layer 52. In this case, after removing the growth substrate 21 and the patterned sacrificial layer 22, the conductive layer needs to be patterned so that the conductive layer forms a plurality of independent conductive blocks 54. Each conductive block 54 corresponds to the position of each second backplane electrode 42 one by one. The conductive block 54 is located between the corresponding epitaxial layer 31 and the second backplane electrode 42. Figure 7 In this case, when the passivation layer 33 is provided, the passivation layer 33 will not only cover the epitaxial layer 31, but also cover the side of the conductive block 54. The first chip electrode 32 can be provided along the surface of the passivation layer 33 away from the epitaxial layer 31 and the conductive block 54, with one end connected to the first backplane electrode 41 of the driving backplane 40, and the other end connected to the first semiconductor layer of each epitaxial layer 31.

[0108] In some examples of this embodiment, the first chip electrode 32 includes a nano-metal material, such as a nano-silver wire, etc. In some other examples, the first chip electrode 32 includes a transparent conductive material. It is understandable that because the first chip electrode 32 covers a part of the epitaxial layer 31, if the first chip electrode 32 is transparent, the effect of the setting of the first chip electrode 32 on the light emission of the epitaxial layer 31 can be reduced, thereby improving the display performance of the display panel 10.

[0109] In some examples of the present embodiment, the display panel 10 is a grayscale display device, and in some examples, the display panel 10 is a full-color display device: in some examples, when the epitaxial layer 31 is grown on the growth substrate 21, red light epitaxy is grown in some through holes 220, green light epitaxy is grown in some through holes 220, and blue light epitaxy is grown in some through holes 220, so that the display panel 10 can achieve full-color display; in some examples, the wavelengths of light emitted by each epitaxial layer 31 grown on the growth substrate 21 are the same, for example, all are blue light, or all are purple light, and in some examples, each epitaxial layer 31 on the growth substrate 21 emits ultraviolet light. In these examples, in order to enable the display panel 10 to achieve full-color display, it is also necessary to perform color conversion on the light emitted by at least part of the epitaxial layer 31. Based on this, in some display panels 10 provided in the present embodiment, a light conversion material is also provided on the light-emitting surface of the epitaxial layer 31 away from the driving backplane 40, such as at least one of a quantum dot material and a phosphor material.

[0110] The display panel preparation method provided in the present embodiment is to set a patterned sacrificial layer 22 on the growth substrate 21, and then perform epitaxial growth through the patterned sacrificial layer 22. In this way, after the patterned sacrificial layer 22 is subsequently removed, it is not necessary to etch the epitaxial layer 31 to obtain multiple independent epitaxial layers 31, thereby avoiding the influence of etching damage on the radiation recombination efficiency in the epitaxial layer 31, improving the brightness of the light-emitting chip and the display panel 10 prepared based on the epitaxial layer 31, and enhancing the display performance of the display panel 10; and after the growth of the epitaxial layer 31 is completed, before the chip electrode is set on the epitaxial layer 31, the entire surface of the epitaxial layer 31 on the growth substrate 21 is first bound to the driving backplane 40, and then the preparation of the light-emitting chip is completed, thereby avoiding the process of the chip electrode of the light-emitting chip and the backplane electrode on the driving backplane 40, reducing the difficulty of alignment, improving the preparation yield of the display panel 10, and reducing the production cost of the display panel 10.

[0111] Another optional embodiment of the present application:

[0112] This embodiment provides a manufacturing method of a display panel 10. Figure 8 and Fig. 9 ,in Figure 8FIG. 1 is a schematic diagram of the manufacturing process of the display panel 10 in the first stage A. Fig. 9 The figure shows a schematic diagram of the manufacturing process of the display panel 10 in the second stage B. It should be noted that: Figure 8 and Fig. 9 The division of the first stage A and the second stage B is only because there are many preparation processes of the display panel 10, which are difficult to be clearly presented in one figure. Therefore, the division of the first stage A and the second stage B is not necessary, and the specific division method is not limited to this one:

[0113] First, in Figure 8 In (a), a growth substrate 21 having a patterned sacrificial layer 22 is provided. In this embodiment, the growth substrate 21 is a sapphire substrate, and the patterned sacrificial layer 22 includes at least one of oxide materials such as SiO2 and Si3N4. A plurality of through holes 220 are arranged in an array in the patterned sacrificial layer 22, and the radial size of the through holes 220 gradually increases from the bottom of the hole to the hole mouth.

[0114] Then as Figure 8 As shown in (b), epitaxial growth is performed in the through hole 220 of the patterned sacrificial layer 22. In this embodiment, the top surface of the grown epitaxial layer 31 away from the growth substrate 21 is flush with the top surface of the patterned sacrificial layer 22 away from the growth substrate 21. The grown epitaxial layer 31 is GaN-based epitaxial.

[0115] exist Figure 8 In (c), a current spreading layer 53 and a first bonding metal layer 51 are sequentially arranged on a side of the epitaxial layer 31 away from the growth substrate 21. The current spreading layer 53 is an ITO layer, which is located between the first bonding metal layer 51 and the epitaxial layer 31. The first bonding metal layer 51 can be a composite metal layer including at least two of several metals such as Ti, Al, Au, Cr, Pt, In, Sn, and Ag.

[0116] exist Figure 8 In (d), a driving backplane 40 is provided, and a second bonding metal layer 52 is set on the bonding surface of the driving backplane 40. In some examples of this embodiment, the second bonding metal layer 52 has the same material and structure as the first bonding metal layer 51, and covers each second backplane electrode 42 of the driving backplane 40, is combined with each second backplane electrode 42, but is electrically isolated from the first backplane electrode 41.

[0117] Then as Figure 8 As shown in (e) in FIG. 1 , the first bonding metal layer 51 is bonded to the second bonding metal layer 52 , so that the first bonding metal layer 51 and the second bonding metal layer 52 form a bonding metal layer, and the bonding metal layer and the current spreading layer 53 together form a conductive layer.

[0118] exist Figure 8 In step (f), the growth substrate 21 is removed, for example, by emitting laser light from a solid-state laser to peel off the sapphire substrate. Then, the patterned sacrificial layer 22 is removed by wet etching, such as Figure 8 As shown in (g) in .

[0119] Then, a mask layer 36 is disposed on the epitaxial layer 31. The mask layer 36 and the conductive layer together fully encapsulate the epitaxial layer 31. Meanwhile, a portion of the conductive layer between adjacent epitaxial layers 31 is exposed from the mask layer 36. Figure 8 In some examples, the mask layer 36 can be formed by depositing SiO2, for example, first depositing SiO2 material on the entire surface, so that the SiO2 film layer formed will cover the surface of the epitaxial layer 31 and the conductive layer at the same time, and then the SiO2 film layer is patterned so that the conductive layer between adjacent epitaxial layers 31 is partially exposed.

[0120] Subsequently, the conductive layer is patterned through the mask layer 36 to form a plurality of independent conductive blocks 54, each conductive block 54 uniquely corresponds to one epitaxial layer 31 and also uniquely corresponds to one second backplane electrode 42 on the driving backplane 40, and the conductive block 54 is located between the corresponding epitaxial layer 31 and the second backplane electrode 42. Figure 8 (i) in .

[0121] See next Fig. 9 ,exist Fig. 9 In (a), a passivation layer 33 is provided to cover both the epitaxial layer 31 and the side of the conductive block 54. The passivation layer 33 may be Al2O3 prepared by an ALD (Atomic Layer deposition) process, or SiO2 prepared by a PECVD (Plasma Enhanced Chemical Vapor Deposition). It should be noted that in some examples of the present embodiment, the mask layer 36 may be removed before preparing the passivation layer 33. For example, if the mask layer 36 is a glue layer, it may be removed before the passivation layer 33 is provided. In other examples, the mask layer 36 may be retained on the epitaxial layer 31. For example, when the mask layer 36 is made of SiO2, the existence of the mask layer 36 does not affect the electrical performance and light-emitting effect of the epitaxial layer 31. Even if its material is the same as that of the passivation layer 33, it may not be removed. In some other examples of this embodiment, even if the mask layer 36 and the passivation layer 33 are made of different materials, the mask layer 36 does not need to be removed as long as the existence of the mask layer 36 does not affect the electrical performance and light extraction effect of the epitaxial layer 31 .

[0122] exist Fig. 9In (b), a first reflective layer 35 is provided on the surface of the passivation layer 33 away from the epitaxial layer 31. The first reflective layer 35 covers the side of the epitaxial layer 31, but the top surface of the epitaxial layer 31 away from the driving backplane 40 is exposed to the first reflective layer 35 to ensure that the light emitted from the top surface of the epitaxial layer 31 is not affected by the first reflective layer 35. In some examples of this embodiment, the first reflective layer 35 can be made of a metal with a high reflectivity, or can be a DBR layer. Fig. 9 The first reflective layer 35 only covers the side of the epitaxial layer 31 and is not distributed on the side of the conductive block 54 . However, in some examples of this embodiment, the first reflective layer 35 may also simultaneously cover the side of the epitaxial layer 31 and the conductive block 54 and cover the gap area between adjacent conductive blocks 54 .

[0123] Fig. 9 In (c), a light absorbing material is provided in the gap between adjacent conductive blocks 54 to form a light absorbing layer 34. The top surface of the light absorbing layer 34 away from the driving backplane 40 may be flush with or slightly lower than the bottom surface of the active layer in the epitaxial layer 31. In some examples of this embodiment, the light absorbing layer 34 may be made of materials including but not limited to oxides, polymers, etc. It is worth noting that although Fig. 9 In the embodiment, the light absorption layer 34 is disposed later than the first reflection layer 35 , but in some other examples of this embodiment, the light absorption layer 34 may be disposed first and then the first reflection layer 35 .

[0124] Then in Fig. 9 In (d), the first chip electrode 32 is provided, and the first chip electrode 32 passes through the passivation layer 33 and the mask layer 36, and is electrically connected to the first semiconductor layer in the epitaxial layer 31. It can be understood that before the first chip electrode 32 is provided, it is necessary to ensure that the top surface of the epitaxial layer 31 is exposed to the mask layer 36 and the passivation layer 33. Therefore, in some examples, the passivation layer 33 and the mask layer 36 can be etched in sequence to form an electrode hole that passes through the passivation layer 33 and the mask layer 36 in sequence, and a part of the epitaxial layer 31 is exposed from the bottom of the electrode hole. In this embodiment, each epitaxial layer 31 has a first chip electrode 32, so the first chip electrode 32 can be electrically connected to the first semiconductor layer of each epitaxial layer 31 at the same time, and at the same time, the first chip electrode 32 is also electrically connected to the first backplane electrode 41 on the driving backplane 40.

[0125] exist Fig. 9In (e), a cavity material layer 60 can be formed by arranging a cavity material on one side of the drive backplane 40 provided with an epitaxial layer 31, and a plurality of reflective cavities 600 are arranged in the cavity material layer 60, each reflective cavity 600 corresponds to an epitaxial layer 31, and the cavity bottom of the reflective cavity 600 faces the epitaxial layer 31, the cavity top is opposite to the cavity bottom, and the cavity top is open. A second reflective layer 61 formed of a reflective material is arranged on the side wall of the reflective cavity 600, and the second reflective layer 61 can also reduce the optical crosstalk between adjacent epitaxial layers 31 to a certain extent. In this embodiment, the cross section of the reflective cavity 600 gradually increases from the side close to the epitaxial layer 31 to the side away from the epitaxial layer 31. In some examples, the space inside the reflective cavity 600 is in the shape of an inverted truncated cone. It can be understood that if the cavity material layer 60 is light-transmitting, part of the cavity material may exist at the cavity bottom of the reflective cavity 600, but if the cavity material layer 60 is not light-transmitting, then there is basically no cavity material in the cavity bottom of the reflective cavity 600.

[0126] exist Fig. 9 In (f), a light conversion material may be disposed in the reflective cavity 600 to form a light conversion layer 62, and the light conversion material may include but is not limited to quantum dot materials. Fig. 9 In (f), each reflective cavity 600 is provided with a light conversion layer 62, part of which is a red light conversion layer, another part is a green light conversion layer, and another part of the reflective cavity 600 is provided with a blue light conversion layer, because the epitaxial layer 31 corresponding to the reflective cavity 600 is a violet light epitaxial layer or a UV light epitaxial layer. However, in some other embodiments of the present invention, if the epitaxial layer 31 is a blue light epitaxial layer, then there may be some reflective cavities 600 in the display panel 10 without a light conversion layer 62.

[0127] After the light conversion layer 62 is provided, in order to improve its reliability, for example, to prevent external water vapor and oxygen from causing the quantum dot material to fail and affect its light conversion performance, in some examples, a water-oxygen isolation layer 63 is also covered on the light conversion layer 62, such as Fig. 9 As shown in (g) in .

[0128] Then in Fig. 9 In (h), a filter film layer 64 is set. In this example, the filter film layer 64 is stacked with the cavity material layer 60, and the position of the filter unit in the filter film layer 64 corresponds one-to-one to the epitaxial layer 31. For example, the filter unit is located at the top of the reflective cavity 600.

[0129] Finally, in Fig. 9In (i), a lens array layer 65 is provided, and each microlens 650 in the lens array layer 65 is hemispherical and is located on the reflection cavity 600. In this embodiment, the lens array layer 65 can be provided on the cavity material layer 60 by methods including but not limited to nanoimprinting, hot melt photoresist etching, etc., or the lens array layer 65 can be prepared on other substrates and then transferred to the cavity material layer 60. In this embodiment, there is no specific limitation on the material for forming the lens array layer 65. For example, a material with a transmittance greater than 90% in the visible light band and a refractive index greater than 1.30 can be used.

[0130] This embodiment further provides a display panel 10. The display panel 10 can be manufactured based on the display panel manufacturing method provided in any of the above examples. Fig.10 A schematic diagram of the structure of the display panel 10 is shown:

[0131] The display panel 10 includes a driving backplane 40 , which is any one of a CMOS (Complementary Metal Oxide Semiconductor) backplane, a TFT (Thin Film Transistor) backplane, and a LTPS (Low Temperature Poly-Silicon) backplane.

[0132] A plurality of conductive blocks 54 are disposed on the driving back plate 40 and are connected to the second back plate electrode 42 ( Fig.10 The conductive blocks 54 are arranged in an array, and the conductive blocks 54 include a bonding metal layer. In some examples of the present embodiment, the conductive blocks 54 also include a current spreading layer 53, such as an ITO layer. In one example of the present embodiment, the ITO layer is disposed on a side of the bonding metal layer away from the driving back plate 40. In some examples of the present embodiment, the cross section of the conductive block 54 (a plane parallel to the bonding surface of the driving back plate 40) gradually decreases in a direction away from the driving back plate 40, for example, Fig.10 As shown, the cross-section (a plane perpendicular to the bonding surface of the driving back plate 40) of the conductive block 54 is trapezoidal. However, in some other examples of this embodiment, in the direction away from the driving back plate 40, the cross-sectional shape and size of the conductive block 54 are consistent at all locations, and the cross-section of the conductive block 54 is rectangular.

[0133] At the same time, the display panel 10 also includes a plurality of epitaxial layers 31 corresponding to the conductive blocks 54 one by one. The plurality of epitaxial layers 31 are also distributed in an array on the driving backplane 40 and stacked on the side of the conductive block 54 away from the driving backplane 40. From the side close to the driving backplane 40 to the side away from the driving backplane 40, the epitaxial layer 31 includes a second semiconductor layer, an active layer and a first semiconductor layer in sequence. At the same time, in this direction, the cross section of the epitaxial layer 31 gradually decreases, so from Fig.10 From the cross-sectional perspective shown, the cross-section of the epitaxial layer 31 is trapezoidal. It is understandable that in some other examples of this embodiment, the shape and size of the cross section of the epitaxial layer 31 in the direction away from the driving back plate 40 can also remain consistent, and the cross section of the epitaxial layer 31 is rectangular; or in some other examples, the cross section of the epitaxial layer 31 can gradually increase in the direction away from the driving back plate 40.

[0134] The surfaces of the epitaxial layer 31 and the conductive block 54 are coated with a passivation layer 33 . Part of the first semiconductor layer in the epitaxial layer 31 is exposed from the passivation layer 33 . The passivation layer 33 can electrically isolate the epitaxial layer 31 and the conductive block 54 from the outside, thereby improving the reliability of the display panel 10 .

[0135] In some examples of this embodiment, after the passivation layer 33 is set, a light absorbing material can be set between the gaps of adjacent conductive blocks 54 to form a light absorbing layer 34. In this embodiment, the distance between the side of the light absorbing layer 34 away from the driving backplane 40 and the bonding surface of the driving backplane 40 is less than or equal to the distance between the side of the active layer facing the driving backplane 40 and the bonding surface of the driving backplane 40. According to the orientation that the driving backplane 40 is at the bottom and the epitaxial layer 31 is at the top, that is, the top surface of the light absorbing layer 34 is not higher than the bottom surface of the active layer. In some examples, the top surface of the light absorbing layer 34 can be flush with the bottom surface of the active layer; in other examples, the top surface of the light absorbing layer 34 is lower than the bottom surface of the active layer. It can be understood that the setting of the light absorbing layer 34 can also block the light of the epitaxial layer 31 from irradiating to the adjacent epitaxial layer 31 to a certain extent, reducing the occurrence of light crosstalk. At the same time, the top surface of the light absorbing layer 34 is set not higher than the bottom surface of the active layer, which can reduce the absorption of light by the light absorbing layer 34, improve the light output brightness of the epitaxial layer 31, and enhance the display performance of the display panel 10.

[0136] In some examples of this embodiment, a first reflective layer 35 is further provided on the side of the passivation layer 33 away from the epitaxial layer 31. The first reflective layer 35 covers the side of the epitaxial layer 31 and is used to block the epitaxial layer 31 from emitting light from the side, prevent the light between adjacent epitaxial layers 31 from influencing each other, and reduce light crosstalk. At the same time, the provision of the first reflective layer 35 also improves the light extraction rate of the top surface of the epitaxial layer 31. In some examples of this embodiment, the first reflective layer 35 can be a DBR (Distributed Bragg Reflection) layer or a metal layer with high reflectivity.

[0137] It is understandable that if the first reflective layer 35 and the light absorbing layer 34 are both made of insulating materials, then in some examples of this embodiment, the passivation layer 33 may not be provided and the light absorbing layer 34 may be directly provided on the side of the conductive block 54 and the first reflective layer 35 may be provided on the surface of the epitaxial layer 31 .

[0138] A first chip electrode 32 is also provided on a surface of the passivation layer 33 away from the epitaxial layer 31 and the conductive block 54. The first chip electrode 32 electrically connects the first semiconductor layer in the epitaxial layer 31 and the first backplane electrode 41 on the driving backplane 40. In this embodiment, only one first backplane electrode 41 is provided on the driving backplane 40, and each epitaxial layer 31 shares the first chip electrode 32, that is, the same first chip electrode 32 simultaneously connects the first semiconductor layer of each epitaxial layer 31. The first chip electrode 32 is provided along the surface of the first reflective layer 35 away from the epitaxial layer 31 and the surface of the light absorbing layer 34 away from the driving backplane 40. Since the light absorbing layer 34 is filled in the gap between adjacent conductive blocks 54, the first chip electrode 32 does not need to meander into the gap between the conductive blocks 54 when it is provided. The light absorbing layer 34 plays a certain flattening role, which can facilitate the provision of the first chip electrode 32, reduce the probability of the first chip electrode 32 being broken, and improve the reliability of the display panel 10.

[0139] A cavity material layer 60 is also disposed on the side of the drive back plate 40 on which the epitaxial layer 31 is disposed. The surface of the cavity material layer 60 away from the drive back plate 40 is parallel to the bonding surface of the drive back plate 40. A plurality of reflective cavities 600 are disposed in the cavity material layer 60. Fig.10The light emitted by the epitaxial layer 31 can be emitted into the reflective cavity 600 from the bottom of the reflective cavity 600. A second reflective layer 61 formed of a reflective material is disposed on the side wall of the reflective cavity 600. The second reflective layer 61 can prevent the light from being emitted from the side wall of the reflective cavity 600, thereby preventing the light emitted by adjacent epitaxial layers 31 from interfering with each other. In some examples of the present embodiment, a light conversion layer 62 formed of a light conversion material is further disposed in the reflective cavity 600. The light conversion layer 62 can convert the wavelength and color of the light emitted from the bottom of the cavity. In some examples, the epitaxial layer 31 emits blue light. In this case, a red light conversion layer is provided in the reflective cavity 600 corresponding to a portion of the epitaxial layer 31 on the driving backplane 40, which can convert the blue light emitted by the epitaxial layer 31 into red light before emitting it; a green light conversion layer is provided in the reflective cavity 600 corresponding to another portion of the epitaxial layer 31, which can convert the blue light emitted by the epitaxial layer 31 into green light before emitting it; and a light conversion material is provided inside the reflective cavity 600 corresponding to another portion of the epitaxial layer 31, so that the light emitted from the reflective cavity 600 remains blue light. In some other examples, the epitaxial layer 31 emits purple light or ultraviolet light, then a red light conversion layer is provided in the reflective cavity 600 corresponding to a portion of the epitaxial layer 31 on the driving backplane 40, a green light conversion layer is provided in the reflective cavity 600 corresponding to another portion of the epitaxial layer 31, and a blue light conversion layer is provided inside the reflective cavity 600 corresponding to another portion of the epitaxial layer 31. By disposing the light conversion layer 62 , full-color display of the display panel 10 can be achieved without increasing the complexity of the growth process of the epitaxial layer 31 , thereby reducing the manufacturing cost of the display panel 10 .

[0140] In some examples of this embodiment, after the light conversion layer 62 is set, a water-oxygen isolation layer 63 can also be set. The water-oxygen isolation layer 63 is adhered and covered on the light conversion layer 62. It can isolate the light conversion layer 62 from the outside, prevent the light conversion layer 62 from failing due to the influence of external water and oxygen, and improve the quality and reliability of the display panel 10.

[0141] In some other examples of this embodiment, after the light conversion layer 62 is provided, a filter film layer 64 may be provided on the light emitting surface of the light conversion layer 62. The filter film layer 64 includes a plurality of filter units, and the positions of the filter units correspond to the positions of the epitaxial layer 31 one by one, which can selectively allow light to pass through. It can be understood that some of the plurality of filter units allow red light to pass through while blocking blue light and green light; another portion allows green light to pass through while blocking blue light and red light; and another portion allows blue light to pass through while blocking red light and green light.

[0142] In some examples of this embodiment, after the light conversion layer 62 is provided, a lens array layer 65 is also provided. The lens array layer 65 includes a plurality of microlenses 650. Each microlens 650 corresponds to the epitaxial layer 31 one by one and is relatively positioned. The microlens 650 can adjust the optical path of the incident light, thereby changing the light-emitting light pattern of the epitaxial layer 31. In some examples of this embodiment, the microlens 650 can be semi-spherical and covered on the top light-emitting surface of the epitaxial layer 31. The "semi-spherical" mentioned here only means that the shape of the microlens 650 is close to a semi-spherical shape, and does not require the microlens 650 to be exactly half of a sphere, nor does it require the microlens 650 to be a part of a sphere.

[0143] exist Fig.10 In the embodiment, the display panel 10 is provided with a water-oxygen isolation layer 63, a filter film layer 64 and a lens array layer 65 at the same time, but in some other examples of the present embodiment, only one or two of them may be provided. Fig.10 The middle filter film layer 64 is arranged outside the reflective cavity 600 , but in some other examples of this embodiment, each filter unit in the filter film layer 64 can also be arranged in the reflective cavity 600 , for example, directly attached to the surface of the water-oxygen isolation layer 63 away from the light conversion layer 62 .

[0144] The display panel and preparation method thereof provided in the present embodiment bonds the epitaxial layer 31 to the driving backplane 40 before preparing the light-emitting chip, thereby solving the problems of high difficulty in aligning the chip electrode and the backplane electrode and low bonding yield when bonding the light-emitting chip, and can improve the resolution of the display panel 10; moreover, a patterned sacrificial layer 22 is provided on the growth substrate 21, and then the epitaxial layer 31 is selectively grown to directly obtain the Mesa table, thereby avoiding epitaxial damage caused by dry etching of the epitaxial layer 31 and improving the radiation efficiency of the epitaxial layer 31; at the same time, multiple microstructures such as the reflective cavity 600, the light absorption layer 34, and the microlens 650 are introduced into the display panel 10 to realize pixel-level light extraction, modify the light emission type of a single light-emitting chip in the display panel 10, and improve the display performance of the display panel 10.

[0145] It should be understood that the application of the present application is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to this application.

Claims

1. A method for preparing a display panel, characterized in that: include: Disposing a patterned sacrificial layer on the growth substrate, wherein the patterned sacrificial layer includes a plurality of through holes; Growing an epitaxial layer of the light-emitting chip in the plurality of through holes, wherein the thickness of the epitaxial layer is less than or equal to the depth of the through holes, and the epitaxial layer comprises a first semiconductor layer, an active layer, and a second semiconductor layer, the distances between the epitaxial layer and the growth substrate increasing in sequence; Providing a driving backplane provided with a first backplane electrode and a second backplane electrode, and bonding the epitaxial layer on the growth substrate to the driving backplane so that the second semiconductor layer is electrically connected to the second backplane electrode; removing the growth substrate and the patterned sacrificial layer; A first chip electrode electrically connecting the first semiconductor layer and the first backplane electrode is prepared.

2. The method for preparing a display panel according to claim 1, wherein: The step of providing a patterned sacrificial layer on the growth substrate comprises: Providing a growth substrate as described above; Disposing a sacrificial material on the surface of the growth substrate to form a sacrificial layer; The sacrificial layer is patterned to form a plurality of through holes, wherein radial dimensions of the through holes gradually increase from a side close to the growth substrate to a side far from the growth substrate.

3. The method for preparing a display panel according to claim 1, wherein: The step of bonding the epitaxial layer on the growth substrate to the driving backplane comprises: A first bonding metal layer is arranged on a side of the epitaxial layer away from the growth substrate, and a second bonding metal layer is arranged on a bonding surface of the driving backplane, wherein the first bonding metal layer and the second bonding metal layer are electrically connected to the second semiconductor layer and the second backplane electrode respectively, and the second bonding metal layer is electrically isolated from the first backplane electrode; The surface of the first bonding metal layer away from the epitaxial layer is bonded to the surface of the second bonding metal layer away from the driving back plate to form a conductive layer including the first bonding metal layer and the second bonding metal layer.

4. The method for preparing a display panel according to claim 3, wherein: The plurality of second backplane electrodes on the driving backplane are arranged in an array, after removing the growth substrate and the patterned sacrificial layer, and before preparing the first chip electrode electrically connecting the first semiconductor layer and the first backplane electrode, further comprising: The conductive layer is patterned to form a plurality of independent conductive blocks, and the conductive blocks correspond to the second back plate electrodes one by one.

5. The method for preparing a display panel according to claim 4, wherein: After removing the growth substrate and the patterned sacrificial layer and before preparing a first chip electrode electrically connecting the first semiconductor layer and the first backplane electrode, the method further includes: Disposing a passivation layer at least covering the epitaxial layer; An insulating first reflective layer is arranged on a side of the passivation layer away from the epitaxial layer, and a light absorbing layer is arranged in a gap between adjacent conductive blocks, wherein the first reflective layer at least covers a side surface of the epitaxial layer, and a distance between a side of the light absorbing layer away from the driving backplane and the driving backplane is less than or equal to a distance between a side of the active layer facing the driving backplane and the driving backplane; A first chip electrode is arranged along a surface of the first reflective layer away from the passivation layer and a surface of the light absorbing layer away from the driving backplane, and the first chip electrode is electrically connected to the first backplane electrode on the driving backplane.

6. The method for preparing a display panel according to any one of claims 1 to 5, characterized in that: After preparing the first chip electrode electrically connecting the first semiconductor layer and the first backplane electrode, the method further includes: Depositing a cavity material on a side of the driving back plate provided with the epitaxial layer to form a cavity material layer; Etching the cavity material layer to form a plurality of reflective cavities at positions corresponding to the epitaxial layer, so that the light emitted by the epitaxial layer can be emitted into the reflective cavity from the cavity bottom of the reflective cavity; Disposing a reflective material on the side wall of the reflective cavity to form a second reflective layer; A light conversion material is arranged in the reflective cavity to form a light conversion layer.

7. A display panel, characterized in that: The display panel is manufactured by the method for manufacturing a display panel according to any one of claims 1 to 6, wherein the display panel comprises: A driving backplane, wherein a first backplane electrode and a plurality of second backplane electrodes are arranged on a bonding surface of the driving backplane; A plurality of mutually independent conductive blocks disposed on the bonding surface, the conductive blocks corresponding to the second back plate electrodes one by one; A plurality of epitaxial layers corresponding to the conductive blocks one by one, the epitaxial layers comprising a second semiconductor layer, an active layer and a first semiconductor layer, the distances between the epitaxial layers and the driving back plate increasing in sequence, the second semiconductor layer being electrically connected to the second back plate electrode through the corresponding conductive blocks; A light absorbing layer filled between adjacent conductive blocks, wherein the distance between the side of the light absorbing layer away from the driving backplane and the driving backplane is less than or equal to the distance between the side of the active layer facing the driving backplane and the driving backplane; a first reflective layer covering the side surfaces of the epitaxial layer; and A first chip electrode is arranged along a surface of the first reflective layer away from the epitaxial layer and a surface of the light absorbing layer away from the driving backplane, and the first chip electrode is configured to electrically connect the first backplane electrode and the first semiconductor layer.

8. The display panel according to claim 7, wherein: The conductive block includes a stacked bonding metal layer and a current spreading layer, and the current spreading layer is located between the bonding metal layer and the epitaxial layer; the number of the first backplane electrodes on the driving backplane is less than the number of the second backplane electrodes, and at least two of the epitaxial layers share one first backplane electrode.

9. The display panel according to claim 7, wherein: In a direction away from the driving back plate, a cross-sectional area of ​​at least one of the conductive block and the epitaxial layer gradually decreases, and the cross-section is parallel to a bonding surface of the driving back plate.

10. The display panel according to any one of claims 7 to 9, characterized in that: The display panel further includes: a cavity material layer, wherein a plurality of reflective cavities are arranged in the cavity material layer at positions corresponding to the epitaxial layer, and light emitted by the epitaxial layer can be emitted into the reflective cavity from the cavity bottom of the reflective cavity; a second reflective layer disposed on a side wall of the reflective cavity; a light conversion layer disposed in the reflective cavity; A water-oxygen isolation layer disposed in the reflection cavity and covering the light conversion layer; A filter film layer is arranged on the light output side of the light conversion layer, wherein the filter film layer includes a plurality of filter units corresponding to the epitaxial layers one by one; A lens array layer is arranged on a side of the cavity material layer away from the driving backplane, wherein the lens array layer comprises a plurality of micro lenses corresponding to the epitaxial layers one by one.

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