Over-current protection circuit arranged for providing over-current signal, and corresponding method and computer program product

Abstract

An overcurrent protection circuit arranged to provide an overcurrent signal, the overcurrent protection circuit comprising: a comparison stage arranged to determine that a blanking time value is higher than a predefined reference value; an output stage arranged for outputting an overcurrent signal based on the determination; a blanking time stage arranged for generating a blanking time value, and the blanking time stage arranged to begin generating the blanking time value when the load current exceeds a predefined set current, the blanking time stage further arranged to modulate the blanking time value based on a magnitude in which the load current exceeds the predefined set current.

Description

Technical Field

[0001] The present disclosure relates generally to the field of overcurrent protection, and more particularly to overcurrent protection circuits that are better designed to handle current loads that tend to have high peak-to-average ratios. Background Art

[0002] Overcurrent protection is a mechanism used in electrical and electronic systems to prevent a component or device from being damaged by excessive current flowing through it. Overcurrent can be caused by various reasons, such as a short circuit, system fault, or overload condition.

[0003] There are several methods for providing overcurrent protection, including fuses, circuit breakers, and current limiting devices. These methods are designed to interrupt or limit the flow of current when the current exceeds a certain threshold to prevent damage to the system.

[0004] Fuses are one of the most common overcurrent protection devices. They are simple devices consisting of a wire or filament that melts when the current exceeds a certain threshold. The melted wire or filament opens the circuit, interrupting the flow of current and protecting the system. Fuses come in a variety of sizes and ratings, and they need to be replaced after they melt.

[0005] Current limiting devices are another type of overcurrent protection mechanism. Their job is to limit the amount of current that can flow through a system, even in an overcurrent condition. This type of protection is often used in power supplies and electronic circuits to prevent damage to components and devices. Examples of current limiting devices include current limiting resistors, transistors, and integrated circuits.

[0006] An E-fuse (ie, electronic fuse) is an overcurrent protection device that uses solid-state technology to provide protection against overcurrent conditions. E-fuses are commonly used in electronic circuits where they provide reliable and accurate overcurrent protection.

[0007] The working principle of electronic fuses is to monitor the current flowing through the circuit and respond to overcurrent conditions by limiting the current or completely disconnecting the circuit. Unlike traditional fuses, electronic fuses do not rely on physical components to disconnect the circuit, but use semiconductor devices (such as MOSFETs) to provide protection.

[0008] One advantage of electronic fuses over traditional fuses is that they reset automatically, eliminating the need for replacement. This can save time and money, especially in applications where the fuse may frequently experience overcurrent conditions.

[0009] Overcurrent protection can be important in ensuring safe and reliable operation of electrical and electronic systems. It can prevent damage to components and devices, as well as prevent fire and other hazards. Designers and engineers may need to carefully consider the overcurrent protection requirements of the system and select the appropriate protection mechanism based on the application and specific requirements. Summary of the invention

[0010] The inventors have discovered that it may be beneficial to provide an overcurrent protection circuit that is better able to cope with current loads that tend to have high peak-to-average ratios.

[0011] In a first aspect of the present disclosure, there is provided an overcurrent protection circuit arranged to provide an overcurrent signal, the overcurrent protection circuit comprising:

[0012] - a comparison stage arranged to determine that the blanking time value is above a predefined reference value;

[0013] - an output stage arranged for outputting said overcurrent signal based on said determination,

[0014] - a blanking time stage arranged for generating said blanking time value,

[0015] wherein the blanking time stage is arranged to start generating the blanking time value when the load current exceeds a predefined set current;

[0016] Wherein the blanking time stage is further arranged to modulate a blanking time value based on an amount by which the load current exceeds the predefined set current.

[0017] The inventors have recognized that load switches and electronic fuses generally include overcurrent protection, which turns off the corresponding power switch or limits the corresponding current when the load current exceeds a predefined current limit.

[0018] In some applications (for example, audio amplifiers and motor drives), the load currents tend to have a relatively high peak-to-average ratio, that is, they have high peak currents that last for a short time. Generally, there are two ways to deal with this situation:

[0019] One option is to set a trip current higher than the peak current, i.e. a predefined set current for the output overcurrent signal. However, this means that an output short circuit, which results in a current greater than the average load current but less than the peak current, will not be detected and may result in damage to the system.

[0020] Another option is to set the trip current to be greater than the average current but less than the peak current. This will prevent damage to the system but may result in false tripping of the load switch or electronic fuse.

[0021] Manufacturers of electronic fuses and load switches have attempted to overcome this problem by adding an overcurrent blanking timer. This blanking timer starts when the load current exceeds the programmed current limit. The switch will not turn off until the blanking timer times out. The user can program the blanking timer based on the system requirements.

[0022] The inventors have recognized that the problem with the overcurrent blanking timer is that the time is fixed and is independent of the magnitude of the overcurrent. For example, it treats a 10% overcurrent condition the same as a 50% overcurrent condition. If the timer is not designed correctly, the system may be damaged.

[0023] Therefore, the present disclosure aims to no longer provide a fixed blanking time, ie a fixed blanking time value, but to modulate the blanking time based on the magnitude of the overcurrent.

[0024] If the overcurrent is high (eg, a 50% overcurrent condition), the overcurrent signal will be generated after a relatively short delay. If the overcurrent is low (eg, a 10% overcurrent condition), the overcurrent signal will be generated after a relatively long delay.

[0025] In an example, the blanking time stage is arranged to modulate a blanking time value such that the blanking time value is inversely proportional to the magnitude by which the load current exceeds the predefined set current.

[0026] This will allow a small overcurrent condition to last for a long time, while a large overcurrent condition may only last for a short time.

[0027] In yet another example, the blanking time stage is arranged to modularize the blanking time value such that the blanking time value is proportional to the square of the magnitude by which the load current exceeds the predefined set current.

[0028] This allows the overcurrent protection circuit to mimic an I 2 Therefore, from a functional point of view, the overcurrent protection circuit will be more closely related to the traditional fuse.

[0029] In yet another example, the blanking time levels include:

[0030] - a timing capacitor arranged to store energy;

[0031] - a first current source arranged for charging said timing capacitor, wherein a current provided by said first current source is proportional to said predefined set current;

[0032] - a second current source arranged to discharge the timing capacitor, wherein the current provided by the second current source is proportional to the load current;

[0033] Wherein the output of the timing capacitor is connected to the comparison stage.

[0034] This specific example describes an implementation of an overcurrent protection circuit. The working principle of the implementation is discussed below.

[0035] The basic function of the system is related to the charging and discharging of the timing capacitor. If the load current is relatively high, the timing capacitor will discharge quickly. If the load current is relatively low, the timing capacitor will discharge slowly. Therefore, the timer value for when the overcurrent signal is generated is modulated based on the magnitude of the load current.

[0036] In this particular example, there may be two aspects to consider. The capacitor is charged with a predefined set current (i.e., the trip current). The capacitor is discharged with the load current. If the predefined set current is higher than the load current, the capacitor will be charged to its maximum value. An overload condition will then not occur.

[0037] However, if the load current is higher than the trip current, the capacitor will (slowly) discharge. The voltage on the capacitor will (slowly) decrease. The comparison stage of the present disclosure can compare the voltage on the capacitor with a predefined reference voltage. If the voltage on the capacitor is lower than the predefined reference voltage, the comparison stage can signal an overload condition.

[0038] In yet another example, the blanking time level further includes:

[0039] - a third current source for discharging the timing capacitor, wherein the current provided by the third current source is constant.

[0040] The third current source may additionally be used to provide some kind of reference current.

[0041] In another example, comparatives include:

[0042] - a first comparator, wherein the inverting input of the first comparator is connected to the output of the timing capacitor, and wherein the non-inverting output of the first comparator is connected to the predefined reference value.

[0043] The comparator can be implemented, for example, as an operational amplifier OPAMP. The OPAMP compares two input signals. If the signal supplied to the non-inverting input is higher than the signal supplied to the inverting input, a high output signal is provided. If the signal supplied to the non-inverting input is lower than the signal supplied to the inverting input, a low output signal is provided.

[0044] In yet another example, the comparative further includes:

[0045] - a second comparator, wherein the inverting output of the second comparator is arranged to receive the predefined set current, and wherein the non-inverting input of the second comparator is connected to the load current,

[0046] The output stage comprises:

[0047] - an AND port arranged to receive the output of the first comparator and the output of the second comparator,

[0048] The output of the AND port is the overcurrent signal.

[0049] In yet another example, the blanking time stage further includes:

[0050] - a switch connected in series with the third current source for enabling and disabling the third current source, wherein the switch is controlled by the output of the second comparator.

[0051] In a second aspect of the present disclosure, a method for providing an overcurrent signal using an overcurrent protection circuit according to any of the foregoing examples is provided, wherein the method comprises the following steps:

[0052] - the blanking time value is determined by the comparison stage to be higher than a predefined reference value;

[0053] - outputting, by the output stage, the overcurrent signal based on the determination,

[0054] - generating the blanking time value by the blanking time stage, wherein the blanking time value starts to be generated when the load current exceeds a predefined set current;

[0055] Wherein the generating step comprises modulating the blanking time value based on an amount by which the load current exceeds the predefined set current.

[0056] Note that the advantages explained with respect to the first aspect of the disclosure (ie the overcurrent protection circuit) also apply to the second aspect of the disclosure (ie the method of operating such an overcurrent protection circuit).

[0057] In an example, the modulating step further comprises:

[0058] - modulating a blanking time value such that the blanking time value is inversely proportional to the amount by which the load current exceeds the predefined set current.

[0059] In another example, the modulating step further comprises:

[0060] - modulating a blanking time value such that the blanking time value is proportional to the square of the magnitude by which the load current exceeds the predefined set current.

[0061] In yet another example, the blanking time levels include:

[0062] - a timing capacitor arranged to store energy;

[0063] - a first current source arranged for charging said timing capacitor, wherein a current provided by said first current source is proportional to said predefined set current;

[0064] - a second current source arranged to discharge the timing capacitor, wherein the current provided by the second current source is proportional to the load current;

[0065] Wherein the output of the timing capacitor is connected to the comparison stage.

[0066] In yet another example, the blanking time level further includes:

[0067] - a third current source for discharging the timing capacitor, wherein the current provided by the third current source is constant.

[0068] In detailed examples, comparatives include:

[0069] - a first comparator, wherein the inverting input of the first comparator is connected to the output of the timing capacitor, and wherein the non-inverting output of the first comparator is connected to the predefined reference value,

[0070] - a second comparator, wherein the inverting output of the second comparator is arranged to receive the predefined set current, and wherein the non-inverting input of the second comparator is connected to the load current,

[0071] - a switch connected in series with the third current source for enabling and disabling the third current source, wherein the switch is controlled by the output of the second comparator,

[0072] The output stage comprises:

[0073] - an AND port arranged to receive the output of the first comparator and the output of the second comparator,

[0074] The output of the AND port is the overcurrent signal.

[0075] In a third aspect of the present disclosure, there is provided a computer program product comprising a computer-readable medium having instructions stored thereon, which instructions, when executed by a controller, cause the controller to implement a method according to any one of the examples provided above.

[0076] In the drawings, similar components and / or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the implementation description applies to any similar component with the same first reference label, regardless of the second reference label.

[0077] The above and other aspects of the disclosure will be apparent from and elucidated with reference to the examples described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] Figure 1 Examples of overcurrent protection circuits according to the present disclosure are disclosed.

[0079] Figure 2 Typical waveforms associated with an overcurrent protection circuit according to the present disclosure are disclosed.

[0080] Figure 3 Exposes the blanking time value versus overcurrent percentage. DETAILED DESCRIPTION

[0081] Note that in the description of the figures, the same reference numbers indicate the same or similar components performing the same or substantially similar functions.

[0082] A more detailed description will be given with reference to specific examples, some of which are illustrated in the accompanying drawings so that the manner in which the features of the present disclosure may be understood in more detail. Note that the drawings illustrate only typical examples and therefore should not be considered to limit the scope of the subject matter of the claims. The drawings are included to facilitate understanding of the present disclosure and are therefore not necessarily drawn to scale. The advantages of the claimed subject matter will become apparent to those skilled in the art by reading the description in conjunction with the drawings.

[0083] The following description above provides only preferred exemplary embodiments and is not intended to limit the scope, applicability or configuration of the present disclosure. Instead, the following description of the preferred exemplary embodiments will provide those skilled in the art with an illustration of the preferred exemplary embodiments of the present disclosure, and it should be understood that various changes may be made to the function and arrangement of elements, including combinations of features of different embodiments, without departing from the scope of the present disclosure.

[0084] Unless the context clearly requires otherwise, throughout the specification and claims, the words "comprise", "comprising", etc. should be interpreted as inclusive, rather than exclusive or exhaustive; that is, in the sense of "including but not limited to". As used herein, the terms "connected", "coupled" or any variation thereof mean any direct or indirect connection or coupling between two or more elements; the coupling or connection between elements may be physical, logical, electromagnetic, or a combination thereof. In addition, when used in this application, the words "herein", "above", "below" and words of similar meaning refer to the entirety of this application and not to any particular part of this application. Where the context permits, words used in the singular or plural in the detailed description may also include the plural or singular, respectively. The word "or", when referring to a list of two or more items, covers all of the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list.

[0085] These and other changes can be made to the technology according to the following detailed description. Although the description describes certain examples of the technology and describes the expected best mode, no matter how detailed the description seems, the technology can be implemented in many ways. The details of the system can vary considerably in its specific implementation, but are still included in the technology disclosed in this article. As mentioned above, the specific terms used in describing certain features or aspects of the technology should not be understood to imply that the terms are redefined herein to be limited to any specific characteristics, features or aspects of the technology associated with the terms. In general, the terms used in the following claims should not be interpreted as limiting the technology to the specific examples disclosed in the specification unless the specific implementation section explicitly defines these terms. Therefore, the actual scope of the technology includes not only the disclosed examples, but also all equivalent ways of practicing or implementing the technology according to the claims.

[0086] Figure 1 Examples of overcurrent protection circuits according to the present disclosure are disclosed.

[0087] As described above, in one of the embodiments of the present disclosure, the timing capacitor 4 is used. The timing capacitor 4 is charged and discharged using the first current source 1 and the second current source 2, respectively.

[0088] Note that the current sources 1, 2 may alternatively be interchanged. In this case, the inputs to the comparison stage may also need to be interchanged. In the remainder, it is assumed that the first current source 1 is proportional to a predefined set current and the second current source 2 is proportional to the load current.

[0089] It is clear that whenever the load current is lower than the predefined set current, the timing capacitor 4 is charged. Whenever the load current is higher than the predefined set current, the timing capacitor 4 is discharged.

[0090] A first comparator 5 is provided. The first comparator 5 compares two inputs with each other. If the input provided at the non-inverting input of the first comparator 5 is higher than the input provided at the inverting input of the first comparator 5, the comparator will output a logic high level.

[0091] The inverting input of the first comparator 5 is connected to the timing capacitor 4. This means that the voltage on the timing capacitor 4 is provided to the inverting input of the first comparator 5 as input.

[0092] The predefined reference value is connected to the non-inverting input of the first comparator 5. The predefined reference value is directly related to the value at which the overcurrent protection circuit should start, ie to the tripping current.

[0093] It is clear from this particular embodiment that there is a delay before the first comparator 5 issues a logic high signal. When the load current is higher than the predefined set current, the first comparator 5 will not immediately issue a logic high signal. First, the timing capacitor 4 needs to be discharged to below the predefined reference value before the first comparator 5 issues a logic high level. This is one of the concepts of the present disclosure.

[0094] This particular embodiment may further comprise an AND gate indicated with reference numeral 7, a second comparator indicated with reference numeral 6, a switch indicated with reference numeral 8 and a third current source indicated with reference numeral 3. These will be explained below.

[0095] The third current source 3 is used to accelerate the discharge process. It is a predefined constant current that can be initially set to calibrate the overcurrent protection circuit.

[0096] Only when the load current is actually higher than the predefined set current can the third current source 3 be triggered (i.e. enabled). This is achieved by using a switch 8 in combination with a second comparator 6. The second comparator 6 compares the load current with the predefined set current and outputs a logic high signal whenever the load current is higher than the predefined set current.

[0097] This logic high signal is used to control the switch 8. If the signal is high, the switch 8 is enabled, so that the third current source 3 is enabled. If the signal is low, the switch 8 is disabled, so that the third current source is disabled.

[0098] Therefore, the overcurrent protection circuit may comprise a second comparator 6, wherein an inverting output of the second comparator is arranged to receive the predefined set current, and wherein a non-inverting input of the second comparator is connected to the load current.

[0099] The output stage may include an AND port 7 for receiving the output of the first comparator and the output of the second comparator, wherein the output of the AND port 7 is the overcurrent signal.

[0100] Figure 2 Disclose typical waveforms associated with an overcurrent protection circuit according to the present disclosure;

[0101] The first phase is associated with operating operation in which the load current is below a predefined set current, i.e. the trip current. During this phase, the timing capacitor will be charged to its maximum value. This is indicated using the words "TMR pulled HI (normal operation)".

[0102] In the second phase, the load current will exceed the predefined set current. This will lead to a situation where the timing capacitor starts to discharge. This second phase is indicated using the words "IOUT exceeds ILIM" and "TMR starts to discharge".

[0103] In the third phase, the timing capacitor has charged to just below the predefined reference value so that the overcurrent protection circuit will enable and issue an overcurrent signal. This third phase is represented by "TMR reaches the lower threshold" and "IOUT is limited to ILIM".

[0104] Note that the overcurrent signal can be used by additional circuitry to limit the load current to the trip current. This is also indicated in stage 3. Finally, if the load current does not drop further to well below the trip current indicated with the words "OTP causes trip", a trip may be initiated.

[0105] Figure 3 Exposes the blanking time value versus overcurrent percentage.

[0106] This particular graph relates to the time that elapses before the overcurrent protection is activated. The first line 1 relates to the prior art, where this particular time is constant, i.e. independent of the percentage of the overcurrent situation. Whether the load current is much higher than the trip current or close to the trip current is irrelevant to the prior art. The delay is always the same, e.g. about 100ms.

[0107] The lines with reference numbers 2 and 3 are relevant to the present disclosure. Line 2 is related to the line without the third current source (see Figure 1 ) is relevant to the case where there is a third current source (see Figure 2). As shown in the figure, the delay time, i.e. the time required before the overcurrent protection circuit issues an overcurrent signal, depends on the percentage of overcurrent conditions. If hardly any overcurrent conditions occur, the so-called blanking time may be relatively long, e.g. 500ms. However, for very high overcurrent conditions, the overcurrent protection circuit may issue an overcurrent signal very quickly, i.e. long before the prior art solutions.

[0108] In order to reduce the number of claims, certain aspects of the technology are presented below in certain claim forms, but applicants contemplate various aspects of the technology in any number of claim forms. For example, while some aspects of the technology may be recited as computer-readable medium claims, other aspects may also be implemented as computer-readable medium claims, or in other forms, such as in means-plus-function claims.

[0109] In the above description, for the purpose of explanation, many specific details are set forth in order to provide a comprehensive understanding of the embodiments of the disclosed technology. However, it is obvious to those skilled in the art that the embodiments of the disclosed technology can be implemented without some of these specific details.

[0110] Other variations of the disclosed embodiments may be understood and implemented by those skilled in the art in practicing the claimed invention by studying the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a / an" does not exclude a plurality. The fact that certain measures are cited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope thereof.

Claims

1. An overcurrent protection circuit, arranged to provide an overcurrent signal, the overcurrent protection circuit comprising: a comparison stage arranged to determine that the blanking time value is above a predefined reference value; an output stage arranged to output the overcurrent signal based on the determination, a blanking time stage arranged to generate said blanking time value, wherein said blanking time stage is arranged to start generating said blanking time value when the load current exceeds a predefined set current; Wherein the blanking time stage is further arranged to modulate the blanking time value based on an amount by which the load current exceeds the predefined set current.

2. The overcurrent protection circuit of claim 1, wherein the blanking time stage is arranged to modulate the blanking time value such that the blanking time value is inversely proportional to the magnitude by which the load current exceeds the predefined set current.

3. The overcurrent protection circuit of claim 1 , wherein the blanking time stage is arranged to modularize the blanking time value such that the blanking time value is proportional to the square of the magnitude by which the load current exceeds the predefined set current.

4. The overcurrent protection circuit according to any one of the preceding claims, wherein the blanking time stage comprises: a timing capacitor arranged to store energy; a first current source arranged to charge the timing capacitor; The current provided by the first current source is proportional to the predefined set current; a second current source arranged to discharge the timing capacitor; The current provided by the second current source is proportional to the load current; and The output of the timing capacitor is connected to the comparison stage.

5. The overcurrent protection circuit according to claim 4, wherein the blanking time level further comprises: A third current source is used to discharge the timing capacitor, wherein the third current source has a constant supplied current.

6. The overcurrent protection circuit according to any one of claims 4 and 5, wherein the comparison stage comprises: A first comparator has an inverting input and a non-inverting input, and the inverting input of the first comparator is connected to the output of the timing capacitor, and the non-inverting output of the first comparator is connected to the predefined reference value.

7. The overcurrent protection circuit according to any one of claims 5 and 6, wherein the comparison stage further comprises: a second comparator having an inverting output arranged to receive said predefined set current and a non-inverting input connected to said load current, The output stage comprises: An AND port is arranged to receive the output of the first comparator and the output of the second comparator, and the output of the AND port is the overcurrent signal.

8. The overcurrent protection circuit according to claim 7, wherein the blanking time level further comprises: a switch connected in series with the third current source for enabling and disabling the third current source, The switch is controlled by the output of the second comparator.

9. A method of providing an overcurrent signal using an overcurrent protection circuit according to any one of the preceding claims, wherein the method comprises the following steps: Determining by the comparison stage that the blanking time value is higher than a predefined reference value; outputting, by the output stage, the overcurrent signal based on the determination, The blanking time value is generated by the blanking time stage, wherein the blanking time value begins to be generated when the load current exceeds a predefined set current; and Wherein the generating step comprises modulating the blanking time value based on an amount by which the load current exceeds the predefined set current.

10. The method of claim 9, wherein the modulating step further comprises: The blanking time value is modulated such that the blanking time value is inversely proportional to the magnitude by which the load current exceeds the predefined set current.

11. The method of claim 9, wherein the modulating step further comprises: The blanking time value is modulated such that the blanking time value is proportional to the square of the magnitude by which the load current exceeds the predefined set current.

12. The method according to any one of claims 9 to 11, wherein the blanking time level comprises: a timing capacitor arranged to store energy; a first current source arranged to charge the timing capacitor; The current provided by the first current source is proportional to the predefined set current; a second current source arranged to discharge the timing capacitor; The current provided by the second current source is proportional to the load current; and The output of the timing capacitor is connected to the comparison stage.

13. The method of claim 12, wherein the blanking time level further comprises: The third current source is used to discharge the timing capacitor, and the current provided by the third current source is constant.

14. The method according to any one of claims 12 and 13, wherein the comparison level comprises: a first comparator having an inverting input connected to the output of the timing capacitor and a non-inverting output connected to the predefined reference value; a second comparator having an inverting output arranged to receive the predefined set current and a non-inverting input connected to the load current; a switch connected in series with the third current source for enabling and disabling the third current source, wherein the switch is controlled by the output of the second comparator, The output stage comprises: An AND port is arranged to receive the output of the first comparator and the output of the second comparator, and the output of the AND port is the overcurrent signal.

15. A computer program product comprising a computer readable medium having stored thereon instructions which, when executed by a controller, cause the controller to implement the method according to any one of claims 9 to 14.

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