Control device for a pfc circuit and electronic device

Abstract

This application discloses a control device and electronic device for a PFC circuit, relating to the power supply field. The technical solution of this application integrates an auxiliary winding, a signal clamping circuit, a reference voltage circuit, a comparator, diodes, resistors, and a control chip with complex logic functions (including a second comparator, an event module, a first counter module, and a second counter module), achieving precise control over the operating frequency and switching timing of the switching transistors in the PFC circuit, particularly for optimization under CRM (Critical On-Mode).

Description

Technical Field

[0001] This invention relates to the field of power supplies, and more particularly to a control device and electronic device for a PFC circuit. Background Technology

[0002] In the continuous evolution of digital power supply technology, PFC (Power Factor Correction) has become one of the most widely used topologies in the AC / DC conversion field. Based on the characteristics of the inductor current, PFC can be clearly distinguished into three basic operating modes: Continuous On-Mode (CCM), Discontinuous On-Mode (DCM), and Critical On-Mode (CRM). Among them, CRM is favored in PFC control in the small to medium power range due to its unique advantages. The core feature of CRM mode is that the switching transistor achieves zero-current conduction, while the boost diode avoids the reverse recovery process. This mechanism significantly reduces system losses and improves overall efficiency.

[0003] Under the CRM control strategy, the switching frequency of the switching transistor is not fixed like in CCM or DCM, but is adjusted in real time according to a variety of dynamic factors, including input voltage fluctuations, desired output voltage levels, specific inductor parameters, and the turn-on time length of each switching cycle. This characteristic gives the CRM mode extremely high flexibility and adaptability, especially when facing complex and ever-changing power environments.

[0004] However, CRM mode also faces some challenges. Especially at low input voltages, frequent switching of the switching transistors is necessary to maintain a stable output voltage, leading to a sharp increase in switching frequency and potentially higher switching losses. Furthermore, during the transient process of rapid load transition from light to heavy load, particularly during the input voltage trough to peak period, the MOSFET's on-time is relatively prolonged, resulting in a corresponding increase in the discharge process. This direct consequence is a significant decrease in the switching transistor's operating frequency. This significant frequency change not only exacerbates switching losses but may also adversely affect the current waveform, causing waveform distortion and impacting system stability and output quality. Summary of the Invention

[0005] The control device and electronic device for the FC circuit provided in this application embodiment can solve the problems of excessive switching losses and current waveform distortion in the PFC circuit operating in CRM mode. The technical solution is as follows:

[0006] In a first aspect, embodiments of this application provide a control device for a PFC circuit, comprising:

[0007] The system includes an auxiliary winding, a signal clamping circuit, a first reference voltage circuit, a first comparator, a sixth resistor, a third diode, a fourth diode, a seventh resistor, and a control chip; the control chip includes a second reference voltage circuit, a second comparator, an event module, a first counter module, and a second counter module.

[0008] Wherein, the first end of the auxiliary winding is grounded, the second end of the auxiliary winding is connected to the input end of the signal clamping circuit, the output end of the signal clamping circuit is connected to the negative input pin of the first comparator, the positive input pin of the first comparator is connected to the first reference voltage circuit, the output pin of the first comparator is connected to the first end of the sixth resistor, the second end of the sixth resistor is connected to the anode of the third diode, the cathode of the diode is connected to the anode of the fourth diode, the positive input pin of the second comparator in the control chip, and the first end of the seventh resistor; the cathode of the fourth diode is connected to the output end of the second counter module, and the second end of the seventh resistor is grounded;

[0009] In the control chip, the negative input pin of the second comparator is connected to the second reference voltage circuit, the output pin of the second comparator is connected to the input terminal of the event module, the output terminal of the event module is connected to the input terminals of the first counter module and the second counter module respectively, and the output terminal of the first counter module is connected to the switching transistor in the PFC circuit.

[0010] The first counter module and the second counter module are provided with a first threshold CMPA, a second threshold CMPB, a third threshold CMPC, and a fourth threshold CMPD; the counting period value of the first counter module and the second counter module is equal to the reciprocal of the lowest switching frequency of the PFC circuit.

[0011] Event module E1 is used to output a counting event signal to the first counter module and the second counter module when a rising edge is detected in the output signal of the second comparator U2; wherein, when the current count value of the event module is between 0 and the first threshold CMPA, the output of the counting event signal to the first counter module and the second counter module is stopped.

[0012] The first counter module PWM1 and the second counter module PWM2 are used to count based on the counting event signal output by the event module; when the current count value reaches the second threshold CMPB, a high-level signal is output to the switch of the PFC circuit; when the current count value reaches the fourth threshold CMPD, a low-level signal is output to the switch of the PFC circuit; and when the current count value is equal to the counting period value, a count reset operation is performed.

[0013] Secondly, this application provides an electronic device, including a PFC circuit and the aforementioned control device.

[0014] The beneficial effects of the technical solutions provided in some embodiments of this application include at least the following:

[0015] By accurately capturing the zero-crossing signal of the inductor current through auxiliary windings and signal clamping circuits, combined with the complex logic within the control chip, dynamic adjustment of the switching transistor's operating frequency is achieved. This adjustment mechanism automatically optimizes the switching frequency based on changes in input voltage, output voltage, and load conditions, effectively avoiding excessively high or low switching frequencies when the input voltage is low or the load varies significantly, thereby reducing switching losses and improving system efficiency. Precise control of the switching transistor's turn-on and turn-off times, particularly utilizing multiple threshold values ​​(CMPA, CMPB, CMPC, CMPD) set by the first and second counter modules, enables fine-grained management of the switching transistor's operating state. This helps reduce current waveform distortion caused by switching frequency variations, improving the power supply's output quality. The control chip in this technical solution integrates multiple functional modules, such as event modules and counter modules. These modules work collaboratively to quickly respond to changes in system state and take corresponding control measures. This highly integrated control method improves system stability and reliability, reducing system anomalies caused by component failures or parameter mismatches. To address the characteristics of CRM mode, this technical solution achieves zero-current conduction of the switching transistor and zero reverse recovery process of the boost diode by dynamically adjusting the switching frequency and switching time, thereby further reducing system losses. This optimization is particularly suitable for low-to-medium power PFC control, helping to improve overall energy efficiency. The design of this technical solution offers high flexibility and scalability; by adjusting the parameters and logic within the control chip, it can adapt to the PFC circuit requirements of different power levels and application scenarios. Furthermore, this solution facilitates subsequent functional upgrades and performance optimization. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a structural diagram of the PFC circuit provided in the embodiments of this application;

[0018] Figure 2 and Figure 3This is a circuit diagram of the control device for the PFC circuit provided in the embodiments of this application;

[0019] Figure 4 This is a signal timing diagram of the control device of the PFC circuit provided in the embodiments of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Please see Figure 1 This invention provides a schematic diagram of a PFC circuit, including: a rectifier circuit, an inductor L1, a switching transistor Q1, a diode D5, and a filter capacitor C1. The rectifier circuit consists of four diode groups D1 to D4. The connection relationships of the above components can be referred to... Figure 1 As shown, this will not be repeated here. It should be noted that... Figure 1 The structure of the PFC circuit is only illustrative and can be adapted to specific implementations as needed. Figure 1 Add or modify components based on the PFC circuit.

[0022] Please see Figure 2 and Figure 3 This invention provides a control device for a PFC circuit, comprising: an auxiliary winding T1, a signal clamping circuit, a first reference voltage circuit, a first comparator U1, a sixth resistor R6, a third diode D3, a fourth diode D4, a seventh resistor R7, and a control chip P1. The control chip P1 includes: a second reference voltage circuit, a second comparator U2, an event module E1, a first counter module PWM1, and a second counter module PWM2. The auxiliary winding T1 is disposed on an inductor in the PFC circuit and is used to measure the changing voltage signal across the inductor. The signal clamping circuit clamps the voltage signal measured by the auxiliary winding T1. The first reference voltage circuit provides a reference voltage signal for the first comparator U1, and the second reference voltage circuit provides a reference voltage signal for the second comparator U2.

[0023] In this circuit, the first end of the auxiliary winding T1 is grounded, the second end of the auxiliary winding T1 is connected to the input end of the signal clamping circuit, the output end of the signal clamping circuit is connected to the negative input pin of the first comparator U1, the positive input pin of the first comparator U1 is connected to the first reference voltage circuit, the output pin of the first comparator U1 is connected to the first end of the sixth resistor D6, the second end of the sixth resistor D6 is connected to the anode of the third diode D3, the cathode of the diode D3 is connected to the anode of the fourth diode D4, the positive input pin of the second comparator U2 in the control chip P1, and the first end of the seventh resistor R7, respectively; the cathode of the fourth diode D4 is connected to the output end of the second counter module PWM2, and the second end of the seventh resistor R7 is grounded.

[0024] In the control chip P1, the negative input pin of the second comparator U2 is connected to the second reference voltage circuit, the output pin of the second comparator U2 is connected to the input terminal of the event module E1, the output terminal of the event module E1 is connected to the input terminals of the first counter module PWM1 and the second counter module PWM2 respectively, and the output terminal of the first counter module PWM1 is connected to the switching transistor in the PFC circuit.

[0025] In some embodiments of this application, the signal clamping circuit includes: a first resistor R1, a second resistor R2, a first diode D1, a second diode D2, and a third resistor R3.

[0026] In this circuit, the first end of the first resistor R1 is connected to the second end of the auxiliary winding T1, and the second end of the first resistor R1 is connected to the first end of the second resistor R2 and the cathode of the first diode D1. The second end of the second resistor R2 is connected to the negative input pin of the first comparator U1. The anode of the first diode D1 is grounded. The cathode of the second diode D2 is connected to the negative input pin of the first comparator U1, and the anode of the second diode D2 is grounded. The first end of the third resistor R3 is connected to the negative input pin of the second comparator U2, and the second end of the third resistor R3 is grounded.

[0027] In some embodiments of this application, the first reference voltage circuit includes a fourth resistor R4 and a fifth resistor R5. The first terminal of the fifth resistor R5 is connected to the power supply VCC, the first terminal of the fourth resistor R4 is grounded, and the second terminal of the fifth resistor R5 is connected to the second terminal of the fourth resistor R4 and the positive input pin of the first comparator U1.

[0028] See Figure 2 and Figure 3 The working principle of the control device of the PFC circuit of this application will be explained below.

[0029] The PFC circuit has an auxiliary winding T1 on its inductor. The auxiliary winding T1 measures the voltage signal across the inductor. One end of the auxiliary winding T1 is grounded, and the second end is connected to the first end of the first resistor R1. The first resistor R1, the second resistor R2, the third resistor R3, the first diode D1, and the second diode D2 constitute a signal clamping circuit. The first diode D1 can be an IN4148, and the second diode D2 is a Zener diode, for example, with a Zener voltage of 3V. The signal clamping circuit processes the voltage signal measured by the auxiliary winding to obtain signal S0. When the switching transistor Q1 in the PFC circuit is on, the voltage value of signal S0 is 0V; when the switching transistor Q1 is off, the level of signal S0 is clamped at 3V; when the current of inductor L1 is less than 0, the voltage value of signal S0 is clamped at 0V. In other words, the signal clamping circuit clamps the voltage of signal S0 between 0V and 3V.

[0030] The first reference voltage circuit provides a reference voltage signal for the first comparator. For example, if the first comparator U1 is powered by a single power supply with a supply voltage of 3.3V, the fourth resistor R4 and the fifth resistor R5 form the first reference voltage circuit, which divides the supply voltage signal VCC into a 2.8V reference voltage signal. This reference voltage signal is input to the positive input pin of the analog first comparator U1, and signal S0 is input to the negative input pin of the first comparator U1. The output of the first comparator U1 is signal S1, which can be either a high-level or low-level signal. Signal S1 passes through the sixth resistor R6 and the third diode D3 to obtain signal S3. When the current in inductor L1 in the PFC circuit is positive, the voltage value of signal S0 is 3V, and signal S3 is a high-level signal; otherwise, signal S3 is a low-level signal.

[0031] The control chip P1 includes a second comparator U2. The positive input pin of the second comparator U2 receives signal S3, while the negative input pin is connected to a second reference voltage circuit, which can be a digital-to-analog converter (DAC) providing a reference voltage signal. For example, if the DAC has a 12-bit width and its output value is configured to be 2048, a 1.5V reference voltage signal is applied to the negative input pin of the second comparator U2. The output signal of the second comparator U2 is signal S6, which can be either a high-level or low-level signal.

[0032] The first counter module PWM1 and the second counter module PWM2 are configured with a first threshold CMPA, a second threshold CMPB, a third threshold CMPC, and a fourth threshold CMPD. The counting period value of the first counter module PWM1 and the second counter module PWM2 is equal to the reciprocal of the lowest switching frequency of the PFC circuit PEROID_MAX_VAULE, and the reciprocal of the highest switching frequency of the PFC circuit is PEROID_MIN_VAULE.

[0033] Event module E1 is used to capture the rising edge of signal S6. When the rising edge of the output signal of the second comparator U2 is detected, it outputs a counting event signal to the first counter module PWM1 and the second counter module PWM2. Among them, when the current count value of the event module E1 is equal to any value between 0 and the first threshold CMPA, the output of the counting event signal to the first counter module and the second counter module is stopped. The event module starts counting from 0. Every time a rising edge is detected, the current count value is incremented by 1. When the current count value is equal to the count period value PEROID_MAX_VAULE, a counting reset operation is performed, that is, it starts counting from 0 again.

[0034] The first counter module PWM1 and the second counter module PWM2 are used to count based on the counting event signal output by the event module. When the current count value reaches the second threshold CMPB, a high-level signal is output to the switching tube of the PFC circuit. When the current count value reaches the fourth threshold CMPD, a low-level signal is output to the switching tube of the PFC circuit. When the current count value is equal to the count period value, a counting reset operation is performed.

[0035] Among them, when the second counter module PWM2 outputs a low-level signal when the current count value reaches the second threshold CMPB and outputs a high-level signal when the current count value reaches the fourth threshold CMPD, the output signal S2 is used to forcibly pull down the ZCD input signal for frequency limiting use.

[0036] The second threshold CMPB of the first count value module PWM1 is set to 0. The setting of the fourth threshold CMPD: Take the smaller value of the loop calculation result and the maximum conduction value DATA_MAX calculated by the volt-second product formula when the switching tube operates at the lowest frequency as the value of the fourth threshold CMPD, denoted as PWM1_CMPD_LOAD.

[0037] The setting of the first threshold CMPA of the first counter module PWM1 and the second counter module PWM2 is as follows: The first threshold CMPA of the two counter modules is the same. When PWM1_CMPD_LOAD + DATA1 < PEROID_MIN_VAULE, the value of the first threshold CMPA is PEROID_MIN_VAULE; otherwise, the value of the first threshold CMPA is PWM1_CMPD_LOAD + DATA1, and the value of the first threshold CMPA is denoted as CMPA_LOAD. Among them, DATA1 is the count value from the turn-off of the switching tube Q1 to the first threshold CMPA, which is used to eliminate the jitter caused by the turn-off of the switching tube Q1. This ensures that the ZCD signal occurs after the count value reaches PEROID_MIN_VAULE, restricting the highest operating frequency.

[0038] The second threshold CMPB of the second counter module PWM2 is set to CMPA_LOAD, and the fourth threshold CMPD is set to CMPA_LOAD+DATA2, where DATA2 is the pulse width of the low level of signal S2.

[0039] Signal S3 is generated by signals S1 and S2. When signal S2 is low, the ZCD signal is low. When signal S2 is high, the ZCD signal level is the same as that of signal S1. Therefore, the ZCD signal will be pulled low when the current count value reaches CMPA_LOAD. At this time, even if the current of inductor L1 reaches the zero-crossing point before the current count value reaches CMPA_LOAD, a rising edge will be generated when the current count value of the second counter module PWM2 reaches the fourth threshold CMPD. This ensures that the switching transistor Q1 operates at a higher switching frequency, rather than the lowest frequency, thus avoiding jitter caused by frequency abrupt changes.

[0040] See Figure 4 The diagram shown is a signal timing diagram of the control device in the application. The user describes the relationship between the various signals of the control device of the PFC circuit under three operating conditions.

[0041] In the first case, t0 to t3, the current zero-crossing point of the switch Q1 occurs after the signal S2 pulls low at t2, and t0 to t2 is the shortest switching period PEROID_MIN_VAULE corresponding to the switch Q1. The signal S2 does not affect the switch. At the current zero-crossing point t3, the first counter module PWM1 and the second counter module PWM2 are reset.

[0042] The second scenario is t3~t5. The current zero-crossing point of the switch Q1 occurs before the signal S2 pulls low t4. The conduction time t3~t4 is less than the shortest switching period PEROID_MIN_VAULE corresponding to the switch Q1. The rising edge of the signal S2 resets the first counter module PWM1 and the second counter module PWM2, limiting the switch Q1 to work at the highest frequency.

[0043] The third scenario is from t5 to t8. The current zero-crossing point of the switch Q1 occurs after the signal S2 is pulled low at t6, and the conduction time of the switch Q1 is greater than the shortest switching period PEROID_MIN_VAULE. The rising edge of the signal S2 is generated after t6. The signal S2 does not affect the switch Q1. At the current zero-crossing point t8, the first counter module PWM1 and the second counter module PWM2 are reset.

[0044] In the embodiments of this application, the application of an auxiliary winding makes current detection more direct and real-time, especially in PFC circuits where the current waveform may fluctuate due to load changes. The signal obtained through the auxiliary winding, combined with a signal clamping circuit and a comparator, can accurately capture the zero-crossing point of the current. This not only helps to achieve more precise current control but also improves the system's response speed and stability.

[0045] Optimizing Power Factor: Accurate zero-crossing current detection is key to achieving high power factor correction. In PFC circuits, controlling the on / off state of the switching transistors allows the input current waveform to closely follow the input voltage waveform, thereby reducing harmonic distortion and improving the power factor. Precise zero-crossing current signals contribute to a smoother current waveform, further enhancing the power factor.

[0046] Inductor saturation and overcurrent protection: By limiting the turn-on time of the switching transistor through volt-second calculations, inductor saturation and overcurrent problems caused by continuous conduction mode (CCM) can be effectively prevented. In CCM mode, the inductor current may continuously rise, exceeding its rated value and damaging the inductor or switching transistor. Limiting the maximum turn-on time ensures that the inductor operates in a safer and more efficient intermittent conduction mode (DCM).

[0047] Improving system efficiency and reliability: Limiting the maximum operating frequency reduces switching losses, as high-frequency switching generates more heat and electromagnetic interference. Simultaneously, protection mechanisms to prevent inductor saturation and overcurrent extend the lifespan of the entire PFC circuit, improving system reliability.

[0048] Enhancing system flexibility and adaptability: By introducing control mechanisms such as signal S2, the system can dynamically adjust the operating frequency and turn-on time of the switching transistors according to different load conditions and input voltage conditions, adapting to different working environments and requirements. This flexibility makes the PFC circuit more adaptable to complex power systems and variable load conditions.

[0049] The electronic device provided in this application embodiment includes a PFC circuit and the control device described above. The electronic device is not limited to communication equipment, terminal equipment, computer equipment, etc. In addition to the PFC circuit described above, the electronic device may also include: a housing for accommodating various components, a display screen, and an input device (e.g., a keyboard, mouse, or touch screen).

[0050] The embodiments described above do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the above embodiments should be included within the scope of protection of this technical solution.

Claims

1. A control device for a PFC circuit, characterized in that, include: The system includes an auxiliary winding, a signal clamping circuit, a first reference voltage circuit, a first comparator, a sixth resistor, a third diode, a fourth diode, a seventh resistor, and a control chip; the control chip includes a second reference voltage circuit, a second comparator, an event module, a first counter module, and a second counter module. Wherein, the first end of the auxiliary winding is grounded, the second end of the auxiliary winding is connected to the input end of the signal clamping circuit, the output end of the signal clamping circuit is connected to the negative input pin of the first comparator, the positive input pin of the first comparator is connected to the first reference voltage circuit, the output pin of the first comparator is connected to the first end of the sixth resistor, the second end of the sixth resistor is connected to the anode of the third diode, the cathode of the third diode is connected to the anode of the fourth diode, the positive input pin of the second comparator in the control chip, and the first end of the seventh resistor; the cathode of the fourth diode is connected to the output end of the second counter module, and the second end of the seventh resistor is grounded; In the control chip, the negative input pin of the second comparator is connected to the second reference voltage circuit, the output pin of the second comparator is connected to the input terminal of the event module, the output terminal of the event module is connected to the input terminals of the first counter module and the second counter module respectively, and the output terminal of the first counter module is connected to the switching transistor in the PFC circuit. The first counter module and the second counter module are each provided with a first threshold CMPA, a second threshold CMPB, a third threshold CMPC, and a fourth threshold CMPD; the counting period value of the first counter module and the second counter module is equal to the reciprocal of the lowest switching frequency of the PFC circuit. The first threshold of the first counter module is set as follows: when PWM1_CMPD_LOAD + DATA1 < PERIOD_MIN_VALUE, the first threshold CMPA is PERIOD_MIN_VALUE; otherwise, the first threshold CMPA is PWM1_CMPD_LOAD + DATA1; the value of the first threshold CMPA is denoted as CMPA_LOAD; where PERIOD_MIN_VALUE represents the reciprocal of the highest switching frequency of the PFC circuit, and DATA1 is used to eliminate jitter caused by the switching transistor being turned off; the second threshold CMPB of the first counter module is set to 0; the fourth threshold CMPD of the first counter module is set as follows: the smaller value between the loop calculation result of the PFC circuit regarding the switching transistor's on-time and the maximum on-time value DATA_MAX calculated by the volt-second product formula when the switching transistor is operating at the lowest switching frequency is taken as the value of the fourth threshold CMPD, denoted as PWM1_CMPD_LOAD; The first threshold CMPA of the second counter module is the same as the first threshold of the first counter module; the value of the second threshold CMPB of the second counter module is set to CMPA_LOAD; the value of the fourth threshold CMPD of the second counter module is set to CMPA_LOAD+DATA2, where DATA2 is the pulse width of the low level of the output signal of the second counter module. The event module is configured to output a counting event signal to the first counter module and the second counter module when a rising edge is detected in the output signal of the second comparator; wherein, when the current count value of the event module is between 0 and the first threshold CMPA, the output of the counting event signal to the first counter module and the second counter module is stopped. The first counter module and the second counter module are used to count based on the counting event signal output by the event module; when the current count value reaches the second threshold CMPB, a high-level signal is output to the switch of the PFC circuit; when the current count value reaches the fourth threshold CMPD, a low-level signal is output to the switch of the PFC circuit; and when the current count value is equal to the counting period value, a count reset operation is performed.

2. The control device according to claim 1, characterized in that, The signal clamping circuit includes: A first resistor, a second resistor, a first diode, a second diode, and a third resistor; Wherein, the first end of the first resistor is connected to the second end of the auxiliary winding, and the second end of the first resistor is connected to the first end of the second resistor and the cathode of the first diode respectively; The second terminal of the second resistor is connected to the negative input pin of the first comparator; The anode of the first diode is grounded; The cathode of the second diode is connected to the negative input pin of the first comparator, and the anode of the second diode is grounded. The first end of the third resistor is connected to the negative input pin of the first comparator, and the second end of the third resistor is grounded.

3. The control device according to claim 1 or 2, characterized in that, The first reference voltage circuit includes: a fourth resistor and a fifth resistor; The first end of the fifth resistor is connected to the power supply, the first end of the fourth resistor is grounded, and the second end of the fifth resistor is connected to the second end of the fourth resistor and the positive input pin of the first comparator.

4. The control device according to claim 3, characterized in that, The second reference voltage circuit includes a DAC converter with a bit width of 12.

5. An electronic device, characterized in that, It includes a PFC circuit and a control device as described in any one of claims 1 to 4.

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