System and method for power conversion using bipolar signaling

Abstract

The present technology relates to systems and methods for power conversion using bipolar signaling. In some embodiments, the present technology provides an apparatus that includes a first switch configured to receive a first signal and a second switch configured to receive a second signal. A voltage generator is coupled to the first switch. The apparatus further includes a first resistor coupled to the first switch and a second resistor coupled to the first resistor. The first switch is further coupled to a first capacitor that acts as a charge pump to generate a negative voltage such that an output of the device includes both positive and negative voltages. Embodiments of the present technology implement bipolar signaling based on a unipolar design, effectively minimizing DC leakage and overall power consumption. Other embodiments are also present.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application is a non-provisional application that claims U.S. patent application No. 63 / 507,247 filed by Walley et al. on June 9, 2023 and entitled “Bipolar Rectifier and Inverter,” which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] The present technology relates to power conversion systems and methods. Background Art

[0004] Over the past few decades, the field of power transmission and conversion systems has witnessed considerable technological advances, particularly in the design and development of rectifiers and inverters. A rectifier is an electrical device that converts an alternating current (AC) signal into a direct current (DC) signal, and an inverter is an electrical device that converts a direct current (DC) signal into an alternating current (AC) signal.

[0005] Various approaches involve designs based on unipolar IPs, where both the input and output operate within a voltage spectrum ranging from near ground to positive voltages. The popularity of unipolar designs can be attributed to their simplicity in both design and operation. However, they have several limitations, including high DC leakage. DC leakage is current that flows through unintended paths in a circuit, which can compromise the efficiency and reliability of the system.

[0006] Various approaches for enhanced power conversion systems have been explored, but they have proven to be insufficient. It is important to recognize the need for new and improved power conversion systems and methods. Summary of the invention

[0007] In one aspect, the present disclosure provides a device comprising: a first switch comprising a first input, the first input being configured to receive a first signal; a voltage generator coupled to the first switch, the voltage generator being characterized by a first voltage; a second switch coupled to the first switch, the second switch comprising a second input configured to receive a second signal; a first ground terminal coupled to the second switch; a first resistor coupled to the first switch and the voltage generator, the first resistor being characterized by a first resistance; a second resistor coupled to the first resistor, the second resistor being characterized by a second resistance; a buffer comprising a third input and a first output, the third input being coupled to the first resistor and the second resistor, the first output being characterized by a second voltage; a third switch coupled to the first output; a first capacitor coupled to the first switch and the third switch; and a second output coupled to the third switch and the first capacitor.

[0008] In another aspect, the present disclosure provides a device comprising: a first switch comprising a first input, the first input being configured to receive a first signal; a voltage generator coupled to the first switch, the voltage generator being characterized by a first voltage; a second switch coupled to the first switch, the second switch comprising a second input configured to receive a second signal; a first ground terminal coupled to the second switch; a first resistor coupled to the first switch and the voltage generator; a second resistor coupled to the first resistor; a buffer comprising a third input and a first output, the third input being coupled to the first resistor and the second resistor, the first output being characterized by a second voltage; a third switch coupled to the first output; a first capacitor coupled to the first switch and the third switch; and a second output coupled to the third switch and the first capacitor.

[0009] In another aspect, the present disclosure provides a device comprising: a first switch comprising a first input, the first input being configured to receive a first signal; a voltage generator coupled to the first switch, the voltage generator being characterized by a first voltage; a second switch coupled to the first switch, the second switch comprising a second input configured to receive a second signal; a first ground terminal coupled to the second switch; a first resistor coupled to the first switch and the voltage generator, the first resistor being characterized by a first resistance; a second resistor coupled to the first resistor, the second resistor being characterized by a second resistance; a second ground terminal coupled to the second resistor; a buffer comprising a third input and a first output, the third input being coupled to the first resistor and the second resistor, the first output being characterized by a second voltage; a third switch coupled to the first output; a first capacitor coupled to the first switch and the third switch; and a second output coupled to the third switch and the first capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A further understanding of the nature and advantages of particular embodiments may be achieved by reference to the remainder of the specification and the accompanying drawings, in which like reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to designate one of multiple similar components. When a reference numeral is mentioned without specifying an existing sub-label, it is intended to refer to all such multiple similar components.

[0011] Figure 1 is a block diagram illustrating a power conversion system according to an embodiment of the present technology.

[0012] Figure 2 is a circuit diagram illustrating a power conversion system according to an embodiment of the present technology.

[0013] Figure 3 is a graph illustrating a voltage / time diagram of components within a power conversion system in accordance with an embodiment of the present technology.

[0014] Figure 4 is a circuit diagram illustrating a power conversion system according to an embodiment of the present technology.

[0015] Figure 5 is a circuit diagram illustrating a power conversion system according to an embodiment of the present technology. DETAILED DESCRIPTION

[0016] The present technology relates to power conversion systems and methods. In some embodiments, the present technology provides a device comprising a first switch configured to receive a first signal and a second switch configured to receive a second signal. A voltage generator is coupled to the first switch. The device further comprises a first resistor coupled to the first switch and a second resistor coupled to the first resistor. The first switch is further coupled to a first capacitor, which acts as a charge pump to generate a negative voltage so that the output of the device includes both positive and negative voltages. Embodiments of the present technology implement bipolar signaling based on a unipolar design, effectively minimizing DC leakage and overall power consumption. Other embodiments also exist.

[0017] Some methods for implementing power conversion systems are mainly based on unipolar designs, in which both input and output operate within a voltage spectrum ranging from near ground to positive voltage. Although this design approach seems simple in its application, it often introduces the adverse effects of high DC leakage - a phenomenon in which current deviates from its expected path - resulting in system inefficiency. This inefficiency can endanger the reliability and operational effectiveness of the system when considered in the context of power conversion. In order to cope with the inherent shortcomings of unipolar systems, bipolar designs have become an attractive alternative, allowing the DC signal on the inverter output or rectifier input to remain close to ground. However, the implementation of bipolar designs brings a set of challenges of its own. One of the challenges is to manage negative voltages. Bipolar systems must be able to handle both positive and negative voltages, which can cause complexity in circuit design and overall power consumption. In addition, the integration complexity of bipolar designs brings difficulties to component selection and requires strict optimization at the full system level.

[0018] In various embodiments, the present technology implements bipolar signaling based on a unipolar design of a power conversion system. By integrating the inherent simplicity of a unipolar system with the advanced efficiency of bipolar signaling, the present invention solves ubiquitous challenges, such as high DC leakage, while maintaining ease of design and operation. The flexibility it provides in voltage control, such as effectively handling both positive and negative voltage states, substantially reduces the complexity typically associated with bipolar systems. In various embodiments, fast bipolar signaling is seamlessly implemented, enhancing the dynamic response of the power conversion system. For example, in fast switching scenarios (such as burst signaling), embodiments of the present technology ensure immediate DC offset adjustment within a minimum duration (such as a single cycle), achieving reliable data transmission with minimized power consumption and reduced interference. Embodiments of the present technology enhance overall system reliability, ensuring reduced interruptions and extended operating life. It should be understood that the present technology is suitable for any power conversion or transmission system, and is not limited to rectifiers and inverters.

[0019] The following description is presented to enable one of ordinary skill in the art to make and use the invention and incorporate it into the context of a particular application. Various modifications and various uses in different applications will be readily apparent to one of ordinary skill in the art, and the general principles defined herein can be applied to a wide range of embodiments. Therefore, the present technology is not intended to be limited to the embodiments presented, but should be consistent with the widest scope consistent with the principles and novel features disclosed herein.

[0020] In the following detailed description, in order to provide a more thorough understanding of the present technology, many specific details are set forth. However, it will be apparent to those skilled in the art that the present technology can be practiced without being limited to these specific details. In other examples, in order to avoid obscuring the present technology, well-known structures and devices are shown in block diagram form rather than in detail.

[0021] The reader's attention is directed to all papers and documents filed concurrently with this specification and disclosed for public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. Unless otherwise expressly stated, all features disclosed in this specification (including any accompanying claims, abstracts and drawings) may be replaced by alternative features for the same, equivalent or similar purposes. Therefore, unless otherwise expressly stated, each feature disclosed is only an example of a general series of equivalent or similar features.

[0022] Furthermore, any element in a claim that does not explicitly state “means for” performing a specified function or “step for” performing a specified function should not be construed as a “means” or “step” clause as specified in 35 U.S.C. 112, paragraph 6. Specifically, the use of “the step of” or “the act of” in the claims herein is not intended to invoke the provisions of 35 U.S.C. 112, paragraph 6.

[0023] When an element is referred to herein as being "connected" or "coupled" to another element, it is understood that the element may be directly connected to the other element or that there may be an intervening element between the elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there may be no intervening elements in the "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which there may be intervening elements.

[0024] When an element is referred to herein as being "disposed" in some manner relative to another element (e.g., disposed on, disposed between, disposed below, disposed adjacent to, or disposed in some other relative manner), it is understood that the element may be disposed directly relative to the other element (e.g., disposed directly on the other element) or that there may be intervening elements between the elements. Conversely, when an element is referred to as being "directly disposed" relative to another element, it is understood that there are no intervening elements in the "direct" instance. However, the presence of a direct placement does not exclude other instances in which there may be intervening elements.

[0025] Similarly, when an element is referred to herein as being "joined" to another element, it is understood that the element may be joined directly to the other element (without any intervening elements), or there may be intervening elements between the joined elements. Conversely, when an element is referred to as being "directly joined" to another element, it is understood that there are no intervening elements in the "direct" joining between the elements. However, the presence of direct joining does not exclude other forms of joining in which there may be intervening elements.

[0026] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include a plurality of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include a plurality of dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include an intervening element that is present between the coupled or connected layers. Conversely, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intervening elements between the layers. However, the presence of a directly coupled or connected layer does not exclude other connections in which an intervening element may be present.

[0027] In addition, the terms left, right, front, back, top, bottom, forward, reverse, clockwise and counterclockwise are used only for explanation purposes and are not limited to any fixed direction or orientation. Instead, they are only used to indicate the relative position and / or direction between the various parts of an object and / or component.

[0028] In addition, for ease of description, the methods and processes described herein may be described in a specific order. However, it should be understood that unless otherwise indicated by the context, the intermediate processes may occur before and / or after any part of the described process, and other various procedures may be reordered, added and / or omitted according to various embodiments.

[0029] Unless otherwise indicated, all numbers used herein to express quantities, dimensions, and the like are to be understood as being modified in all instances by the term "about". In this application, unless expressly stated otherwise, the use of the singular includes the plural, and the use of the terms "and" and "or" means "and / or" unless otherwise indicated. In addition, the use of the terms "including" and "having" and other forms such as "includes, included" and "has, have, had" should be considered non-exclusive. Moreover, unless expressly stated otherwise, terms such as "element" or "component" encompass both elements and components that make up one unit and elements and components that make up more than one unit.

[0030] As used herein, the phrase "at least one of..." preceding a series of items where the terms "and" or "or" are used to separate any items, modifies the list as a whole, rather than each member of the list (i.e., each item). The phrase "at least one of..." does not require selection of at least one of each item listed; rather, the phrase allows for a meaning that includes at least one of any one item and / or at least one of any combination of items. For example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In instances where selection of "at least one of each of A, B, and C," or alternatively "at least one of A, at least one of B, and at least one of C," is desired, it is explicitly described as such.

[0031] One general aspect includes a device comprising a first switch including a first input, the first input being configured to receive a first signal. The device further includes a voltage generator coupled to the first switch, the voltage generator being characterized by a first voltage. The device further includes a second switch coupled to the first switch, the second switch including a second input configured to receive a second signal. The device further includes a first ground terminal coupled to the second switch. The device further includes a first resistor coupled to the first switch and the voltage generator, the first resistor being characterized by a first resistance. The device further includes a second resistor coupled to the first resistor, the second resistor being characterized by a second resistance. The device further includes a buffer including a third input and a first output, the third input being coupled to the first resistor and the second resistor, the first output being characterized by a second voltage; a third switch coupled to the first output. The device further includes a first capacitor coupled to the first switch and the third switch. The device further includes a second output coupled to the third switch and the first capacitor.

[0032] Embodiments may include one or more of the following features. The device further includes a first circuit coupled to the first switch and the second switch, the first circuit being configured to send a first signal to the first input and a second signal to the second input. The second output is configured to output a first output signal. The buffer further includes a fourth input coupled to the first output. The first output signal includes a positive signal and a negative signal. The device further includes a fourth switch coupled to the third switch and the first capacitor. The first switch includes a complementary metal oxide semiconductor (CMOS) or a bipolar junction transistor (BJT). The first switch includes a gate coupled to the first input. The ratio of the first resistance to the second resistance is less than 1.1:1. The second voltage is less than or equal to half of the first voltage. The third switch includes a p-channel metal oxide semiconductor (PMOS) or a lateral diffused metal oxide semiconductor (LDMOS).

[0033] According to another embodiment, the present technology provides a device including a first switch including a first input, the first input being configured to receive a first signal. The device further includes a voltage generator coupled to the first switch, the voltage generator being characterized by a first voltage. The device further includes a second switch coupled to the first switch, the second switch including a second input configured to receive a second signal. The device further includes a first ground terminal coupled to the second switch. The device further includes a first resistor coupled to the first switch and the voltage generator. The device further includes a second resistor coupled to the first resistor. The device further includes a buffer including a third input and a first output, the third input being coupled to the first resistor and the second resistor, the first output being characterized by a second voltage. The device further includes a third switch coupled to the first output. The device further includes a first capacitor coupled to the first switch and the third switch. The device further includes a second output coupled to the third switch and the first capacitor.

[0034] Embodiments may include one or more of the following features. The device further includes a first circuit coupled to the first switch and the second switch, the first circuit being configured to send a first signal to the first input and a second signal to the second input to control switching of the first switch and the second switch. The second output is configured to output a first output signal. The device further includes a fourth switch coupled to the third switch and the first capacitor. The second voltage is less than or equal to half of the first voltage. The device further includes a second ground terminal coupled to the second resistor.

[0035] According to yet another embodiment, the present technology provides a device including a first switch including a first input, the first input being configured to receive a first signal. The device further includes a voltage generator coupled to the first switch, the voltage generator being characterized by a first voltage. The device further includes a second switch coupled to the first switch, the second switch including a second input configured to receive a second signal. The device further includes a first ground terminal coupled to the second switch. The device further includes a first resistor coupled to the first switch and the voltage generator, the first resistor being characterized by a first resistance. The device further includes a second resistor coupled to the first resistor, the second resistor being characterized by a second resistance. The device further includes a second ground terminal coupled to the second resistor. The device further includes a buffer including a third input and a first output, the third input being coupled to the first resistor and the second resistor, the first output being characterized by a second voltage. The device further includes a third switch coupled to the first output. The device further includes a first capacitor coupled to the first switch and the third switch. The device further includes a second output coupled to the third switch and the first capacitor.

[0036] Implementations may include one or more of the following features. The device further includes a first circuit coupled to the first switch, the first circuit configured to send a first signal to the first input. A ratio of the first resistance to the second resistance is less than 1.1:1. The device further includes a fourth switch coupled to the third switch and the first capacitor.

[0037] Figure 1 1 is a block diagram illustrating a power conversion system 100 according to an embodiment of the present technology. This figure merely provides an example, which should not overly limit the scope of the claims. A person of ordinary skill in the art will recognize many variations, substitutions, and modifications. System 100 may be implemented as any type of power conversion system and may be part of a larger device, such as a wireless charger. For example, system 100 may be implemented as a rectifier, which refers to an electrical device that converts an alternating current (AC) signal into a direct current (DC) signal. In another example, system 100 may be implemented as an inverter, which refers to an electrical device that converts a direct current (DC) signal into an alternating current (AC) signal. System 100 may be a power supply, a battery charger, a battery-operated device, and / or the like used. Depending on the implementation, system 100 may be fully or partially integrated into an integrated circuit chip.

[0038] As shown, the system 100 may include at least one of a first circuit 101, a first switch 104, a second switch 105, a voltage generator 106, a first resistor 107, a second resistor 108, a first ground terminal 110, a second ground terminal 109, a buffer 111, a third switch 112, a first capacitor 114, a fourth switch 113, and a second output 115. As an example, the system 100 is configured to receive an AC signal and rectify the AC signal into a DC signal. The voltage generator 106 may output a DC voltage to provide energy for any subsequent processing circuit system. In an example, the system 100 is configured to receive a DC signal and output an AC signal at the second output 115. For example, the term "conversion" (e.g., from AC to DC or vice versa) includes conversion of non-ideal signals that can be implemented into real-world applications. Therefore, the AC signal may include a non-ideal AC signal (e.g., a non-perfect sinusoid). Similarly, the DC signal may include a non-ideal DC signal (e.g., a non-perfect constant).

[0039] In various implementations, the system 100 includes a first switch 104 and a second switch 105. As an example, the term "switch" may refer to an electronic component capable of controlling, directing, or modulating a current within a circuit. The first switch 104 and / or the second switch 105 may include, but are not limited to, a field effect transistor (FET), such as a metal oxide semiconductor FET (MOSFET), a lateral diffused metal oxide semiconductor (LDMOS), a bipolar junction transistor (BJT), a thyristor, or other type of transistor, or other type of switch. In some cases, the first switch 104 includes a complementary metal oxide semiconductor (CMOS) or a bipolar junction transistor (BJT). In some embodiments, the first switch 104 and the second switch 105 may be coupled to a first circuit 101, which is configured to control the operation of the first switch 104 and the second switch 105. The circuit 101 may include circuitry and / or other components, such as programmable logic, a microcontroller, and / or software, and may send control signals to the first switch 104 and the second switch 105 to adjust their operation.

[0040] According to various embodiments, the first switch 104 includes a first input 102, and the second switch includes a second input 103. The term "input" may refer to a point or node in a circuit where a signal (such as a voltage or current) is fed into a device or component. The first input 102 and / or the second input 103 may include, but are not limited to, a terminal, a lead or a pin on a semiconductor device or a connection point on a printed circuit board (PCB). For example, the first switch 104 includes a gate coupled to the first input 102. In an example, the first switch 104 includes a bipolar junction transistor (BJT), which may include a base coupled to the first input 102. Depending on the implementation, the first circuit 101 may be configured to send one or more signals to the first switch 104 and the second switch 105 to change their on / off states. For example, the first input 102 is configured to receive a first signal from the first circuit 101. The first switch 104 may change the on / off state in response to the first signal. In some cases, the first switch 104 may be switched from an off state to an on state after receiving the first signal. Similarly, the first switch 104 may be switched from an on state to an off state after receiving the first signal. The second input 103 may be configured to receive a second signal from the first circuit 101. The second switch 105 may change the on / off state in response to the second signal. For example, the second switch 105 may be switched from an off state to an on state after receiving the second signal. Similarly, the second switch 105 may be switched from an on state to an off state after receiving the second signal.

[0041] In some embodiments, the system 100 further includes a voltage generator 106 coupled to the first switch 104. The voltage generator 106 may be characterized by a first voltage. The term "voltage generator" may refer to a device that generates, regulates, or maintains a specific voltage level within an electrical system by providing or absorbing energy. Depending on the implementation of the present technology, the voltage generator may be configured as a voltage source or a voltage sink. For example, the voltage generator 106 may be configured as a voltage source that supplies energy to the system, converting DC to AC to generate a desired voltage level. In some examples, the voltage generator 106 may be configured as a voltage sink that absorbs energy when converting AC to DC, establishing the necessary voltage level by drawing or absorbing current as needed. Depending on the implementation, the power provided by the voltage generator 106 may include a positive signal and / or a negative signal. The term "positive signal" may refer to a portion of a voltage or current waveform that is maintained above ground in an electrical system. The term "negative signal" may refer to a portion of a voltage or current waveform that drops below ground.

[0042] In some implementations, the first resistor 107 may be coupled to the first switch 104 and / or the voltage generator 106. The first resistor 107 may be characterized by a first resistance. For example, the term "resistance" refers to the resistance to the flow of current provided by a substance. Resistance can be determined or calculated using Ohm's law R=V / I, where V is the voltage across the resistor and I is the current flowing through it. Resistance can be measured in ohms (Ω). The system 100 may further include a second resistor 108 coupled to the first resistor 107. The second resistor 108 may be characterized by a second resistance. Depending on the implementation, the ratio of the first resistance to the second resistance may be less than 1.1:1. For example, the ratio of the first resistance to the second resistance may be 1:1.

[0043] In various implementations, the second switch 105 is coupled to the first ground terminal 110. The second resistor may be coupled to the second ground terminal 109. For example, the term "ground terminal" or "grounding" may refer to a connection point for referencing the potential of a circuit to a ground plane. A ground plane is a conductive surface for dissipating electrical noise and providing a common reference point for all components in a circuit. In some embodiments, the system 100 further includes a buffer 111, which includes a third input and a first output. For example, the term "buffer" or "voltage buffer" may refer to an electronic component that isolates an input from an output, ensures voltage consistency, and prevents any interference from downstream components. The buffer 111 may include, but is not limited to, an operational amplifier (op-amp) voltage buffer, a digital buffer, a current buffer, a voltage divider, and / or the like. The term "output" may refer to a terminal or connection point that provides a signal to another device or circuit element. In an example, the buffer 111 includes an operational amplifier, which refers to a high-gain electronic voltage amplifier with a differential input and a single-ended output. In various examples, the third input of the buffer 111 is coupled to the first resistor 107 and the second resistor 108. The first output of the buffer is characterized by a second voltage. For example, due to the voltage dividing action of the first resistor 107 and the second resistor 108, the second voltage at the first output can be a fraction of the first voltage at the voltage generator 106. In some cases, the second voltage can be less than or equal to half of the first voltage.

[0044] In various implementations, the system 100 further includes a third switch 112 that can be coupled to the first output of the buffer 111. As an example, the third switch 112 can include, but is not limited to, a field effect transistor (FET), such as a metal oxide semiconductor FET (MOSFET), a bipolar junction transistor (BJT), a thyristor, or other types of transistors or other types of switches. In some cases, the third switch 112 can include a p-channel metal oxide semiconductor (PMOS) and / or a lateral diffused metal oxide semiconductor (LDPMOS). In some embodiments, a first capacitor 114 can be coupled to the first switch 104 and / or the third switch 112. The term "capacitor" can refer to an electronic component that stores energy in an electric field. The first capacitor 114 can include, but is not limited to, a ceramic capacitor, a film capacitor, an electrolytic capacitor, and / or the like. In some implementations, a fourth switch 113 is coupled to the third switch 112 and the first capacitor 114. The fourth switch 113 can include, but is not limited to, a field effect transistor (FET), such as a metal oxide semiconductor FET (MOSFET), a bipolar junction transistor (BJT), a thyristor, or other types of transistors or other types of switches.

[0045] In various examples, the system 100 includes a second output configured to provide an output signal of the system 100 to a subsequent circuit system for further processing. The second output 115 may be coupled to the third switch 112 and the first capacitor 114. As an example, the second output 115 is configured to output a first output signal. Depending on the implementation, the first output signal may include an AC signal and / or a DC signal. The term "AC signal" or "alternating current signal" may refer to a current, voltage, or sequence of values ​​that periodically reverses direction. In an AC signal, the current or voltage alternates between positive and negative polarities. The AC signal may include, but is not limited to, a sine waveform, a square waveform, a triangular waveform, and / or the like. The term "DC signal" or "direct current signal" may refer to a current, voltage, or sequence of values ​​that exhibit only positive values ​​or only negative values. The current flows in a constant direction without changing polarity. The DC signal may include, but is not limited to, a constant voltage signal, a constant current signal, and / or the like.

[0046] Figure 2 is a circuit diagram illustrating a power conversion system 200 according to an embodiment of the present technology. This figure merely provides an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art will recognize many variations, substitutions, and modifications. As previously mentioned, the system 200 can be implemented as any type of power conversion system, such as a rectifier, inverter, or other bidirectional converter.

[0047] As shown, the system 200 may include at least one of a first circuit 201, a first switch 204, a second switch 205, a voltage generator 206, a first resistor 207, a second resistor 208, a first ground terminal 210, a second ground terminal 209, a buffer 211, a third switch 212, a first capacitor 214, a fourth switch 213, and a second output 215. For example, the system 200 may be implemented as an inverter configured to receive an input signal (e.g., a DC signal provided by the voltage generator 206) and generate an output signal (e.g., an AC signal output at the second output 215). For example, the voltage generator 206 may be characterized by a first voltage, denoted as VRECT. The second output 215 may be configured to output a first output signal, which may be characterized by a target voltage, depending on the application. In various implementations, the first voltage of the voltage generator 206 may be determined or adjusted based on the target voltage.

[0048] In some embodiments, the operation of the system 200 relies on the systematic and coordinated switching of the first switch 204 and the second switch 205 according to specific conditions. For example, the first switch 204, designated as TOPx, includes a first input 202. The second switch 205, designated as BOTx, includes a second input 203. The first switch 204 and the second switch 205 can be controlled by the first circuit 201. For example, the first circuit 201 is configured to send one or more signals to the first switch 204 and the second switch 205 to change their on / off states. The first resistor 207 can be coupled to the first switch 204 and / or the voltage generator 206. The first resistor 207 can be characterized by a first resistance. The second resistor 208 can be coupled to the first resistor 207. The second resistor 208 can be characterized by a second resistance. Depending on the implementation, the first resistance and the second resistance can be closely matched. For example, the ratio of the first resistance to the second resistance can be less than 1.1:1. In some cases, the ratio of the first resistance to the second resistance can be 1:1. The second switch 205 may be coupled to a first ground terminal 210 , labeled RGND. The second resistor 208 may be coupled to a second ground terminal 209 .

[0049] In some embodiments, the system 200 further includes a buffer 211, which includes a third input and a first output. The first output may be characterized by a second voltage, labeled ACx_BIAS. The buffer 211 may further include a fourth input coupled to the first output. A third switch 212, labeled CMx, may be coupled to the first output of the buffer 211. In various examples, a resistor may be integrated from the CMx pin to ground, acting as an effective means to maintain a bipolar signal after DC stabilization has occurred. The resistance value of the resistor may be dynamically adjusted to accommodate a range of operating conditions and requirements, enhancing the adaptability and efficiency of the system. A first capacitor 214, labeled CNCPx - may be coupled to the first switch 204 and / or the third switch 212. For example, the first capacitor 214 includes a first side coupled to the first switch 204 and a second side coupled to the third switch 212. In some cases, the system 200 further includes a fourth switch 213 coupled to the third switch 212 and the first capacitor 214 - labeled CMx_AC.

[0050] In operation, the first voltage is set to twice the target voltage (e.g., 5V, 10V, etc.). This means that if the first voltage is VRECT, the target voltage will be VRECT / 2. After startup, the first circuit 201 may send a first signal to the first input 202 to activate the transition of the first switch 204 to its on state. At the same time, the first circuit 201 may send a second signal to the second input 203 to keep the second switch 205 in its off state while the first switch is actively turned on. In a tightly coordinated sequence, the third switch 212 may be turned on after the on transition of the first switch 204. For example, the first circuit 201 may send a third signal to turn on the third switch 212 in coordination with the on transition of the first switch 204. In some cases, a time delay may be imposed on the activation of the third switch 212, ensuring that it switches to its on state only after the first switch 204 has achieved full activation. It should be understood that the states of the first switch 204 and the second switch 205 controlled by the first circuit 201 should remain opposite to each other during operation to eliminate the risk of short circuits.

[0051] Due to the voltage dividing action of the first resistor 207 and the second resistor 208, the second voltage at the first output can be a fraction of the first voltage at the voltage generator 106. For example, the second voltage ACx_BIAS can be less than or equal to half of the first voltage VRECT. In an example, ACx_BIAS is half the value of VRECT (e.g., VRECT / 2). The first side of the first capacitor 214 can be coupled to the pin output ACx.

[0052] During an operation cycle in which the first switch 204 and the third switch 212 are turned on and the second switch 205 is turned off, the first side of the first capacitor 214 is charged to the value of VRECT. At the same time, the second side of the first capacitor 214 connected to the first output of the buffer 211 by the third switch 212 is charged to half the value of VRECT (e.g., VRECT / 2). This systematic charge distribution ensures that the DC bias across the first capacitor 214 is maintained at VRECT / 2. The DC bias subtraction at the first capacitor 214 is an important step in generating a bipolar signal. When the first switch 204 and the third switch 212 are turned off and the second switch 205 is turned on, the first side of the first capacitor 214 is discharged to ground. Because the second side of the first capacitor 214 is VRECT / 2 lower than the first side, this causes the second side of the first capacitor 214 to drop to a voltage of -VRECT / 2 about ground. This process effectively removes the DC component from the input signal to generate the first output signal second output 215. By using the first capacitor 214 to perform DC subtraction, DC leakage can be effectively minimized, generating a bipolar signal with a reduced DC component. In real world applications, VRECT may experience occasional fluctuations, and the operating frequency of the first capacitor 214 may therefore be optimized to respond immediately. The timely subtraction of the DC bias allows the system 200 to consistently output the desired bipolar signal even in the presence of voltage fluctuations.

[0053] In various embodiments, when the system 200 is idle (e.g., both the first switch 204 and the second switch 205 are off), the first output signal at the second output 215 may be approximately ±VRECT / 2. This is because the first capacitor 214 acts as a negative charge pump. When the first switch 204 and the third switch 212 are off, the first capacitor 214 may be charged to a voltage of VRECT / 2. In order to normalize the first output signal to 0 volts, the fourth switch 213 may be activated to charge the first capacitor 214 up to a voltage equal to VRECT / 2, thus stabilizing the first output signal at 0 volts. It should be appreciated that the system 200 strategically generates a bipolar output signal based on a unipolar-based design by configuring the first capacitor 214 to act as a negative charge pump. By taking advantage of this configuration, the system 200 effectively subtracts a voltage, facilitating the conversion of a unipolar input into a bipolar signal. This approach not only maintains the integrity of the signal, but also substantially minimizes potential DC leakage, resulting in more efficient and reliable operation.

[0054] Figure 3 The present invention is a power conversion system (eg Figure 2200 ). This figure provides an example only, which should not unduly limit the scope of the claims. One of ordinary skill in the art will recognize many variations, substitutions, and modifications. In various embodiments, waveform 302 represents the waveform of a first voltage measured at pin output ACx. Waveform 304 represents the waveform of a second voltage measured at pin output ACx_BIAS. Waveform 306 represents the waveform of a first signal measured on first switch 204. Waveform 308 represents the waveform of a third signal measured on third switch 212. Waveform 310 represents the waveform of a second signal measured on second switch 205. The turning on of first switch 204, second switch 205, and third switch 212 is indicated by a rise in the measured voltage; the turning off of first switch 204, second switch 205, and third switch 212 is indicated by a corresponding voltage drop.

[0055] In some embodiments, the first voltage is set to twice the target voltage (e.g., 5V, 10V, etc.). As an example, if the target voltage (e.g., the desired output signal) is ±5V, the first voltage may be set to 10V. The operation of the system 200 may be performed via one or more specific sequences. For example, after startup, the first switch 204 is turned on at a first time t1, as indicated by a voltage rise. At the same time, the second switch 205 is cut off at a first time t1, as indicated by a voltage drop. In a tightly coordinated sequence, the third switch 212 is turned on at a second time t2 after the first switch 204 is turned on. The sequence of switch activation and deactivation is an important aspect of the present technology for achieving the desired bipolar signal while maintaining minimized DC leakage. The relationship between the duty cycles of the first, second, and third signals is important in coordinating the operation of the first switch 204, the second switch 205, and the third switch 212. In a specific embodiment, the third switch 212 is activated after the first switch 204 is fully activated. In other words, the third signal may be characterized by a duty cycle that lags behind a certain fraction of the duty cycle of the first signal. This staggered operation ensures that each component is given sufficient response time, promoting coordinated operation and mitigating the risk of signal interference or overlap. In addition, it should be understood that the duty cycle of the first switch 204 can be consistent and opposite to the duty cycle of the second switch 205, ensuring that their operating states remain anti-correlated, thereby preventing potential short circuits.

[0056] It should be understood that the switching circuit (e.g., the first switch 204, the second switch 205, or the third switch 212) may be operated at a variable frequency depending on the application. By monitoring the characteristics of the input signal, the system dynamically modulates its switching pattern. For example, during the start-up of a signal burst, the system may actively switch several consecutive cycles to quickly establish the desired bipolar state. Once the state is stable, the system can optimize its operation by reducing the switching frequency, perhaps once every 10, 50, or 100 cycles. This intermittent switching can be used for maintenance or correction purposes. In some cases, the system may determine the need for a bipolar adjustment cycle based on the voltage level measured at the CMx pin. By dynamically adjusting its operating frequency based on real-time feedback, the system not only saves energy, but also extends the durability of its components.

[0057] Due to the voltage dividing action of the first resistor 207 and the second resistor 208, the second voltage at the first output can be a fraction of the first voltage at the voltage generator 106. As an example, when the first switch 204 and the third switch 212 are turned on and the second switch 205 is turned off (e.g., immediately after the first time t1), the first voltage is about 10V and the second voltage is about 5V. When the first switch 204 and the third switch 212 are cut off and the second switch 205 is turned on at the third time t3, the first capacitor 214 (e.g., the second side of the first capacitor 214) is discharged to a negative voltage (e.g., -5V), which is then used to offset the positive voltage from the unipolar input signal. This process effectively removes the DC component from the input signal to generate the first output signal. The cycle of these switch operations indicating the activation and deactivation sequence can be repeated multiple times, allowing adaptability and responsiveness based on specific system requirements or environmental conditions.

[0058] Figure 4 4 is a circuit diagram illustrating a power conversion system according to an embodiment of the present technology. This figure merely provides an example, which should not overly limit the scope of the claims. A person of ordinary skill in the art will recognize many variations, substitutions, and modifications. As previously mentioned, system 400 may be implemented as any type of power conversion system, such as a rectifier, an inverter, or other bidirectional converter. As shown, system 400 may include at least one of a first circuit 401, a first switch 404, a second switch 405, a voltage generator 406, a first resistor 407, a second resistor 408, a first ground terminal 410, a second ground terminal 409, a buffer 411, a third switch 412, a first capacitor 414, a fourth switch 413, and a second output 415. For example, system 400 may be implemented as an inverter, which is configured to receive an input signal (e.g., a DC signal) and generate an output signal (e.g., an AC signal output). In other examples, system 400 may be implemented as a rectifier, which is configured to receive an input signal (e.g., an AC signal) and generate an output signal (e.g., a DC signal output).

[0059] In various embodiments, the voltage generator 406 may be characterized by a first voltage, denoted as VRECT. For example, the first voltage is set to twice the target voltage (e.g., 5V, 10V, etc.). This means that if the first voltage is VRECT, then the target voltage will be VRECT / 2. The second output 415 may be configured to output a first output signal, which may be characterized by a target voltage, depending on the application. In various embodiments, the first voltage of the voltage generator 406 may be determined or adjusted based on the target voltage.

[0060] In some embodiments, the operation of system 400 relies on systematic and coordinated switching of first switch 404 and second switch 405 according to certain conditions. For example, circuit 401 is configured to control the operation of first switch 404, second switch 405, and third switch 412. Circuit 410, labeled ACx_DIN, may include circuitry and / or other components, such as programmable logic, a microcontroller, and / or software, and may send control signals to first switch 404 and second switch 405 to adjust their operation. In some cases, a level shifter circuit (e.g., labeled Figure 4 LS in the first circuit 401 may be coupled to the first switch 404. The level shifter circuit is configured to translate the voltage level, ensuring that the first switch 404 is driven with the appropriate voltage level to optimize its operation. After startup, the first circuit 401 may send a first signal to the first input 402 to activate the transition of the first switch 404 to its on state. At the same time, the first circuit 401 may send a second signal to the second input 403 to keep the second switch 405 in its off state while the first switch is actively turned on. In a tightly coordinated sequence, the third switch 412 may be turned on after the on transition of the first switch 404. For example, the first circuit 401 may send a third signal to turn on the third switch 412 in coordination with the on transition of the first switch 404. In some cases, a time delay may be imposed on the activation of the third switch 412, ensuring that it switches to its on state only after the first switch 404 has achieved full activation. In some embodiments, the third switch 412 may include, but is not limited to, a field effect transistor (FET), such as a metal oxide semiconductor FET (MOSFET), a bipolar junction transistor (BJT), a thyristor, or other type of transistor, or other type of switch. For example, the third switch 412 may be implemented as a PMOS (e.g., back-to-back PMOS), an LDPMOS, and / or the like. In some cases, a level shifter circuit may be coupled to the third switch 412. The level shifter circuit is configured to translate voltage levels, ensuring that the third switch 412 is driven with an appropriate voltage level to optimize its operation.

[0061] Due to the voltage dividing action of the first resistor 407 and the second resistor 408, the second voltage at the first output can be a fraction of the first voltage at the voltage generator 106. For example, the second voltage ACx_BIAS can be less than or equal to half of the first voltage VRECT. In an example, ACx_BIAS is half the value of VRECT (e.g., VRECT / 2). The first side of the first capacitor 414 can be coupled to the pin output ACx.

[0062] During an operation cycle in which the first switch 404 and the third switch 412 are turned on and the second switch 405 is turned off, the first side of the first capacitor 414 is charged to the value of VRECT. At the same time, the second side of the first capacitor 414 connected to the first output of the buffer 411 through the third switch 412 is charged to half the value of VRECT (e.g., VRECT / 2). This systematic charge distribution ensures that the DC bias across the first capacitor 414 is maintained at VRECT / 2. The DC bias subtraction at the first capacitor 414 is an important step in generating a bipolar signal. When the first switch 404 and the third switch 412 are turned off and the second switch 405 is turned on, the first capacitor 414 (e.g., the second side of the first capacitor 414) is discharged to a negative voltage (e.g., -VRECT / 2), which is then used to offset the positive voltage from the unipolar input signal. This process effectively removes the DC component from the input signal to generate the first output signal second output 415. By using the first capacitor 414 to perform DC subtraction, DC leakage can be effectively minimized, generating a bipolar signal with a reduced DC component.

[0063] In various implementations, when the system 400 is idle (e.g., both the first switch 404 and the second switch 405 are off), the fourth switch 413 may be turned on to normalize the first output signal to 0 volts. In some embodiments, the fourth switch 413 may include, but is not limited to, a field effect transistor (FET), such as a metal oxide semiconductor FET (MOSFET), a bipolar junction transistor (BJT), a thyristor, or other type of transistor, or other type of switch. For example, the fourth switch 413 may be implemented as a PMOS (e.g., back-to-back PMOS), an LDPMOS, and / or the like. In some cases, a level shifter circuit may be coupled to the fourth switch 413. The level shifter circuit is configured to translate the voltage level, ensuring that the fourth switch 413 is driven with the appropriate voltage level to optimize its operation.

[0064] Figure 55 is a circuit diagram illustrating a power conversion system 500 according to an embodiment of the present technology. This figure merely provides an example, which should not overly limit the scope of the claims. A person of ordinary skill in the art will recognize many variations, substitutions, and modifications. As previously mentioned, system 500 may be implemented as any type of power conversion system, such as a rectifier, an inverter, or other bidirectional converter. As with system 400, system 500 may include at least one of a first circuit 501, a first switch 504, a second switch 505, a voltage generator 506, a first resistor 507, a second resistor 508, a first ground terminal 510, a second ground terminal 509, a buffer 511, a third switch 512, a first capacitor 514, a fourth switch 513, and a second output 515. For example, system 500 may be implemented as an inverter, which is configured to receive an input signal (e.g., a DC signal) and generate an output signal (e.g., an AC signal output). In other examples, system 500 can be implemented as a rectifier configured to receive an input signal (eg, an AC signal) and generate an output signal (eg, a DC signal output).

[0065] In various embodiments, the voltage generator 506 may be characterized by a first voltage, denoted as VRECT. For example, the first voltage is set to twice the target voltage (e.g., 5V, 10V, etc.). This means that if the first voltage is VRECT, then the target voltage will be VRECT / 2. The second output 515 may be configured to output a first output signal, which may be characterized by a target voltage, depending on the application. In various embodiments, the first voltage of the voltage generator 506 may be determined or adjusted based on the target voltage.

[0066] In some embodiments, the operation of the system 500 relies on the systematic and coordinated switching of the first switch 504 and the second switch 505 according to specific conditions. For example, the circuit 501 is configured to control the operation of the first switch 504, the second switch 505, and the third switch 512. The circuit 510, labeled ACx_DIN, may include circuit systems and / or other components, such as programmable logic, microcontrollers, and / or software, and may send control signals to the first switch 104 and the second switch 105 to regulate their operation. After startup, the first circuit 501 may send a first signal to the first input 502 to activate the transition of the first switch 504 to its on state. At the same time, the first circuit 501 may send a second signal to the second input 503 to keep the second switch 505 in its off state while the first switch is actively turned on. In a tightly coordinated sequence, the third switch 512 may be turned on after the on transition of the first switch 504. For example, the first circuit 501 may send a third signal to turn on the third switch 512 in coordination with the on transition of the first switch 504. In some cases, a time delay may be imposed on the activation of the third switch 512, ensuring that it switches to its on state only after the first switch 504 has achieved full activation. In some embodiments, the third switch 512 may include, but is not limited to, a field effect transistor (FET), such as a metal oxide semiconductor FET (MOSFET), a bipolar junction transistor (BJT), a thyristor, or other type of transistor, or other type of switch. For example, the third switch 512 may be implemented as a PMOS (e.g., back-to-back PMOS), an LDPMOS, and / or the like.

[0067] Due to the voltage dividing action of the first resistor 507 and the second resistor 508, the second voltage at the first output can be a fraction of the first voltage at the voltage generator 106. For example, the second voltage ACx_BIAS can be less than or equal to half of the first voltage VRECT. In an example, ACx_BIAS is half the value of VRECT (e.g., VRECT / 2). The first side of the first capacitor 514 can be coupled to the pin output ACx.

[0068] During an operation cycle in which the first switch 504 and the third switch 512 are turned on and the second switch 505 is turned off, the first side of the first capacitor 514 is charged to the value of VRECT. At the same time, the second side of the first capacitor 514 connected to the first output of the buffer 511 through the third switch 512 is charged to half the value of VRECT (e.g., VRECT / 2). This systematic charge distribution ensures that the DC bias across the first capacitor 514 is maintained at VRECT / 2. The DC bias subtraction at the first capacitor 514 is an important step in generating a bipolar signal. When the first switch 504 and the third switch 512 are turned off and the second switch 505 is turned on, the first capacitor 514 (e.g., the second side of the first capacitor 514) is discharged to a negative voltage (e.g., -VRECT / 2), which is then used to offset the positive voltage from the unipolar input signal. This process effectively removes the DC component from the input signal to generate the first output signal second output 515. By using the first capacitor 514 to perform DC subtraction, DC leakage can be effectively minimized, generating a bipolar signal with a reduced DC component.

[0069] In various implementations, when the system 500 is idle (e.g., both the first switch 504 and the second switch 505 are off), the fourth switch 513 may be turned on to normalize the first output signal to 0 volts. In some embodiments, the fourth switch 513 may include, but is not limited to, a field effect transistor (FET), such as a metal oxide semiconductor FET (MOSFET), a bipolar junction transistor (BJT), a thyristor, or other type of transistor, or other type of switch. For example, the fourth switch 513 may be implemented as a PMOS (e.g., back-to-back PMOS), an LDPMOS, and / or the like.

[0070] Although the above is a complete description of specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present technology as defined by the appended claims.

Claims

1. A device comprising: a first switch comprising a first input configured to receive a first signal; a voltage generator coupled to the first switch, the voltage generator being characterized by a first voltage; a second switch coupled to the first switch, the second switch comprising a second input configured to receive a second signal; a first ground terminal coupled to the second switch; a first resistor coupled to the first switch and the voltage generator, the first resistor being characterized by a first resistance; a second resistor coupled to the first resistor, the second resistor being characterized by a second resistance; a buffer comprising a third input coupled to the first resistor and the second resistor and a first output characterized by a second voltage; a third switch coupled to the first output; a first capacitor coupled to the first switch and the third switch; and A second output is coupled to the third switch and the first capacitor.

2. The device of claim 1, further comprising a first circuit coupled to the first switch and the second switch, the first circuit configured to send the first signal to the first input and to send the second signal to the second input.

3. The device according to claim 1, wherein: The second output is configured to output a first output signal; and The buffer further includes a fourth input coupled to the first output. The device of claim 3 , wherein the first output signal comprises a positive signal and a negative signal.

5. The device of claim 1, further comprising a fourth switch coupled to the third switch and the first capacitor. 6 . The apparatus of claim 1 , wherein the first switch comprises a complementary metal oxide semiconductor (CMOS) or a bipolar junction transistor (BJT).

7. The apparatus of claim 1, wherein the first switch comprises a gate coupled to the first input.

8. The device of claim 1, wherein a ratio of the first resistor to the second resistor is less than 1.1:

1.

9. The device of claim 1, wherein the second voltage is less than or equal to half of the first voltage. 10 . The apparatus of claim 1 , wherein the third switch comprises a p-channel metal oxide semiconductor (PMOS) or a laterally diffused metal oxide semiconductor (LDMOS).

11. An apparatus comprising: a first switch comprising a first input configured to receive a first signal; a voltage generator coupled to the first switch, the voltage generator being characterized by a first voltage; a second switch coupled to the first switch, the second switch comprising a second input configured to receive a second signal; a first ground terminal coupled to the second switch; a first resistor coupled to the first switch and the voltage generator; a second resistor coupled to the first resistor; a buffer comprising a third input coupled to the first resistor and the second resistor and a first output characterized by a second voltage; a third switch coupled to the first output; a first capacitor coupled to the first switch and the third switch; and A second output is coupled to the third switch and the first capacitor.

12. The device of claim 11, further comprising a first circuit coupled to the first switch and the second switch, the first circuit configured to send the first signal to the first input and send the second signal to the second input to control switching of the first switch and the second switch.

13. The device of claim 11, wherein the second output is configured to output a first output signal.

14. The device of claim 11, further comprising a fourth switch coupled to the third switch and the first capacitor.

15. The device of claim 11, wherein the second voltage is less than or equal to half of the first voltage.

16. The device of claim 11, further comprising a second ground terminal coupled to the second resistor.

17. An apparatus comprising: a first switch comprising a first input configured to receive a first signal; a voltage generator coupled to the first switch, the voltage generator being characterized by a first voltage; a second switch coupled to the first switch, the second switch comprising a second input configured to receive a second signal; a first ground terminal coupled to the second switch; a first resistor coupled to the first switch and the voltage generator, the first resistor being characterized by a first resistance; a second resistor coupled to the first resistor, the second resistor being characterized by a second resistance; a second ground terminal coupled to the second resistor; a buffer comprising a third input coupled to the first resistor and the second resistor and a first output characterized by a second voltage; a third switch coupled to the first output; a first capacitor coupled to the first switch and the third switch; and A second output is coupled to the third switch and the first capacitor.

18. The device of claim 17, further comprising a first circuit coupled to the first switch, the first circuit configured to send the first signal to the first input.

19. The device of claim 17, wherein a ratio of the first resistor to the second resistor is less than 1.1:

1.

20. The device of claim 17, further comprising a fourth switch coupled to the third switch and the first capacitor.

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