Multi-level buck converter

Abstract

The invention discloses a multi-level buck converter. The multi-level buck converter comprises a plurality of switches, an inductor, a flying capacitor and a control circuit. The plurality of switches are coupled between an input terminal and a ground terminal, and the input terminal has an input voltage. The inductor is coupled between the plurality of switches and the output end and is used for generating an inductive current signal. The flying capacitor is coupled to the plurality of switches for generating a flying capacitor voltage. The control circuit is coupled to the output end and the plurality of switches and is used for generating a plurality of switching signals according to the feedback voltage and the inductive current signal. The control circuit operates in a valley current mode with dual slope compensation.

Description

Technical Field

[0001] The present invention provides a buck converter, and more particularly, relates to a multi-level buck converter operating in a valley current mode and having dual slope compensation. Background Art

[0002] A multi-level buck converter is a step-down DC converter that can handle high input voltages and achieve high efficiency. It consists of multiple capacitors and switches that can generate voltage levels between the input and output. The voltage across each switch is lower than the input voltage, which reduces switching losses and stress on semiconductors. The output voltage is regulated by controlling the duty cycle of each switch. Multi-level buck converters can also use small inductors and output filters, thereby reducing the size and weight of the converter. A multi-level buck converter can be a three-level buck converter, which includes four capacitors and four switches. A three-level buck converter can generate three levels: input, output, and half of the input, and capacitor voltage balance control ensures that each capacitor maintains its desired level.

[0003] Multi-level buck converters can be implemented using eGaN FETs, which have lower on-resistance and faster switching speeds than traditional metal oxide semiconductor field effect transistors (MOSFETs), further improving converter efficiency and power density.

[0004] Early developments in multilevel buck converters include: (1) “Three-Level Buck Converter for RF Power Amplifier Envelope Tracking,” presented at the 2005 IEEE Applied Power Electronics Conference and Expo; (2) “0.4V-1V 0.2A / mm2 70% Efficiency 500MHz Fully Integrated Digitally Controlled Three-Level Buck Regulator in 22nm Triple-Gate Complementary Metal Oxide Semiconductor (CMOS) Package with On-Chip High-Density MIM Capacitors,” presented at the IEEE Custom Integrated Circuits Conference (CICC), September 28-30, 2015; (3) “50MHz 5V 3W 90% Efficiency Three-Level Buck Converter with On-the-Fly Calibration and Wide Output Range for Fast DVS in 65nm Complementary Metal Oxide Semiconductor (CMOS),” presented at the IEEE VLSI Circuits Symposium, June 15-17, 2016; and (4) U.S. Patent 9,866,113: “Multilevel Buck Converter with Flying Capacitors and Charge Pump.”

[0005] However, these early inventions have significant disadvantages, such as complex circuits for capacitor voltage balancing and slow response time of the balancing loop. Another problem is that when the duty cycle of the switching signal fluctuates around 50% (i.e., less than 50% to greater than 50% and vice versa), instability will occur. This situation is usually caused by peak current mode control, so a solution is needed to solve these problems. Summary of the invention

[0006] An embodiment provides a multi-level buck converter, including a plurality of switches, an inductor, a flying capacitor, and a control circuit, wherein the plurality of switches are coupled between an input terminal and a ground terminal, and the input terminal has an input voltage. The inductor is coupled between the plurality of switches and the output terminal for generating an inductor current signal. The flying capacitor is coupled to the plurality of switches for generating a flying capacitor voltage. The control circuit couples the output terminal and the plurality of switches for generating a plurality of switch signals according to a feedback voltage and an inductor current signal. The control circuit operates in a valley current mode with dual slope compensation.

[0007] Another embodiment provides a multi-level buck converter, including multiple switches, an inductor, a flying capacitor, a control circuit and a VCF compensation circuit. Multiple switches are coupled between an input terminal and ground, and the input terminal has an input voltage. The inductor is coupled between the multiple switches and the output terminal to generate an inductor current signal. The flying capacitor is coupled to the multiple switches to generate a flying capacitor voltage. The control circuit couples the output terminal and the multiple switches to generate multiple switch signals based on the feedback voltage and the inductor current signal. The control circuit operates in a valley current mode with dual slope compensation. The VCF compensation circuit is coupled to the control circuit to generate a duty cycle compensation signal based on the input voltage and the flying capacitor voltage, and the duty cycle compensation signal balances the flying capacitor voltage.

[0008] Another embodiment provides a multi-level buck converter, including a first switch, a second switch, a third switch and a fourth switch, an inductor, a flying capacitor, an error amplifier, a first summing module, a second summing module, a third summing module, a first comparator, a second comparator, a first trigger, a second trigger, a first buffer, a second buffer, a third buffer and a fourth buffer. The first switch includes a first end coupled to an input end, a second end and a control end. The second switch includes a first end coupled to a second end of the first switch, a second end and a control end. The third switch includes a first end coupled to a second end of the second switch, a second end and a control end. The fourth switch includes a first end coupled to a second end of the third switch, a second end coupled to a ground end and a control end. The inductor is coupled between the second end of the second switch and an output end to generate an inductor current signal. The flying capacitor is coupled between the second end of the first switch and the second end of the third switch to generate a flying capacitor voltage. The error amplifier includes an inverting end coupled to a feedback end to receive a feedback voltage, a non-phase end for receiving a reference voltage, and an output end for outputting an error amplified voltage. The first summing module is coupled to the output end of the error amplifier, and is used to generate a first slope compensation signal according to the first ramp signal and the error amplified voltage. The second summing module is coupled to the output end of the error amplifier, and is used to generate a second slope compensation signal according to the second ramp signal and the error amplified voltage. The third summing module is coupled to the inductor, and is used to generate an inductor summing signal according to the inductor current signal and the bias voltage. The first comparator includes an output end coupled to the inverting end of the third summing module, coupled to the non-phase end of the first summing module, and used to generate a first pulse width modulation (PWM) signal according to the first slope compensation signal and the inductor summing signal. The second comparator includes an output end coupled to the inverting end of the third summing module, coupled to the non-phase end of the second summing module, and used to generate a second pulse width modulation signal according to the second slope compensation signal and the inductor summing signal. The first trigger includes: a set terminal coupled to the output terminal of the first comparator; a reset terminal for receiving a first clock signal; an output terminal coupled to the control terminal of the first switch for outputting the first switch signal; and an inverting output terminal coupled to the control terminal of the fourth switch for outputting the fourth switch signal. The second trigger includes: a set terminal coupled to the output terminal of the second comparator; a reset terminal for receiving a second clock signal; an output terminal coupled to the control terminal of the second switch for outputting the second switch signal; and an inverting output terminal coupled to the control terminal of the third switch for outputting the third switch signal. The first buffer is coupled between the control terminal of the first switch and the output terminal of the first trigger. The second buffer is coupled between the control terminal of the second switch and the output terminal of the second trigger. The third buffer is coupled between the control terminal of the third switch and the inverting output terminal of the second trigger. The fourth buffer is coupled between the control terminal of the fourth switch and the inverting output terminal of the first trigger. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 4 is a circuit diagram of a multi-level buck converter according to an embodiment of the present invention.

[0010] Figure 2 For the production of Figure 1 Circuit diagram of the inductor current signal.

[0011] Figure 3 for Figure 1 Operation waveforms of a multi-level buck converter.

[0012] Figure 4 for Figure 1 Another operating waveform diagram of the multi-level buck converter.

[0013] Figure 5 for Figure 1 Another operating waveform diagram of the multi-level buck converter.

[0014] Figure 6 for Figure 1 Another operating waveform diagram of the multi-level buck converter.

[0015] Figure 7 FIG. 4 is a circuit diagram of a multi-level buck converter according to another embodiment of the present invention.

[0016]

Explanation of symbols

[0017] 1, 2: Multi-level buck converter

[0018] 100: Control circuit

[0019] 10, 20, 30, 40: switch

[0020] 50: Flying capacitor

[0021] 60: Inductor

[0022] IN: Input terminal

[0023] GND: Ground terminal

[0024] VIN: Input voltage

[0025] OUT: Output terminal

[0026] ViL: Inductor current signal

[0027] VCF: Flying capacitor voltage

[0028] VF: Feedback voltage

[0029] S1-S4: switch signal

[0030] SX: Switching Node

[0031] 90: Error amplifier

[0032] 110, 120, 180: summation module

[0033] 150, 160: Comparator

[0034] 155, 165: Trigger

[0035] FB: Feedback terminal

[0036] VR: Reference voltage

[0037] VEA: Error amplifier voltage

[0038] RMP1, RMP2: Ramp signal

[0039] XA, XB: Slope compensation signal

[0040] VB: Bias voltage

[0041] VI: Inductance summation signal

[0042] PWM1, PWM2: pulse width modulation signal

[0043] CK1, CK2: clock signal

[0044] 15, 25, 35, 45: Buffer

[0045] 80, 85: Resistance

[0046] 70: Capacitor

[0047] VO: Output voltage

[0048] IO: output current

[0049] VX: Voltage

[0050] VGND: Ground reference voltage

[0051] iL1: Inductor current

[0052] DCR: Parasitic resistance

[0053] 210: Resistance

[0054] 215: Capacitor

[0055] 230: Differential Amplifier

[0056] t0-t4: time

[0057] Tsw: switching cycle

[0058] 200:VCF compensation circuit

[0059] VD: Voltage difference

[0060] VDT: Duty cycle compensation signal

[0061] 210: Subtraction module

[0062] 250: Gain adjustment module DETAILED DESCRIPTION

[0063] For the purpose of describing the innovative aspects of the present invention, the following description is directed to a specific embodiment. However, those skilled in the art will appreciate that the teachings herein can be applied in a variety of different ways. The present invention solves the above limitations through an innovative method of valley current mode control with dual slope compensation. This method simplifies the balancing process of the flying capacitor and eliminates the instability that occurs when the duty cycle of the switching signal deviates from 50%.

[0064] According to the present invention, "valley current mode (VCM) control" refers to a type of current mode control used in a buck converter. In valley current mode control, the duty cycle of the switch can be determined by the valley value of the inductor current waveform instead of the peak value, which has multiple advantages over peak current mode control, such as improving the dynamic response time, reducing the sensitivity to load changes, and reducing the occurrence of subharmonic oscillations. However, for valley current mode control, when the duty cycle deviates from 50%, subharmonic oscillations may still occur, so slope compensation equivalent to the rising slope of the inductor current is required.

[0065] Also in accordance with the present invention, "slope compensation" refers to a technique for improving the stability and performance of a current mode controlled buck converter, and can be applied to buck converters with duty cycles that deviate from 50%. When slope compensation is used, a resistor is added in series with the inductor. The voltage across this resistor is accumulated over a fixed period of time, and the result is subtracted from the reference voltage. This effectively shifts the peak of the inductor current waveform to the left, making the converter more stable. Since the slope of the inductor current waveform is not affected by the load current, slope compensation can also effectively reduce the sensitivity of the buck converter to load changes.

[0066] This specification describes some embodiments of the present invention by way of example and with the aid of the accompanying drawings, and now with specific reference to the accompanying drawings in detail, the details shown are by way of example and are only for the purpose of illustrative discussion of selected embodiments of the present invention, and are intended to provide a useful and easy to understand description of the principles and concepts of the present invention. Therefore, no attempt is made to show more detailed structural details of the present invention than is necessary for a basic understanding of the present invention, and the description in conjunction with the accompanying drawings can enable those skilled in the art to understand how to implement several forms of the present invention in practice.

[0067] Figure 11 is a circuit diagram of a multi-level buck converter 1 according to an embodiment of the present invention. The multi-level buck converter 1 includes a plurality of switches 10, 20, 30, 40, a flying capacitor 50, an inductor 60 and a control circuit 100. The switches 10, 20, 30 and 40 are coupled between an input terminal IN and a ground terminal GND. The input terminal IN has an input voltage VIN. The inductor 60 is coupled between the switches 10, 20, 30, 40 and an output terminal OUT for generating an inductor current signal ViL. The flying capacitor 50 is coupled to the switches 10, 20, 30 and 40 for generating a flying capacitor voltage VCF. The control circuit 100 is coupled to the output terminal OUT and a plurality of switches 10, 20, 30, 40 for generating a plurality of switch signals S1-S4 according to a feedback voltage VF and an inductor current signal ViL. The control circuit 100 operates in a valley current mode with dual slope compensation. The flying capacitor voltage VCF is self-balanced at approximately half of the input voltage VIN.

[0068] The first switch 10 includes a first end, a second end, and a control end coupled to the input terminal IN. The second switch 20 includes a first end, a second end, and a control end coupled to the second end of the first switch 10. The third switch 30 includes a first end, a second end, and a control end coupled to the second end of the second switch 20. The fourth switch 40 includes a first end coupled to the second end of the third switch 30, a second end coupled to the ground terminal GND, and a control end. The inductor 60 is coupled between the switch node SX and the output terminal OUT. The flying capacitor 50 is coupled between the second end of the first switch 10 and the second end of the third switch 30.

[0069] The control circuit 100 may include an error amplifier 90, summing modules 110, 120 and 180, comparators 150 and 160, and triggers 155 and 165. The error amplifier 90 may include: an inverting terminal coupled to the feedback terminal FB for receiving a feedback voltage VF; a non-phase terminal for receiving a reference voltage VR; and an output terminal for outputting an error amplified voltage VEA. The summing module 110 may be coupled to the output terminal of the error amplifier 90 to generate a first slope compensation signal XA according to the first ramp signal RMP1 and the error amplified voltage VEA. The summing module 120 may be coupled to the output terminal of the error amplifier 90 to generate a second slope compensation signal XB according to the second ramp signal RMP2 and the error amplified voltage VEA. The summing module 180 may be coupled to the inductor 60 to generate an inductor summation signal VI according to the inductor current signal ViL and the bias voltage VB. The comparator 150 may include an output terminal coupled to the inverting terminal of the summing module 180, coupled to the non-inverting terminal of the summing module 110, and used to generate a first pulse-width modulation (PWM) signal PWM1 according to the slope compensation signal XA and the inductance sum signal VI. The comparator 160 may include an output terminal coupled to the inverting terminal of the summing module 180, coupled to the non-inverting terminal of the summing module 120, and used to generate a second pulse-width modulation signal PWM2 according to the second slope compensation signal XB and the inductance sum signal VI. The trigger 155 may include: a set terminal coupled to the output terminal of the comparator 150; a reset terminal for receiving the first clock signal CK1; an output terminal coupled to the control terminal of the first switch 10, for outputting the first switch signal S1; and an inverting output terminal coupled to the control terminal of the fourth switch 40, for outputting the fourth switch signal S4. The trigger 165 may include: a set end coupled to the output end of the comparator 160; a reset end for receiving the second clock signal CK2; an output end coupled to the control end of the second switch 20 for outputting the second switch signal S2; and an inverting output end coupled to the control end of the third switch 30 for outputting the third switch signal S3.

[0070] It should be understood that the summing modules 110 , 120 , and 180 may be circuits for adding analog signals and / or digital signals or equivalent signals thereof.

[0071] The first buffer 15 may be coupled between the control terminal of the first switch 10 and the output terminal of the flip-flop 155. The second buffer 25 may be coupled between the control terminal of the second switch 20 and the output terminal of the flip-flop 165. The third buffer 35 may be coupled between the control terminal of the third switch 30 and the inverting output terminal of the flip-flop 165. The fourth buffer 45 may be coupled between the control terminal of the fourth switch 40 and the inverting output terminal of the flip-flop 155.

[0072] The resistor 80 may be coupled between the output terminal OUT and the inverting terminal of the error amplifier 90. Another resistor 85 may be coupled between the ground terminal GND and the inverting terminal of the error amplifier 90. The capacitor 70 may be coupled between the output terminal OUT and the ground terminal GND.

[0073] The switches 10, 20, 30 and 40 are equipped with duty cycle control to generate the output voltage VO via the inductor 60. The flying capacitor 50 is used in the multi-level buck converter 1 to generate the voltage level. Since the flying capacitor 50 is not connected to the ground terminal GND or any other reference voltage, the flying capacitor voltage VCF (i.e., the voltage across the flying capacitor 50) can change rapidly according to the switching of the multi-level buck converter 1.

[0074] The first ramp signal RMP1 and the second ramp signal RMP2 are in opposite phases (ie, 180 degrees phase shift). The first ramp signal RMP1 and the second ramp signal RMP2 may both have sawtooth waves. The amplitude of the first ramp signal RMP1 may be substantially the same as the amplitude of the second ramp signal RMP2.

[0075] The first slope compensation signal XA is generated by adding the first ramp signal RMP1 to the error amplifier voltage VEA, the second slope compensation signal XB is generated by adding the second ramp signal RMP2 to the error amplifier voltage VEA, and the inductor sum signal VI is generated by adding the inductor current signal ViL to the bias voltage VB.

[0076] The comparator 150 compares the inductance sum signal VI with the first slope compensation signal XA to generate a first pulse width modulation signal PWM1, and the first pulse width modulation signal PWM1 can control switches 10 and 40 through a trigger 155, that is, switches 10 and 40 can be controlled by switch signals S1 and S4, respectively. Similarly, the comparator 160 compares the inductance sum signal VI with the second slope compensation signal XB to generate a second pulse width modulation signal PWM2, and the second pulse width modulation signal PWM2 can control switches 20 and 30 through a trigger 165, that is, switches 20 and 30 can be controlled by switch signals S2 and S3, respectively.

[0077] When the inductor current signal ViL is lower than the first slope compensation signal XA, the first switch 10 is turned on by the first switch signal S1, and when the inductor current signal ViL is lower than the second slope compensation signal XB, the second switch 20 is turned on by the second switch signal S2. The first switch signal S1 and the second switch signal S2 can be reset by the clock signals CK1 and CK2 to turn off the first switch 10 and the second switch 20, respectively.

[0078] The control circuit 100 can operate in a valley current mode with dual slope compensation. The clock signals CK1 and CK2 can determine the switching frequency of the multi-level buck converter 1. The ramp signals RMP1 and RMP2 are synchronized by the clock signals CK1 and CK2, respectively. The clock signals CK1 and CK2 have the same fixed frequency.

[0079] When the first switch 10 and the third switch 30 are turned on, the charging current can flow from the input terminal IN to the output terminal OUT through the first switch 10, the flying capacitor 50, the third switch 30 and the inductor 60. When the second switch 20 and the fourth switch 40 are turned on, the discharging current can flow from the flying capacitor 50 to the output terminal OUT through the second switch 20 and the inductor 60. In order to make the magnitude of the charging current substantially equal to the magnitude of the discharging current, the flying capacitor voltage VCF needs to be balanced at half of the input voltage VIN (i.e., VIN / 2).

[0080] Figure 2 For the production of Figure 1 Schematic diagram of a circuit for generating an inductor current signal ViL in FIG. The inductor 60 has an inductance value L1 and a parasitic resistance DCR. The resistor 210 with a resistance value Rx is coupled between the switch node SX and the non-inverting terminal of the differential amplifier 230. The capacitor 215 with a capacitance value Cx is coupled between the non-inverting terminal and the inverting terminal of the differential amplifier 230.

[0081] when Figure 2 When the time constant of the RLC circuit is properly adjusted, the inductor current iL1 can be obtained from the voltage Vcx of the capacitor 215, which is also equal to the voltage Vcx of the inductor 60 (i.e., the voltage generated by the parasitic resistance DCR). The inductor current iL1 can be calculated by the following formula:

[0082]

[0083] Vcx=iL1×DCR

[0084] Therefore, the differential amplifier 230 can generate the inductor current signal ViL based on the cross voltage Vcx of the capacitor 215 .

[0085] Figure 3 for Figure 1The operating waveform diagram of the multi-level buck converter 1. This waveform diagram illustrates the case where the duty cycles of the switching signals S1 and S2 are less than 50%. In this case, the output voltage VO is less than half of the input voltage VIN (i.e., VO < VIN / 2). The first clock signal CK1 and the second clock signal CK2 are in antiphase (i.e., 180-degree phase shift). The ramp signals RMP1 and RMP2 are generated according to the clock signals CK1 and CK2 respectively, so the ramp signals RMP1 and RMP2 are also in antiphase. The slope compensation signals XA and XB are the ramp signals RMP1 and RMP2 boosted by the error amplification voltage VEA, so the slope compensation signals XA and XB have the same waveforms as the ramp signals RMP1 and RMP2 respectively.

[0086] At time t0, the second clock signal CK2 resets the flip-flop 165, causing the second switching signal S2 to be at a low level. The first slope compensation signal XA is lower than the inductor summing signal VI, causing the first pulse width modulation PWM1 generated by the comparator 150 to be at a low level. Similarly, the second slope compensation signal XB is lower than the inductor summing signal VI, causing the second pulse width modulation PWM2 generated by the comparator 160 to be at a low level. Therefore, the first switching signal S1 generated by the flip-flop 155 and the second switching signal S2 generated by the flip-flop 165 are also at low levels. Between time t0 and t1, the slope compensation signals XA and XB rise with the ramp signals RMP1 and RMP2.

[0087] At time t1, the first slope compensation signal XA exceeds the inductor summing signal VI, pulling the first pulse width modulation signal PWM1 high. Therefore, the first switching signal S1 is also pulled high, turning on the first switch 10. At the same time, the third switching signal S3 remains high, keeping the third switch 30 on. Therefore, the voltage VX at the switching node SX is pulled high. Between time t1 and t2, since switches 10 and 30 are on and switches 20 and 40 are off, current can flow out from the input terminal IN, through the first switch 10, the flying capacitor VCF, the third switch 30, and the inductor 60 to the output terminal OUT. Therefore, both the inductor current signal ViL and the inductor summing signal VI gradually increase.

[0088] At time t2, the first clock signal CK1 resets the trigger 155, so that the first switch signal S1 is pulled down to a low level. The first slope compensation signal XA is pulled down to cross the inductance sum signal VI, so that the first pulse width modulation signal PWM1 generated by the comparator 150 is at a low level. The second slope compensation signal XB has not yet reached the inductance sum signal VI, resulting in the second pulse width modulation signal PWM2 generated by the comparator 160 remaining at a low level. Therefore, the first switch signal S1 generated by the trigger 155 and the second switch signal S2 generated by the trigger 165 are also at a low level. Therefore, the first switch 10 and the second switch 20 are turned off, and the third switch 30 and the fourth switch 40 are turned on. The voltage VX at the switch node SX is pulled to a high level. Therefore, between time t2 and t3, the inductor current can flow from the inductor 60 through the third switch 30 and the fourth switch 40 to the ground terminal GND. Therefore, the inductor current signal ViL and the inductor sum signal VI will gradually decrease, and the slope compensation signals XA and XB will increase again along with the ramp signals RMP1 and RMP2.

[0089] At time t3, the second slope compensation signal XB exceeds the inductor sum signal VI, causing the second pulse width modulation signal PWM2 to be pulled up to a high level. Therefore, the second switch signal S2 is also pulled up to a high level, causing the second switch 20 to be turned on. At the same time, the fourth switch signal S4 maintains a high level, so that the fourth switch 40 remains turned on. Therefore, the voltage VX at the switch node SX is pulled to a high level. Between time t3 and t4, since switches 20 and 40 are turned on and switches 10 and 30 are turned off, current can flow from the flying capacitor VCF through the second switch 20 and the inductor 60 to the output terminal OUT. As a result, the inductor current signal ViL and the inductor sum signal VI will gradually rise.

[0090] At time t4, the second clock signal CK2 resets the trigger 165, so that the second switch signal S2 is at a low level. The first slope compensation signal XA is lower than the inductance sum signal VI, so that the first pulse width modulation signal PWM1 generated by the comparator 150 is at a low level. Similarly, the second slope compensation signal XB is lower than the inductance sum signal VI, so that the second pulse width modulation signal PWM2 generated by the comparator 160 is at a low level. Therefore, the first switch signal S1 generated by the trigger 155 and the second switch signal S2 generated by the trigger 165 are also at a low level.

[0091] The time t0 to t4 is the switching period Tsw. The operation of the multi-level buck converter 1 is continuously repeated in the same manner as the switching period Tsw, so it is not described again here. It should also be understood that since the waveforms of the inductor current iL1 and the inductor sum signal VI are substantially the same, they are not discussed separately here.

[0092] like Figure 3 As shown, the high level of the voltage VX between time t1 and t2 is substantially equal to the input voltage VIN minus the flying capacitor voltage VCF, which is substantially equal to half of the input voltage VIN (VIN-VCF=VIN / 2). The high level voltage VX between time t3 and t4 is substantially equal to the flying capacitor voltage VCF, and is also substantially equal to half of the input voltage VIN (VCF=VIN / 2). The low level voltage VX between time t2 and t3 is substantially equal to the ground reference voltage VGND. Therefore, through the above operation, the flying capacitor voltage VCF can be properly balanced at half of the input voltage VIN (i.e., VIN / 2).

[0093] Figure 4 for Figure 1 1 is another operation waveform diagram of the multi-level buck converter 1. This waveform diagram illustrates the case where the duty cycle of the switching signals S1 and S2 is greater than 50%. In this case, the output voltage VO is greater than half of the input voltage VIN (i.e., VO>Vin / 2). The first clock signal CK1 and the second clock signal CK2 are inverted (i.e., 180 degrees phase shift). The ramp signals RMP1 and RMP2 are generated according to the clock signals CK1 and CK2, respectively, so the ramp signals RMP1 and RMP2 are also inverted. The slope compensation signals XA and XB are ramp signals RMP1 and RMP2 boosted by the error amplifier voltage VEA, so the slope compensation signals XA and XB have the same waveforms as the ramp signals RMP1 and RMP2, respectively.

[0094] At time t0, the second clock signal CK2 resets the flip-flop 165, so that the second switch signal S2 is at a low level. The first switch signal S1 generated by the flip-flop 155 is at a high level. Between time t0 and t1, the slope compensation signals XA and XB rise along with the ramp signals RMP1 and RMP2.

[0095] At time t1, the second slope compensation signal XB reaches the inductor summation signal VI, causing the second pulse width modulation signal PWM2 to be pulled up to a high level, and the first switch signal S1 remains at a high level, so that the first switch 10 remains turned on; the second switch signal S2 is pulled up to a high level, causing the second switch 20 to be turned on. At the same time, the third switch signal S3 is also pulled down to a low level, so that the third switch 30 is turned off and the fourth switch 40 remains turned off. Therefore, the voltage VX at the switch node SX is pulled to a high level. Between time t1 and t2, since switches 10 and 20 are turned on and switches 30 and 40 are turned off, current can flow from the input terminal IN, through the first switch 10, the second switch 20 and the inductor 60, to the output terminal OUT. Therefore, the inductor current signal ViL and the inductor summation signal VI will gradually rise.

[0096] At time t2, the first clock signal CK1 resets the trigger 155, so that the first switch signal S1 is pulled down to a low level. The first slope compensation signal XA is pulled down to be lower than the inductance sum signal VI, so that the first pulse width modulation signal PWM1 generated by the comparator 150 is at a low level. At this time, the second slope compensation signal XB has not yet intersected with the inductance sum signal VI, so the second pulse width modulation signal PWM2 generated by the comparator 160 is still maintained at a high level. Therefore, the first switch signal S1 generated by the trigger 155 is pulled down to a low level, and the second switch signal S2 generated by the trigger 165 is maintained at a high level. Therefore, switches 10 and 30 are turned off, and switches 20 and 40 are turned on. The voltage VX at the switch node SX is pulled to a low level, so between time t2 and t3, current can flow from the flying capacitor 50 through the second switch 20 and the inductor 60 to the output terminal OUT. Therefore, the inductor current signal ViL and the inductance sum signal VI will gradually decrease. Furthermore, the slope compensation signals XA and XB rise again along with the ramp signals RMP1 and RMP2.

[0097] At time t3, the first slope compensation signal XA reaches the inductor sum signal VI, causing the first pulse width modulation signal PWM1 to be pulled up to a high level. Therefore, the first switch signal S1 is also pulled up to a high level, causing the first switch 10 to be turned on. At this time, the second switch signal S2 remains at a high level, so that the second switch 20 remains turned on. Therefore, the voltage VX at the switch node SX is pulled to a high level. Between time t3 and t4, since switches 10 and 20 are turned on and switches 30 and 40 are turned off, current can flow from the input terminal IN, through the first switch 10, the second switch 20 and the inductor 60, to the output terminal OUT. Therefore, the inductor current signal ViL and the inductor sum signal VI will gradually rise again.

[0098] At time t4, the second clock signal CK2 resets the trigger 165, so that the second switch signal S2 is pulled down to a low level. Since the first slope compensation signal XA has not yet intersected the inductance sum signal VI, the first pulse width modulation signal PWM1 generated by the comparator 150 is maintained at a high level, and therefore, the first switch signal S1 generated by the trigger 155 is maintained at a high level.

[0099] The operation of the multi-level buck converter 1 is continuously repeated in the same manner as the switching period Tsw, so it is not described again here. It should also be understood that since the waveforms of the inductor current iL1 and the inductor sum signal VI are substantially the same, they are not discussed separately here.

[0100] like Figure 4As shown, the high level voltage VX between time t1 and t2 and between time t3 and t4 is substantially equal to the input voltage VIN. The low level of the voltage VX between time t0 and t1 is substantially equal to the input voltage VIN minus the flying capacitor voltage VCF, which is substantially equal to half of the input voltage VIN (VIN-VCF=VIN / 2). The low level voltage VX between time t2 and t3 is substantially equal to the flying capacitor voltage VCF, which is substantially equal to half of the input voltage VIN (VCF=VIN / 2). Therefore, through the above operation, the flying capacitor voltage VCF can be properly balanced at half of the input voltage VIN (i.e., VIN / 2).

[0101] Figure 5 for Figure 1 Another operation waveform of the multi-level buck converter 1 in FIG. 1 is shown in FIG. 1 . In this example, the input voltage VIN is set to 48V and the output load is designed to be 2Ω. The output voltage VO can be adjusted between 0V and 40V according to the reference voltage VR. The output current IO and the inductor current iL1 change in response to the output voltage VO. Figure 5 As shown, when the multi-level buck converter 1 is operated at a 50% duty cycle (i.e., VO=24V), the inductor current iL1 has the least ripple (subharmonic). In addition, through the control circuit 100, the average flying capacitor voltage VCF (with ripple) in the multi-level buck converter 1 can be automatically balanced at half of the input voltage VIN (i.e., VCF=24V). This shows that the multi-level buck converter 1 can work normally in all ranges (i.e., from 0% to 100%).

[0102] Figure 6 for Figure 1 Another operation waveform diagram of the multi-level buck converter 1 in FIG. When the input voltage VIN varies from 20V to 80V, the output voltage VO can be stabilized at 20V. In addition, the output current IO can be adjusted and fixed at 20A, and the inductor current iL1 has a ripple that varies in response to the input voltage VIN. Through the control circuit 100, in the multi-level buck converter 1, the average flying capacitor voltage VCF (with ripple) can be automatically balanced at half of the input voltage VIN (i.e., VIN / 2). Similarly, when the multi-level buck converter 1 operates at a duty cycle of 50% (i.e., VIN=40V), the inductor current iL1 has the smallest ripple. This shows that the multi-level buck converter 1 can work normally in all ranges (i.e., from 0% to 100%). In addition, it should be noted that the ripples of the flying capacitor voltage VCF and the inductor current iL1 in the above example can be triangular waves.

[0103] Figure 7FIG. 1 is a circuit diagram of a multi-level buck converter 2 according to another embodiment of the present invention. The difference between the multi-level buck converter 1 and the multi-level buck converter 2 is that the multi-level buck converter 2 further includes a VCF compensation circuit 200 coupled to the control circuit 100. The VCF compensation circuit 200 is used to generate a duty cycle compensation signal according to the input voltage VIN and the flying capacitor voltage VCF.

[0104] The VCF compensation circuit 200 may include a subtraction module 210 and a gain adjustment module 250. The subtraction module 210 may receive half of the input voltage VIN (i.e., VIN / 2) and the flying capacitor voltage VCF, and may generate a voltage difference VD accordingly. The gain adjustment module 250 may be coupled to the subtraction module 210 to generate a duty cycle compensation signal VDT according to the voltage difference VD. The output of the gain adjustment module 250 may be coupled to the summing modules 110 and 120. It should be understood that the subtraction module 210 may be a circuit or an equivalent device for subtracting analog signals and / or digital signals. The gain adjustment module 250 may be a proportional integrator or an equivalent device.

[0105] In this embodiment, the summing module 110 can generate a first slope compensation signal XA according to the duty cycle compensation signal VDT, the first ramp signal RMP1 and the error amplified voltage VEA. The summing module 120 can generate a second slope compensation signal XB according to the inversion of the duty cycle compensation signal VDT, the second ramp signal RMP and the error amplified voltage VEA. When the voltage difference VD between the flying capacitor voltage VCF and half of the input voltage VIN (i.e., VIN / 2) exceeds the threshold, the duty cycle compensation signal VDT can be generated to fine-tune the duty cycle of the switching signals S1-S4. Therefore, the VCF compensation circuit 200 can achieve feedback stability of the multi-level buck converter 2.

[0106] Similar to the multi-level buck converter 1, the multi-level buck converter 2 includes a plurality of switches 10, 20, 30 and 40, a flying capacitor 50, an inductor 60 and a control circuit 100. The switches 10, 20, 30 and 40 are coupled between an input terminal IN and a ground terminal GND. The input terminal IN has an input voltage VIN. The inductor 60 is coupled between the switches 10, 20, 30, 40 and the output terminal OUT for generating an inductor current signal ViL. The flying capacitor 50 is coupled to the switches 10, 20, 30 and 40 for generating a flying capacitor voltage VCF. The control circuit 100 is coupled to the output terminal OUT and the plurality of switches 10, 20, 30, 40 for generating a plurality of switch signals S1-S4 according to the feedback voltage VF and the inductor current signal ViL. The control circuit 100 operates in a valley current mode with dual slope compensation. The flying capacitor voltage VCF is self-balanced at approximately half of the input voltage VIN.

[0107] The first switch 10 includes a first end, a second end, and a control end coupled to the input terminal IN. The second switch 20 includes a first end, a second end, and a control end coupled to the second end of the first switch 10. The third switch 30 includes a first end, a second end, and a control end coupled to the second end of the second switch 20. The fourth switch 40 includes a first end coupled to the second end of the third switch 30, a second end coupled to the ground terminal GND, and a control end. The inductor 60 is coupled between the switch node SX and the output terminal OUT. The flying capacitor 50 is coupled between the second end of the first switch 10 and the second end of the third switch 30.

[0108] The control circuit 100 may include an error amplifier 90, summing modules 110, 120 and 180, comparators 150 and 160, and triggers 155 and 165. The error amplifier 90 may include: an inverting terminal coupled to the feedback terminal FB for receiving a feedback voltage VF; a non-inverting terminal for receiving a reference voltage VR; and an output terminal for outputting an error amplified voltage VEA.

[0109] In this embodiment, the summing module 110 can generate a first slope compensation signal XA according to the duty cycle compensation signal VDT, the first ramp signal RMP1 and the error amplification voltage VEA. The summing module 120 can generate a second slope compensation signal XB according to the inverse of the duty cycle compensation signal VDT, the second ramp signal RMP and the error amplification voltage VEA.

[0110] The summing module 180 may be coupled to the inductor 60, and used to generate the inductor sum signal VI according to the inductor current signal ViL and the bias voltage VB. The comparator 150 may include an output terminal coupled to the inverting terminal of the summing module 180, coupled to the non-inverting terminal of the summing module 110, and used to generate the first pulse width modulation signal PWM1 according to the slope compensation signal XA and the inductor sum signal VI. The comparator 160 may include an output terminal coupled to the inverting terminal of the summing module 180, coupled to the non-inverting terminal of the summing module 120, and used to generate the second pulse width modulation signal PWM2 according to the second slope compensation signal XB and the inductor sum signal VI. The trigger 155 may include: a set terminal coupled to the output terminal of the comparator 150; a reset terminal for receiving the first clock signal CK1; an output terminal coupled to the control terminal of the first switch 10, and used to output the first switch signal S1; and an inverting output terminal coupled to the control terminal of the fourth switch 40, and used to output the fourth switch signal S4. The trigger 165 may include: a set end coupled to the output end of the comparator 160; a reset end for receiving the second clock signal CK2; an output end coupled to the control end of the second switch 20 for outputting the second switch signal S2; and an inverting output end coupled to the control end of the third switch 30 for outputting the third switch signal S3.

[0111] The first buffer 15 may be coupled between the control terminal of the first switch 10 and the output terminal of the flip-flop 155. The second buffer 25 may be coupled between the control terminal of the second switch 20 and the output terminal of the flip-flop 165. The third buffer 35 may be coupled between the control terminal of the third switch 30 and the inverting output terminal of the flip-flop 165. The fourth buffer 45 may be coupled between the control terminal of the fourth switch 40 and the inverting output terminal of the flip-flop 155.

[0112] The resistor 80 may be coupled between the output terminal OUT and the inverting terminal of the error amplifier 90. Another resistor 85 may be coupled between the ground terminal GND and the inverting terminal of the error amplifier 90. The capacitor 70 may be coupled between the output terminal OUT and the ground terminal GND.

[0113] When the voltage difference VD between the flying capacitor voltage VCF and half of the input voltage VIN (ie, VIN / 2) exceeds a threshold, a duty cycle compensation signal VDT can be generated to fine-tune the duty cycle of the switching signals S1 - S4 . Therefore, the VCF compensation circuit 200 can achieve feedback stability of the multi-level buck converter 2 .

[0114] Except for feedback stability, the operating principle of the multi-level buck converter 2 is almost the same as that of the multi-level buck converter 1. Therefore, the description will not be repeated here.

[0115] Implementations have been described in detail for reference, and examples thereof are shown in the accompanying drawings. In the above detailed description, numerous specific details have been set forth in order to provide a thorough understanding of the various described implementations. However, it will be apparent to one of ordinary skill in the art that the various described implementations may be practiced without these specific details. Otherwise well-known methods, processes, components, circuits, and networks are not described in detail herein to avoid unnecessarily obscuring implementation aspects.

[0116] The terms used in the description of the various embodiments described herein are only for describing specific embodiments and are not intended to be limiting. The singular forms "one", "an" and "the" used in the description of the various described embodiments and the attached claims also include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more related listed items. It should also be understood that the terms "include", "comprise", "include" and / or "include" are used in this specification to specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integralities, steps, operations, elements and / or components.

[0117] Additionally, in the specification and claims, the terms "coupled" and "connected" and their derivatives may be used. In some embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other, and "coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements may not be in direct contact with each other, but may still cooperate or interact with each other.

[0118] The hardware and data processing devices used to implement the various illustrative elements, logic, logic blocks, modules and circuits described in conjunction with the aspects disclosed herein can be implemented or executed with a general-purpose single-chip processor or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic element (PLD), discrete gate or transistor logic, discrete hardware elements or any combination thereof to perform the functions described herein. A general-purpose processor can be a microprocessor, or any conventional processor, controller, microcontroller or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. In some embodiments, specific processes, operations and methods can be performed by circuits of specific functions.

[0119] Various modifications of the embodiments described in the present disclosure are obvious to those of ordinary skill in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the claims are not limited to the embodiments shown herein, but are consistent with the widest scope consistent with the present disclosure, the principles and novel features disclosed herein.

[0120] In addition, various features described in this specification as being implemented separately may be implemented in combination in a single implementation. Conversely, various features described in a single implementation may also be implemented separately in multiple implementations or in any suitable sub-combination. Thus, while features may be described above as functioning in a particular combination, or even initially claimed as such, in some cases one or more features from the claimed combination may be deleted from the claimed combination, and the claimed combination may be directed to a sub-combination or a variation of a sub-combination.

[0121] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring such operations to be performed in the particular order shown or in a continuous order, or performing all the operations shown, to achieve the desired result. In addition, the accompanying drawings can schematically depict another example process in the form of a flow chart. However, other operations that are not depicted can be incorporated into the example process shown in the schematic diagram. For example, one or more additional operations can be performed before, after, simultaneously or between any of the operations shown. In some cases, multi-tasking and parallel processing may be advantageous. In addition, the separation of various system components in the described implementation should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be assembled in a single software product or packaged into multiple software products. In addition, other implementations are also within the scope of the attached claims. In some cases, the actions recorded in the claims can be performed in different orders and still achieve the desired result.

[0122] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A multi-level buck converter, comprising: A plurality of switches coupled between an input terminal and a ground terminal, the input terminal having an input voltage; an inductor, coupled between the switch and one output terminal of the multi-level buck converter, for generating an inductor current signal; A flying capacitor, coupled to the switch, for generating a flying capacitor voltage; and A control circuit, coupled to the output terminal of the multi-level buck converter and the switch, for generating a plurality of switch signals according to a feedback voltage and the inductor current signal; The control circuit operates in a valley current mode with dual slope compensation.

2. The multi-level buck converter of claim 1, wherein the flying capacitor voltage is self-balanced at approximately half of the input voltage.

3. The multi-level buck converter of claim 1 , wherein the switch comprises: The first switch comprises: A first terminal coupled to the input terminal; the second end; and A control terminal coupled to the control circuit; The second switch comprises: A first end coupled to the second end of the first switch; the second end; and A control terminal coupled to the control circuit; The third switch comprises: A first end coupled to the second end of the second switch; the second end; and A control terminal coupled to the control circuit; and The fourth switch comprises: A first end coupled to the second end of the third switch; A second terminal coupled to the ground terminal; and The control terminal is coupled to the control circuit.

4. The multi-level buck converter as claimed in claim 3, wherein the flying capacitor is coupled between the second end of the first switch and the second end of the third switch, and the inductor is coupled between the second end of the second switch and the output terminal of the multi-level buck converter.

5. The multi-level buck converter as claimed in claim 3, wherein the control circuit comprises: Error amplifier, including: An inverting terminal, coupled to the feedback terminal, for receiving the feedback voltage; Positive phase terminal, used to receive reference voltage ； and An output terminal, used for outputting an error amplified voltage; A first summing module, coupled to the output terminal of the error amplifier, for generating a first slope compensation signal according to the first ramp signal and the error amplified voltage; A second summing module, coupled to the output terminal of the error amplifier, for generating a second slope compensation signal according to a second ramp signal and the error amplified voltage; A third summing module, coupled to the inductor, for generating an inductance summing signal according to the inductor current signal and a bias voltage; A first comparator comprises: An inverting terminal coupled to the third summing module; A positive phase terminal coupled to the first summing module; and An output terminal, used for generating a first pulse width modulation signal according to the first slope compensation signal and the inductance sum signal; The second comparator comprises: An inverting terminal coupled to the third summing module; A positive phase terminal coupled to the second summing module; and An output terminal, used for generating a second pulse width modulation signal according to the second slope compensation signal and the inductance sum signal; The first trigger includes: A set terminal coupled to the output terminal of the first comparator; A reset terminal, used for receiving a first clock signal; An output terminal, coupled to the control terminal of the first switch, for outputting a first switch signal; and an inverting output terminal, coupled to the control terminal of the fourth switch, and configured to output a fourth switch signal; and The second trigger contains: a set terminal coupled to the output terminal of the second comparator; A reset terminal, used for receiving a second clock signal; An output terminal, coupled to the control terminal of the second switch, for outputting a second switch signal; and The inverting output terminal is coupled to the control terminal of the third switch and is used for outputting a third switch signal.

6. The multi-level buck converter of claim 5, wherein: The first ramp signal is in antiphase with the second ramp signal; The first ramp signal and the second ramp signal have sawtooth waves; and The amplitude of the first ramp signal is substantially the same as the amplitude of the second ramp signal.

7. The multi-level buck converter according to claim 5, further comprising: A first buffer coupled between the control terminal of the first switch and the output terminal of the first trigger; a second buffer coupled between the control terminal of the second switch and the output terminal of the second trigger; A third buffer coupled between the control terminal of the third switch and the inverting output terminal of the second trigger; and The fourth buffer is coupled between the control terminal of the fourth switch and the inverting output terminal of the first trigger.

8. The multi-level buck converter according to claim 5, further comprising: A first resistor coupled between the output terminal of the multi-level buck converter and the inverting terminal of the error amplifier; A second resistor is coupled between the ground terminal and the inverting terminal of the error amplifier; and The capacitor is coupled between the output terminal of the multi-level buck converter and the ground terminal.

9. The multi-level buck converter as claimed in claim 5, wherein when the inductor current signal is lower than the first slope compensation signal, the first switch is turned on, and when the inductor current signal is lower than the second slope compensation signal, the second switch is turned on. 10 . The multi-level buck converter as claimed in claim 5 , wherein the third switching signal is an inverted signal of the second switching signal, and the fourth switching signal is an inverted signal of the first switching signal.

11. A multi-level buck converter, comprising: A plurality of switches coupled between an input terminal and a ground terminal, the input terminal having an input voltage; an inductor, coupled between the switch and one output terminal of the multi-level buck converter, for generating an inductor current signal; A flying capacitor, coupled to the switch, for generating a flying capacitor voltage; and A control circuit, coupled to the output terminal of the multi-level buck converter and the switch, for generating a plurality of switch signals according to a feedback voltage and the inductor current signal; and A compensation circuit, coupled to the control circuit, for generating a duty cycle compensation signal according to the input voltage and the flying capacitor voltage; in: The control circuit operates in valley current mode with dual slope compensation; and The duty cycle compensation signal balances the flying capacitor voltage.

12. The multi-level buck converter of claim 11, wherein the flying capacitor voltage is self-balanced at approximately half of the input voltage.

13. The multi-level buck converter of claim 11, wherein the switch comprises: The first switch comprises: A first terminal coupled to the input terminal; the second end; and A control terminal coupled to the control circuit; The second switch comprises: A first end coupled to the second end of the first switch; the second end; and A control terminal coupled to the control circuit; The third switch comprises: A first end coupled to the second end of the second switch; the second end; and A control terminal coupled to the control circuit; and The fourth switch comprises: A first end coupled to the second end of the third switch; A second terminal coupled to the ground terminal; and The control terminal is coupled to the control circuit.

14. The multi-level buck converter as claimed in claim 13, wherein the flying capacitor is coupled between the second terminal of the first switch and the second terminal of the third switch, and the inductor is coupled between the second terminal of the second switch and the output terminal of the multi-level buck converter.

15. The multi-level buck converter as claimed in claim 13, wherein the VCF compensation circuit comprises: a subtraction module, used for generating a voltage difference between half of the input voltage and the flying capacitor voltage; and The gain adjustment module is coupled to the subtraction module and is used for generating the duty ratio compensation signal according to the voltage difference.

16. The multi-level buck converter as claimed in claim 15, wherein the control circuit comprises: Error amplifier, including: An inverting terminal, coupled to the feedback terminal, for receiving the feedback voltage; Positive phase terminal, used to receive reference voltage ； and An output terminal, used for outputting an error amplified voltage; A first summing module, coupled to the output terminal of the error amplifier, for generating a first slope compensation signal according to the duty cycle compensation signal, the first ramp signal and the error amplified voltage; A second summing module, coupled to the output terminal of the error amplifier, for generating a second slope compensation signal according to the inversion of the duty cycle compensation signal, a second ramp signal and the error amplified voltage; A third summing module, coupled to the inductor, for generating an inductance summing signal according to the inductor current signal and a bias voltage; The first comparator comprises: An inverting terminal coupled to the third summing module; A positive phase terminal coupled to the first summing module; and An output terminal, used for generating a first pulse width modulation signal according to the first slope compensation signal and the inductance sum signal; The second comparator comprises: An inverting terminal coupled to the third summing module; A positive phase terminal coupled to the second summing module; and An output terminal, used for generating a second pulse width modulation signal according to the second slope compensation signal and the inductance sum signal; The first trigger includes: A set terminal coupled to the output terminal of the first comparator; A reset terminal, used for receiving a first clock signal; An output terminal, coupled to the control terminal of the first switch, for outputting a first switch signal; and an inverting output terminal, coupled to the control terminal of the fourth switch, and configured to output a fourth switch signal; and The second trigger contains: a set terminal coupled to the output terminal of the second comparator; A reset terminal, used for receiving a second clock signal; An output terminal, coupled to the control terminal of the second switch, for outputting a second switch signal; and The inverting output terminal is coupled to the control terminal of the third switch and is used for outputting a third switch signal.

17. The multi-level buck converter of claim 16, wherein: The first ramp signal is in antiphase with the second ramp signal; The first ramp signal and the second ramp signal have sawtooth waves; and The amplitude of the first ramp signal is substantially the same as the amplitude of the second ramp signal.

18. The multi-level buck converter of claim 16, further comprising: A first buffer coupled between the control terminal of the first switch and the output terminal of the first trigger; a second buffer coupled between the control terminal of the second switch and the output terminal of the second trigger; A third buffer coupled between the control terminal of the third switch and the inverting output terminal of the second trigger; and The fourth buffer is coupled between the control terminal of the fourth switch and the inverting output terminal of the first trigger.

19. The multi-level buck converter of claim 16, further comprising: A first resistor coupled between the output terminal of the multi-level buck converter and the inverting terminal of the error amplifier; A second resistor is coupled between the ground terminal and the inverting terminal of the error amplifier; and The capacitor is coupled between the output terminal of the multi-level buck converter and the ground terminal.

20. A multi-level buck converter, comprising: The first switch comprises: A first terminal is coupled to an input terminal, the input terminal having an input voltage; the second end; and Control terminal; The second switch comprises: A first end coupled to the second end of the first switch; the second end; and Control terminal; The third switch comprises: A first end coupled to the second end of the second switch; the second end; and Control terminal; and The fourth switch comprises: A first end coupled to the second end of the third switch; A second terminal coupled to the ground terminal; and Control terminal; an inductor, coupled between the second end of the second switch and an output end, and used for generating an inductor current signal; A flying capacitor, coupled between the second end of the first switch and the second end of the third switch, for generating a flying capacitor voltage; Error amplifier, including: An inverting terminal, coupled to the feedback terminal, for receiving a feedback voltage; A positive phase terminal, used for receiving a reference voltage; and An output terminal, used for outputting an error amplified voltage; A first summing module, coupled to the output terminal of the error amplifier, for generating a first slope compensation signal according to the first ramp signal and the error amplified voltage; A second summing module, coupled to the output terminal of the error amplifier, for generating a second slope compensation signal according to a second ramp signal and the error amplified voltage; A third summing module, coupled to the inductor, for generating an inductance summing signal according to the inductor current signal and a bias voltage; A first comparator comprises: An inverting terminal coupled to the third summing module; A positive phase terminal coupled to the first summing module; and An output terminal, used for generating a first pulse width modulation signal according to the first slope compensation signal and the inductance sum signal; The second comparator comprises: An inverting terminal coupled to the third summing module; A positive phase terminal coupled to the second summing module; and An output terminal, used for generating a second pulse width modulation signal according to the second slope compensation signal and the inductance sum signal; The first trigger includes: A set terminal coupled to the output terminal of the first comparator; A reset terminal, used for receiving a first clock signal; An output terminal, coupled to the control terminal of the first switch, for outputting a first switch signal; and an inverting output terminal, coupled to the control terminal of the fourth switch, and configured to output a fourth switch signal; and The second trigger contains: A set terminal coupled to the output terminal of the second comparator; A reset terminal, used for receiving a second clock signal; An output terminal, coupled to the control terminal of the second switch, for outputting a second switch signal; and an inverting output terminal, coupled to the control terminal of the third switch, and configured to output a third switch signal; A first buffer coupled between the control terminal of the first switch and the output terminal of the first trigger; a second buffer coupled between the control terminal of the second switch and the output terminal of the second trigger; A third buffer coupled between the control terminal of the third switch and the inverting output terminal of the second trigger; and The fourth buffer is coupled between the control terminal of the fourth switch and the inverting output terminal of the first trigger.

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