X-Ka wave band ultra-wideband low-power-consumption low-noise amplifier adopting CMOS (Complementary Metal Oxide Semiconductor) process

Abstract

The invention discloses an X-Ka band ultra-wideband low-power-consumption low-noise amplifier adopting a CMOS (Complementary Metal Oxide Semiconductor) process. Two wideband low-power-consumption low-noise amplifier units are respectively a wideband low-power-consumption low-noise amplifier first unit and a wideband low-power-consumption low-noise amplifier second unit; the broadband low-power-consumption low-noise amplifier unit comprises a multi-coil coupling broadband input matching network, the first unit of the broadband low-power-consumption low-noise amplifier takes a tertiary coil coupling broadband input matching network as input, and the second unit of the broadband low-power-consumption low-noise amplifier takes a secondary coil coupling broadband input matching network as input; the first unit and the second unit further comprise the same self-biased inverter resistance feedback structure, a cascode gain amplification module and a broadband output matching network. According to the invention, the design indexes of wide bandwidth, low noise, high gain, low power consumption and high linearity can be met at the same time.

Description

Technical Field

[0001] The present invention relates to a low-power, low-noise, broadband input matching technology for a low-noise amplifier, belonging to the technical field of microwave and millimeter-wave integrated circuit design, and in particular to a CMOS process X-Ka band ultra-wideband low-power low-noise amplifier. Background Art

[0002] In today's wireless communication field, large-scale phased array systems are rapidly developing in microwave and millimeter wave technologies to meet the application requirements of many high-frequency communications, and specific performance requirements have been established for individual module circuits. In particular, the performance of the low-noise amplifier (LNA), as the first stage of the receiving link, directly affects the working effect of the entire communication system. In addition to ensuring the high gain and low noise (NF) required for communication or detection quality, it is also necessary to maintain low power consumption and low cost. With the commercial deployment of many millimeter wave frequency bands such as 5G communication systems, the demand for high-speed, large-capacity, and low-latency data transmission continues to increase. Therefore, in order to meet the growing demand for broadband wireless communication systems, research on multi-band or broadband communication systems has received more and more attention from industry and academia.

[0003] Compared with semiconductor processes such as gallium arsenide (GaAs), indium phosphide (InP) and III-V compounds, the CMOS (complementary metal oxide semiconductor) process is the preferred process for designing large-scale integrated circuits because of its unique low cost and high integration, which is conducive to large-scale mass production. However, when realizing broadband low-power CMOS low-noise amplifiers, the following important challenges will be faced:

[0004] 1) The parasitic effects of CMOS process are obvious, which hinders the broadband performance of low-noise amplifiers, especially in the high-frequency field.

[0005] 2) The movement of carriers inside active devices on discontinuous dielectric layers, large substrate losses and low quality factors of passive devices all lead to an increase in the overall noise factor of the low-noise amplifier.

[0006] 3) The commonly used LNA circuit topology is difficult to simultaneously meet the design requirements of wide bandwidth, low noise, high gain, high linearity and low power consumption in the microwave and millimeter wave frequency bands.

[0007] Considering the above design challenges, there is an urgent need for a low-noise amplifier that can provide high gain and low noise in a broadband range, and can achieve stable and reliable performance at low power consumption and high linearity. Currently, there are many reports on the design of low-noise amplifiers for microwave and millimeter-wave broadband communication systems, but most of these works sacrifice one or more performance indicators such as power consumption, bandwidth, noise, gain, and linearity, and cannot meet the actual application requirements of various performance indicators at the same time. Summary of the invention

[0008] The present invention aims to provide a CMOS process X-Ka band ultra-wideband low-power low-noise amplifier, which is based on an ultra-wideband, low-noise input matching network with multiple coil couplings, combined with a low-power self-biased inverter resistor feedback structure as an input stage, a cascode gain amplifier module and a broadband output matching network, to solve the technical bottleneck that the conventional LNA circuit topology structure of the CMOS process is difficult to simultaneously meet high performance indicators such as ultra-wideband, low noise, high gain, low power consumption and high linearity in the microwave and millimeter wave frequency bands.

[0009] A CMOS process X-Ka band ultra-wideband low-power low-noise amplifier, the X-Ka band ultra-wideband low-power low-noise amplifier is realized by cascading two broadband low-power low-noise amplifier units, the two broadband low-power low-noise amplifier units are respectively a broadband low-power low-noise amplifier first unit and a broadband low-power low-noise amplifier second unit; the broadband low-power low-noise amplifier unit comprises a multiple coil-coupled broadband input matching network, wherein the broadband low-power low-noise amplifier first unit is coupled to a broadband input matching network by a tertiary coil as an input, and the broadband low-power low-noise amplifier second unit is coupled to a broadband input matching network by a secondary coil as an input;

[0010] The broadband low power consumption low noise amplifier first unit and the broadband low power consumption low noise amplifier second unit also include the same self-biased inverter resistor feedback structure, common source and common gate cascode gain amplifier module and broadband output matching network;

[0011] A multiple coil-coupled broadband input matching network, a self-biased inverter resistor feedback structure, a common-source and common-gate cascode gain amplifier module and a broadband output matching network are connected in series; wherein, the multiple coil-coupled broadband input matching network is used to improve input bandwidth and low noise matching, the self-biased inverter resistor feedback structure is used to achieve low noise and low power consumption performance, the common-source and common-gate cascode gain amplifier module improves gain and linearity performance, and the broadband output matching network completes broadband output matching.

[0012] Furthermore, the multiple coil-coupled broadband input matching network in the first unit of the broadband low-power low-noise amplifier includes a coil L1, a coil L2, a coil L3 and a parallel capacitor C2, the input end of the coil L1 is used as the input of the tertiary coil-coupled broadband input matching network, connected to the output end of the DC blocking capacitor C1, the output end of the coil L1 is connected to the input end of the coil L2 and the parallel capacitor C2; the output end of the coil L2 is connected to the input end of the coil L3, and the output end of the coil L3 is used as the output of the tertiary coil-coupled broadband input matching network; the coil L2 is coupled with the coil L1 and the coil L3 respectively, and the coupling coefficients correspond to k1 and k2 respectively, and k1 is equal to k2; the weak coupling between the coil L1 and the coil L3 is not considered;

[0013] The self-biased inverter resistor feedback structure is composed of an NMOS transistor MN1 and a PMOS transistor MP1, a feedback resistor Rf1 and a source inductor Ls1; the input ends of the self-biased inverter resistor feedback structure are the gates of the NMOS transistor MN1 and the PMOS transistor MP1, respectively, and are respectively connected to the two ends of the tertiary coil coupled broadband input matching network coil L3; the output end of the self-biased inverter resistor feedback structure is the drain of the NMOS transistor MN1 and the PMOS transistor MP1; the input of the feedback resistor Rf1 is connected to the output end of the tertiary coil coupled broadband input matching network coil L1, and the output of the feedback resistor Rf1 is connected to the drain of the NMOS transistor MN1 and the PMOS transistor MP1; the source inductor is connected between the source of the NMOS transistor MN1 and the ground;

[0014] The common-source and common-gate cascode gain amplifier module is composed of a common-source transistor M1 and a common-gate transistor M2, wherein the input end is the gate end of the common-source transistor M1, connected to the output of the self-biased inverter resistor feedback structure; the output end of the common-source and common-gate cascode gain amplifier module is the drain end of the common-gate transistor M2, connected to the input of the broadband output matching network; the source of the common-source transistor M1 is grounded;

[0015] The broadband output matching network is composed of a resistor R1, an inductor Lo1, an inductor Lo2 and a capacitor C3; the output end of the inductor Lo1 is connected in series with the input of the capacitor C3 and the input of the inductor Lo2; the output of the capacitor C3 is the output of the ultra-wideband low-power low-noise amplifier unit; the output of the inductor Lo2 is connected in series with the resistor R1 to reach the power supply voltage VDD;

[0016] The multiple coil-coupled broadband input matching network in the second unit of the broadband low-power low-noise amplifier only includes coils L2 and L3.

[0017] Furthermore, the broadband input matching network of the tertiary coil coupling includes two different types of low-pass filter network structures, namely, a T-type low-pass filter network structure composed of the coil L1, the parallel capacitor C2 and the coil L2; and a π-type low-pass filter network structure composed of the coil L3 and the gate-source parasitic capacitance Cgs of the NMOS and PMOS transistors in the self-biased inverter resistance feedback structure.

[0018] Furthermore, the self-biased inverter resistor feedback structure provides an adaptive bias voltage and a bias voltage for the subsequent cascode gain amplifier module without the need for an additional bias circuit, because the two ends of the feedback resistor Rf1 are equivalently connected to the gate and drain of the PMOS transistor respectively; the NMOS transistor and the PMOS transistor are of the same size; the source inductor Ls1 is used to match the real part of the input matching network to the source impedance of 50 ohms.

[0019] Furthermore, the common source transistor M1 and the common gate transistor M2 in the cascode gain amplifier module are of the same size; the gate of the common gate transistor M2 is connected in parallel with a 2pF decoupling capacitor to ground and in series with a 10K resistor to VDD to provide bias and suppress high-frequency signal interference.

[0020] Furthermore, in the broadband output matching network, the inductor Lo1, the inductor Lo2 and the capacitor C3 form a T-type low-pass filter network structure, and the parallel resistor R1 reduces the quality factor Q value of the broadband output matching network; the inductor Lo1 is used to resonate the parasitic capacitance at the drain end of the common gate transistor M2 in the cascode gain amplifier module.

[0021] The present invention also discloses a design method for a CMOS process X-Ka band ultra-wideband low power consumption low noise amplifier, comprising the following steps:

[0022] Step 1, determine the quiescent current and optimize the minimum noise factor; determine the size of the NMOS transistor and the PMOS transistor in the self-biased inverter resistor feedback structure, the resistance value of the feedback resistor, and the size of the common source transistor M1 and the common gate transistor M2 in the cascade gain amplifier module;

[0023] Step 2, perform broadband input impedance matching, and determine the size of coil L1, coil L2, coil L3, the coupling coefficient k1 between coil L1 and coil L2, the coupling coefficient k2 between coil L2 and coil L3, the parallel capacitor C2, and the source inductance Ls1 in the coil-coupled ultra-wideband input matching network;

[0024] Step 3: Perform broadband output impedance matching and determine the sizes of inductor Lo1, inductor Lo2, capacitor C3 and resistor R1 in the broadband output matching network.

[0025] The CMOS process X-Ka band ultra-wideband low power consumption low noise amplifier of the present invention has the following advantages:

[0026] The present invention has ultra-wideband, high gain, low power consumption, low noise and high linearity performance, and its broadband has scalable characteristics. The present invention can simultaneously achieve high performance indicators such as broadband, high gain, low power consumption, low noise and high linearity, effectively improve the signal reception and transmission quality of microwave and millimeter wave broadband wireless communication systems, and promote the wide application of microwave and millimeter wave broadband high-performance low-noise amplifiers in 5G multi-bandwidth communications, large-scale phased array systems and other fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the structure of a CMOS process X-Ka band ultra-wideband low power consumption low noise amplifier;

[0028] Figure 2 A schematic diagram showing the effect of different input matching methods on noise performance based on the self-biased inverter resistor feedback structure;

[0029] Figure 3 Schematic diagram of the effect of the parallel capacitance and coupling coefficient of the broadband input matching network coupled with the tertiary coil on the input standing wave;

[0030] Figure 4 Schematic diagram of electromagnetic simulation model of broadband input matching network with tertiary coil coupling;

[0031] Figure 5 The schematic diagram of the self-biased inverter resistor feedback structure of the ultra-wideband tertiary coil coupled input matching network;

[0032] Figure 6 Schematic diagram of small signal noise model of self-biased inverter resistor feedback structure with ultra-wideband input matching network;

[0033] Figure 7 It is a schematic diagram of simulation results of various indicators of a CMOS process X-Ka band ultra-wideband low power consumption low noise amplifier;

[0034] Figure 8 This is a schematic diagram of the layout design of a CMOS process X-Ka band ultra-wideband low-power low-noise amplifier. DETAILED DESCRIPTION

[0035] The scheme of the present invention will be described below in conjunction with the accompanying drawings and specific implementation methods in the embodiments of the present invention:

[0036] The present invention designs a CMOS process X-Ka band ultra-wideband low power consumption low noise amplifier, which is realized by cascading a first broadband low power consumption low noise amplifier unit and a second broadband low power consumption low noise amplifier unit, as shown in the schematic diagram. Figure 1 shown.

[0037] The first unit of the broadband low power low noise amplifier comprises: a broadband input matching network coupled by three coils, a resistor feedback structure based on a self-biased inverter, a cascode gain amplification structure and a broadband output matching network.

[0038] The broadband input matching network of the tertiary coil coupling is characterized in that the input end of the coil L1 is used as the input of the tertiary coil coupling broadband input matching network and is connected to the output end of the DC blocking capacitor C1, and its output end is connected to the input end of the coil L2 and the parallel capacitor C2; the output end of the coil L2 is connected to the input end of the coil L3, and its output end is used as the output of the tertiary coil coupling broadband input matching network; the coil L2 is coupled with the coil L1 and the coil L3 respectively, and the coupling coefficients correspond to k1 and k2 respectively, and k1 is equal to k2; the weak coupling between the coil L1 and the coil L3 is not considered; the broadband input matching network includes two different types of low-pass filter network structures, namely, a T-type low-pass filter network structure composed of the coil L1, the parallel capacitor C2 and the coil L2; and a π-type low-pass filter network structure composed of the coil L3 and the gate-source parasitic capacitors Cgs of the NMOS transistor MN1 and the PMOS transistor MP1 in the self-biased inverter resistance feedback structure.

[0039] The self-biased inverter resistor feedback structure is composed of an NMOS transistor MN1 and a PMOS transistor MP1, a feedback resistor and a source inductor Ls1. The input ends of the structure are the gates of the NMOS transistor MN1 and the PMOS transistor MP1, respectively, which are connected to the two ends of the tertiary coil coupled broadband input matching network coil L3; the output ends of the structure are the drains of the NMOS transistor MN1 and the PMOS transistor MP1; the input of the feedback resistor Rf1 is connected to the output end of the tertiary coil coupled broadband input matching network coil L1, and the output is connected to the output end of the self-biased inverter resistor feedback structure; the source inductor Ls1 is connected between the source of the NMOS transistor MN1 and the ground.

[0040] The cascode gain amplifier module is composed of a common source transistor M1 and a common gate transistor M2 to form a common source and common gate structure. The common source transistor M1 and the common gate transistor M2 are of the same size. The gate of the common gate transistor M2 is connected in parallel with a 2pF capacitor to the ground, which is used to achieve decoupling. A 10K resistor is connected in series to VDD to provide bias and suppress high-frequency signal interference. Since the cascode structure has better isolation and linearity, the cascode gain amplifier module is selected as the output part with high linearity characteristics.

[0041] The broadband output matching network, the output end of the inductor Lo1 is connected in series to the input of the capacitor C3, and in parallel to the input of the inductor Lo2; the output of the inductor Lo2 is connected in series to the resistor R1 to reach the power supply voltage VDD. The inductor Lo1, the inductor Lo2 and the capacitor C3 form a T-type low-pass filter network structure, which can effectively filter out high-frequency noise signals, and the high-frequency nature of the noise is improved. According to the formula Q=wL / R, adding the parallel resistor R1 can reduce the Q value of the broadband output matching network, thereby improving the output bandwidth. The inductor Lo1 is used to resonate the parasitic capacitance of the drain end of the common-gate transistor M2.

[0042] The second unit of the broadband low power low noise amplifier comprises: a broadband input matching network coupled with a secondary coil, a resistor feedback structure based on a self-biased inverter, a cascode gain amplification structure and a broadband output matching network.

[0043] The present invention also discloses a design method for a CMOS process X-Ka band ultra-wideband low power consumption low noise amplifier, comprising the following steps:

[0044] Step 1, determine the quiescent current and optimize the minimum noise factor; determine the size of the NMOS transistor and the PMOS transistor in the self-biased inverter resistor feedback structure, the resistance value of the feedback resistor, and the size of the common source transistor M1 and the common gate transistor M2 in the cascade gain amplifier module;

[0045] Step 2, perform broadband input impedance matching, and determine the size of coil L1, coil L2, coil L3, the coupling coefficient k1 between coil L1 and coil L2, the coupling coefficient k2 between coil L2 and coil L3, the parallel capacitor C2, and the source inductance Ls1 in the coil-coupled ultra-wideband input matching network;

[0046] Step 3: Perform broadband output impedance matching and determine the sizes of inductor Lo1, inductor Lo2, capacitor C3 and resistor R1 in the broadband output matching network.

[0047] The broadband input matching network coupled with the secondary coil, the input end of the coil L4 serves as the input of the broadband input matching network coupled with the secondary coil, the output end of the coil L4 is connected to the input end of the coil L5 and the gate end of the PMOS transistor MP2; the output end of the coil L5 is connected to the gate end of the NMOS transistor MN2, serving as the output of the broadband input matching network coupled with the secondary coil; the coupling coefficient between the coil L4 and the coil L5 is k3; the broadband input matching network coupled with the secondary coil comprises a π-type low-pass filter network structure composed of the coil L5 and the gate-source parasitic capacitance Cgs of the NMOS transistor MN2 and the PMOS transistor MP2 in the resistance feedback structure of the self-biased inverter.

[0048] The self-biased inverter resistor feedback structure is composed of an NMOS transistor MN2 and a PMOS transistor MP2, a feedback resistor Rf2, and a source inductor Ls2. The input ends of the structure are the gates of the NMOS transistor MN2 and the PMOS transistor MP2, respectively, which are connected to the two ends of the secondary coil coupled broadband input matching network coil L5; the output ends of the structure are the drains of the NMOS transistor MN2 and the PMOS transistor MP2; the input of the feedback resistor Rf2 is connected to the input end of the secondary coil coupled broadband input matching network, and the output is connected to the output end of the self-biased inverter resistor feedback structure; the source inductor Ls2 is connected between the source of the NMOS transistor MN2 and the ground.

[0049] The cascode gain amplifier module is composed of a common-source transistor M3 and a common-gate transistor M4 to form a common-source common-gate structure. The common-source transistor M3 and the common-gate transistor M4 are of the same size. The gate of the common-gate transistor M4 is connected in parallel with a 2pF capacitor to the ground, which is used to achieve decoupling. A 10K resistor is connected in series to VDD to provide bias and suppress high-frequency signal interference.

[0050] The broadband output matching network, the output end of the inductor Lo3 is connected in series with the input of the capacitor C4, and in parallel with the input of the inductor Lo4; the output of the inductor Lo4 is connected in series with the resistor R2 to reach the power supply voltage VDD. The inductor Lo3, the inductor Lo4 and the capacitor C4 form a T-type low-pass filter network structure, which can effectively filter out high-frequency noise signals, and the high-frequency nature of the noise is improved.

[0051] The broadband input matching network of the tertiary coil coupling is realized based on the self-biased inverter resistor feedback structure. Figure 2 Schematic diagram of the effect of different input matching methods on noise performance based on the self-biased inverter resistor feedback structure. Figure 2In FIG. 1 , 1-1 represents the noise coefficient characteristic of the self-biased inverter resistor feedback structure without an input matching network.1-2 represents the influence of the series inductance L1 at the input end of the self-biased inverter resistor feedback structure on its noise coefficient. It can be seen from the curve in the figure that the larger the series inductance value, the worse the flatness of the noise coefficient (the minimum noise shifts to the low frequency, and the noise at the high frequency increases exponentially); 1-3 represents the influence of the gate series inductance L3 of the NMOS transistor in the self-biased inverter resistor feedback structure on its noise coefficient. It can be seen from the curve in the figure that compared with L1, the series inductance L3 has a significant improvement on the noise coefficient, and its characteristics are the same as L1, that is, the larger the inductance value, the smaller the value of the noise coefficient at low frequency, but the worse the flatness (the minimum noise shifts to the low frequency, and the noise at the high frequency increases exponentially); 1-4 represents the gate series inductance L3 of the NMOS transistor in the self-biased inverter resistor feedback structure. The influence of the gate series inductance L2 of MOS and PMOS transistors on their noise coefficients. As can be seen from the curves in the figure, compared with 1-2 and 1-3, the series inductance L2 has a significant improvement on the noise coefficient, and its characteristics are the same as L1 and L2, that is, the larger the inductance, the smaller the noise coefficient at low frequencies, but the worse the flatness (the minimum noise shifts to low frequencies, and the noise at high frequencies increases exponentially); 1-5 represents the influence of the input series inductance L1 and the gate series inductance L3 of the NMOS transistor in the resistive feedback structure of the self-biased inverter on its noise coefficient. As can be seen from the curves in the figure, compared with 1-1, the series inductances L1 and L3 have a significant improvement on the noise coefficient in the full frequency band; 1-6 represents the series inductance L1 and L3 in the resistive feedback structure of the self-biased inverter. The influence of the gate series inductance L2 of the NMOS and PMOS transistors and the gate series inductance L3 of the NMOS transistor on their noise coefficients is shown in the curve in the figure. Compared with 1-1, the improvement of the noise coefficient in the full frequency band by the series inductance L2 and L3 is more obvious than that in 1-5; 1-7 represents the influence of the input series inductance L1, the gate series inductance L2 of the NMOS and PMOS transistors and the gate series inductance L3 of the NMOS transistor on their noise coefficients in the self-biased inverter resistor feedback structure. According to the curve in the figure, compared with 1-5 and 1-6, the improvement of the noise coefficient in the full frequency band by the series inductance L1, L2 and L3 is better than that in 1-5 and 1-6, and the flatness of the noise coefficient is also obtained. Improvement; 1-8 represents the influence of adding a parallel capacitor C between L1 and L2 in the resistive feedback structure of the self-biased inverter based on the three-series inductor input matching network of 1-7 on the noise coefficient. It can be seen from the curve in the figure that compared with 1-7, adding a parallel capacitor C between the series inductors L1 and L2 improves the noise coefficient better than 1-7, but the flatness of the noise coefficient at high frequencies is slightly higher; 1-9 represents the influence of L1 and L2, L2 and L3 coupling with each other in the resistive feedback structure of the self-biased inverter based on the input matching network parallel capacitor C of 1-8 on the noise coefficient. It can be seen from the curve in the figure that compared with 1-1 to 1-8, the series inductors L1 and L2, L2 and L3 coupling with each other have the best improvement on the noise coefficient performance; therefore, passed. Figure 2From the influence of each input matching network structure on the noise coefficient, it is known that the broadband input matching network structure with triple coil coupling has the best noise coefficient characteristic. Figure 3 The diagram shows the effect of the parallel capacitance of the broadband input matching network coupled by the three coils on the input standing wave and the coupling coefficient on the noise performance. It can be seen from the figure that the input standing wave resonance frequency gradually shifts to high frequency with the increase of the parallel capacitance value (20f-200f), and the standing wave coefficient first drops to below -10dB, and then gradually increases. When the capacitance value is 100f, the input standing wave characteristic of the broadband input matching network coupled by the three coils is the best. Although the minimum noise coefficient decreases and shifts to low frequency with the increase of the coupling coefficient k of the series inductance L1 and L2, L2 and L3 (0.1-1), its noise coefficient flatness in the frequency band also gradually deteriorates. Therefore, considering the minimum noise coefficient and the flatness in the band, when the coupling coefficient k is 0.4, it has better broadband noise performance. Figure 4 The figure shows a schematic diagram of the electromagnetic simulation model of a broadband input matching network with three coil couplings, where coils L1 and L3 are the second top layer thick metal, and coil L2 is the top layer thick metal. The signal input terminals and corresponding positions of each coil are marked in the figure. Coil L2 has the same coupling coefficient as coils L1 and L3, and is distributed on both sides of coil L2. Coil L1 and coil L3 are spaced far apart, and the weak coupling between them is not considered.

[0052] Figure 5 The figure shows a schematic diagram of a self-biased inverter resistor feedback structure with a tertiary coil coupled input matching network. The self-biased inverter resistor feedback structure is composed of an NMOS transistor and a PMOS transistor, a feedback resistor and an NMOS source inductor. Since the two ends of the feedback resistor are respectively connected to the gate and drain of the PMOS transistor, an adaptive bias voltage can be provided and a bias voltage can be provided for the subsequent cascode gain amplifier module without the need for an additional bias circuit, which greatly reduces power consumption. The feedback resistor has a resistance of kilo-ohms. The larger the resistance of the feedback resistor, the better the noise coefficient and stability performance. The NMOS transistor and the PMOS transistor are of the same size. The source degeneration inductor Ls1 is used to match the real part of the input matching network to a source impedance of 50 ohms.

[0053] Figure 6 The following is a schematic diagram of the small signal noise model of the self-biased inverter resistor feedback structure with a tertiary coil coupled broadband input matching network. In the figure, the noise source Vs is the input signal source noise; the noise sources Vn,m and Vn,p are the flicker noise (1 / f noise) of the NMOS transistor and the PMOS transistor respectively; the noise sources In,m, In,p and In,Rf are the thermal noise of the NMOS transistor, the thermal noise of the PMOS transistor and the thermal noise of the feedback resistor Rf respectively. The noise analysis of the above noise sources yields the following formula:

[0054] Noise Sources: Feedback resistor thermal noise: In the above formula, k represents the Boltzmann constant, T is the temperature, and Δf represents the bandwidth;

[0055] NMOS transistor flicker noise: PMOS transistor flicker noise: In the above formula, K is a process-related constant, Cox is the gate oxide capacitance, W represents the gate width, and L represents the gate length;

[0056] NMOS transistor thermal noise: PMOS transistor thermal noise: In the above formula, γ is not the body effect coefficient of the transistor, which is 2 / 3 for long channel devices and 2, 3 or more for short channel devices; g is the transistor transconductance; the noise source at the output end of formula (1-5) or formula (1-6) is approximately:

[0057]

[0058] Voltage gain: A V ≈g n (r n / / R f ) Formula (1-8)

[0059] The noise voltage relative to the gate terminal of the NMOS transistor is: Based on the circuit structure of the inverter, only one of the NMOS transistor and the PMOS transistor is turned on and the other is turned off during operation. Combining equations (1-1)-(1-9), it can be seen that the total noise voltage relative to the input signal source is:

[0060]

[0061] It can be seen from formula (1-10) that the noise of the self-biased inverter resistor feedback structure of the tertiary coil coupled broadband input matching network mainly depends on the internal noise of the NMOS transistor and the PMOS transistor. Figure 6In the small signal equivalent circuit model, the primary coil L1, the secondary coil L2 and the parallel capacitor C1 form a T-type low-pass filter network structure; the coil L3 and the gate-source parasitic capacitance Cgs of the NMOS transistor and the PMOS transistor respectively form another π-type low-pass filter network structure; the two low-pass filter network structures of the signal input matching network effectively filter out the high-frequency noise signals from the signal source and the internal noise of the transistor, and the noise performance is effectively improved.

[0062] The above analysis is a specific implementation of the design of an ultra-wideband low-power low-noise amplifier unit. The X-Ka band (10-40GHz) low-noise, low-power, high-gain and high-linearity low-noise amplifier designed by the present invention is realized by cascading two ultra-wideband low-power low-noise amplifier design units. Since the input and output ends are matched to 50 ohms, no additional matching is required, which effectively reduces the design complexity. It should be noted that, unlike the first unit design scheme of the ultra-wideband low-power, low-noise amplifier, the input matching network of the second unit design scheme adopts a broadband transformer structure with two coil couplings, which is coupled by series inductors L4 and L5. The input of inductor L4 is connected to the input of the feedback resistor Rf2 in the self-biased inverter resistance feedback structure as the input end of the second unit design scheme; the output of inductor L4 is respectively connected to the input of inductor L5 and the gate of the PMOS transistor in the self-biased inverter resistance feedback structure; the inductor L5 and the gate-source parasitic capacitance Cgs of the NMOS and PMOS transistors in the self-biased inverter resistance feedback structure form a π-type low-pass filter network. The second unit π-type low-pass filter input matching network and the first unit ultra-wideband low-power, low-noise amplifier unit design output matching network T-type-π-type broadband interstage low-pass filter matching network, to achieve the X-Ka band low-noise, low-power, high-gain and high-linearity low-noise amplifier design. In addition, through the cascade of multiple units, it can be used to achieve ultra-wideband low-power low-noise amplifier design.

[0063] Figure 7 The figure shows the simulation results of various indicators of the X-Ka band ultra-wideband low-power low-noise amplifier based on CMOS process. As can be seen from the figure, the maximum gain of the low-noise amplifier is 20dB, the 3dB bandwidth is 10-40GHz, the input and output standing waves are both below -10dB, the noise figure range is 2.8-6.8dB, and the input 1dB compression point in the full band is less than -19.5dBm. The layout design diagram of the CMOS process X-Ka band ultra-wideband low-power low-noise amplifier is shown in the figure. Figure 8 As shown, the entire chip size is 744um x 468um, including PAD.

[0064] The present invention can extend its bandwidth characteristics according to actual needs. The present invention responds to the urgent needs of current broadband wireless communication systems for high-performance RF front-end low-noise amplifiers. Through the design of this low-noise amplifier, it will be able to effectively improve the signal reception and transmission quality of microwave and millimeter-wave broadband wireless communication systems, and promote the widespread application of microwave and millimeter-wave broadband high-performance low-noise amplifiers in 5G multi-bandwidth communications, large-scale phased array systems and other fields. This is crucial for the use of CMOS technology to realize microwave and millimeter-wave ultra-wideband low-noise amplifiers, and represents a key bottleneck in this field. The present invention can not only provide high gain and low noise in the ultra-wideband range, but also achieve stable and reliable high-performance characteristics with low power consumption and high linearity.

[0065] The CMOS process X-Ka band ultra-wideband low-power low-noise amplifier proposed in the present invention is not limited to the cascaded implementation of the first unit and the second unit of the broadband low-power low-noise amplifier, but can be expanded to the cascade between the nth units, and the frequency band of the corresponding ultra-wideband low-power low-noise amplifier is changed. Therefore, according to the requirements of the high-performance low-noise amplifier design index, an appropriate number of unit cascade designs can be selected.

[0066] Relevant researchers and technicians in this field can make non-substantial improvements, modifications or substitutions according to the application fields mentioned in the above scheme without departing from the purpose of the present invention, and should also fall within the scope of protection of the claims of the present invention. The present invention is not limited to the contents disclosed in the above implementation scheme, and the scope of protection of the present invention shall be subject to the claims.

Claims

1. A CMOS process X-Ka band ultra-wideband low power consumption low noise amplifier, characterized in that: The X-Ka band ultra-wideband low-power low-noise amplifier is realized by cascading two wideband low-power low-noise amplifier units, wherein the two wideband low-power low-noise amplifier units are respectively a wideband low-power low-noise amplifier first unit and a wideband low-power low-noise amplifier second unit; the wideband low-power low-noise amplifier unit comprises a multiple coil-coupled wideband input matching network, wherein the wideband low-power low-noise amplifier first unit has a tertiary coil-coupled wideband input matching network as an input, and the wideband low-power low-noise amplifier second unit has a secondary coil-coupled wideband input matching network as an input; The broadband low power consumption low noise amplifier first unit and the broadband low power consumption low noise amplifier second unit also include the same self-biased inverter resistor feedback structure, common source and common gate cascode gain amplifier module and broadband output matching network; A multiple coil-coupled broadband input matching network, a self-biased inverter resistor feedback structure, a common-source and common-gate cascode gain amplifier module and a broadband output matching network are connected in series in sequence; among them, the multiple coil-coupled broadband input matching network is used to improve input bandwidth and low noise matching, the self-biased inverter resistor feedback structure is used to achieve low noise and low power consumption performance, the common-source and common-gate cascode gain amplifier module improves gain and linearity performance, and the broadband output matching network completes broadband output matching.

2. The CMOS process X-Ka band ultra-wideband low power consumption low noise amplifier according to claim 1, characterized in that: The multiple coil-coupled broadband input matching network in the first unit of the broadband low-power low-noise amplifier includes a coil L1, a coil L2, a coil L3 and a parallel capacitor C2, the input end of the coil L1 is used as the input of the tertiary coil-coupled broadband input matching network, and is connected to the output end of the DC blocking capacitor C1, the output end of the coil L1 is connected to the coil L2 and the input end of the parallel capacitor C2; the output end of the coil L2 is connected to the input end of the coil L3, and the output end of the coil L3 is used as the output of the tertiary coil-coupled broadband input matching network; Coil L2 is coupled with coil L1 and coil L3 respectively, and the coupling coefficients correspond to k1 and k2 respectively, and k1 is equal to k2; the weak coupling between coil L1 and coil L3 is not considered; The self-biased inverter resistor feedback structure is composed of an NMOS transistor MN1 and a PMOS transistor MP1, a feedback resistor Rf1 and a source inductor Ls1; the input ends of the self-biased inverter resistor feedback structure are the gates of the NMOS transistor MN1 and the PMOS transistor MP1, respectively, and are respectively connected to the two ends of the tertiary coil coupled broadband input matching network coil L3; the output end of the self-biased inverter resistor feedback structure is the drain of the NMOS transistor MN1 and the PMOS transistor MP1; the input of the feedback resistor Rf1 is connected to the output end of the tertiary coil coupled broadband input matching network coil L1, and the output of the feedback resistor Rf1 is connected to the drain of the NMOS transistor MN1 and the PMOS transistor MP1; the source inductor is connected between the source of the NMOS transistor MN1 and the ground; The common-source and common-gate cascode gain amplifier module is composed of a common-source transistor M1 and a common-gate transistor M2, wherein the input end is the gate end of the common-source transistor M1, connected to the output of the self-biased inverter resistor feedback structure; the output end of the common-source and common-gate cascode gain amplifier module is the drain end of the common-gate transistor M2, connected to the input of the broadband output matching network; the source of the common-source transistor M1 is grounded; The broadband output matching network is composed of a resistor R1, an inductor Lo1, an inductor Lo2 and a capacitor C3; the output end of the inductor Lo1 is connected in series with the input of the capacitor C3 and the input of the inductor Lo2; the output of the capacitor C3 is the output of the broadband low-power low-noise amplifier unit; the output of the inductor Lo2 is connected in series with the resistor R1 to reach the power supply voltage VDD; The multiple coil-coupled broadband input matching network in the second unit of the broadband low-power low-noise amplifier only includes coils L2 and L3.

3. The CMOS process X-Ka band ultra-wideband low power consumption low noise amplifier according to claim 1, characterized in that: The broadband input matching network coupled by the tertiary coil includes two different types of low-pass filter network structures, namely, a T-type low-pass filter network structure composed of the coil L1, the parallel capacitor C2 and the coil L2; and a π-type low-pass filter network structure composed of the coil L3 and the gate-source parasitic capacitors Cgs of the NMOS and PMOS transistors in the self-biased inverter resistance feedback structure.

4. The CMOS process X-Ka band ultra-wideband low power consumption low noise amplifier according to claim 1, characterized in that: The self-biased inverter resistor feedback structure provides an adaptive bias voltage and a bias voltage for the subsequent cascode gain amplifier module, because the two ends of the feedback resistor Rf1 are equivalently connected to the gate and drain of the PMOS transistor respectively, without the need for an additional bias circuit; the NMOS transistor and the PMOS transistor are of the same size; the source inductor Ls1 is used to match the real part of the input matching network to a source impedance of 50 ohms.

5. The CMOS process X-Ka band ultra-wideband low power consumption low noise amplifier according to claim 1, characterized in that: The common source transistor M1 and the common gate transistor M2 in the cascode gain amplifier module are of the same size; the gate of the common gate transistor M2 is connected in parallel with a 2pF decoupling capacitor to ground and in series with a 10K resistor to VDD to provide bias and suppress high-frequency signal interference.

6. The CMOS process X-Ka band ultra-wideband low power consumption low noise amplifier according to claim 1, characterized in that: In the broadband output matching network, the inductor Lo1, the inductor Lo2 and the capacitor C3 form a T-type low-pass filter network structure, and the parallel resistor R1 reduces the quality factor Q value of the broadband output matching network; the inductor Lo1 is used to resonate the parasitic capacitance of the drain end of the common gate transistor M2 in the cascode gain amplifier module.

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