64B / 66B coded signal processing method, device, equipment and storage medium

Abstract

The embodiment of the invention provides a 64B / 66B coding signal processing method, device and equipment and a storage medium, and the method comprises the steps: converting eight 64B / 66B coding blocks into 512B / 513B coding blocks, each 64B / 66B coding block being a 64B / 66B data coding block or a 64B / 66B control coding block; forming a 512B / 513B coding signal by the 512B / 513B coding block, and sending the 512B / 513B coding signal; wherein the first L1 bits of the 512B / 513B coding block are an indication field, the last L2 bits of the 512B / 513B coding block are an information field, and the indication field comprises at least one of the following information: the number of the 64B / 66B control coding blocks in the 8 64B / 66B coding blocks, or the positions of the 64B / 66B control coding blocks in the 8 64B / 66B coding blocks; the information field comprises eight information blocks, and the number of bits contained in each information block is determined by the value of the L1 bit indication field. According to the embodiment of the invention, the number of bits needing to be deleted and added in the compression process can be reduced, most bits of each coding block can be kept unchanged, and hardware implementation is simplified.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a 64B / 66B coded signal processing method, apparatus, device and storage medium. Background Art

[0002] The 64B / 66B coding block is the most common encoding method of the Ethernet Physical Coding Sublayer (PCS), which is used to convert the Media Access Control Frame (MAC) into a fixed-rate bit block and add some necessary control information.

[0003] The 64B / 66B coding block is a bit block with a length of 66 bits, which can be called a 66-bit block. The first two bits in the 66B bit block are named as synchronization bits. If the synchronization header is 01, this bit block can be called a 64B / 66B data coding block. The 3rd to 66th bits in the bit block can be called the information field. The length of the information field is 64 bits, and the information field contains 8 bytes of data characters. If the synchronization header is 10, this bit block can be called a 64B / 66B control coding block. The last 64 bits of the bit block contain control information, which may contain at least 1 control character, or contain an ordered set control block, where the length of a control character is 7 bits and the length of an ordered set control block is 28 bits. When the synchronization header is 10, the 3rd to 10th bits in the 66-bit block can be called the type field (block type field). The length of the type field is 8 bits. The 11th to 66th bits in the 66-bit block can be called the information field. The length of the information field is 56 bits.

[0004] In some application scenarios, it is necessary to compress the 64B / 66B coded signal to reduce the signal rate. For example, the 64B / 66B coded signal can be converted into a 256B / 257B coded signal, or the 64B / 66B coded signal can be converted into a 512B / 513B coded signal, wherein the conversion into a 512B / 513B coded signal can obtain better compression efficiency. In the related art, 8 64B / 66B coded blocks are converted into 1 512B / 513B coded block. During the conversion process, the 8 64B / 66B coded blocks need to be shifted according to the specific values ​​of the 2-bit synchronization headers of the 8 64B / 66B coded blocks, and all 64B / 66B coded blocks starting with 10 are moved to the front, while keeping the relative front and back timings between the 8 64B / 66B coded blocks unchanged. However, the shift operation is complex to implement, which increases the difficulty of hardware implementation. Summary of the invention

[0005] The embodiments of the present application provide a 64B / 66B coded signal processing method, a 64B / 66B coded signal processing device, an electronic device and a computer-readable storage medium, which can compress 8 64B / 66B coded blocks into 1 512B / 513B coded block, and keep the relative positions of the 8 64B / 66B coded blocks unchanged during the operation, thereby reducing the complexity of the operation and the difficulty of hardware implementation.

[0006] In a first aspect, an embodiment of the present application provides a 64B / 66B coded signal processing method, wherein the 64B / 66B coded signal is composed of 64B / 66B coded blocks, and the method includes:

[0007] Convert the eight 64B / 66B coding blocks into 512B / 513B coding blocks, each of the 64B / 66B coding blocks being a 64B / 66B data coding block or a 64B / 66B control coding block;

[0008] composing a 512B / 513B coded signal from the 512B / 513B coded blocks, and sending the 512B / 513B coded signal;

[0009] The first L1 bits of the 512B / 513B coding block are the indication field, the last L2 bits are the information field, L1 is an integer greater than or equal to 1, L2 is an integer greater than 1 and L2=513-L1;

[0010] The L1 bit indication field includes at least one of the following information: the number of the 64B / 66B control coding blocks in the eight 64B / 66B coding blocks, or the position of the 64B / 66B control coding block in the eight 64B / 66B coding blocks;

[0011] The L2 bit information field contains 8 information blocks corresponding one by one to the 8 64B / 66B coding blocks, the length of each information block is 64 bits or 60 bits, and the number of bits contained in each information block is determined by the value of the L1 bit indication field.

[0012] In a second aspect, an embodiment of the present application provides a 64B / 66B coded signal processing device, the device comprising:

[0013] A sending module, used to execute: converting the eight 64B / 66B coding blocks into 512B / 513B coding blocks, forming a 512B / 513B coding signal from the 512B / 513B coding blocks, and sending the 512B / 513B coding signal;

[0014] A receiving module, configured to execute: receiving the 512B / 513B coded signal, and converting the 512B / 513B coded block in the 512B / 513B coded signal into eight 64B / 66B coded blocks;

[0015] Wherein, each of the 64B / 66B coding blocks is a 64B / 66B data coding block or a 64B / 66B control coding block;

[0016] The first L1 bits of the 512B / 513B coding block are the indication field, and the last L2 bits are the information field, wherein L1 is an integer greater than or equal to 1, L2 is an integer greater than 1, and L2=513-L1;

[0017] The L1 bit indication field includes at least one of the following information: the number of the 64B / 66B control coding blocks in the eight 64B / 66B coding blocks, or the position of the 64B / 66B control coding block in the eight 64B / 66B coding blocks;

[0018] The L2 bit information field contains 8 information blocks corresponding one by one to the 8 64B / 66B coding blocks, the length of each information block is 64 bits or 60 bits, and the number of bits contained in each information block is determined by the value of the L1 bit indication field.

[0019] In a third aspect, an embodiment of the present application provides an electronic device, including:

[0020] one or more processors;

[0021] A memory having one or more programs stored thereon, when the one or more programs are executed by the one or more processors, the one or more processors implement the 64B / 66B coded signal processing method as described in the first aspect above.

[0022] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the program is executed by a processor, the 64B / 66B encoded signal processing method as described in the first aspect above is implemented.

[0023] In an embodiment of the present application, eight of the 64B / 66B coding blocks are converted into 512B / 513B coding blocks, a 512B / 513B coding signal is formed from the 512B / 513B coding blocks, and the 512B / 513B coding signal is sent, wherein the first L1 bits of the 512B / 513B coding block are an indication field, the last L2 bits are an information field, the L1 is an integer greater than or equal to 1, the L2 is an integer greater than 1 and L2=513-L1. The number of the 64B / 66B control coding blocks in the eight 64B / 66B coding blocks or the position of the 64B / 66B control coding blocks in the eight 64B / 66B coding blocks can be determined by the L1 bit indication field. The L2 bit information field contains eight information blocks corresponding to the eight 64B / 66B coding blocks one by one, and the length of each of the information blocks can be 64 bits or 60 bits. According to the embodiments of the present application, eight 64B / 66B coding blocks can be compressed into one 512B / 513B coding block, and the number of bits required to be deleted and added during the compression conversion process is reduced, so that most of the bits of each 64B / 66B coding block remain unchanged, that is, the position of each 64B / 66B coding block does not change, thereby greatly simplifying the hardware implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of various types of 64B / 66B coding blocks;

[0025] Figure 2 A schematic diagram of a processing method for converting eight 64B / 66B coding blocks into one 512B / 513B coding block provided for related technology;

[0026] Figure 3 A schematic diagram of a 64B / 66B coded signal processing method provided in an embodiment of the present application;

[0027] Figure 4 A schematic diagram of a 64B / 66B coded signal processing method provided in an embodiment of the present application;

[0028] Figure 5 A schematic diagram of converting eight 64B / 66B coding blocks into one 512B / 513B coding block provided in Embodiment 1 of the present application;

[0029] Figure 6 A schematic diagram of converting eight 64B / 66B coding blocks into one 512B / 513B coding block provided in Embodiment 2 of the present application;

[0030] Figure 7 A schematic diagram of converting eight 64B / 66B coding blocks into one 512B / 513B coding block provided in Example 3 of the present application;

[0031] Figure 8 A schematic diagram of converting eight 64B / 66B coding blocks into one 512B / 513B coding block provided in Embodiment 4 of the present application;

[0032] Fig. 9 A schematic diagram of converting one 512B / 513B coding block into eight 64B / 66B coding blocks provided in Example 5 of the present application;

[0033] Fig.10 A schematic diagram of converting one 512B / 513B coding block into eight 64B / 66B coding blocks provided in Example 6 of the present application;

[0034] Fig.11 A schematic diagram of converting one 512B / 513B coding block into eight 64B / 66B coding blocks provided in Example 7 of the present application;

[0035] Fig.12 A schematic diagram of converting one 512B / 513B coding block into eight 64B / 66B coding blocks provided in Example 8 of the present application;

[0036] Fig.13 A schematic diagram of a 64B / 66B coded signal processing device provided in an embodiment of the present application;

[0037] Fig.14 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to enable those skilled in the art to better understand the technical solution of the present application, the 64B / 66B coded signal processing method, 64B / 66B coded signal processing device, electronic device and computer-readable storage medium provided by the present application are described in detail below in conjunction with the accompanying drawings.

[0039] Hereinafter, example embodiments will be described more fully in conjunction with the accompanying drawings, but the described example embodiments may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make this application thorough and complete, and will enable those skilled in the art to fully understand the scope of this application.

[0040] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] The terms used herein are only used to describe specific embodiments and are not intended to limit the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0042] In the description of the embodiments of the present application, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0043] In the description of the embodiments of the present application, any embodiment or design scheme of "exemplary", "for example" or "for example" should not be understood as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a specific way.

[0044] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "include", "comprises", "has" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present application, and will not be interpreted as having an idealized or excessive formal meaning, unless clearly defined in the present application examples.

[0046] 64B / 66B coding is a physical coding sublayer (PCS) coding established by the IEEE802.3 standard, which is used to convert a media access control frame into a fixed rate signal and can identify the media access control frame and control information. The content of the media access control frame corresponds to the data information. In addition to the content of the media access control frame, 64B / 66B coding also needs to transmit some control information, including the frame header and frame trailer of the media access control frame, idle control information for implementing rate filling, local error (LocalFault) control information or remote error (RemoteFault) control information for indicating a special state of the signal, etc. 64B / 66B coding is implemented by a bit block with a length of 66 bits, which contains a maximum of 64 bits of control information or data information. The bit block based on 64B / 66B coding is called a 64B / 66B coding block, where B represents a bit, and a 64B / 66B coded signal is a signal composed of 64B / 66B coding blocks. The 64B / 66B coding block is divided into a 64B / 66B data coding block and a 64B / 66B control coding block according to whether it contains control information.

[0047] Reference Figure 1 , Figure 1 Schematic diagram of various types of 64B / 66B coding blocks. Figure 1 As shown, the 64B / 66B coding block is a bit block with a length of 66 bits, which can be called a 66-bit block, and the first 2 bits of the 66-bit block can be called a synchronization header. Among them, the 66-bit block with a synchronization header of 01 can be called a 64B / 66B data coding block; the 66-bit block with a synchronization header of 10 can be called a 64B / 66B control coding block. Figure 1 Fifteen types of 64B / 66B control coding blocks are shown in FIG.

[0048] For a 64B / 66B data encoding block, the first to second bits are the synchronization header, the third to the 66th bits are the information field, and the length of the information field is 64 bits, so it can also be called a 64-bit information field. The information field consists of 8 bytes (64 bits) of data characters.

[0049] For a 64B / 66B control coding block, the first to second bits are the synchronization header, the third to tenth bits are the type field, and the length of the type field is 8 bits, so it can also be called an 8-bit type field; the 11th to 66th bits are named the information field, and the length is 56 bits, so it can also be called a 56-bit information field. The last 64 bits of the 64B / 66B control coding block may contain at least one control character, or an ordered set control block, in which a control character is 7 bits long and an ordered set control block is 28 bits long. The specific type of the 64B / 66B control coding block can be determined based on the 8-bit type field.

[0050] In some application scenarios, it is necessary to compress the 64B / 66B coded signal to reduce the signal rate. For example, the 64B / 66B coded signal can be converted into a 256B / 257B coded signal, or the 64B / 66B coded signal can be converted into a 512B / 513B coded signal, wherein the conversion into a 512B / 513B coded signal can obtain better compression efficiency. The 64B / 66B coded signal involved in the embodiment of the present application is a coded signal composed of 64B / 66B coded blocks, the 256B / 257B coded signal is a coded signal composed of 256B / 257B coded blocks, and the 512B / 513B coded signal is a coded signal composed of 512B / 513B coded blocks.

[0051] It is understandable that the conversion of a 64B / 66B coded signal into a 512B / 513B coded signal can be specifically achieved by converting 8 64B / 66B coded blocks into 1 512B / 513B coded block. In the related art, in the conversion process of converting 8 64B / 66B coded blocks into 1 512B / 513B coded block, it is necessary to perform shift processing on the 8 64B / 66B coded blocks according to the specific values ​​of the 2-bit synchronization headers of the 8 64B / 66B coded blocks, and move all 64B / 66B coded blocks starting with 10 to the front, while keeping the relative front and back timings between the 8 64B / 66B coded blocks unchanged, and the shift operation is complex to implement.

[0052] See also Figure 2 , Figure 2 A schematic diagram of a processing method for converting eight 64B / 66B coding blocks into one 512B / 513B coding block is provided for related technology. Figure 2In the figure, on the left are 8 64B / 66B coded blocks that need to be converted, and on the right is a 512B / 513B coded block after conversion. A 512B / 513B coded block can be called a 513-bit block. The first bit in the 513-bit block is the F field, which indicates the header of the 513-bit block. The remaining 512 bits can be divided into 8 64-bit blocks. During the conversion process, the 64 bits in the fifth 64B / 66B coded block of the 8 64B / 66B coded blocks are moved to the first 64-bit position in the 512B / 513B coded block, and the 64 bits in the sixth 64B / 66B coded block of the 8 64B / 66B coded blocks are moved to the 512 The 64 bits in the 7th 64B / 66B coding block among the 8 64B / 66B coding blocks need to be moved to the 3rd 64-bit position in the 512B / 513B coding block. It can be considered that the above movement is equivalent to deleting 3 64 bits in the 8 64B / 66B coding blocks and then adding them to the front. In this way, the number of bits that need to be deleted and added is 192 bits. In this way, a large number of bits need to be deleted and then added in the above conversion, which will make the hardware implementation complicated.

[0053] Based on this, the embodiments of the present application provide a 64B / 66B coded signal processing method, a 64B / 66B coded signal processing device, an electronic device and a computer-readable storage medium, which can reduce the number of bits deleted and added during the conversion process, and can achieve that most of the bits of each 64B / 66B coding block remain unchanged, that is, the position of each 64B / 66B coding block does not change, which greatly simplifies the hardware implementation.

[0054] See also Figure 3 , Figure 3 A schematic diagram of a 64B / 66B coded signal processing method provided in an embodiment of the present application. Figure 3 As shown, the 64B / 66B coded signal processing method includes the following steps.

[0055] Step S110, converting eight 64B / 66B coding blocks into 512B / 513B coding blocks, each 64B / 66B coding block being a 64B / 66B data coding block or a 64B / 66B control coding block.

[0056] The 64B / 66B coded signal described in the embodiment of the present application is composed of 64B / 66B coded blocks.

[0057] Exemplarily, the media access control frame and the control information are encoded into a 66-bit block for transmission. The 66-bit block is a 64B / 66B coding block. A 64B / 66B coding signal is composed of one or more 64B / 66B coding blocks.

[0058] The embodiment of the present application obtains a 64B / 66B coding block from a 64B / 66B coding signal, and then uses eight consecutive 64B / 66B coding blocks as one group of 64B / 66B coding blocks to obtain multiple groups of 64B / 66B coding blocks, and each group of 64B / 66B coding blocks is compressed into a 512B / 513B coding block for transmission, that is, eight 66B data (a total of 528B) are compressed into 513B. It is worth noting that these eight 64B / 66B coding blocks have a sequential order according to the transmission order.

[0059] In one example, the eight 64B / 66B coding blocks are all 64B / 66B data coding blocks. In another example, the eight 64B / 66B coding blocks are all 64B / 66B control coding blocks. In yet another example, the eight 64B / 66B coding blocks include both 64B / 66B data coding blocks and 64B / 66B control coding blocks.

[0060] Among them, the 64B / 66B data coding block refers to the 64B / 66B coding block with a synchronization header of 01, and the 64B / 66B control coding block refers to the 64B / 66B coding block with a synchronization header of 10.

[0061] The first L1 bits of the 512B / 513B coding block provided in the embodiment of the present application are the indication field, and the last L2 bits are the information field. L1 is an integer greater than or equal to 1, L2 is an integer greater than 1, and L2=513-L1.

[0062] The L1 bit indication field described in the embodiment of the present application includes at least one of the following information: the number of 64B / 66B control coding blocks in 8 64B / 66B coding blocks, or the position of the 64B / 66B control coding block in the 8 64B / 66B coding blocks.

[0063] The L2 bit information field described in the embodiment of the present application includes 8 information blocks corresponding to 8 64B / 66B coding blocks one by one, the length of each information block is 64 bits or 60 bits, and the number of bits contained in each information block is determined by the value of the L1 bit indication field.

[0064] Exemplarily, the eight 64B / 66B coding blocks are named in sequence as 64B / 66B coding block #1, 64B / 66B coding block #2, ..., 64B / 66B coding block #8, and the eight information blocks in the L2 bit information domain are named in sequence as information block #1, information block #2, ..., information block #8, where information block #X corresponds to 64B / 66B coding block #X, X=1, 2, ..., 8.

[0065] Exemplarily, the value range of L1 is 1≤L1≤13, and the value range of L2 is 500≤L2≤512.

[0066] Exemplarily, the value of L1 is one of the following: 1, 5, 9 or 13; correspondingly, the value of L2 is one of the following: 512, 508, 504 or 490.

[0067] In an exemplary embodiment, the eight 64B / 66B coding blocks do not include a 64B / 66B control coding block, L1 is equal to 1, and L2 is equal to 512. That is, all of the eight 64B / 66B coding blocks are 64B / 66B data coding blocks, in which case the length of the indication field is 1 bit, and the length of the information field is 512 bits.

[0068] Exemplarily, the 1-bit indication field contains a binary value a1, and the value of a1 can be equal to 0 or 1. In the 512-bit information field, the length of each information block is 64 bits, and each information block contains the value of the last 64 bits of the corresponding 64B / 66B data encoding block.

[0069] Exemplarily, when all of the 8 64B / 66B coding blocks are 64B / 66B data coding blocks, in order to convert the 8 64B / 66B coding blocks into 512B / 513B coding blocks, the first bit of the 512B / 513B coding block is set to a1; the second bit to the 513th bit of the 512B / 513B coding block are divided into 8 64-bit information blocks, and each 64-bit information block is set to the value of the last 64 bits in the corresponding 64B / 66B coding block.

[0070] In an exemplary embodiment, eight 64B / 66B coding blocks include one 64B / 66B control coding block, then L1 is equal to 5, and L2 is equal to 508. That is, when eight 64B / 66B coding blocks have and only have one 64B / 66B control coding block, the length of the indication field is 5 bits, and the length of the information field is 508 bits.

[0071] Exemplarily, in the 5-bit indication field, the first and second bits contain binary values ​​a2a3, where a2 is not equal to the aforementioned a1. For example, when a1 is equal to 1, a2 is equal to 0; or, when a1 is equal to 0, a2 is equal to 1. The value of a3 can be equal to 0 or 1.

[0072] The one and only 64B / 66B control coding block is the Nth 64B / 66B coding block among the 8 64B / 66B coding blocks, where N is an integer greater than or equal to 1 and less than or equal to 8, and the values ​​of the 3rd to 5th bits in the 5-bit indication field are equal to N-1. In this way, the position of the one and only 64B / 66B control coding block among the 8 64B / 66B coding blocks is indicated by the 3rd to 5th bits in the 5-bit indication field.

[0073] Exemplarily, the 1st to 2nd bits in the above-mentioned 5-bit indication field can be used to determine that the subsequent 508-bit information field is composed of 1 60-bit information block and 7 64-bit information blocks, wherein the 60-bit information block is the Nth information block among the 8 information blocks, and the value of N can be determined by the values ​​of the 3rd to 5th bits in the above-mentioned 5-bit indication field.

[0074] Exemplarily, the length of the Nth information block in the information domain is 60 bits, including the values ​​of the 3rd to 6th bits and the values ​​of the 11th to 66th bits of the Nth 64B / 66B coding block, or including the values ​​of the 7th to 66th bits of the Nth 64B / 66B coding block. The length of the remaining information blocks in the information domain except the Nth information block is 64 bits, including the value of the last 64 bits of the corresponding 64B / 66B data coding block.

[0075] It should be noted that for the 64B / 66B control coding block with a synchronization header of 10, its type field actually occupies 8 bits, but the valid information can be represented by 4 bits, so the 8-bit type field can actually be reduced to 4 bits, and different type fields can still be distinguished after being reduced to a 4-bit type field.

[0076] Exemplarily, there are two ways to actually reduce the 8-bit type field to a 4-bit type field.

[0077] Mode 1: By deleting the last 4 bits in the 8-bit type field, the 8-bit type field is converted into a 4-bit type field. For details, please refer to Table 1, which provides the 4-bit type fields corresponding to the 15 8-bit type fields in Mode 1.

[0078] Table 1 The 4-bit type fields corresponding to the 15 8-bit type fields in mode 1

[0079] 8-bit type field 4-bit type field 0x1e 0x1 0x2d 0x2 0x33 0x3 0x4b 0x4 0x55 0x5 0x66 0x6 0x78 0x7 0x87 0x8 0x99 0x9 0xaa 0xa 0xb4 0xb 0xcc 0xc 0xd2 0xd 0xe1 0xe 0xff 0xf

[0080] Mode 2: By deleting the first 4 bits in the 8-bit type field, the 8-bit type field is converted into a 4-bit type field. For details, please refer to Table 2, which exemplarily provides 15 8-bit type fields corresponding to 4-bit type fields.

[0081] Table 2

[0082]

[0083]

[0084] Based on the above embodiments, it can be known that there is compression space for the last 64 bits of the 64B / 66B control coding block, and the last 64 bits of the 64B / 66B control coding block can actually be compressed into 60 bits, which include the 4-bit type field and the 56-bit information field of the 64B / 66B control coding block. The 60-bit information block is composed of the values ​​of the 3rd to 6th bits and the values ​​of the 11th to 66th bits of the corresponding 64B / 66B coding block, or the 60-bit information block is composed of the values ​​of the 7th to 66th bits of the corresponding 64B / 66B coding block.

[0085] In an exemplary embodiment, eight 64B / 66B coding blocks include two 64B / 66B control coding blocks, then L1 is equal to 9, and L2 is equal to 504. That is, when eight 64B / 66B coding blocks have and only have two 64B / 66B control coding blocks, the length of the indication field is 9 bits, and the length of the information field is 504 bits.

[0086] Exemplarily, in the 9-bit indication field, the first to third bits contain binary values ​​a2a4a5, where a4 is not equal to the aforementioned a3, for example, when a3 is equal to 0, a4 is equal to 1; or, when a3 is equal to 1, a4 is equal to 0. The value of a5 can be equal to 0 or 1.

[0087] Exemplarily, the only two 64B / 66B control coding blocks are the N1th 64B / 66B coding block and the N2th 64B / 66B coding block among the eight 64B / 66B coding blocks, wherein N1 and N2 are both integers greater than or equal to 1 and less than or equal to 8, and N1 is less than N2. In this case, in the 9-bit indication field, the values ​​of the 4th to 6th bits are equal to N1-1, and the values ​​of the 7th to 9th bits in the indication field are equal to N2-1.

[0088] Exemplarily, the 1st to 3rd bits in the above-mentioned 9-bit indication field can be used to determine that the subsequent 504-bit information field is composed of 2 60-bit information blocks and 6 64-bit information blocks, wherein the 2 60-bit information blocks are the N1th information block and the N2th information block in the 8 information blocks, the value of N1 can be determined by the values ​​of the 4th to 6th bits in the above-mentioned 9-bit indication field, and the value of N2 can be determined by the values ​​of the 7th to 9th bits in the above-mentioned 9-bit indication field.

[0089] Exemplarily, the length of the N1th information block in the information domain is 60 bits, including the values ​​of the 3rd to 6th bits and the values ​​of the 11th to 66th bits of the N1th 64B / 66B coding block, or, including the values ​​of the 7th to 66th bits of the N1th 64B / 66B coding block. The length of the N2th information block in the information domain is 60 bits, including the values ​​of the 3rd to 6th bits and the values ​​of the 11th to 66th bits of the N2th 64B / 66B coding block, or, including the values ​​of the 7th to 66th bits of the N2th 64B / 66B coding block. The length of the remaining information blocks in the information domain except the N1th and N2th information blocks is 64 bits, including the value of the last 64 bits of the corresponding 64B / 66B data coding block.

[0090] In an exemplary embodiment, 8 64B / 66B coding blocks include at least 3 64B / 66B control coding blocks, then L1 is equal to 13, and L2 is equal to 500. That is, when 8 64B / 66B coding blocks include 3 or more 64B / 66B control coding blocks, the length of the indication field is 13 bits, and the length of the information field is 500 bits.

[0091] Exemplarily, the first to fifth bits of the 13-bit indication field contain binary values ​​a2a4a6a7a8, where a6 is not equal to the aforementioned a5, for example, when a5 is equal to 1, a6 is equal to 0; or, when a5 is equal to 0, a6 is equal to 1. The values ​​of a7 and a8 can be equal to 0 or 1, respectively.

[0092] Exemplarily, the 6th to 13th bits in the 13-bit indication field correspond to the value of the first bit of the eight 64B / 66B coding blocks. Alternatively, the 6th to 13th bits in the 13-bit indication field correspond to the value of the second bit of the eight 64B / 66B coding blocks.

[0093] Exemplarily, the above 500-bit information domain includes 3 60-bit information blocks and 5 64-bit information blocks, wherein the 3 60-bit information blocks correspond to the first 3 64B / 66B control coding blocks among the 8 64B / 66B coding blocks. Exemplarily, the information blocks corresponding to the first 3 64B / 66B control coding blocks are 60 bits long, respectively including the values ​​of the 3rd to 6th bits and the values ​​of the 11th to 66th bits of the corresponding 64B / 66B control coding blocks, or including the values ​​of the 7th to 66th bits of the corresponding 64B / 66B control coding blocks. The lengths of the remaining information blocks in the information domain, except for the information blocks corresponding to the first 3 64B / 66B control coding blocks, are all 64 bits long, including the values ​​of the last 64 bits of the corresponding 64B / 66B coding blocks.

[0094] In an embodiment of the present application, when there are k (k is greater than or equal to 1, and less than or equal to 8) 64B / 66B control coding blocks in 8 64B / 66B coding blocks, m 64B / 66B control coding blocks in the k 64B / 66B control coding blocks are compressed from 66 bits to 60 bits, where m is less than or equal to k, thereby achieving the purpose of saving information domain overhead. The information domain overhead thus saved can be used for the indication domain, so that the indication domain has sufficient bits to store the quantity indication information and position indication information of the control coding blocks.

[0095] Step S120, compose a 512B / 513B coded signal from the 512B / 513B coded blocks.

[0096] Step S130, sending 512B / 513B encoded signal.

[0097] Exemplarily, by converting eight 64B / 66B coding blocks into one 512B / 513B coding block, the service signal or the control information of the service signal is converted into a 512B / 513B coding format, thereby obtaining a 512B / 513B coded signal composed of 512B / 513B coding blocks, which is equivalent to converting a 64B / 66B coded signal into a 512B / 513B coded signal, and then transmitting the 512B / 513B coded signal.

[0098] In an embodiment of the present application, a 64B / 66B coded signal is converted into a 512B / 513B coded signal, and the 512B / 513BB coded signal is loaded into a service signal for transmission. Compared with directly loading the 64B / 66B coded signal into the service signal, the rate of the service signal is lower, which is equivalent to reducing the rate of the service signal. At the receiving end, the 512B / 513B coded signal can be extracted from the service signal according to the position information of the 512B / 513B coded block specified in the offset overhead storing the 512B / 513B coded signal in the service signal, and the 512B / 513B coded signal is converted into a 64B / 66B coded signal, thereby realizing the transmission of the 64B / 66B coded signal. When the 64B / 66B coded signal is restored from the 512B / 513B coded signal, the transmission rate of the 64B / 66B coded signal can also be restored, thereby realizing the transmission of a high-speed coded signal using a low-speed service signal.

[0099] The embodiments of the present application do not specifically limit how to send the service signal. In some embodiments, the service signal can be sent directly. In some embodiments, the service signal can be sent indirectly. It should be noted that indirect sending means that the service signal is packed into other signals and sent.

[0100] In some embodiments, the service signal is an optical channel data unit signal, and sending the service signal includes: sending the optical channel data unit signal.

[0101] The embodiment of the present application does not specifically limit how to send the optical channel data unit signal.

[0102] In some embodiments, an optical channel data unit signal is loaded into a payload of an optical channel data unit signal of a higher rate, and then the optical channel data unit signal of the higher rate is converted into an optical channel transport unit (OTU) signal, and the optical channel transport unit signal is transmitted in an optical transport network. For example, an optical channel data unit-0 signal is loaded into a 512B / 513B encoded signal, the optical channel data unit-0 signal is loaded into a payload of an optical channel data unit-4 signal, the optical channel data unit-4 signal is converted into an optical channel transport unit-4 signal, and the optical channel transport unit-4 signal is transmitted in an optical transport network.

[0103] In some embodiments, the optical channel data unit signal is converted into an optical channel transport unit signal, and the optical channel transport unit signal is transmitted in the optical transport network. For example, the optical channel data unit-2 signal is loaded with a 512B / 513B encoded signal, the optical channel data unit-2 signal is converted into an optical channel transport unit-2 signal, and the optical channel transport unit-2 signal is transmitted in the optical transport network.

[0104] In some embodiments, the OCU signal is loaded into the payload of the OCU-Cn signal, and then the OCU-Cn signal is converted into the OCU-Cn signal, and the OCU-Cn signal is loaded into other signals for transmission in the optical transport network. For example, the OCU-4 signal is loaded into the 512B / 513B encoded signal, the OCU-4 signal is loaded into the payload of the OCU-C2 signal, the OCU-C2 signal is converted into the OCU-C2 signal, and the OCU-C2 signal is loaded into the Flexible Optical Transport Network (FlexO) signal for transmission in the optical transport network.

[0105] The embodiment of the present application does not specifically limit how to load the 512B / 513B encoded signal into the service signal.

[0106] See also Figure 4 , Figure 4 A schematic diagram of a 64B / 66B coded signal processing method provided in an embodiment of the present application. Figure 4 As shown, the 64B / 66B coded signal processing method includes the following steps.

[0107] Step S210, receiving a 512B / 513B encoded signal.

[0108] Step S220, converting the 512B / 513B coding block in the 512B / 513B coding signal into eight 64B / 66B coding blocks, and the 64B / 66B coding blocks form a 64B / 66B coding signal.

[0109] Exemplarily, after receiving a 512B / 513B coded signal, the network node can use the 512B / 513B coded signal to recover a 64B / 66B coded signal, so that the transmission rate of the 64B / 66B coded signal can also be recovered, thereby enabling the transmission of a high-rate coded signal using a low-rate service signal.

[0110] Exemplarily, converting a 512B / 513B coded signal into a 64B / 66B coded signal is achieved by converting one 512B / 513B coded block into eight 64B / 66B coded blocks.

[0111] In an exemplary embodiment, the first bit of the 512B / 513B coding block is equal to the binary value a1, and the 512B / 513B coding block is converted into eight 64B / 66B coding blocks, including:

[0112] Step S310: divide the last 512 bits of the 512B / 513B coding block into 8 information blocks, each of which has a length of 64 bits.

[0113] Step S320, adding a synchronization header 01 before each information block in turn, to obtain a 64B / 66B coding block corresponding to each information block.

[0114] In an exemplary embodiment, the first bit to the second bit of the 512B / 513B coding block are equal to the binary value a2a3, and the 512B / 513B coding block is converted into eight 64B / 66B coding blocks, including:

[0115] Step S410, determining the value of N-1 according to the 3rd to 5th bits of the 512B / 513B coding block, where N is an integer greater than or equal to 1 and less than or equal to 8.

[0116] Step S420: divide the last 508 bits of the 512B / 513B coding block into 8 information blocks, wherein the length of the Nth information block is 60 bits, and the lengths of the remaining information blocks are all 64 bits.

[0117] Step S430, determining the 8-bit type field corresponding to the Nth information block according to the 1st to 4th bits of the Nth information block, and then adding 4 bits after the 4th bit of the Nth information block, or adding 4 bits before the 1st bit of the Nth information block.

[0118] Step S440, adding a synchronization header before each information block in turn to obtain a 64B / 66B coding block corresponding to each information block, wherein the synchronization header added before the Nth information block is 10, and the synchronization headers added before the remaining information blocks are 01.

[0119] Exemplarily, in the process of converting 8 64B / 66B coding blocks into 512B / 513B coding blocks, a 64B / 66B control coding block in the 8 64B / 66B coding blocks is compressed into a 60-bit information block, and one optional method is to delete the last 4 bits of the type field in the 64B / 66B control coding block. Correspondingly, when it is necessary to restore the 60-bit information block to a 64B / 66B control coding block, the corresponding 4 bits can be added after the 4th bit of the 60-bit information block, thereby restoring the original 8-bit type field of the 64B / 66B control coding block.

[0120] Exemplarily, in the process of converting eight 64B / 66B coding blocks into 512B / 513B coding blocks, a 64B / 66B control coding block in the eight 64B / 66B coding blocks is compressed into a 60-bit information block, and one optional method is to delete the first 4 bits of the type field in the 64B / 66B control coding block. Correspondingly, when it is necessary to restore the 60-bit information block to a 64B / 66B control coding block, the corresponding 4 bits can be added before the first bit of the 60-bit information block, thereby restoring the original 8-bit type field of the 64B / 66B control coding block.

[0121] In an exemplary embodiment, the first to third bits of the 512B / 513B coding block are equal to the binary value a2a4a5, and the 512B / 513B coding block is converted into eight 64B / 66B coding blocks, including:

[0122] Step S510, determine the value of N1-1 according to the 4th to 6th bits of the 512B / 513B coding block, and determine the value of N2-1 according to the 7th to 9th bits of the 512B / 513B coding block, where N1 and N2 are both integers greater than or equal to 1 and less than or equal to 8, and N1 is less than N2.

[0123] Step S520: divide the last 504 bits of the 512B / 513B coding block into 8 information blocks, wherein the lengths of the N1th and N2th information blocks are 60 bits, and the lengths of the remaining information blocks are all 64 bits.

[0124] Step S530, determine the 8-bit type field corresponding to the N1th information block according to the values ​​of the 1st to 4th bits of the N1th information block, and then add 4 bits after the 4th bit of the N1th information block, or add 4 bits before the 1st bit of the N1th information block.

[0125] Step S540, determine the 8-bit type field corresponding to the N2th information block according to the values ​​of the 1st to 4th bits of the N2th information block, and then add 4 bits after the 4th bit of the N2th information block, or add 4 bits before the 1st bit of the N2th information block.

[0126] Step S550, adding a synchronization header before each information block in turn to obtain a 64B / 66B coding block corresponding to each information block, wherein the synchronization header added before the N1th and N2th information blocks is 10, and the synchronization header added before the remaining information blocks is 01.

[0127] In an exemplary embodiment, the first to fifth bits of the 512B / 513B coding block are equal to the binary value a2a4a6a7a8, and the 512B / 513B coding block is converted into eight 64B / 66B coding blocks, including:

[0128] Step S610, determining, according to the 6th to 13th bits of the 512B / 513B coding block, that eight 64B / 66B coding blocks correspond to 64B / 66B data coding blocks or 64B / 66B control coding blocks respectively.

[0129] Step S620: According to the positions of the first three 64B / 66B control coding blocks, the last 500 bits of the 512B / 513B coding block are divided into eight information blocks, wherein the eight information blocks include five information blocks with a length of 64 bits and three information blocks with a length of 60 bits, wherein the first three 64B / 66B control coding blocks among the eight 64B / 66B coding blocks correspond to information blocks of 60 bits, and the remaining 64B / 66B coding blocks correspond to information blocks of 64 bits.

[0130] Step S630, for the information blocks corresponding to the first three 64B / 66B control coding blocks, determine the 8-bit type field corresponding to the information block according to the values ​​of the 1st to 4th bits of the information block, add 4 bits after the 4th bit of the information block, or add 4 bits before the 1st bit of the information block.

[0131] Step S640, adding a synchronization header before each information block in turn to obtain a 64B / 66B coding block corresponding to each information block, wherein the synchronization header added before the information block corresponding to the 64B / 66B control coding block is 10, and the synchronization header added before the information block corresponding to the 64B / 66B data coding block is 01.

[0132] In an exemplary embodiment, if the 1st to 3rd bits of the 512B / 513B coding block are equal to a2a4a6, and the 4th to 5th bits are not equal to a7a8, the 512B / 513B coding block is converted into 8 64B / 66B control coding blocks representing error information, wherein the type field of the 64B / 66B control coding block representing the error information is 0x1e, and the information field of the 64B / 66B control coding block representing the error information is 8 7-bit 0x1e.

[0133] In order to better understand the solutions of the embodiments of the present application, specific embodiments are provided below for explanation.

[0134] Example 1

[0135] In one embodiment, the values ​​of the synchronization headers of the eight 64B / 66B coding blocks are all 01. In order to convert the eight 64B / 66B coding blocks into one 512B / 513B coding block, the following processing is performed according to the values ​​of the eight synchronization headers of the eight 64B / 66B coding blocks:

[0136] Since the values ​​of the synchronization headers of the eight 64B / 66B coding blocks are all 01, the first bit of the 512B / 513B coding block is set to 1, and the eight synchronization headers of the eight 64B / 66B coding blocks are removed to obtain 512 bits; the 512 bits are set to the second bit to the 513th bit of the 512B / 513B coding block, and the relative positions of the eight 64B / 66B coding blocks remain unchanged.

[0137] Specifically, the synchronization header of the first 64B / 66B coding block is deleted to obtain 64 bits, and the 64 bits are set to the 2nd bit to the 65th bit of the 512B / 513B coding block; the synchronization header of the second 64B / 66B coding block is deleted to obtain 64 bits, and the 64 bits are set to the 66th bit to the 129th bit of the 512B / 513B coding block; the synchronization header of the third 64B / 66B coding block is deleted to obtain 64 bits, and the 64 bits are set to the 130th bit to the 193rd bit of the 512B / 513B coding block; the synchronization header of the fourth 64B / 66B coding block is deleted to obtain 64 bits, and the 64 bits are set to the 194th bit to the 257th bit of the 512B / 513B coding block; The synchronization header of the fifth 64B / 66B coding block is deleted to obtain 64 bits, and the 64 bits are set to the 258th bit to the 321st bit of the 512B / 513B coding block; the synchronization header of the sixth 64B / 66B coding block is deleted to obtain 64 bits, and the 64 bits are set to the 322nd bit to the 385th bit of the 512B / 513B coding block; the synchronization header of the seventh 64B / 66B coding block is deleted to obtain 64 bits, and the 64 bits are set to the 386th bit to the 449th bit of the 512B / 513B coding block; the synchronization header of the eighth 64B / 66B coding block is deleted to obtain 64 bits, and the 64 bits are set to the 450th bit to the 513th bit of the 512B / 513B coding block.

[0138] The above conversion process is as follows Figure 5 shown. Figure 5 In the figure, the synchronization header of each 64B / 66B coding block is 01, and the 64-bit information field of each 64B / 66B coding block is represented by Xp-1 to Xp-64, where p is an integer, p takes a value from 1 to 8, and p represents the p-th 64B / 66B coding block among the 8 64B / 66B coding blocks. For example, X1-1 to X1-64 represent the 64 bits of the 64-bit information field of the first 64B / 66B coding block, where X1-1 represents the first bit in the 64-bit information field of the first 64B / 66B coding block, and X1-64 represents the 64th bit in the 64-bit information field of the first 64B / 66B coding block. The first bit of the 512B / 513B coding block is 1, which means that the 512B / 513B coding block contains 8 64B / 66B coding blocks with synchronization headers of 01. At this time, the second to 513th bits store the 64-bit information field of the 8 64B / 66B coding blocks with synchronization headers of 01.

[0139] Example 2

[0140] In one embodiment, only one of the eight 64B / 66B coding blocks has a synchronization header value of 10. In order to convert the eight 64B / 66B coding blocks into one 512B / 513B coding block, the following processing is performed according to the values ​​of the eight synchronization headers of the eight 64B / 66B coding blocks:

[0141] Since the value of the synchronization header of only one coding block among the eight 64B / 66B coding blocks is 10, and assuming that the synchronization header of the Nth 64B / 66B coding block is 10, and N is an integer greater than or equal to 1 and less than or equal to 8, the first bit of the 512B / 513B coding block is set to 0, and the second bit of the 512B / 513B coding block is set to 0; the values ​​of the third bit to the fifth bit of the 512B / 513B coding block are set to be equal to the decimal value N-1; the eight synchronization headers of the eight 64B / 66B coding blocks are removed to obtain 512 bits, and the relative positions of the eight 64B / 66B coding blocks remain unchanged; the last 4 bits of the type field of the Nth 64B / 66B coding block are deleted to obtain 508 bits; and the sixth bit to the 513th bit of the 512B / 513B coding block are set to this 508 bits.

[0142] Here are some examples:

[0143] Among the 8 64B / 66B coding blocks, the synchronization header of the fifth 64B / 66B coding block is 10, and the synchronization headers of the remaining 7 64B / 66B coding blocks are all 01, so N is 5. The conversion process is as follows Figure 6 shown. Figure 6In the example, the first bit and the second bit of the 512B / 513B coding block are both 0, where the first bit is 0, indicating that the 512B / 513B coding block contains at least one 64B / 66B coding block with a synchronization header of 10, and the second bit is 0, indicating that the 512B / 513B coding block contains a 64B / 66B coding block with a synchronization header of 10. Since N is 5, N-1 is placed from the 3rd bit to the 5th bit of the 512B / 513B coding block, so the 3rd bit to the 5th bit of the 512B / 513B coding block is The special bit is set to 4; the synchronization header of the first 64B / 66B coding block is deleted to obtain 64 bits, and the 64 bits are set to the 6th to 69th bits of the 512B / 513B coding block; the synchronization header of the second 64B / 66B coding block is deleted to obtain 64 bits, and the 64 bits are set to the 70th to 133rd bits of the 512B / 513B coding block; the synchronization header of the third 64B / 66B coding block is deleted to obtain 64 bits, and the 64 bits are set to the 13th bit of the 512B / 513B coding block 4 to 197 bits; delete the synchronization header of the 4th 64B / 66B coding block to obtain 64 bits, and set the 64 bits to the 198th to 261st bits of the 512B / 513B coding block; delete the synchronization header of the 5th 64B / 66B coding block, and delete the last 4 bits in the type field to obtain 60 bits, and set the 60 bits to the 262nd to 321st bits of the 512B / 513B coding block, where the 262nd to 265th bits are the 4-bit type field; The synchronization header of the 64B / 66B coding block is deleted to obtain 64 bits, and the 64 bits are set to the 322nd to 385th bits of the 512B / 513B coding block; the synchronization header of the 7th 64B / 66B coding block is deleted to obtain 64 bits, and the 64 bits are set to the 386th to 449th bits of the 512B / 513B coding block; the synchronization header of the 8th 64B / 66B coding block is deleted to obtain 64 bits, and the 64 bits are set to the 450th to 513th bits of the 512B / 513B coding block.

[0144] Example 3

[0145] In one embodiment, only the synchronization header value of two of the eight 64B / 66B coding blocks is 10. In order to convert the eight 64B / 66B coding blocks into one 512B / 513B coding block, the following processing is performed according to the values ​​of the eight synchronization headers of the eight 64B / 66B coding blocks:

[0146] Since only two of the eight 64B / 66B coding blocks have a synchronization header value of 10, the first 64B / 66B coding block with a synchronization header value of 10 is located in the N1th 64B / 66B coding block among the eight 64B / 66B coding blocks, N1 is an integer greater than or equal to 1 and less than or equal to 8, and the second 64B / 66B coding block with a synchronization header value of 10 is located in the N2th 64B / 66B coding block among the eight 64B / 66B coding blocks, N2 is an integer greater than or equal to 1 and less than or equal to 8, and N2 is greater than N1, then the first bit of the 512B / 513B coding block is set to 0; Set the second bit to the third bit of the 512B / 513B coding block to 10; set the fourth bit to the sixth bit of the 512B / 513B coding block to N1-1; set the seventh bit to the ninth bit of the 512B / 513B coding block to N2-1; remove the eight synchronization headers from the eight 64B / 66B coding blocks to obtain 512 bits, and keep the relative positions of the eight 64B / 66B coding blocks unchanged; delete the last four bits of the type field of the N1th and N2th 64B / 66B coding blocks to obtain 504 bits; set the tenth bit to the 513th bit of the 512B / 513B coding block to these 504 bits.

[0147] Here are some examples:

[0148] Among the 8 64B / 66B coding blocks, the synchronization header value of 2 64B / 66B coding blocks is 10. The positions of the 2 64B / 66B coding blocks with synchronization header value 10 are the third and fifth respectively in the 8 64B / 66B coding blocks. Then N1 is equal to 3 and N2 is equal to 5, that is, N1 corresponds to the position of the first 64B / 66B coding block with synchronization header value 10 in the 8 64B / 66B coding blocks, and N2 corresponds to the position of the second 64B / 66B coding block with synchronization header value 10 in the 8 64B / 66B coding blocks. At this time, the conversion process is as follows: Figure 7 As shown, Figure 7In the example, the first bit of the 512B / 513B coding block is 0, indicating that the 512B / 513B coding block contains at least one 64B / 66B coding block with a synchronization header of 10. The second to third bits of the 512B / 513B coding block are 10, indicating that the 512B / 513B coding block contains two 64B / 66B coding blocks with synchronization headers of 10. The fourth to sixth bits of the 512B / 513B coding block are N1-1, and the seventh to ninth bits are N2-1. Here, since N1 is 3, the fourth to sixth bits of the 512B / 513B coding block are set to 2; since N2 is 5, the seventh to ninth bits of the 512B / 513B coding block are set to 4. The last 64 bits of 8 64B / 66B coding blocks are arranged in sequence to obtain 512 bits. The 512 bits are divided into 8 groups, each group corresponds to the last 64 bits of 1 64B / 66B coding block, and the 5th to 8th bits of the 64 bits of the N1th group are deleted to obtain 60 bits. The 5th to 8th bits of the 64 bits of the N2th group are deleted to obtain 60 bits, so that 504 bits are obtained. The 10th bit to the 513th bit of the 512B / 513B coding block are set to these 504 bits.

[0149] Example 4

[0150] In one embodiment, among eight 64B / 66B coding blocks, the value of the synchronization header of m (m is an integer greater than or equal to 3 and less than or equal to 8) coding blocks is 10. In order to convert eight 64B / 66B coding blocks into one 512B / 513B coding block, the following processing is performed according to the values ​​of eight synchronization headers of eight 64B / 66B coding blocks:

[0151] If the value of the synchronization header of m 64B / 66B coding blocks among 8 synchronization headers is 10, and m is an integer greater than or equal to 3 and less than or equal to 8, the first 64B / 66B coding block with the synchronization header of 10 is located at the N1th 64B / 66B coding block among the 8 64B / 66B coding blocks, and N1 is an integer greater than or equal to 1 and less than or equal to 8; the second 64B / 66B coding block with the synchronization header of 10 is located at the N2th 64B / 66B coding block among the 8 64B / 66B coding blocks, N2 is an integer greater than or equal to 1 and less than or equal to 8, and N2 is greater than N1; the third 64B / 66B coding block with the synchronization header of 10 is located at the N3th 64B / 66B coding block among the 8 64B / 66B coding blocks, N3 is an integer greater than or equal to 1 and less than or equal to 8, and N3 is greater than N2. In this case, the first bit of the 512B / 513B coding block is set to 0, the second bit to the fifth bit of the 512B / 513B coding block are set to 1100, and the sixth bit to the thirteenth bit of the 512B / 513B coding block are set to the second bit of eight 64B / 66B coding blocks respectively; eight synchronization headers are removed from eight 64B / 66B coding blocks to obtain 512 bits, the relative positions of the eight 64B / 66B coding blocks are kept unchanged, and the last four bits of the type fields of the N1th, N2th and N3th 64B / 66B coding blocks are deleted to obtain 500 bits; the 14th to the 513th bits of the 512B / 513B coding block are set to these 500 bits.

[0152] Here are some examples:

[0153] If the synchronization header value of 4 64B / 66B coding blocks among the 8 synchronization headers is 10, that is, m is equal to 4, and the positions of the 4 64B / 66B coding blocks with the synchronization header value of 10 are the 3rd, 5th, 7th, and 8th among the 8 64B / 66B coding blocks, then N1 is equal to 3, N2 is equal to 5, and N3 is equal to 7, that is, N1 corresponds to the first 64B / 66B coding block with the synchronization header of 10, N2 corresponds to the second 64B / 66B coding block with the synchronization header of 10, and N3 corresponds to the third 64B / 66B coding block with the synchronization header of 10. In this case, the conversion process is as follows: Figure 8 As shown, Figure 8In the example, the first bit of the 512B / 513B coding block is 0, indicating that the 512B / 513B coding block contains at least one 64B / 66B coding block with a synchronization header of 10; the second to fifth bits of the 512B / 513B coding block are 1100, indicating that the 512B / 513B coding block contains at least three 64B / 66B coding blocks with synchronization headers of 10; the sixth to thirteenth bits of the 512B / 513B coding block correspond to the second bits of the eight 64B / 66B coding blocks in sequence; the eight 64B / 66B The last 64 bits of the coding block are arranged in sequence to obtain 512 bits. The 512 bits are divided into 8 groups, each group corresponds to the last 64 bits of a 64B / 66B coding block, and the 5th to 8th bits are deleted from the 64 bits of the N1th group to obtain 60 bits, the 5th to 8th bits are deleted from the 64 bits of the N2th group to obtain 60 bits, and the 5th to 8th bits are deleted from the 64 bits of the N3th group to obtain 60 bits, so as to obtain 500 bits; the 14th bit to the 513th bit of the 512B / 513B coding block are set to these 500 bits.

[0154] Example 5

[0155] In one embodiment, in order to convert one 512B / 513B coding block into eight 64B / 66B coding blocks, the following processing is performed according to the value of the first 13 bits of the 512B / 513B coding block:

[0156] If the first bit of the 512B / 513B coding block is 1, the synchronization headers of the eight converted 64B / 66B coding blocks are all set to 01, and the second bit to the 513th bit of the 512B / 513B coding block are sequentially set to the 64-bit information fields of the eight 64B / 66B coding blocks, specifically including: setting the second bit to the 65th bit of the 512B / 513B coding block as the 64-bit information field of the first 64B / 66B coding block; setting the 66th bit to the 129th bit of the 512B / 513B coding block as the 64-bit information field of the second 64B / 66B coding block; setting the 130th bit to the 193rd bit of the 512B / 513B coding block as the 64-bit information field of the third 64B / 66B coding block; setting The 194th to 257th bits of the 512B / 513B coding block are set as the 64-bit information field of the 4th 64B / 66B coding block; the 258th to 321st bits of the 512B / 513B coding block are set as the 64-bit information field of the 5th 64B / 66B coding block; the 322nd to 385th bits of the 512B / 513B coding block are set as the 64-bit information field of the 6th 64B / 66B coding block; the 386th to 449th bits of the 512B / 513B coding block are set as the 64-bit information field of the 7th 64B / 66B coding block; the 450th to 513th bits of the 512B / 513B coding block are set as the 64-bit information field of the 8th 64B / 66B coding block. The above conversion process is as follows Fig. 9 As shown, Fig. 9 In the 512B / 513 coding block, the first bit is 1, the second to the 513th bits are represented by y-2 to y-513, and yq represents the qth bit in the 512B / 513 coding block, where q is an integer greater than or equal to 1 and less than or equal to 513. The first bit of the 512B / 513B coding block is 1, indicating that the 512B / 513B coding block contains 8 64B / 66B coding blocks with synchronization headers of 01. In this case, the second to the 513th bits store the 64-bit information field of the 8 64B / 66B coding blocks with synchronization headers of 01.

[0157] Example 6

[0158] In one embodiment, in order to convert one 512B / 513B coding block into eight 64B / 66B coding blocks, the following processing is performed according to the value of the first 13 bits of the 512B / 513B coding block:

[0159] If the first bit to the second bit of the 512B / 513B coding block is 00, the synchronization header of the Nth 64B / 66B coding block among the eight 64B / 66B coding blocks after conversion is set to 10, and the synchronization headers of the remaining seven 64B / 66B coding blocks are set to 01, where N is an integer greater than or equal to 1 and less than or equal to 8, and N-1 is located at the third to fifth bits of the 512B / 513B coding block, that is, the value represented by the third to fifth bits of the 512B / 513B coding block plus 1 is taken as N; the 512B / 513B coding The 6th bit to the 513th bit of the code block are arranged in sequence into 508 bits, and 4 bits are added after the (N-1)*64+4th bit in the 508 bits. The content of the added 4 bits is determined according to the content of the 4 bits before the adding position. Since the 4 bits before the adding position correspond to the (N-1)*64+1th bit to the (N-1)*64+4th bit in the 508 bits, the added 4-bit content is obtained according to the above 4-bit content and Table 3. Table 3 shows the correspondence between the 4-bit content before the adding position and the added 4-bit content. After adding 4 bits, 512 bits are obtained; the 512 bits are set in sequence as the 3rd to 66th bits of 8 64B / 66B coding blocks, specifically including: setting the 1st to 64th bits of the 512 bits as the 3rd to 66th bits of the first 64B / 66B coding block; setting the 65th to 128th bits of the 512 bits as the 3rd to 66th bits of the second 64B / 66B coding block; setting the 129th to 192nd bits of the 512 bits as the 3rd to 66th bits of the third 64B / 66B coding block; setting the 193rd to 256th bits of the 512 bits as The 3rd to 66th bits of the 4th 64B / 66B coding block are set; the 257th to 320th bits of the 512 bits are set as the 3rd to 66th bits of the 5th 64B / 66B coding block; the 321st to 384th bits of the 512 bits are set as the 3rd to 66th bits of the 6th 64B / 66B coding block; the 385th to 448th bits of the 512 bits are set as the 3rd to 66th bits of the 7th 64B / 66B coding block; the 449th to 512th bits of the 512 bits are set as the 3rd to 66th bits of the 8th 64B / 66B coding block.

[0160] In the above conversion process, the first bit to the second bit of the 512B / 513B coding block is 00, indicating that the 512B / 513B coding block contains a 64B / 66B coding block with a synchronization header of 10, and the third bit to the fifth bit of the 512B / 513B coding block indicates that the 64B / 66B coding block with a synchronization header of 10 is located in the Nth 64B / 66B coding block among the eight 64B / 66B coding blocks, where N is equal to the value represented by the third bit to the fifth bit of the 512B / 513B coding block plus 1.

[0161] Table 3

[0162]

[0163]

[0164] The following example illustrates the above conversion process:

[0165] Fig.10 This is an example of converting one 512B / 513B coding block into eight 64B / 66B coding blocks. The first to second bits of the 512B / 513B coding block are 00, and the third to fifth bits are 2. Since the third to fifth bits of the 512B / 513B coding block are 2, and N is equal to the value of the third to fifth bits of the 512B / 513B coding block plus 1, N is equal to 3. That is, among the eight 64B / 66B coding blocks obtained by conversion, the synchronization header of the third 64B / 66B coding block is 10, and the synchronization headers of the remaining seven 64B / 66B coding blocks are 01. The 6th to 513th bits of the 512B / 513B coding block are arranged in sequence into 508 bits, and 4 bits are added after the (N-1)*64+4th bit in the 508 bits. Since N is equal to 3, it is equivalent to adding 4 bits after the 132nd bit in the 508 bits, that is, it is equivalent to adding 4 bits after the 137th bit of the 512B / 513B coding block. It is necessary to add 4 bits according to the contents of the (N-1)*64+1th to (N-1)*64+4th bits in the 508 bits, that is, it is equivalent to adding 4 bits according to the contents of the 134th to 137th bits in the 512B / 513B coding block. Fig.10 In the figure, 4 bits Z-1 to Z-4 are added after y-134 to y-137, so that 512 bits are obtained. These 512 bits are used as the 3rd to 66th bits in 8 64B / 66B coding blocks in turn, where Z-1 to Z-4 are obtained by looking up y-134 to y-137 in Table 3.

[0166] Example 7

[0167] In one embodiment, in order to convert one 512B / 513B coding block into eight 64B / 66B coding blocks, the following processing is performed according to the value of the first 13 bits of the 512B / 513B coding block:

[0168] If the first bit to the third bit of the 512B / 513B coding block is 010, the synchronization headers of the N1th and N2th 64B / 66B coding blocks among the eight 64B / 66B coding blocks after conversion are set to 10, and the synchronization headers of the remaining six 64B / 66B coding blocks are set to 01, wherein N1 and N2 are both integers greater than or equal to 1 and less than or equal to 8, and N2 is greater than N1, the 4th to 6th bits of the 512B / 513B coding block can determine the value of N1-1, and the 7th to 9th bits of the 512B / 513B coding block can determine the value of N2-1, that is, the value represented by the 4th to 6th bits of the 512B / 513B coding block plus 1 is used as N1, and the value represented by the 7th to 9th bits of the 512B / 513B coding block plus 1 is used as N2; the 4th to 6th bits of the 512B / 513B coding block are used as N2. The 10th bit to the 513th bit are arranged in sequence into 504 bits. In the 504 bits, 4 bits are added after the (N1-1)*64+4th bit, and the content of the added 4 bits is determined according to the content of the 4 bits before the adding position. Since the 4 bits before the adding position correspond to the (N1-1)*64+1th bit to the (N1-1)*64+4th bit in the 504 bits, the content of the added 4 bits is obtained according to the above 4-bit content and Table 3; at the same time, 4 bits need to be added after the (N2-1)*64th bit, and the content of the added 4 bits is determined according to the content of the 4 bits before the adding position. Since the 4 bits before the adding position correspond to the (N2-1)*64-3th bit to the (N2-1)*64th bit in the 504 bits, the content of the added 4 bits is obtained according to the above 4-bit content and Table 3. After adding 8 bits in total, 512 bits are obtained, and the 512 bits are set in sequence as the 3rd to 66th bits of the 8 64B / 66B coding blocks, specifically including: setting the 1st to 64th bits of the 512 bits as the 3rd to 66th bits of the first 64B / 66B coding block; setting the 65th to 128th bits of the 512 bits as the 3rd to 66th bits of the second 64B / 66B coding block; setting the 129th to 192nd bits of the 512 bits as the 3rd to 66th bits of the third 64B / 66B coding block; setting the 193rd to 256th bits of the 512 bits as the 3rd to 66th bits of the third 64B / 66B coding block; The 512 bits are specially set to the 3rd to 66th bits of the 4th 64B / 66B coding block; the 257th to 320th bits of the 512 bits are set to the 3rd to 66th bits of the 5th 64B / 66B coding block; the 321st to 384th bits of the 512 bits are set to the 3rd to 66th bits of the 6th 64B / 66B coding block; the 385th to 448th bits of the 512 bits are set to the 3rd to 66th bits of the 7th 64B / 66B coding block; the 449th to 512th bits of the 512 bits are set to the 3rd to 66th bits of the 8th 64B / 66B coding block.

[0169] In the above conversion process, the 1st to 3rd bits of the 512B / 513B coding block are 010, indicating that the 512B / 513B coding block contains two 64B / 66B coding blocks with synchronization headers of 10. The 4th to 6th bits of the 512B / 513B coding block indicate that the first 64B / 66B coding block with synchronization headers of 10 is located in the N1th 64B / 66B coding block among the 8 64B / 66B coding blocks, where N1 is equal to 512B / 513B. The value represented by the 4th to 6th bits of the coding block is added by 1, and the 7th to 9th bits of the 512B / 513B coding block indicate that the second 64B / 66B coding block with a synchronization header of 10 is located in the N2th 64B / 66B coding block among the 8 64B / 66B coding blocks, where N2 is equal to the value represented by the 7th to 9th bits of the 512B / 513B coding block plus 1, and N1 and N2 are both integers greater than or equal to 1 and less than or equal to 8, and N2 is greater than N1.

[0170] The following example illustrates the above conversion process:

[0171] Fig.11 This is an example of converting one 512B / 513B coding block into eight 64B / 66B coding blocks, where the first to third bits of the 512B / 513B coding block are 010, the fourth to sixth bits are 2, and the seventh to ninth bits are 6. Since the fourth to sixth bits of the 512B / 513B coding block are 2, and N1 is equal to the value of the fourth to sixth bits of the 512B / 513B coding block plus 1, N1 is equal to 3; the seventh to ninth bits of the 512B / 513B coding block are 6, and N2 is equal to the value of the seventh to ninth bits of the 512B / 513B coding block plus 1, so N2 is equal to 7, that is, among the eight 64B / 66B coding blocks obtained by conversion, the synchronization headers of the third and seventh 64B / 66B coding blocks are 10, and the synchronization headers of the remaining six 64B / 66B coding blocks are 01. The 10th to 513th bits of the 512B / 513B coding block are arranged in sequence into 504 bits, and 4 bits are added after the (N1-1)*64+4th bit in the 504 bits. Since N1 is equal to 3, it is equivalent to adding 4 bits after the 132nd bit in the 504 bits, that is, it is equivalent to adding 4 bits after the 141st bit of the 512B / 513B coding block. It is necessary to add 4 bits according to the contents of the (N1-1)*64+1th to (N1-1)*64+4th bits in the 504 bits, that is, it is equivalent to adding 4 bits according to the contents of the 138th to 141st bits in the 512B / 513B coding block. Fig.11In , 4 bits Z-1 to Z-4 are added after y-138 to y-141. At the same time, 4 bits are added after the (N2-1)*64th bit in the 504 bits. Since N2 is equal to 7, it is equivalent to adding 4 bits after the 384th bit in the 504 bits, that is, it is equivalent to adding 4 bits after the 393rd bit of the 512B / 513B coding block. It is necessary to add 4 bits according to the contents of the (N2-1)*64-3th to the (N2-1)*64th bits in the 504 bits, that is, it is equivalent to adding 4 bits according to the contents of the 390th to the 393rd bits in the 512B / 513B coding block. Fig.11 In the figure, 4 bits Z-5 to Z-8 are added after y-390 to y-393. Since 4 bits are added twice in total, 512 bits are obtained. These 512 bits are used as the 3rd to 66th bits in 8 64B / 66B coding blocks in turn, among which Z-1 to Z-4 are obtained by looking up y-138 to y-141 in Table 3, and Z-5 to Z-8 are obtained by looking up y-390 to y-393 in Table 3.

[0172] Example 8

[0173] In one embodiment, in order to convert one 512B / 513B coding block into eight 64B / 66B coding blocks, the following processing is performed according to the value of the first 13 bits of the 512B / 513B coding block:

[0174] If the first to fifth bits of the 512B / 513B coding block are 01100, the synchronization headers in the converted eight 64B / 66B coding blocks are set in sequence according to the sixth to thirteenth bits of the 512B / 513B coding block, where the sixth bit corresponds to the synchronization header in the first 64B / 66B coding block, the seventh bit corresponds to the synchronization header in the second 64B / 66B coding block, the eighth bit corresponds to the synchronization header in the third 64B / 66B coding block, and the ninth bit corresponds to the synchronization header in the fourth 64B / 66B coding block. The 10th bit corresponds to the synchronization header in the 5th 64B / 66B coding block, the 11th bit corresponds to the synchronization header in the 6th 64B / 66B coding block, the 12th bit corresponds to the synchronization header in the 1st 64B / 66B coding block, and the 13th bit corresponds to the synchronization header in the 1st 64B / 66B coding block. If a bit from the 6th to the 13th bit is 0, the corresponding synchronization header in the 64B / 66B coding block is 10. If a bit is 1, the corresponding synchronization header in the 64B / 66B coding block is 01. The 6th bit to the 13th bit of the 512B / 513B coding block are sequentially formed into an 8-bit block, and at least 3 bits of 0 are expected to be included in the 8-bit block. The first bit 0 is assumed to be located at the N1th bit in the 8-bit block, where N1 is an integer greater than or equal to 1 and less than or equal to 8. The second bit 0 is assumed to be located at the N2th bit in the 8-bit block, where N2 is an integer greater than or equal to 1 and less than or equal to 8 and N2 is greater than N1. The third bit 0 is assumed to be located at the N3th bit in the 8-bit block, where N3 is an integer greater than or equal to 1 and less than or equal to 8 and N3 is greater than N2. N1, N2, and N3 represent positions where 4 bits need to be added.The 14th to 513th bits of the 512B / 513B coding block are arranged in sequence into 500 bits. In the 500 bits, 4 bits are added after the (N1-1)*64+4th bit. The content of the added 4 bits is determined according to the content of the 4 bits before the adding position. Since the 4 bits before the adding position correspond to the (N1-1)*64+1th to (N1-1)*64+4th bits in the 500 bits, the content of the added 4 bits is obtained according to the above 4-bit content and Table 3; at the same time, 4 bits need to be added after the (N2-1)*64th bit. The content of the added 4 bits is determined according to the content of the 4 bits before the adding position. The 4-bit content is determined. Since the 4 bits before the adding position correspond to the (N2-1)*64-3th bit to the (N2-1)*64th bit in 500 bits, the added 4-bit content is obtained according to the above 4-bit content and Table 3; at the same time, 4 bits need to be added after the (N3-1)*64-4th bit. The added 4-bit content is determined according to the 4-bit content before the adding position. Since the 4 bits before the adding position correspond to the (N3-1)*64-7th bit to the (N3-1)*64-4th bit in 500 bits, the added 4-bit content is obtained according to the above 4-bit content and Table 3. The above adds a total of After 12 bits are obtained, 512 bits are set in sequence as the 3rd to 66th bits of 8 64B / 66B coding blocks, specifically including: setting the 1st to 64th bits of the 512 bits as the 3rd to 66th bits of the first 64B / 66B coding block; setting the 65th to 128th bits of the 512 bits as the 3rd to 66th bits of the second 64B / 66B coding block; setting the 129th to 192nd bits of the 512 bits as the 3rd to 66th bits of the third 64B / 66B coding block; setting the 193rd to 256th bits of the 512 bits as the The 3rd to 66th bits of the 4th 64B / 66B coding block are set; the 257th to 320th bits of the 512 bits are set as the 3rd to 66th bits of the 5th 64B / 66B coding block; the 321st to 384th bits of the 512 bits are set as the 3rd to 66th bits of the 6th 64B / 66B coding block; the 385th to 448th bits of the 512 bits are set as the 3rd to 66th bits of the 7th 64B / 66B coding block; the 449th to 512th bits of the 512 bits are set as the 3rd to 66th bits of the 8th 64B / 66B coding block.

[0175] In the above conversion process, the 1st to 5th bits of the 512B / 513B coding block are 01100, indicating that the 512B / 513B coding block contains at least 3 64B / 66B coding blocks with synchronization headers of 10, and the 6th to 13th bits of the 512B / 513B coding block respectively represent the synchronization headers in the 8 converted 64B / 66B coding blocks. Among the 6th to 13th bits of the 512B / 513B coding block, if a bit is 0, the synchronization header in the corresponding 64B / 66B coding block is 10, and if a bit is 1, the synchronization header in the corresponding 64B / 66B coding block is 01. The 6th to 13th bits of the 512B / 513B coding block are combined into an 8-bit block. In this 8-bit block, N1, N2, and N3 are obtained according to the positions of the first three bits 0, where N1 indicates that the first bit 0 in this 8-bit block is located at the N1th bit, N2 indicates that the second bit 0 in this 8-bit block is located at the N2th bit, and N3 indicates that the third bit 0 in this 8-bit block is located at the N3th bit. For example, this 8-bit block is 10011010, there are 4 bits 0 in this 8-bit block, and the first three bits 0 are located at the 2nd, 3rd, and 6th bits in the 8-bit block, respectively, so N1 is equal to 2, N2 is equal to 3, and N3 is equal to 6. According to N1, N2, and N3, 12 bits are obtained and inserted into the 500 bits composed of the 14th to 513th bits of the 512B / 513B coding block, and finally 512 bits are obtained, and the 512 bits are used as the 3rd to 66th bits of 8 64B / 66B coding blocks.

[0176] The following example illustrates the above conversion process:

[0177] Fig.12This is an example of converting one 512B / 513B coding block into eight 64B / 66B coding blocks, where the first to fifth bits of the 512B / 513B coding block are 01100, and the sixth to thirteenth bits are 11010010. Since the sixth to thirteenth bits of the 512B / 513B coding block represent the synchronization headers in the eight 64B / 66B coding blocks after conversion, the synchronization headers of the eight 64B / 66B coding blocks after conversion are 01, 01, 10, 01, 10, 10, 01, 10, respectively. Among the eight bits 11010010, the first bit 0 is located at the third bit of the eight bits, the second bit 0 is located at the fifth bit of the eight bits, and the third bit 0 is located at the sixth bit of the eight bits. Therefore, N1 is equal to 3, N2 is equal to 5, and N3 is equal to 6. The 14th to 513th bits of the 512B / 513B coding block are arranged in sequence into 500 bits, and 4 bits are added after the (N1-1)*64+4th bit in the 500 bits. Since N1 is equal to 3, it is equivalent to adding 4 bits after the 132nd bit in the 500 bits, that is, it is equivalent to adding 4 bits after the 145th bit of the 512B / 513B coding block. It is necessary to add 4 bits according to the contents of the (N1-1)*64+1th to (N1-1)*64+4th bits in the 500 bits, that is, it is equivalent to adding 4 bits according to the contents of the 142nd to 145th bits in the 512B / 513B coding block. Fig.12 In , 4 bits Z-1 to Z-4 are added after y-142 to y-145. At the same time, 4 bits are added after the (N2-1)*64th bit in the 500 bits. Since N2 is equal to 5, it is equivalent to adding 4 bits after the 256th bit in the 500 bits, that is, it is equivalent to adding 4 bits after the 269th bit of the 512B / 513B coding block. It is necessary to add 4 bits according to the contents of the (N2-1)*64-3th to the (N2-1)*64th bits in the 500 bits, that is, it is equivalent to adding 4 bits according to the contents of the 266th to the 269th bits in the 512B / 513B coding block. Fig.12 In , 4 bits Z-5 to Z-8 are added after y-266 to y-269. At the same time, 4 bits are added after the (N3-1)*64-4th bit in the 500 bits. Since N3 is equal to 6, it is equivalent to adding 4 bits after the 316th bit in the 500 bits, that is, it is equivalent to adding 4 bits after the 329th bit of the 512B / 513B coding block. It is necessary to add 4 bits according to the contents of the (N3-1)*64-7th to (N3-1)*64-4th bits in the 500 bits, that is, it is equivalent to adding 4 bits according to the contents of the 326th to 329th bits in the 512B / 513B coding block. Fig.12In the figure, 4 bits Z-9 to Z-12 are added after y-326 to y-329. Since 4 bits are added 3 times in total, 512 bits are obtained. These 512 bits are used as the 3rd to 66th bits in 8 64B / 66B coding blocks in sequence. Among them, Z-1 to Z-4 are obtained by looking up y-142 to y-145 in Table 3, Z-5 to Z-8 are obtained by looking up y-266 to y-269 in Table 3, and Z-9 to Z-12 are obtained by looking up y-326 to y-329 in Table 3.

[0178] Example 9

[0179] If the first to third bits of the 512B / 513B coding block are 011, and the fourth to fifth bits are not 00, it is considered that there is an error in the 512B / 513B coding block. In this case, the 512B / 513B coding block is converted into 8 64B / 66B coding blocks representing error information, where the synchronization header of the 64B / 66B coding block representing the error information is 10, the domain type is 0x1e (letters and numbers starting with 0x represent hexadecimal values), and the 56-bit information domain is 7 0x1e.

[0180] See also Fig.13 The embodiment of the present application further provides a 64B / 66B coded signal processing device, the 64B / 66B coded signal processing device 1000 comprising:

[0181] The sending module 1001 is used to execute: converting the eight 64B / 66B coding blocks into 512B / 513B coding blocks, composing a 512B / 513B coded signal from the 512B / 513B coding blocks, and sending the 512B / 513B coded signal;

[0182] The receiving module 1002 is used to execute: receiving the 512B / 513B coded signal, and converting the 512B / 513B coded block in the 512B / 513B coded signal into eight 64B / 66B coded blocks;

[0183] Wherein, each of the 64B / 66B coding blocks is a 64B / 66B data coding block or a 64B / 66B control coding block;

[0184] The first L1 bits of the 512B / 513B coding block are the indication field, and the last L2 bits are the information field, wherein L1 is an integer greater than or equal to 1, L2 is an integer greater than 1, and L2=513-L1;

[0185] The L1 bit indication field includes at least one of the following information: the number of the 64B / 66B control coding blocks in the eight 64B / 66B coding blocks, or the position of the 64B / 66B control coding block in the eight 64B / 66B coding blocks;

[0186] The L2 bit information field contains 8 information blocks corresponding to the 8 64B / 66B coding blocks one by one, the length of each information block is 64 bits or 60 bits, and the number of bits contained in each information block is determined by the value of the L1 bit indication field.

[0187] See also Fig.14 The present application also provides an electronic device, the electronic device 2000 includes but is not limited to:

[0188] One or more processors 2001;

[0189] The memory 2002 stores one or more programs. When the one or more programs are executed by one or more processors, the one or more processors implement the 64B / 66B coded signal processing method described in any of the above embodiments.

[0190] It should be understood that the processor 2001 and the memory 2002 may be connected via a bus or other means.

[0191] It should be understood that the processor 2001 can use a central processing unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. Or the processor 2001 uses one or more integrated circuits to execute related programs to implement the technical solutions provided in the embodiments of the present application.

[0192] The memory 2002, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer executable programs, such as the 64B / 66B encoded signal processing method described in any embodiment of the present application.

[0193] The processor 2001 implements the above-mentioned 64B / 66B encoded signal processing method by running the non-transitory software program and instructions stored in the memory 2002.

[0194] The memory 2002 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store and execute the above-mentioned 64B / 66B coded signal processing method. In addition, the memory 2002 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory 2002 may optionally include a memory remotely arranged relative to the processor 2001, and these remote memories may be connected to the processor 2001 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0195] An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the 64B / 66B encoded signal processing method described in any of the above embodiments is implemented.

[0196] The computer storage medium of the embodiment of the present application can adopt any combination of one or more computer-readable media. Computer-readable media can be computer-readable signal media or computer-readable storage media. Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples (non-exhaustive) of computer-readable storage media include: electrical connections with one or more wires, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this document, computer-readable storage media can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0197] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0198] The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0199] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0200] An embodiment of the present application also provides a computer program product, including a computer program or computer instructions, wherein the computer program or computer instructions are stored in a computer-readable storage medium, a processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium, and the processor executes the computer program or computer instructions, so that the computer device executes the 64B / 66B encoded signal processing method described in any of the above embodiments.

[0201] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above implementation. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the present application.

Claims

1. A method for processing a 64B / 66B coded signal, wherein the 64B / 66B coded signal is composed of 64B / 66B coded blocks, the method comprising: Convert the eight 64B / 66B coding blocks into 512B / 513B coding blocks, each of the 64B / 66B coding blocks being a 64B / 66B data coding block or a 64B / 66B control coding block; composing a 512B / 513B coded signal from the 512B / 513B coded blocks, and sending the 512B / 513B coded signal; The first L1 bits of the 512B / 513B coding block are the indication field, the last L2 bits are the information field, L1 is an integer greater than or equal to 1, L2 is an integer greater than 1 and L2=513-L1; The L1 bit indication field includes at least one of the following information: the number of the 64B / 66B control coding blocks in the eight 64B / 66B coding blocks, or the position of the 64B / 66B control coding block in the eight 64B / 66B coding blocks; The L2 bit information field contains 8 information blocks corresponding to the 8 64B / 66B coding blocks one by one, the length of each information block is 64 bits or 60 bits, and the number of bits contained in each information block is determined by the value of the L1 bit indication field.

2. The method according to claim 1, characterized in that The value range of L1 is 1≤L1≤13, and the value range of L2 is 500≤L2≤512.

3. The method according to claim 2, characterized in that The value of L1 is one of the following: 1, 5, 9 or 13; The value of L2 is one of the following: 512, 508, 504 or 490.

4. The method according to claim 3, characterized in that When the 8 64B / 66B coding blocks do not include the 64B / 66B control coding block, the L1 is equal to 1, and the L2 is equal to 512; The indication field contains a binary value a1; The length of each information block in the information domain is 64 bits, and each information block contains the value of the last 64 bits of the corresponding 64B / 66B data encoding block.

5. The method according to claim 4, characterized in that When the eight 64B / 66B coding blocks include one 64B / 66B control coding block, and the 64B / 66B control coding block is the Nth 64B / 66B coding block among the eight 64B / 66B coding blocks, where N is an integer greater than or equal to 1 and less than or equal to 8, then L1 is equal to 5, and L2 is equal to 508; Bits 1 to 2 of the indication field contain binary values ​​a2a3, where a2 is not equal to a1; The value of the 3rd to 5th bits of the indication field is equal to N-1; The length of the Nth information block in the information field is 60 bits, including the values ​​of bits 3 to 6 and bits 11 to 66 of the Nth 64B / 66B coding block, or including the values ​​of bits 7 to 66 of the Nth 64B / 66B coding block; The lengths of the remaining information blocks in the information domain except the Nth information block are all 64 bits, including the value of the last 64 bits of the corresponding 64B / 66B data encoding block.

6. The method according to claim 5, characterized in that When the eight 64B / 66B coding blocks include two 64B / 66B control coding blocks, and the two 64B / 66B control coding blocks are the N1th 64B / 66B coding block and the N2th 64B / 66B coding block among the eight 64B / 66B coding blocks, wherein both N1 and N2 are integers greater than or equal to 1 and less than or equal to 8, and N1 is less than N2, then L1 is equal to 9, and L2 is equal to 504; Bits 1 to 3 in the indication field contain binary values ​​a2a4a5, where a4 is not equal to a3; The value of the 4th to 6th bits in the indication field is equal to N1-1; The values ​​of bits 7 to 9 in the indication field are equal to N2-1; The length of the N1th information block in the information field is 60 bits, including the values ​​of bits 3 to 6 and bits 11 to 66 of the N1th 64B / 66B coding block, or including the values ​​of bits 7 to 66 of bits of the N1th 64B / 66B coding block; The length of the N2th information block in the information field is 60 bits, including the values ​​of bits 3 to 6 and bits 11 to 66 of the N2th 64B / 66B coding block, or including the values ​​of bits 7 to 66 of bits of the N2th 64B / 66B coding block; The lengths of the remaining information blocks in the information domain, except for the N1th and N2th information blocks, are all 64 bits, including the value of the last 64 bits of the corresponding 64B / 66B data encoding block.

7. The method according to claim 6, characterized in that When the eight 64B / 66B coding blocks include at least three 64B / 66B control coding blocks, L1 is equal to 13, and L2 is equal to 500; Bits 1 to 5 in the indication field contain binary values ​​a2a4a6a7a8, where a6 is not equal to a5; The 6th to 13th bits in the indication field correspond to the value of the first bit of the eight 64B / 66B coding blocks, or correspond to the value of the second bit of the eight 64B / 66B coding blocks; The information block corresponding to the first three 64B / 66B control coding blocks in the information field has a length of 60 bits, and includes the values ​​of the 3rd to 6th bits and the values ​​of the 11th to 66th bits of the corresponding 64B / 66B control coding blocks, or includes the values ​​of the 7th to 66th bits of the corresponding 64B / 66B control coding blocks; The length of the remaining information blocks in the information field, except for the information blocks corresponding to the first three 64B / 66B control coding blocks, are all 64 bits, including the value of the last 64 bits of the corresponding 64B / 66B coding blocks.

8. The method according to claim 7, characterized in that The method further comprises: Receiving the 512B / 513B encoded signal; The 512B / 513B coding block in the 512B / 513B coding signal is converted into eight 64B / 66B coding blocks, and the 64B / 66B coding blocks constitute the 64B / 66B coding signal.

9. The method according to claim 8, characterized in that When the first bit of the 512B / 513B coding block is equal to the binary value a1, the L1 is equal to 1, the L2 is equal to 512, and the 512B / 513B coding block is converted into eight 64B / 66B coding blocks, including: Divide the last 512 bits of the 512B / 513B coding block into 8 information blocks, each of which has a length of 64 bits; Add a synchronization header 01 in front of each of the information blocks in turn to obtain the 64B / 66B coding block corresponding to each of the information blocks.

10. The method according to claim 9, characterized in that When the first bit to the second bit of the 512B / 513B coding block are equal to the binary value a2a3, and the a2 is not equal to the a1, then the L1 is equal to 5, the L2 is equal to 508, and the 512B / 513B coding block is converted into 8 64B / 66B coding blocks, including: Determine a value of N-1 according to bits 3 to 5 of the 512B / 513B coding block, where N is an integer greater than or equal to 1 and less than or equal to 8; Divide the last 508 bits of the 512B / 513B coding block into 8 information blocks, wherein the length of the Nth information block is 60 bits, and the lengths of the remaining information blocks are all 64 bits; According to the values ​​of the first to fourth bits of the Nth information block, add 4 bits after the fourth bit of the Nth information block, or add 4 bits before the first bit of the Nth information block; A synchronization header is added before each of the information blocks in turn to obtain the 64B / 66B coding block corresponding to each of the information blocks, wherein the synchronization header added before the Nth information block is 10, and the synchronization headers added before the remaining information blocks are 01.

11. The method according to claim 10, characterized in that When the first to third bits of the 512B / 513B coding block are equal to the binary value a2a4a5, and the a4 is not equal to the a3, then the L1 is equal to 9, the L2 is equal to 504, and the 512B / 513B coding block is converted into 8 64B / 66B coding blocks, including: The value of N1-1 is determined according to the 4th to 6th bits of the 512B / 513B coding block, and the value of N2-1 is determined according to the 7th to 9th bits of the 512B / 513B coding block, wherein both N1 and N2 are integers greater than or equal to 1 and less than or equal to 8; Divide the last 504 bits of the 512B / 513B coding block into 8 information blocks, wherein the lengths of the N1th and N2th information blocks are 60 bits, and the lengths of the remaining information blocks are all 64 bits; According to the values ​​of the first to fourth bits of the N1th information block, add 4 bits after the fourth bit of the N1th information block, or add 4 bits before the first bit of the N1th information block; According to the values ​​of the first to fourth bits of the N2th information block, add 4 bits after the fourth bit of the Nth information block, or add 4 bits before the first bit of the N2th information block; A synchronization header is added before each of the information blocks in turn to obtain the 64B / 66B coding block corresponding to each of the information blocks, wherein the synchronization header added before the N1th and N2th information blocks is 10, and the synchronization header added before the remaining information blocks is 01.

12. The method according to claim 11, characterized in that When the first to fifth bits of the 512B / 513B coding block are equal to the binary values ​​a2a4a6a7a8, and a6 is not equal to a5, then L1 is equal to 13, and L2 is equal to 500, the 512B / 513B coding block is converted into eight 64B / 66B coding blocks, including: Determine, according to bits 6 to 13 of the 512B / 513B coding block, that the eight 64B / 66B coding blocks correspond to the 64B / 66B data coding blocks or the 64B / 66B control coding blocks respectively; According to the positions of the first three 64B / 66B control coding blocks, the last 500 bits of the 512B / 513B coding block are divided into 8 information blocks, wherein the 8 information blocks include 5 information blocks with a length of 64 bits and 3 information blocks with a length of 60 bits, wherein the first three 64B / 66B control coding blocks among the 8 64B / 66B coding blocks correspond to 60 bits of information blocks, and the remaining 64B / 66B coding blocks correspond to 64 bits of information blocks; For the information blocks corresponding to the first three 64B / 66B control coding blocks, add 4 bits after the 4th bit of the information block, or add 4 bits before the 1st bit of the information block, according to the values ​​of the 1st to 4th bits of the information block; Add a synchronization header before each of the information blocks in turn to obtain the 64B / 66B coding block corresponding to each of the information blocks, wherein the synchronization header added before the information block corresponding to the 64B / 66B control coding block is 10, and the synchronization header added before the information block corresponding to the 64B / 66B data coding block is 01.

13. The method according to claim 12, characterized in that When the first to third bits of the 512B / 513B coding block are equal to a2a4a6 and the fourth to fifth bits are not equal to a7a8, the 512B / 513B coding block is converted into 8 64B / 66B control coding blocks representing error information, wherein: The type field of the 64B / 66B control coding block indicating error information is 0x1e, and the information field of the 64B / 66B control coding block indicating error information is 8 7-bit 0x1e.

14. A 64B / 66B coded signal processing device, the device comprising: A sending module, used to execute the method described in any one of claims 1 to 7; A receiving module, used to execute the method described in any one of claims 8-13.

15. An electronic device, comprising: one or more processors; A memory having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the 64B / 66B coded signal processing method according to any one of claims 1 to 13.

16. A computer-readable storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the 64B / 66B coded signal processing method according to any one of claims 1 to 13 is implemented.

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