CAN bus drive circuit, CAN transceiver and CAN bus structure

Abstract

The present invention provides a CAN bus driver circuit, a CAN transceiver, and a CAN bus structure, comprising: a bias generation module that generates a first bias signal and a second bias signal; a current slope control module that is connected to the output end of the bias generation module and receives and transmits signals, and is used to generate a first current and a second current, and to control the magnitude of the first and second currents in a step-by-step manner; a first high-voltage driver module that is connected to the first current at one end and outputs a first output signal at the other end for providing high-voltage protection; a second high-voltage driver module that is connected to the second current at one end and outputs a second output signal at the other end for providing high-voltage protection; the first output signal and the second output signal form a differential signal. The present invention not only has a high-voltage protection function, but also provides a bus signal with excellent stability and symmetry, thereby having low electromagnetic radiation performance.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuit design, and in particular to a CAN bus driving circuit, a CAN transceiver and a CAN bus structure. Background Art

[0002] The Controller Area Network (CAN) is a serial communication protocol bus designed for real-time applications. It uses twisted-pair cables for signal transmission and is one of the world's most widely used fieldbuses. The CAN protocol is used for communication between various components in automobiles, replacing expensive and bulky wiring harnesses. The protocol's sophistication has led to its widespread use in automation and industrial applications.

[0003] The symmetry and stability of existing CAN bus driver circuits need to be improved, and their high-voltage protection capabilities are relatively incomplete. Therefore, how to improve the symmetry and stability of CAN bus driver circuits while also enhancing the high-voltage protection capabilities of CAN bus drivers has become a pressing technical challenge for those skilled in the art.

[0004] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a CAN bus drive circuit, a CAN transceiver and a CAN bus structure, which are used to solve the problems of the CAN bus drive circuit in the prior art, such as poor symmetry and stability, and imperfect high-voltage protection function.

[0006] To achieve the above-mentioned and other related objectives, the present invention provides a CAN bus driver circuit, which at least includes:

[0007] A bias generating module, a current slope control module, a first high-voltage driving module and a second high-voltage driving module;

[0008] The bias generating module is used to generate a first bias signal and a second bias signal;

[0009] The current slope control module is connected to the output end of the bias generation module and receives a transmission signal, and is used to generate a first current and a second current, and to control the magnitudes of the first current and the second current step by step;

[0010] One end of the first high-voltage driving module is connected to the first current, and the other end thereof outputs a first output signal for providing high-voltage protection;

[0011] One end of the second high-voltage driving module is connected to the second current, and the other end outputs a second output signal for providing high-voltage protection; the first output signal and the second output signal form a differential signal.

[0012] Optionally, the current slope control module includes N levels of slope control units cascaded in sequence, where N is a natural number greater than or equal to 2; each slope control unit generates a corresponding pull-up current and pull-down current based on the first bias signal and the second bias signal; and outputs the corresponding pull-up current and pull-down current step by step when switching to a dominant working state based on the control of the transmission signal, and shuts off the corresponding pull-up current and pull-down current step by step when switching to a recessive working state;

[0013] The sum of the pull-up currents of the slope control units constitutes the first current; and the sum of the pull-down currents of the slope control units constitutes the second current.

[0014] More optionally, each slope control unit includes a first inverter, a second inverter, a first transmission gate, a second transmission gate, a pull-up tube, a pull-down tube, a first PMOS tube and a first NMOS tube;

[0015] The input end of the first inverter serves as the input end of the slope control unit, and the output end of the first inverter is connected to the input end of the second inverter; the output end of the second inverter serves as the output end of the slope control unit;

[0016] The source of the first PMOS transistor is connected to the power supply voltage, the gate is connected to the first bias signal via the first transmission gate, and the drain is connected to the first high-voltage driving module;

[0017] The source of the first NMOS transistor is grounded, the gate is connected to the second bias signal via the second transmission gate, and the drain is connected to the second high-voltage driving module;

[0018] The control ends of the first transmission gate and the second transmission gate are connected to the first inverter, and when switched to a dominant working state, the first transmission gate and the second transmission gate are turned on, and when switched to a recessive working state, the first transmission gate and the second transmission gate are turned off;

[0019] The source of the pull-up tube is connected to the power supply voltage, the drain is connected to the gate of the first PMOS tube, and the gate is connected to the output end of the first inverter;

[0020] The source of the pull-down tube is grounded, the drain is connected to the gate of the first NMOS tube, and the gate is connected to the input end of the first inverter;

[0021] The input end of the first-stage slope control unit receives the transmission signal, and the input end of the subsequent-stage slope control unit is connected to the output end of the previous-stage slope control unit.

[0022] More optionally, the pull-up tube is a PMOS tube, and the pull-down tube is an NMOS tube.

[0023] More optionally, N is set to 10-30.

[0024] More optionally, the bias generating module includes a second PMOS transistor, a second NMOS transistor and a current source; the source of the second PMOS transistor is connected to the power supply voltage, the gate and the drain are connected and output the first bias signal; the source of the second NMOS transistor is grounded, the gate and the drain are connected and output the second bias signal; the current source is connected between the drain of the second PMOS transistor and the drain of the second NMOS transistor.

[0025] More optionally, the first high-voltage driving module includes a first high-voltage PMOS tube and a first high-voltage NMOS tube; the source of the first high-voltage NMOS tube receives the first current, and the drain is connected to the source of the first high-voltage PMOS tube; the drain of the first high-voltage PMOS tube outputs the first output signal; the gates of the first high-voltage PMOS tube and the first high-voltage NMOS tube receive a driving control signal.

[0026] More optionally, the second high-voltage driving module includes a second high-voltage PMOS tube and a second high-voltage NMOS tube; the source of the second high-voltage NMOS tube receives the second current, and the drain is connected to the source of the second high-voltage PMOS tube; the drain of the second high-voltage PMOS tube outputs the second output signal; the gates of the second high-voltage PMOS tube and the second high-voltage NMOS tube receive a driving control signal.

[0027] To achieve the above-mentioned object and other related objects, the present invention further provides a CAN transceiver, which at least includes: the above-mentioned CAN bus driving circuit.

[0028] To achieve the above-mentioned purpose and other related purposes, the present invention also provides a CAN bus structure, which at least includes: a CAN controller, a bus and the above-mentioned CAN transceiver; one end of the CAN transceiver is connected to the CAN controller, and the other end is connected to the bus for transmitting and receiving signals.

[0029] As described above, the CAN bus driving circuit, CAN transceiver and CAN bus structure of the present invention have the following beneficial effects:

[0030] The CAN bus drive circuit, CAN transceiver and CAN bus structure of the present invention not only have a high-voltage protection function, but also provide bus signals with excellent stability and symmetry, thereby having lower electromagnetic radiation performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Shown is a structural schematic diagram of the CAN bus driving circuit of the present invention.

[0032] Figure 2 Shown is a structural schematic diagram of the current slope control module of the present invention.

[0033] Figure 3 Shown is a schematic diagram of the working principle of the CAN bus driving circuit of the present invention.

[0034] Figure 4 Shown is a schematic diagram of the CAN bus structure of the present invention.

[0035] Component number description

[0036] 1 CAN transceiver

[0037] 10 CAN bus drive circuit

[0038] 11 Bias generation module

[0039] 12 Current slope control module

[0040] 12a Slope control unit

[0041] 13. First high-voltage driver module

[0042] 14. Second high-voltage driver module

[0043] 2 CAN controller DETAILED DESCRIPTION

[0044] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] See also Figures 1 to 4 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0046] like Figure 1 As shown, the present invention provides a CAN bus driving circuit 10, and the CAN bus driving circuit 10 at least includes:

[0047] The bias generating module 11 , the current slope controlling module 12 , the first high voltage driving module 13 and the second high voltage driving module 14 .

[0048] like Figure 1 As shown, the bias generating module 11 is used to generate a first bias signal vbp and a second bias signal vbn.

[0049] Specifically, in this embodiment, the bias generation module 11 includes a second PMOS transistor PM2, a second NMOS transistor NM2, and a current source Idc. The source of the second PMOS transistor PM2 is connected to the power supply voltage VCC, and its gate and drain are connected to output the first bias signal vbp. The source of the second NMOS transistor NM2 is connected to ground GND, and its gate and drain are connected to output the second bias signal vbn. The current source Idc is connected between the drain of the second PMOS transistor PM2 and the drain of the second NMOS transistor NM2. As an example, the current source Idc has a current mirror structure.

[0050] It should be noted that, in actual use, any circuit structure that can generate the first bias signal vbp and the second bias signal vbn is applicable to the present invention, and is not limited to this embodiment.

[0051] like Figure 1 As shown, the current slope control module 12 is connected to the output end of the bias generation module 11 and receives a transmission signal TXD, and is used to generate a first current CH and a second current CL, and control the magnitudes of the first current CH and the second current CL step by step.

[0052] Specifically, the current slope control module 12 includes N stages of slope control units 12a cascaded in sequence, where N is a natural number greater than or equal to 2. Each slope control unit 12a generates a corresponding pull-up current and pull-down current based on the first bias signal vbp and the second bias signal vbn. The corresponding pull-up current is obtained by mirroring the first bias signal vbp, and the corresponding pull-down current is obtained by mirroring the second bias signal vbn. Each slope control unit also outputs the corresponding pull-up current and pull-down current in stages when switching to a dominant operating state, and shuts off the corresponding pull-up current and pull-down current in stages when switching to a recessive operating state, based on the control of the transmit signal TXD. The transmit signal TXD controls the on and off of each slope control unit 12a in sequence through a delay. The sum of the pull-up currents of each slope control unit 12a constitutes the first current CH, and the sum of the pull-down currents of each slope control unit 12a constitutes the second current CL.

[0053] More specifically, if Figure 2As shown, in this embodiment, each slope control unit 12a includes a first inverter INV1, a second inverter INV2, a first transmission gate TG1, a second transmission gate TG2, a pull-up transistor UP, a pull-down transistor DN, a first PMOS transistor PM1, and a first NMOS transistor NM1. The input of the first inverter INV1 serves as the input terminal step_in of the slope control unit, and the output terminal is connected to the input terminal of the second inverter INV2. The output terminal of the second inverter INV2 serves as the output terminal step_out of the slope control unit. The first inverter INV1 and the second inverter INV2 both have a delay. As an example, the delay of the first inverter INV1 is as small as possible to ensure that the switching control signals at the input and output terminals of the first inverter INV1 are as synchronized as possible. The delay time of the second inverter INV2 can be configured according to the required delay time of each stage and the number of stages N. The source of the first PMOS transistor PM1 is connected to the power supply voltage VCC, the gate is connected to the first bias signal vbp via the first transmission gate TG1, and the drain is connected to the first high-voltage driver module 13. The source of the first NMOS transistor NM1 is grounded GND, the gate is connected to the second bias signal vbn via the second transmission gate TG2, and the drain is connected to the second high-voltage driver module 14. The control terminals of the first transmission gate TG1 and the second transmission gate TG2 are connected to the first inverter INV1. When switched to the dominant working state, the first transmission gate TG1 and the second transmission gate TG2 are turned on, and when switched to the recessive working state, the first transmission gate TG1 and the second transmission gate TG2 are turned off. In this example, the positive phase control terminal (i.e., the gate of the PMOS) of the first transmission gate TG1 is connected to the input terminal of the first inverter INV1, and the negative phase control terminal (i.e., the gate of the NMOS) is connected to the output terminal of the first inverter INV1. The positive phase control terminal of the second transmission gate TG2 is connected to the input terminal of the first inverter INV1, and the negative phase control terminal is connected to the output terminal of the first inverter INV1. The source of the pull-up transistor UP is connected to the power supply voltage VCC, and the drain is connected to the gate of the first PMOS transistor PM1, which is connected to the output of the first inverter INV1. As an example, the pull-up transistor UP is a PMOS transistor. The source of the pull-down transistor DN is grounded GND, and the drain is connected to the gate of the first NMOS transistor NM1, which is connected to the input of the first inverter INV1. As an example, the pull-down transistor DN is an NMOS transistor.In the cascade structure, the input terminal step_in of the first-stage slope control unit receives the transmit signal TXD, the input terminal step_in of the subsequent-stage slope control unit is connected to the output terminal step_out of the previous-stage slope control unit, that is, the input terminal step_in of the second-stage slope control unit is connected to the output terminal step_out of the first-stage slope control unit, the input terminal step_in of the third-stage slope control unit is connected to the output terminal step_out of the second-stage slope control unit, and so on. The output terminal of the last-stage slope control unit is left floating or serves as the input signal of other circuits, which are not described in detail here. In actual use, any circuit structure that can achieve current slope control is applicable to the present invention, and is not limited to this embodiment.

[0054] It should be noted that a larger number N of levels of slope control units 12a included in the current slope control module 12 results in smoother bus switching, but this also increases the design difficulty. The value of N can be determined based on a balance between smoothness and design difficulty. For example, N is set to 10 to 30, including but not limited to 12, 15, 18, 20, 23, 27, and 29.

[0055] like Figure 1 As shown, one end of the first high-voltage driving module 13 is connected to the first current CH, and the other end outputs a first output signal CANH for providing high-voltage protection.

[0056] Specifically, the components in the first high-voltage driver module 13 are high-voltage transistors. In this embodiment, the first high-voltage driver module 13 includes a first high-voltage PMOS transistor HP1 and a first high-voltage NMOS transistor HN1. The source of the first high-voltage NMOS transistor HN1 receives the first current CH, and the drain is connected to the source of the first high-voltage PMOS transistor HP1. The drain of the first high-voltage PMOS transistor HP1 outputs the first output signal CANH. The gates of the first high-voltage PMOS transistor HP1 and the first high-voltage NMOS transistor HN1 receive a drive control signal. Any circuit capable of implementing drive and high-voltage protection is applicable to the present invention, and is not limited to this embodiment.

[0057] like Figure 1 As shown, one end of the second high-voltage driving module 14 is connected to the second current CL, and the other end outputs a second output signal CANL for providing high-voltage protection.

[0058] Specifically, the components in the second high-voltage driver module 14 are high-voltage transistors. In this embodiment, the second high-voltage driver module 14 includes a second high-voltage PMOS transistor HP2 and a second high-voltage NMOS transistor HN2. The source of the second high-voltage NMOS transistor HN2 receives the second current CL, and the drain is connected to the source of the second high-voltage PMOS transistor HP2. The drain of the second high-voltage PMOS transistor HP2 outputs the second output signal CANL. The gates of the second high-voltage PMOS transistor HP2 and the second high-voltage NMOS transistor HN2 receive a drive control signal. Any circuit capable of implementing drive and high-voltage protection is applicable to the present invention, and is not limited to this embodiment.

[0059] It should be noted that the first high-voltage driver module 13 and the second high-voltage driver module 14 are used to provide high-voltage protection. When switched to the dominant working state, the first high-voltage driver module 13 and the second high-voltage driver module 14 can be regarded as linear region resistors. The output signals of the first high-voltage driver module 13 and the second high-voltage driver module 14 constitute a differential signal.

[0060] The working principle of the CAN bus driving circuit 10 is as follows:

[0061] When the signal is switched from recessive to dominant, the transmit signal TXD changes from a high level to a low level. This means that the input signal of the first inverter INV1 in the first-stage slope control unit changes from a high level to a low level, and the output signal of the first inverter INV1 in the first-stage slope control unit changes from a low level to a high level. The first transmission gate TG1 and the second transmission gate TG2 in the first-stage slope control unit switch from an off state to an on state, and both the pull-up transistor UP and the pull-down transistor DN are turned off. At this point, the gate of the first PMOS transistor PM1 is connected to the first bias signal vbp, generating a corresponding pull-up current that flows into the first high-voltage driver module 13. The gate of the first NMOS transistor NM1 is connected to the second bias signal vbn, generating a corresponding pull-down current that flows into the second high-voltage driver module 14. After a delay, the input signal of the first inverter INV1 in the second-stage slope control unit jumps from a high level to a low level, performing the same operation as the first-stage slope control unit, and generating a second-stage pull-up current and a pull-down current. After a delay, N levels of pull-up current and pull-down current are generated in sequence. The N-level pull-up currents converge to form the first current CH (gradually increasing), and the N-level pull-down currents converge to form the second current CL (gradually increasing).

[0062] When the dominant mode switches to the recessive mode, the transmit signal TXD changes from a low level to a high level. This means that the input signal of the first inverter INV1 in the first-stage slope control unit changes from a low level to a high level, and the output signal of the first inverter INV1 in the first-stage slope control unit changes from a high level to a low level. The first transmission gate TG1 and the second transmission gate TG2 in the first-stage slope control unit switch from an on state to an off state, and both the pull-up transistor UP and the pull-down transistor DN are turned on. At this point, the gate of the first PMOS transistor PM1 is pulled up to the power supply voltage VCC, turning it off, and the corresponding pull-up current is cut off. The gate of the first NMOS transistor NM1 is pulled down to ground GND, turning it off, and the corresponding pull-down current is cut off. After a delay, the input signal of the first inverter INV1 in the second-stage slope control unit jumps from a low level to a high level, performs the same operation as the first-stage slope control unit, and turns off the pull-up current and pull-down current of the second stage. After a delay, the N-stage pull-up current and pull-down current are turned off in turn, and the first current CH gradually decreases to zero, and the second current CL gradually decreases to zero.

[0063] like Figure 3 As shown, when switching from recessive to dominant, the transmit signal TXD jumps from a high level to a low level, the first output signal CANH gradually increases, the second output signal CANL gradually decreases, and the difference between the first output signal CANH and the second output signal CANL gradually increases. When switching from dominant to recessive, the transmit signal TXD jumps from a low level to a high level, the first output signal CANH gradually decreases, the second output signal CANL gradually increases, and the difference between the first output signal CANH and the second output signal CANL gradually decreases. During the switching process, the waveforms of the first output signal CANH and the second output signal CANL are very symmetrical, and the bus differential voltage (the difference between the first output signal CANH and the second output signal CANL) can change linearly.

[0064] The present invention further provides a CAN transceiver 1 , which at least includes: a CAN bus driving circuit 10 of the present invention.

[0065] like Figure 4 As shown, the present invention also provides a CAN bus structure, which includes at least: a CAN transceiver 1, a CAN controller 2, and a bus. One end of the CAN transceiver 1 is connected to the CAN controller 2, and the other end is connected to the bus for transmitting and receiving signals. The differential signal on the bus is the CAN signal. The CAN bus can have a high-speed CAN bus topology or a low-speed CAN bus topology, which will not be described in detail here.

[0066] In summary, the present invention provides a CAN bus driver circuit, a CAN transceiver, and a CAN bus structure, comprising: a bias generation module, a current slope control module, a first high-voltage driver module, and a second high-voltage driver module; the bias generation module is used to generate a first bias signal and a second bias signal; the current slope control module is connected to the output end of the bias generation module and receives and transmits a signal, is used to generate a first current and a second current, and step-by-step control the magnitude of the first current and the second current; one end of the first high-voltage driver module is connected to the first current, and the other end outputs a first output signal for providing high-voltage protection; one end of the second high-voltage driver module is connected to the second current, and the other end outputs a second output signal for providing high-voltage protection; the first output signal and the second output signal form a differential signal. The CAN bus driver circuit, CAN transceiver, and CAN bus structure of the present invention not only have high-voltage protection functions, but also provide bus signals with excellent stability and symmetry, thereby having low electromagnetic radiation performance. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A CAN bus driving circuit, characterized in that: The CAN bus driving circuit at least includes: A bias generating module, a current slope control module, a first high-voltage driving module and a second high-voltage driving module; The bias generating module is used to generate a first bias signal and a second bias signal; The current slope control module is connected to the output end of the bias generating module and receives a transmission signal, and is used to generate a first current and a second current, and to control the magnitudes of the first current and the second current step by step; wherein the current slope control module includes N stages of slope control units cascaded in sequence, where N is a natural number greater than or equal to 2; each slope control unit generates a corresponding pull-up current and a pull-down current based on the first bias signal and the second bias signal; and based on the control of the transmission signal, the corresponding pull-up current and pull-down current are output step by step when switching to a dominant working state, and the corresponding pull-up current and pull-down current are turned off step by step when switching to a recessive working state; the sum of the pull-up currents of the slope control units constitutes the first current; the sum of the pull-down currents of the slope control units constitutes the second current; One end of the first high-voltage driving module is connected to the first current, and the other end thereof outputs a first output signal for providing high-voltage protection; One end of the second high-voltage driving module is connected to the second current, and the other end outputs a second output signal for providing high-voltage protection; the first output signal and the second output signal form a differential signal.

2. The CAN bus driving circuit according to claim 1, wherein: Each slope control unit includes a first inverter, a second inverter, a first transmission gate, a second transmission gate, a pull-up tube, a pull-down tube, a first PMOS tube and a first NMOS tube; The input end of the first inverter serves as the input end of the slope control unit, and the output end of the first inverter is connected to the input end of the second inverter; the output end of the second inverter serves as the output end of the slope control unit; The source of the first PMOS transistor is connected to the power supply voltage, the gate is connected to the first bias signal via the first transmission gate, and the drain is connected to the first high-voltage driving module; The source of the first NMOS transistor is grounded, the gate is connected to the second bias signal via the second transmission gate, and the drain is connected to the second high-voltage driving module; The control ends of the first transmission gate and the second transmission gate are connected to the first inverter, and when switched to a dominant working state, the first transmission gate and the second transmission gate are turned on, and when switched to a recessive working state, the first transmission gate and the second transmission gate are turned off; The source of the pull-up tube is connected to the power supply voltage, the drain is connected to the gate of the first PMOS tube, and the gate is connected to the output end of the first inverter; The source of the pull-down tube is grounded, the drain is connected to the gate of the first NMOS tube, and the gate is connected to the input end of the first inverter; The input end of the first-stage slope control unit receives the transmission signal, and the input end of the subsequent-stage slope control unit is connected to the output end of the previous-stage slope control unit.

3. The CAN bus driving circuit according to claim 2, wherein: The pull-up tube is a PMOS tube, and the pull-down tube is an NMOS tube.

4. The CAN bus driving circuit according to any one of claims 1 to 3, characterized in that: N is set to 10 to 30.

5. The CAN bus driving circuit according to any one of claims 1 to 3, characterized in that: The bias generating module includes a second PMOS transistor, a second NMOS transistor and a current source; the source of the second PMOS transistor is connected to the power supply voltage, the gate and the drain are connected and output the first bias signal; the source of the second NMOS transistor is grounded, the gate and the drain are connected and output the second bias signal; The current source is connected between the drain of the second PMOS transistor and the drain of the second NMOS transistor.

6. The CAN bus driving circuit according to any one of claims 1 to 3, characterized in that: The first high-voltage driving module includes a first high-voltage PMOS transistor and a first high-voltage NMOS transistor; the source of the first high-voltage NMOS transistor receives the first current, and the drain is connected to the source of the first high-voltage PMOS transistor; the drain of the first high-voltage PMOS transistor outputs the first output signal; the gates of the first high-voltage PMOS transistor and the first high-voltage NMOS transistor receive a driving control signal.

7. The CAN bus driving circuit according to any one of claims 1 to 3, characterized in that: The second high-voltage driving module includes a second high-voltage PMOS tube and a second high-voltage NMOS tube; the source of the second high-voltage NMOS tube receives the second current, and the drain is connected to the source of the second high-voltage PMOS tube; the drain of the second high-voltage PMOS tube outputs the second output signal; the gates of the second high-voltage PMOS tube and the second high-voltage NMOS tube receive a driving control signal.

8. A CAN transceiver, characterized in that: The CAN transceiver comprises at least: a CAN bus driving circuit according to any one of claims 1 to 7.

9. A CAN bus structure, characterized in that: The CAN bus structure comprises at least: a CAN controller, a bus and the CAN transceiver as claimed in claim 8; one end of the CAN transceiver is connected to the CAN controller, and the other end is connected to the bus for transmitting and receiving signals.

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