A micro-power redundant task layered universal execution circuit

Abstract

The present invention relates to a micro-power consumption redundant task layered universal execution circuit. The execution circuit is arranged in a terminal, which is connected to a gateway. The execution circuit includes a central controller, a task instruction cache circuit, a sensor control circuit, an off-chip task execution circuit, and a data encoder. The central controller parses the control instructions of the gateway, controls the task instruction cache circuit to write and erase instructions, outputs instructions to the sensor control circuit and the off-chip task execution circuit, and controls the data encoder to output uplink data. The sensor control circuit outputs data to the off-chip task execution circuit, and the off-chip task execution circuit outputs control data to the task instruction cache circuit. The present invention implements data processing and sensor control task logic with a minimalist hardware circuit combination, replacing the traditional task execution method of running software programs on a microprocessor platform, thereby reducing the terminal's power consumption, circuit complexity, and development cost.

Description

Technical Field

[0001] The present invention relates to the field of Internet of Things, and in particular to a micro-power consumption redundant task layered universal execution circuit. Background Art

[0002] The Internet of Things perceives and connects the world through terminals. The traditional terminal architecture is mainly evolved from the embedded computer architecture. Its essence is to use a general-purpose computer platform as a carrier and simulate the control method of the target control logic through software, thus having good versatility, such as Figure 1 However, this approach has significant redundancy in system design, limiting its potential for power consumption and cost optimization. This makes it difficult to further reduce system power consumption and keeps microprocessor development costs high.

[0003] To address this issue, some have proposed designing application-specific integrated circuits (ASICs) to implement specific functions. Compared to microprocessors, ASICs can perform the same tasks with lower power consumption. However, designing ASICs for different scenarios incurs significant development costs. Therefore, ASICs are more suitable for large-scale applications with fixed functions, rather than for IoT terminal designs with diverse functionality. Another approach is to replace the microprocessor with a dedicated signal conversion circuit, allowing the gateway to exchange data with sensors solely through wireless signals. However, the essence of this terminal design is to transfer all data processing tasks and sensor control logic originally carried out by the microprocessor to the gateway. This results in a large amount of redundancy at the communication level, causing communication congestion in actual use and hindering large-scale application.

[0004] In general, existing architectures struggle to meet the demand for low-cost, long-term, large-scale deployment of sensing terminals. The core reason lies in the significant redundancy introduced at the architectural or communication levels to achieve universal functionality. Therefore, the core issue with traditional IoT terminal design lies in the high level of redundancy required to ensure universal functionality. Specifically, to implement access control and data processing for various sensor chips (such as temperature sensors, hygrometers, and barometers), traditional terminals must rely on a general-purpose computing platform, a microprocessor, capable of running embedded software programs. This allows users to write embedded software programs to achieve various control objectives. Under this constraint, traditional terminals must rely on microprocessors with general-purpose computer architectures. The most straightforward approach is to rely on local microprocessors, compromising universality by increasing architectural redundancy. However, this leads to a series of issues, such as complex terminal architecture and difficulty optimizing cost and power consumption. A second option is to utilize a gateway-side microprocessor. However, this shifts the underlying signal exchange tasks previously handled by the local microprocessor to the gateway, introducing significant redundancy at the communication level and increasing communication overhead, making it difficult to meet the needs of large-scale applications. Summary of the Invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a micro-power consumption redundant task layered universal execution circuit to solve the deficiencies of the prior art.

[0006] The objectives of the present invention are achieved through the following technical solutions: a micro-power consumption redundant task layered universal execution circuit, the execution circuit is arranged in a terminal, the terminal is connected to a gateway, the execution circuit includes a central controller, a task instruction cache circuit, a sensor control circuit, an off-chip task execution circuit and a data encoder; the central controller and the data encoder are respectively connected to a communication interface arranged in the terminal, and the sensor control circuit is connected to a sensor arranged in the terminal;

[0007] The central controller parses the control instructions of the gateway, controls the erasing and outputting of instructions of the task instruction cache circuit to the sensor control circuit and the off-chip task execution circuit, and controls the data encoder to output uplink data; the sensor control circuit outputs data to the off-chip task execution circuit, and the off-chip task execution circuit outputs control data to the task instruction cache circuit.

[0008] The central controller includes a downlink data buffer, a status register, a control instruction parser and a preamble detector; the downlink data buffer is a first shift register with serial input and parallel output. The data stream sent by the gateway is transmitted to the downlink data buffer. The preamble detector enables the control instruction parser when it matches the preamble. The control instruction parser completes the parsing of the control instruction, updates the status register according to the instruction content, generates a control signal, and realizes control of the rest of the circuit.

[0009] The task instruction cache circuit includes an instruction eraser, a task counter, an off-chip task controller and an instruction register group. The off-chip task controller contains an execution cycle timer and a start delay timer corresponding to each off-chip task; the output end of the instruction eraser is connected to the input end of the instruction register group, and the instruction register group is interconnected with the sensor control circuit; the output end of the off-chip task controller outputs the off-chip task to the off-chip task execution circuit, and the task counter counts the off-chip tasks.

[0010] When the central controller detects a task assignment instruction, it sends a control signal to the task instruction cache circuit to activate the eraser therein. The instruction eraser selects the instruction register to be erased according to the task type and task number carried in the task assignment instruction, and erases the contents therein. If the instruction received is an off-chip task instruction, the instruction eraser configures the timer of the corresponding task number in the off-chip task controller, and then the instruction eraser transmits the gateway data stream to the selected instruction register according to the task instruction length information.

[0011] The central controller includes a registration state, a stop state, and a running state. When the central controller is in the running state, the task counter cyclically detects whether the start delay timer and execution cycle timer of each off-chip task have reached the preset time. If a task meets the execution condition, its corresponding task register outputs once, that is, the off-chip task is completely executed once.

[0012] When the off-chip task execution circuit calls a sensor control task, it controls the called task register to output instruction data to the sensor control circuit, and will not continue to execute the off-chip task until the sensor control task is completed.

[0013] The sensor control circuit includes a first instruction parser, a second shift register, a delay timer, a raw data register group, an interface configuration unit and a signal interaction unit;

[0014] When executing the sensor control task, the task instruction cache circuit transfers the sensor control instruction to the second shift register so that the first instruction parser can parse it and send control signals to the remaining units. The delay timer meets the timing requirements of different sensors. The raw data register group is used to temporarily store the data output by the sensor. The signal interaction unit realizes bus signal interaction, pin level reading and writing, and event signal detection functions. The interface configuration unit realizes flexible configuration of the working mode of the sensor interface.

[0015] The off-chip task execution circuit includes a third shift register, a second instruction parser, a data clipping circuit, an operation unit, a data combining circuit and a sensor data register group;

[0016] The off-chip task execution circuit obtains the off-chip task instruction data through the third shift register, and the second instruction parser controls the remaining circuit structures to execute the instructions. The data combination circuit is responsible for extracting complete sensor data from the original data. The operation unit performs operation processing on the data in the sensor data register group and transmits the operation result back to the sensor data register group. The data clipping circuit is responsible for clipping the operation result and transmitting it to the data encoder.

[0017] The data combining circuit includes a data position mask register and a valid bit mask register. The data combining circuit selects each original data register in turn and determines whether to participate in data combining based on the output of the data position mask register. The original data register participating in data combining and the valid bit mask register start shifting and outputting at the same time. If the current output is valid, the sensing data register shifts and receives the output of the original data register.

[0018] For signed numbers, if the first valid bit is 1, that is, the sensor data is a negative number, the data combination circuit will fill the entire sensor data register with 1 to expand the sign bit.

[0019] The arithmetic unit interval judgment circuit, difference calculation circuit and recursive average value calculation circuit;

[0020] The interval judgment circuit includes a numerical comparator that compares the sensor data with the left threshold and the right threshold data in sequence, and determines whether the data is valid based on the results of the two comparisons and the type of instruction, and then transmits the valid flag of the data to the data clipping circuit. The interval judgment circuit controls the response pin level based on the value of the response pin level field contained in the between and outside instructions and the judgment result, thereby notifying the external circuit of changes in the sensor data in real time;

[0021] The difference calculation circuit includes a subtractor, a recently uploaded data register, and a latest data register. When the sub instruction is executed, the difference calculation circuit transfers the target sensor data C to the latest data register, then calculates the difference between the latest data C and the recently uploaded data D, and returns the calculation result CD to the sensor data register. The user chooses to perform interval judgment on the calculation result, implement threshold detection processing on the change amount of the sensor data, and control the response pin to output high and low levels, or choose to skip the interval judgment correction and directly upload the change amount of the sensor data to the gateway. When the instruction is executed, if the sensor data is valid, the latest data is updated to the recently uploaded data register.

[0022] The recursive average value calculation circuit comprises a sensor data queue, a queue summing circuit, a summing result register, a right shift circuit and a sampling times counter. When the avg instruction is executed, new sensor data is inserted at the end of the queue, the queue summing circuit reads the summing result register and the data at the head and end of the queue, calculates a new summing result, and writes it back to the summing result register. According to the queue length set by the instruction, the right shift circuit shifts the summing result to the right and transmits the obtained recursive average value back to the sensor data register. The user can choose whether to perform interval judgment on the recursive average value and make a real-time response based on application requirements. When the value of the sampling times counter reaches a preset upload interval, the average value will be allowed to be uploaded.

[0023] The data clipping circuit includes a valid flag register and a counter. When executing an upload instruction, the data clipping circuit selects the sensor data register according to the valid flag, and controls it to shift and output data of corresponding bits to the data encoder according to the bit number information carried in the upload instruction.

[0024] The present invention has the following advantages: a micro-power consumption and redundant task layered universal execution circuit, which realizes data processing and sensor control task logic with a minimalist hardware circuit combination, replaces the traditional task execution method of running software programs on a microprocessor platform, thereby reducing the power consumption, circuit complexity and development cost of the terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a schematic diagram of the architecture of a traditional terminal;

[0026] Figure 2 It is a structural schematic diagram of the present invention;

[0027] Figure 3 This is a diagram of the state switching of the central controller;

[0028] Figure 4 Schematic diagram of the circuit structure of the central controller;

[0029] Figure 5 This is a circuit structure diagram of a task instruction cache circuit;

[0030] Figure 6 Schematic diagram of the circuit structure of the sensor control circuit;

[0031] Figure 7 A schematic diagram of the circuit structure of an off-chip task execution circuit;

[0032] Figure 8 This is a schematic diagram of the working principle of the data combining circuit;

[0033] Figure 9 This is a schematic diagram of the working principle of the interval judgment circuit;

[0034] Figure 10 This is a schematic diagram of the working principle of the difference calculation circuit;

[0035] Figure 11 This is a schematic diagram of the working principle of the recursive average value calculation circuit;

[0036] Figure 12 A schematic diagram of the encoding format for device registration signals;

[0037] Figure 13 This is a schematic diagram of the coding format of the control instruction confirmation signal;

[0038] Figure 14 Schematic diagram of the encoding format of device status information;

[0039] Figure 15 Schematic diagram of the encoding format of sensor data. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application provided below in conjunction with the drawings is not intended to limit the scope of protection of the present application for which protection is claimed, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. The present invention is further described below in conjunction with the drawings.

[0041] like Figure 2 As shown, the present invention specifically relates to a micro-power consumption and redundant task layered universal execution circuit, which is arranged in a terminal, and the terminal is connected to a gateway. The gateway is responsible for sending control instructions and task logic to the terminal. The circuit replaces the microprocessor on the terminal to perform received data processing and sensor control tasks; compared with the microprocessor, this circuit does not have the ability to generate perception terminal task logic, but only has task execution function, which is the key to simplifying the terminal into a gateway wireless peripheral.

[0042] Furthermore, it includes a central controller, a task instruction cache circuit, a sensor control circuit, an off-chip task execution circuit, and a data encoder. With the cooperation of these units, the circuit works as follows:

[0043] 1) Device registration: The UTE circuit (task layered universal execution circuit) is in the registration state after power-on and will periodically send a device registration signal until it receives a task allocation instruction, thereby registering the terminal number that uniquely identifies this terminal into the network.

[0044] 2) Task reception: When the terminal receives a task assignment instruction, the central controller parses the various fields in the task assignment instruction and, accordingly, erases and writes the task instruction cache circuit, temporarily storing the received task instruction data in the cache.

[0045] 3) Task Execution: The central controller sets the execution cycle and startup delay for each off-chip task based on control instructions. When an off-chip task meets the execution conditions, the task instruction cache circuit outputs the off-chip task instruction to the off-chip task execution circuit. The off-chip task execution circuit first calls the sensor control task in the instruction cache, causing the sensor control circuit to execute the task and obtain raw data. The off-chip task execution circuit then processes the raw data according to the instructions.

[0046] 4) Data Upload: Data uploaded by the terminal includes device registration signals, control command confirmation signals, device status information, and processed sensor data. Under the control of the central controller, the data encoder generates data in a fixed encoding format and transmits it to the communication interface for data upload.

[0047] 1. Central controller design;

[0048] The central controller is responsible for parsing the control instructions of the gateway, controlling the erasure and output of the task instruction cache circuit, and controlling the data encoder to output uplink data. The central controller has three working states: registration state, stop state, and running state. The switching between the three states is as follows: Figure 3 shown.

[0049] When the circuit is powered on, the central controller defaults to the registered state. In this state, the central controller controls the data encoder to periodically output a device registration signal until it receives a task assignment command from the gateway, at which point it switches to the stopped state. While the terminal is in the stopped state, the gateway can assign tasks, query device status, request data retransmission, or directly send a task start command to switch it to the running state. In the running state, the central controller sends a signal to the task instruction cache circuit, causing it to output off-chip task instructions according to the set execution cycle. Upon receiving a task stop command, the central controller switches to the stopped state.

[0050] The circuit structure of the central controller is as follows Figure 4As shown in the figure, the downlink data buffer is a shift register with serial input and parallel output. The data stream sent by the gateway is transmitted here. The preamble detector enables the control command parser when it matches the preamble. Because the downlink data buffer can output command data in parallel, the control command parser can quickly parse the control command, update the status register based on the command content, generate control signals, and control the rest of the circuit.

[0051] 2. Task instruction cache circuit design;

[0052] While transferring task logic to the gateway simplifies the terminal development process, it also increases the system's downlink communication load. To address this issue, the present invention designs a task instruction cache circuit in the UTE circuit. Task instructions sent by the gateway to the terminal will be temporarily stored in the task instruction cache circuit. If the terminal task does not need to be updated, the gateway does not need to send the task instruction again, thus saving the system's downlink communication resources. The circuit structure of the task instruction cache circuit is shown in Figure 1. Figure 5 As shown in Figure 1, its internal components include an instruction eraser, a task counter, an off-chip task controller, and an instruction register set. The off-chip task controller contains an execution cycle timer and a start delay timer corresponding to each off-chip task; the instruction register set consists of a set of 256-bit circular shift registers.

[0053] 1. Instruction erase;

[0054] When the central controller detects a task assignment instruction, it sends a control signal to the task instruction cache circuit, activating the eraser within it. Based on the task type and task number contained in the task assignment instruction, the eraser selects the instruction register to be erased and erases the contents. If an off-chip task instruction is received, the instruction eraser also configures the timer for the corresponding task number in the off-chip task controller. The eraser then transfers the gateway data stream to the selected instruction register according to the task instruction length information.

[0055] 2. Command output;

[0056] The terminal's task execution logic conforms to the hierarchical terminal control framework proposed in this invention. Under this framework, the gateway controls the execution cycle and startup delay of each off-chip task, while the off-chip task calls the sensor control task to obtain data. When the central controller is in operation, the task counter cyclically detects whether the startup delay and execution cycle timer of each off-chip task have reached the preset time. If a task meets the execution conditions, its corresponding task register will output once, that is, the off-chip task will be completely executed once. When the off-chip task execution circuit calls a sensor control task, it will control the called task register to output instruction data to the sensor control circuit, and will not continue to execute the off-chip task until the sensor control task is completed.

[0057] 3. Sensor control circuit design;

[0058] The design goal of the sensor control circuit is to give the processor-free terminal a variety of sensor control capabilities with a low-redundancy circuit design. Its circuit structure is as follows: Figure 6 Based on the analysis of the sensor control task of the present invention, the present invention designs an instruction parser, a shift register, a delay timer, a raw data register group, an interface configuration unit and a signal interaction unit in the sensor control circuit.

[0059] When executing a sensor control task, the task instruction cache circuit transfers the sensor control instructions to a serial-input, parallel-output shift register, allowing the instruction parser to parse them and send control signals to the remaining circuits. A delay timer can meet the timing requirements of different sensors, and the raw data register bank is used to temporarily store sensor output data. Furthermore, the signal interaction unit provides bus signal interaction, pin level reading and writing, and event signal detection capabilities, while the interface configuration unit allows flexible configuration of the sensor interface's operating mode.

[0060] 1. Interface configuration unit design;

[0061] This invention incorporates a set of GPIO pin interfaces within the signal interaction unit, featuring four common operating modes for sensor interfaces: pull-up input, pull-down input, push-pull output, and open-drain output. The interface configuration unit configures the GPIO pin operating modes based on the bus interface and the contents of the individual pin configuration instructions, as follows:

[0062] (1) Bus interface configuration: The number of bus pins and the operating mode usually adopt fixed standards. Therefore, the present invention maps the bus interface groups to GPIO pins. For example, pins 1 to 4 are the first group of SPI interfaces, and pins 5 to 8 are the second group of SPI interfaces. Similarly, pins 1 to 2 are the first group of I2C interfaces, and pins 3 to 4 are the second group of I2C interfaces. For different types of bus interfaces, the GPIO configurator will complete the configuration of all their pins at once. For example, the "MISO" pin of the SPI interface is configured as a pull-down input mode, and the "MOSI", "SCK", and "CS" pins are configured as push-pull output modes.

[0063] (2) Single-pin configuration: The single-pin configuration function allows the terminal to more flexibly configure the electrical characteristics of the pin. For example, when reading and writing levels or detecting event signals on pins other than the bus interface, it is necessary to configure the operating mode of a specific single pin. This function enables the UTE circuit to be compatible with a wider variety of sensor chips.

[0064] In addition, the interface configuration unit contains a bus configuration status register that temporarily stores the bus interface configuration status of the current sensor control task. This register controls the multiplexer in the signal interaction unit, allowing the signal interaction unit to select the correct bus signal interaction module and GPIO pin when executing instructions.

[0065] 2. Signal interaction unit design;

[0066] The signal interaction unit is used to implement common sensor control logic such as bus signal interaction, pin level reading and writing, event waiting, etc., and transmits the raw data output by the sensor to the raw data register group. The design of its internal circuit structure specifically includes the following contents:

[0067] (1) Bus signal interaction module: When the sensor control circuit receives a bus read / write instruction, the signal interaction unit selects the bus signal interaction module and GPIO pin according to the interface configuration information temporarily stored in the bus configuration status register. The bus signal interaction module reads and writes data to the sensor according to the instruction content. If the instruction is a read data instruction, the bus signal interaction module transfers the read data byte by byte to the raw data register group as the data source for the off-chip task. In the prototype system of the present invention, two bus signal interaction modules, I2C and SPI, are designed to realize the data interaction function with common sensor chips.

[0068] (2) Pin level reader / writer: The pin level reader / writer configures and reads the level status of a single pin according to instructions. For the 1-bit pin level data read, the pin level reader / writer expands it to a byte length (8 bits) and stores it in the raw data register group. The signal interaction between the sensor chip and the outside world is essentially achieved through a series of pin read and write operations. Therefore, the pin level read and write function enables the terminal to generate various sensor control signals in addition to bus signals, broadening the range of sensor chips that can be controlled by the UTE circuit.

[0069] (3) Event signal detector: The event wait instruction specifies the pin number and target level. When the signal interaction unit receives the instruction, it starts the event signal detector and sends a task blocking signal to the task instruction cache circuit to stop the instruction data output of the task until the level state of the target pin meets the preset conditions or the waiting time expires.

[0070] 4. Design of off-chip task execution circuit;

[0071] The off-chip task execution circuit can give the processor-free perception terminal simple data analysis and filtering capabilities, thereby reducing unnecessary data uploads and improving the performance of the Internet of Things system. Figure 7 shown.

[0072] Similar to the sensor control circuit, the off-chip task execution circuit acquires off-chip task instruction data via a serial-input, parallel-output shift register. The instruction parser then controls the remaining circuitry to execute the instructions. The data combination circuit extracts complete sensor data from the raw data. The arithmetic unit processes the data in the sensor data register bank and transmits the results back to the sensor data register bank. The data clipping circuit clips the results and transmits them to the data encoder.

[0073] 1. Data combining circuit;

[0074] Most sensor chips store their sensor data in single-byte (8-bit) registers (e.g., the TMP125 sensor). Therefore, the first step in sensor data preprocessing is to combine the data scattered across multiple registers to obtain complete sensor data. To achieve this, the present invention designs a data combining unit in the off-chip task execution circuit. Its working principle is as follows: Figure 8 shown.

[0075] The data position mask, validity bit mask, sensor data, and raw data are stored in serial output shift registers of varying lengths. The data combining circuit selects each raw data register in turn and determines whether it participates in data combining based on the output of the data position mask register. The raw data register participating in the combining process begins shifting and outputting simultaneously with the validity bit mask register. If the current output is valid (the validity bit mask register output is "1"), the sensor data register shifts and receives the output of the raw data register. For signed numbers, if the first valid bit is "1" (i.e., the sensor data is negative), the data combining circuit fills the entire sensor data register with "1s" to expand the sign bit. Figure 8 The final result of combining the data is "0001100100" (shown flipped left and right in the figure).

[0076] The present invention designs the combined sensor data as 24-bit signed integer data, covering the common sensor data value range. The design of the data combination circuit is based on the present invention's observation of the characteristics of sensor data. This streamlined circuit efficiently extracts sensor data without the need for microprocessor assistance, providing a data source for the arithmetic unit.

[0077] 2. Arithmetic unit;

[0078] The arithmetic unit is designed to provide basic data processing capabilities for processor-less terminals with a simplified circuit design, enabling them to filter and integrate sensor data, thereby reducing uplink communication data volume and lowering communication overhead. The arithmetic unit features three data processing circuits: interval judgment, difference calculation, and recursive average calculation.

[0079] (1) Interval judgment circuit;

[0080] The interval judgment circuit can limit the sensor data that the terminal needs to upload to a certain interval range, thereby reducing the uplink communication overhead. The core of this circuit is a numerical comparator that can compare two 24-bit signed data. Figure 9 As shown, the interval judgment circuit compares the sensing data with the left threshold and the right threshold data in sequence, and determines whether the data is valid based on the results of the two comparisons and the type of instruction, and then transmits the valid flag of the data to the data clipping circuit.

[0081] In addition to filtering the data, the interval judgment circuit also enables the terminal to respond to changes in sensor data in real time. Figure 9 As shown, the "between" and "outside" instructions contain a response pin level field. The interval judgment circuit can control the level of the response pin according to the value of this field and the judgment result, thereby notifying the external circuit of the change in sensor data in real time.

[0082] The "between" instruction contains five fields: keyword, sensor data number (2 bits), left threshold (24 bits), right threshold (24 bits), and response pin level (1 bit). It performs a range check on the specified sensor data and controls the response pin level based on the result. The "outside" instruction uses the same encoding format as the "between" instruction, but uses different keyword encodings and produces opposite results.

[0083] (2) Difference calculation circuit;

[0084] For scenarios where sensor data changes slowly, the amount of uplink communication data in the system can be reduced by using a change threshold detection method, that is, the terminal will upload data only when the change in the current sensor data exceeds the threshold. In order to perform change threshold detection preprocessing on sensor data without the assistance of a processor, the present invention designs a simple difference calculation circuit in the off-chip task execution circuit, which is mainly composed of a subtractor, a latest data register and multiple recently uploaded data registers. Its working principle is as follows: Figure 10 shown.

[0085] When the "sub" instruction is executed, the difference calculation circuit transfers the target sensor data "C" to the latest data register. It then calculates the difference between the latest data "C" and the most recently uploaded data "D" and returns the calculated result "CD" to the sensor data register. Users can choose to perform interval judgment on the calculation result (i.e., the "sub_between / outside" instruction) to implement threshold detection and processing of the sensor data change and control the output high or low level of the response pin. Alternatively, the interval judgment step can be skipped and the sensor data change is directly uploaded to the gateway. After the "sub" and "sub_between / outside" instructions are executed, if the sensor data is valid, the latest data will be updated to the most recently uploaded data register.

[0086] Among them, the sub instruction: This instruction consists of a keyword and a sensor data number (2 bits). Its function is to calculate the difference of the specified sensor data.

[0087] (3) Recursive average value calculation circuit;

[0088] Average aggregation or average filtering is a commonly used data preprocessing method for sensing terminals. To implement this method, the present invention designs a recursive average calculation circuit. The recursive average calculation method is: regard m consecutive sampled data as a queue. Each time new sampled data is available, the data at the head of the queue is removed from the queue and the new data is placed at the end of the queue. The average value of the data in the queue is the recursive average value. The working principle of the recursive average calculation circuit is as follows: Figure 11 shown.

[0089] The recursive average calculation circuit internally includes a sensor data queue, a queue summation circuit, a summation result register, a right shift circuit, and a sampling counter. Each sensor data queue and summation result register corresponds to an off-chip task, meaning each off-chip task supports recursive average calculation for one sensor data point. Due to the relative complexity of a 24-bit signed divider, the present invention limits the queue lengths supported by the recursive average calculation circuit to four: 2, 4, 8, and 16. Average calculation can be performed simply by right shifting, thus achieving the desired functionality with a simple circuit design. The circuit's workflow is as follows:

[0090] When the "avg" instruction is executed, the new sensor data will be inserted at the end of the queue. Subsequently, the queue summation circuit will read the summation result register and the data at the head and tail of the queue, calculate the new summation result, and write it back to the summation result register. Finally, according to the queue length set by the instruction, the right shift circuit shifts the summation result to the right and transmits the obtained recursive average value back to the sensor data register. Similar to the difference calculation circuit, the user can choose whether to perform interval judgment on the recursive average value and respond in real time based on application requirements. When the value of the sampling counter reaches the preset upload interval, the average value will be allowed to be uploaded. Using the sampling counter, the terminal can flexibly adjust the level of average value aggregation or mean filtering processing, and flexibly control the amount of uplink data.

[0091] The avg command contains four fields: keyword, sensor data number (2 bits), queue length (2 bits), and upload interval (4 bits). It calculates the average value of sensor data and specifies the interval for uploading the average value.

[0092] 3. Data clipping circuit;

[0093] In order to be compatible with more sensor chips, the present invention sets the bit length of the sensor data to 24 bits. For some shorter sensor data, bit expansion will bring invalid uplink communication overhead. To solve this problem, the present invention designs a data clipping circuit in the off-chip task execution circuit, which is responsible for clipping the data to be uploaded to the specified bit length. The structure of this circuit is relatively simple, mainly consisting of a valid flag register and a counter. When executing the "upload" instruction, the data clipping circuit selects the sensor data register according to the valid flag, and controls it to shift and output data of the corresponding number of bits to the data encoder according to the bit information carried in the "upload" instruction.

[0094] The upload command contains two fields: a keyword and the number of bits required to upload each sensor data point (15 bits). Its purpose is to remove invalid bits from the sensor data expanded to 24 bits, thus reducing the amount of uploaded data.

[0095] 5. Data encoder design;

[0096] Under the control of the central controller, the data encoder encodes the uploaded data so that the gateway can correctly identify the data of each terminal. Depending on the input control signal, the data encoder can output the following types of data to the communication interface:

[0097] (1) Device registration signal;

[0098] The UTE circuit is in the registration state by default after power-on. The central controller will control the data encoder to periodically output the device registration signal. The encoding format of the device registration signal is as follows: Figure 12 shown.

[0099] (2) Control command confirmation signal;

[0100] In addition to data retransmission and status query instructions, the data encoder will output a confirmation signal after the execution of other control instructions, thereby promptly notifying the gateway of the control instruction reception status and facilitating the gateway to proceed to the next step. The encoding format of the control instruction confirmation signal is as follows: Figure 13 shown.

[0101] (3) Equipment status information;

[0102] When receiving the status query command, the central controller will control the data encoder to output the current task allocation status of the UTE circuit, that is, the number of off-chip tasks and sensor control tasks in the task instruction cache circuit. The encoding format of the device status information is as follows: Figure 14 As shown, it includes four fields: status preamble, terminal number, number of off-chip tasks, and number of sensor control tasks.

[0103] (4) processed sensor data;

[0104] The data encoder can temporarily store the sensor data output by the data clipping circuit and use a counter to record its length. According to the rules of uploading data, terminal tasks can be divided into two categories: periodic tasks and event tasks. The data encoder will determine its task type based on whether the current task contains an interval judgment statement. When the off-chip task is completed or a data retransmission instruction is received, the central controller will control the data encoder to encode the sensor data and then output it to the communication interface. The encoding format of the sensor data is as follows: Figure 15 shown.

[0105] The foregoing description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the disclosed form and should not be construed as excluding other embodiments. Instead, the present invention is capable of various other combinations, modifications, and improvements, and can be modified within the scope of the present invention through the above teachings or techniques or knowledge in the relevant field. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention are intended to be within the scope of the appended claims.

Claims

1. A micro-power consumption redundant task layered universal execution circuit, characterized by: The execution circuit is arranged in the terminal, and the terminal is connected to the gateway. The execution circuit includes a central controller, a task instruction cache circuit, a sensor control circuit, an off-chip task execution circuit, and a data encoder; the central controller and the data encoder are respectively connected to the communication interface arranged in the terminal, and the sensor control circuit is connected to the sensor arranged in the terminal; The central controller parses the control instructions of the gateway, controls the erasing and writing of the task instruction cache circuit, and outputs instructions to the sensor control circuit and the off-chip task execution circuit, and controls the data encoder to output uplink data; the sensor control circuit outputs data to the off-chip task execution circuit, and the off-chip task execution circuit outputs control data to the task instruction cache circuit; The central controller includes a downlink data buffer, a status register, a control instruction parser, and a preamble detector. The downlink data buffer is a first shift register with serial input and parallel output. The data stream sent by the gateway is transmitted to the downlink data buffer. The preamble detector enables the control instruction parser when it matches the preamble. The control instruction parser completes the parsing of the control instruction, updates the status register according to the instruction content, generates a control signal, and realizes the control of the rest of the circuit. The central controller includes a registration state, a stop state, and a running state. When the central controller is in the running state, the task counter cyclically detects whether the start delay timer and execution cycle timer of each off-chip task have reached the preset time. If a task meets the execution condition, its corresponding task register outputs once, that is, the off-chip task is completely executed once. When the off-chip task execution circuit calls a sensor control task, it controls the called task register to output instruction data to the sensor control circuit, and will not continue to execute the off-chip task until the sensor control task is completed.

2. The micro-power consumption redundant task layered universal execution circuit according to claim 1, characterized in that: The task instruction cache circuit includes an instruction eraser, a task counter, an off-chip task controller and an instruction register group. The off-chip task controller contains an execution cycle timer and a start delay timer corresponding to each off-chip task; the output end of the instruction eraser is connected to the input end of the instruction register group, and the instruction register group is interconnected with the sensor control circuit; the output end of the off-chip task controller outputs the off-chip task to the off-chip task execution circuit, and the task counter counts the off-chip tasks.

3. The micro-power consumption redundant task layered universal execution circuit according to claim 2, characterized in that: When the central controller detects a task assignment instruction, it sends a control signal to the task instruction cache circuit to activate the eraser therein. The instruction eraser selects the instruction register to be erased according to the task type and task number carried in the task assignment instruction and erases the contents therein. If an off-chip task instruction is received, the instruction eraser configures the timer of the corresponding task number in the off-chip task controller. Subsequently, the instruction eraser transmits the gateway data stream to the selected instruction register according to the task instruction length information.

4. The micro-power consumption redundant task layered universal execution circuit according to claim 1, characterized in that: The sensor control circuit includes a first instruction parser, a second shift register, a delay timer, a raw data register group, an interface configuration unit and a signal interaction unit; When executing the sensor control task, the task instruction cache circuit transfers the sensor control instruction to the second shift register so that the first instruction parser can parse it and send control signals to the remaining units. The delay timer meets the timing requirements of different sensors. The raw data register group is used to temporarily store the data output by the sensor. The signal interaction unit realizes bus signal interaction, pin level reading and writing, and event signal detection functions. The interface configuration unit realizes flexible configuration of the working mode of the sensor interface.

5. The micro-power consumption redundant task layered universal execution circuit according to claim 1, characterized in that: The off-chip task execution circuit includes a third shift register, a second instruction parser, a data clipping circuit, an operation unit, a data combining circuit and a sensor data register group; The off-chip task execution circuit obtains the off-chip task instruction data through the third shift register, and the second instruction parser controls the remaining circuit structures to execute the instructions. The data combination circuit is responsible for extracting complete sensor data from the original data. The operation unit performs operation processing on the data in the sensor data register group and transmits the operation result back to the sensor data register group. The data clipping circuit is responsible for clipping the operation result and transmitting it to the data encoder.

6. The micro-power consumption redundant task layered universal execution circuit according to claim 5, characterized in that: The data combining circuit includes a data position mask register and a valid bit mask register. The data combining circuit selects each original data register in turn and determines whether to participate in data combining based on the output of the data position mask register. The original data register participating in data combining and the valid bit mask register start shifting and outputting at the same time. If the current output is valid, the sensing data register shifts and receives the output of the original data register. For signed numbers, if the first valid bit is 1, that is, the sensor data is a negative number, the data combination circuit will fill the entire sensor data register with 1 to expand the sign bit.

7. The micro-power consumption redundant task layered universal execution circuit according to claim 5, characterized in that: The operation unit includes an interval judgment circuit, a difference calculation circuit and a recursive average value calculation circuit; The interval judgment circuit includes a numerical comparator, which compares the sensing data with the left threshold and the right threshold data in sequence, and judges whether the data is valid based on the results of the two comparisons and the type of instruction, and then transmits the valid flag of the data to the data clipping circuit; The interval judgment circuit controls the response pin level according to the value of the response pin level field contained in the between and outside instructions and the judgment result, thereby notifying the external circuit of the change in the sensor data in real time; The difference calculation circuit includes a subtractor, a recently uploaded data register, and a latest data register. When the sub instruction is executed, the difference calculation circuit transfers the latest data C to the latest data register, then calculates the difference between the latest data C and the recently uploaded data D, and returns the calculation result CD to the sensor data register. The user can choose to perform interval judgment on the calculation result to implement threshold detection processing on the change amount of the sensor data and control the response pin to output high and low levels, or choose to skip the interval judgment correction and directly upload the change amount of the sensor data to the gateway. When the instruction is executed, if the sensor data is valid, the latest data is updated to the recently uploaded data register. The recursive average calculation circuit includes a sensor data queue, a queue summing circuit, a summing result register, a right shift circuit, and a sampling times counter; when the avg instruction is executed, the new sensor data is inserted into the end of the queue, the queue summing circuit reads the summing result register and the data at the head and end of the queue, calculates a new summing result, and writes it back to the summing result register; Based on the queue length set by the instruction, the right-shift circuit shifts the summation result rightward and transmits the resulting recursive average value back to the sensor data register. Based on application requirements, the user can choose whether to perform interval judgment on the recursive average value and respond in real time. When the value of the sampling count counter reaches the preset upload interval, the average value will be uploaded.

8. The micro-power consumption redundant task layered universal execution circuit according to claim 5, characterized in that: The data clipping circuit includes a valid flag register and a counter. When executing an upload instruction, the data clipping circuit selects the sensor data register according to the valid flag, and controls it to shift and output data of corresponding bits to the data encoder according to the bit number information carried in the upload instruction.

Images