Current register and control method thereof, image sensor

Abstract

The application provides a current register and a control method thereof and an image sensor, and comprises a transmission module for obtaining a signal current; an operation register module comprising a first register transistor, a second register transistor and a switch control unit; by controlling the state of the switch control unit, the first register transistor and the second register transistor perform inverse, addition, subtraction or multiplication operation on the signal current to obtain a result current, and the result current is stored. Only by using one operation register module, inverse, addition, subtraction and accumulation operations can be realized, and positive and negative currents can be stored, so that the circuit complexity is greatly reduced while the operation function is ensured, and the circuit area consumption is reduced, the integration is improved, the hardware cost is saved, and the problem of large area overhead of the current register is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and in particular, to a current register and a control method thereof, and an image sensor. BACKGROUND

[0002] At present, the basic structure form followed by the development of modern computers is always Von Neumann architecture, the core idea of which is to store programs and data in the same memory and access programs and data using memory addresses. The basic components of Von Neumann architecture include a central processing unit (CPU), a memory, an input device and an output device, wherein the memory is used to store programs and data, including instructions, operands and calculation results; the central processing unit obtains instructions and data from the memory and executes them; and the input device and the output device are respectively used to input and output data.

[0003] However, the separation design of the computing unit and the storage unit in Von Neumann architecture leads to a "memory wall" bottleneck, that is, the transmission rate of data between the memory and the processor is much lower than the processing speed of the computing unit. This contradiction is further intensified with the rapid development of CMOS image sensor (CIS) technology: the resolution of modern CIS chips has entered the era of hundreds of millions of pixels (such as 108MP or more), the frame rate has been increased to 120fps or even higher, and the single-frame data volume increases exponentially, especially in practical application scenarios such as target detection and image recognition, the transmission and storage of massive data not only causes waste of bandwidth resources, but also significantly increases system power consumption and delay.

[0004] To solve the above problems, a local storage and calculation preprocessing technology is proposed by the research and development personnel, which realizes data processing nearby by embedding a computing unit into a storage array, and significantly improves the energy efficiency ratio. Among them, the sense and calculation chip based on the current domain becomes a research hotspot due to its natural parallelism, low voltage operation and anti-noise advantage. However, in the application of the prior art, the current register as an analog storage and calculation unit needs to be matched with multiple current registers to realize simple algorithms, resulting in large area overhead and difficulty in meeting the demand for high integration. SUMMARY

[0005] The present application relates to the technical field of integrated circuit design, and in particular, to a current register and a control method thereof, and an image sensor.

[0006] To solve the above technical problems, the application provides a current register, comprising: a transmission module, used for obtaining a signal current; an operation register module, comprising a first register transistor, a second register transistor and a switch control unit; by controlling the state of the switch control unit, the first register transistor and the second register transistor are used to realize the operation of the signal current in the form of inversion, addition, subtraction or multiplication to obtain a result current, and the result current is stored.

[0007] Optionally, in the current register, the switch control unit comprises a first switch, a second switch, a third switch and a fourth switch.

[0008] The source of the first register transistor is connected to the ground, the gate and the source are connected through the first switch, and the gate and the drain are connected through the second switch; the drain of the first register transistor is also connected to the drain of the second register transistor and the transmission module; the gate and the drain of the second register transistor are connected through the third switch, and the gate and the source are connected through the fourth switch; and the source of the second register transistor is connected to a power supply.

[0009] Optionally, in the current register, the first switch, the second switch, the third switch and the fourth switch are all transistors.

[0010] The gate of the first register transistor is connected to the drain of the first switch and the source of the second switch, the source of the first register transistor is connected to the source of the first switch, and the drain of the first register transistor is connected to the drain of the second switch; the gate of the second register transistor is connected to the source of the third switch and the drain of the fourth switch, the drain of the second register transistor is connected to the drain of the third switch, and the source of the second register transistor is connected to the source of the fourth switch; the gate of the first switch is connected to a first reset signal, the gate of the second switch is connected to a first write signal, the gate of the third switch is connected to a second write signal, and the gate of the fourth switch is connected to a second reset signal.

[0011] Optionally, in the current register, the first register transistor is an NMOS, the second register transistor is a PMOS, the first switch and the second switch are both NMOS, and the third switch and the fourth switch are both PMOS.

[0012] Optionally, in the current register, the transmission module comprises a transmission switch; one end of the transmission switch is connected to the drain of the first register transistor and the drain of the second register transistor, and the other end is connected to a bus.

[0013] Optionally, in the current register, the transmission switch is a transistor group switch, and the transistor group switch comprises a first transmission transistor and a second transmission transistor.

[0014] The drain of the first transmission transistor is connected with the source of the second transmission transistor and is connected to the bus; the source of the first transmission transistor is connected with the drain of the second transmission transistor and is connected to the drain of the first register transistor and the drain of the second register transistor; the gate of the first transmission transistor is connected to an enable signal, and the gate of the second transmission transistor is connected to an inverse enable signal.

[0015] Optionally, in the current register, the first transmission transistor is an NMOS, and the second transmission transistor is a PMOS.

[0016] Optionally, in the current register, the switch control unit comprises a fifth switch, a sixth switch, a seventh switch and an eighth switch; the fifth switch, the sixth switch, the seventh switch and the eighth switch are all transistors.

[0017] The source of the first register transistor is connected to ground, the gate of the first register transistor is connected with the source of the fifth switch, and the drain of the first register transistor is connected with the source of the sixth switch; the drain of the fifth switch is connected with the drain of the sixth switch; the source of the second register transistor is connected to a power supply, the gate of the second register transistor is connected with the source of the seventh switch, and the drain of the second register transistor is connected with the source of the eighth switch; the drain of the seventh switch is connected with the drain of the eighth switch; the drain of the sixth switch and the drain of the eighth switch are connected and connected to a bus; the gate of the fifth switch is connected to a first write signal, the gate of the sixth switch is connected to a first read signal, the gate of the seventh switch is connected to a second write signal, and the gate of the eighth switch is connected to a second read signal.

[0018] Optionally, in the current register, the first register transistor is an NMOS, the second register transistor is a PMOS, the fifth switch and the sixth switch are both NMOS, and the seventh switch and the eighth switch are both PMOS.

[0019] Optionally, in the current register, the transmission module is composed of the sixth switch and the eighth switch.

[0020] To solve the above technical problems, the application further provides a control method of a current register, which is used for realizing the positive current read and write of the current register as described in any one of the above, and the control method comprises the following steps of:

[0021] In the writing process, the state of the transmission module is controlled to connect the operation register module with the bus; the state of the switch control unit is controlled to short the gate-drain of the first register transistor and to turn off the second register transistor; at this time, the positive current at the bus is input into the first register transistor through the transmission module and is converted into gate voltage at the gate of the first register transistor;

[0022] In the holding state, the state of the transmission module is controlled to disconnect the operation register module from the bus; the state of the switch control unit is controlled to disconnect the gate-drain of the first register transistor and to keep the second register transistor turned off; at this time, the drain voltage of the first register transistor is discharged to 0 and the static current is 0;

[0023] In the reading process, the state of the transmission module is controlled to connect the operation register module with the bus; the state of the switch control unit is kept to disconnect the gate-drain of the first register transistor and to keep the second register transistor turned off; at this time, the first register transistor is in the saturation region and the positive current written is read out.

[0024] To solve the above technical problems, the application further provides a control method of the current register, which is used to realize the negative current reading and writing of the current register as claimed in any one of the above.

[0025] In the writing process, the state of the transmission module is controlled to connect the operation register module with the bus; the state of the switch control unit is controlled to short the gate-drain of the first register transistor and to turn off the second register transistor; at this time, the positive current at the bus is input into the first register transistor through the transmission module and is converted into gate voltage at the gate of the first register transistor;

[0026] In the holding state, the state of the transmission module is controlled to disconnect the operation register module from the bus; the state of the switch control unit is controlled to disconnect the gate-drain of the first register transistor and to keep the second register transistor turned off; at this time, the drain voltage of the first register transistor is discharged to 0 and the static current is 0;

[0027] In the reading process, the state of the transmission module is controlled to connect the operation register module with the bus; the state of the switch control unit is kept to disconnect the gate-drain of the first register transistor and to keep the second register transistor turned off; at this time, the first register transistor is in the saturation region and the positive current written is read out.

[0028] To solve the above technical problems, the application further provides a control method of the current register, which is used to realize the current inversion operation of the current register as any one of the above.

[0029] The state of the transmission module and the switch control unit is controlled so that the current register is in a holding state; at this time, the gate-drain of the first register transistor is disconnected, the gate-source is disconnected, the gate-source of the second register transistor is disconnected, and the gate-drain is short-circuited; at this time, the signal current is stored in the gate of the first register transistor in the form of voltage.

[0030] The state of the switch control unit is controlled so that the gate-drain of the first register transistor is disconnected, the gate-source is disconnected, the gate-source of the second register transistor is disconnected, and the gate-drain is short-circuited; at this time, the first register transistor works in the saturation region, the first register transistor transmits the signal current to the second register transistor, and generates a gate voltage at the gate of the second register transistor.

[0031] The state of the switch control unit is controlled so that the gate-source of the second register transistor is disconnected, the gate-drain is disconnected, the gate-drain of the first register transistor is disconnected, and the gate-source is short-circuited; at this time, the gate voltage of the first register transistor is discharged, and the first register transistor is in an off state, the first register transistor transmits the current to the second register transistor for storage, and the current is inverted.

[0032] To solve the above technical problems, the application further provides a control method of the current register, which is used to realize the current inversion operation of the current register as any one of the above.

[0033] The state of the transmission module and the switch control unit is controlled so that the gate-drain of the first register transistor is disconnected, the gate-source is short-circuited, the gate-source of the second register transistor is disconnected, and the gate-drain is disconnected; at this time, the second register transistor stores the signal current after the inversion operation.

[0034] The state of the transmission module is controlled so that the operation register module is connected to the bus; the state of the switch control unit is controlled so that the gate-drain of the first register transistor is short-circuited, the gate-source is disconnected, the gate-source of the second register transistor is disconnected, and the gate-drain is disconnected; at this time, the other signal current to be added at the bus is input into the first register transistor through the transmission module, so that the current flowing through the first register transistor is the sum of the signal current stored in the second register transistor after the inversion operation and the other signal current to be added, and a corresponding gate voltage is generated at the gate of the first register transistor.

[0035] controlling the state of the switch control unit so that the gate-drain of the first register transistor is disconnected, the gate-source remains disconnected, and controlling the state of the transmission module and the switch control unit so that the operation register module is disconnected from the bus, the gate-source of the second register transistor is short-circuited, and the gate-drain remains disconnected; at this time, the second register transistor is in an off state, and the first register transistor stores the result of the current addition operation in the form of voltage at the gate.

[0036] To solve the above technical problems, the application further provides a control method of a current register, which is used for realizing the current subtraction operation of the current register according to any one of the above.

[0037] controlling the state of the switch control unit so that the gate-drain of the first register transistor is disconnected, the gate-source remains disconnected, and controlling the state of the transmission module and the switch control unit so that the operation register module is disconnected from the bus, the gate-source of the second register transistor is short-circuited, and the gate-drain remains disconnected; at this time, the second register transistor is in an off state, and the first register transistor stores the result of the current addition operation in the form of voltage at the gate.

[0038] controlling the state of the switch control unit so that the gate-drain of the first register transistor is disconnected, the gate-source remains disconnected, and controlling the state of the transmission module and the switch control unit so that the operation register module is disconnected from the bus, the gate-source of the second register transistor is short-circuited, and the gate-drain remains disconnected; at this time, the second register transistor is in an off state, and the first register transistor stores the result of the current addition operation in the form of voltage at the gate.

[0039] controlling the state of the switch control unit so that the gate-drain of the first register transistor is disconnected, the gate-source remains disconnected, and controlling the state of the transmission module and the switch control unit so that the operation register module is disconnected from the bus, the gate-source of the second register transistor is short-circuited, and the gate-drain remains disconnected; at this time, the second register transistor is in an off state, and the first register transistor stores the result of the current addition operation in the form of voltage at the gate.

[0040] To solve the above technical problems, the application further provides an image sensor comprising the current register according to any one of the above.

[0041] The present invention provides a current register and its control method, and an image sensor, comprising: a transmission module for acquiring signal current; and an arithmetic register module for performing inversion, addition, subtraction, or multiplication operations on the signal current to obtain a result current, and storing the result current. By using only one arithmetic register module, inversion, addition, subtraction, and accumulation operations can be implemented, and positive and negative currents can be stored. This significantly reduces circuit complexity while ensuring operational functionality, thereby reducing circuit area consumption, improving integration, saving hardware costs, and solving the problem of large area overhead in existing current registers. Attached Figure Description

[0042] Figure 1 The circuit schematic of an existing current register;

[0043] Figure 2 This is a schematic diagram of the module structure of the current register provided in this embodiment;

[0044] Figure 3 The circuit schematic of the current register provided in this embodiment;

[0045] Figure 4 This is a specific circuit structure diagram of the current register provided in this embodiment;

[0046] Figure 5 This is an example. Figure 4 The provided signal control timing diagram for the current register;

[0047] Figure 6 Another specific circuit structure diagram of the current register provided in this embodiment;

[0048] Figure 7 This is an example. Figure 6 The provided signal control timing diagram for the current register;

[0049] Figure 8 The circuit structure diagram for the positive current read / write process of the current register provided in this embodiment;

[0050] Figure 9 The circuit structure diagram for the negative current read / write process of the current register provided in this embodiment;

[0051] Figure 10 The circuit structure diagram for the current inversion operation process of the current register provided in this embodiment;

[0052] Figure 11 The circuit structure diagram of the current addition operation process of the current register provided in this embodiment;

[0053] Figure 12A circuit structure diagram of a current subtraction operation process of the current register provided in the embodiment;

[0054] Figure 13 A system structure diagram of a current division operation process of the current register provided in the embodiment. DETAILED DESCRIPTION

[0055] The current register, the control method thereof and the image sensor according to the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that all the drawings are in a very simplified form and all use non-precise proportions, only for the purpose of conveniently and clearly assisting in the description of the embodiments of the present application. In addition, the structures shown in the drawings are often a part of the actual structures. In particular, the emphasis of each drawing needs to be different, and sometimes different proportions are used.

[0056] It should be noted that "first", "second", and the like in the description and claims of the present application and the drawings are used to distinguish similar objects in order to describe the embodiments of the present application, and are not intended to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0057] The existing current register has a structure as shown in (a) of Figure 1 Generally includes a current source, a MOS transistor and two switches, wherein the source of the MOS transistor MN is grounded, the drain and the gate are connected through the switch Sw, and the drain is connected to the current source; the input and output end is led out through the switch Sr between the drain of the MOS transistor MN and the current source. The working principle is roughly as follows:

[0058] In the writing stage, as shown in (b) of Figure 1 The signal current Iin input through the switch Sr and the bias current Ib provided by the current source both flow through the MOS transistor MN, at this time the drain current Ids of the MOS transistor MN = Iin + Ib, and a corresponding self-bias voltage Vx is generated at the gate.

[0059] In the holding stage, the two switches Sr and Sw are both disconnected, and the self-bias voltage Vx is saved at the gate of the MOS transistor MN.

[0060] In the readout stage, the switch Sr is closed, and the readout current Iread = Ids - Ib, that is, Iread = Iin.

[0061] As can be seen from the working principle of the existing current register, the MOS transistor with the gate-drain short connection converts the input current into a voltage and stores the voltage at the gate of the MOS transistor. The drain current of the MOS transistor working in the saturation region mainly depends on the size of the gate voltage, so that in the readout stage, the gate voltage can be restored to the drain current; and according to the Kirchhoff's current law, the current Ids flowing through the MOS transistor is equal to Ib+Iread, and the readout current Iread=Ids-Ib=Iin is obtained.

[0062] To solve the problem that a plurality of current registers need to be cooperated to realize the inversion, addition, subtraction and accumulation (multiplication) operations, resulting in a large circuit area consumption, the embodiment provides a current register, as shown in the following formula (I): Figure 2 The current register comprises a transmission module, an operation register module and a readout module.

[0063] The transmission module is used for obtaining a signal current from a bus.

[0064] The operation register module comprises a first register transistor, a second register transistor and a switch control unit. By controlling the state of the switch control unit, the first register transistor and the second register transistor perform inversion, addition, subtraction or multiplication operation on the signal current to obtain a result current, and store the result current.

[0065] The current register provided by the embodiment can realize inversion, addition, subtraction and accumulation operations by only one operation register module, and can also store positive and negative currents, so that the circuit complexity is greatly reduced while the operation function is ensured, and the circuit area consumption is reduced, the integration is improved, and the hardware cost is saved.

[0066] Specifically, in the embodiment, as shown in the following formula (I), the operation register module comprises a first register transistor M01, a second register transistor M02 and a switch control unit, and the switch control unit comprises a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4. Figure 3 The source of the first register transistor M01 is grounded, the gate and the source are connected through the first switch S1, and the gate and the drain are connected through the second switch S2. The drain of the first register transistor M01 is also connected with the drain of the second register transistor M02, and is connected with the transmission module. The gate and the drain of the second register transistor M02 are connected through the third switch S3, and the gate and the source are connected through the fourth switch S4. The source of the second register transistor M02 is connected with a power supply.

[0067]

[0068] ​And, the transmission module comprises a transmission switch Sc; one end of the transmission switch Sc is connected with the drain of the first register transistor M01 and the drain of the second register transistor M02, and the other end is connected with the bus.

[0069] In a specific embodiment, as shown in Figure 4 The first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are all transistors, and are sequentially recorded as M11, M12, M13 and M14 respectively.

[0070] The gate of the first register transistor M01 is connected with the drain of the first switch M11 and the source of the second switch M12, the source of the first register transistor M01 is connected with the source of the first switch M11 and grounded, and the drain of the first register transistor M01 is connected with the drain of the second switch M12; the gate of the second register transistor M02 is connected with the source of the third switch M13 and the drain of the fourth switch M14, the drain of the second register transistor M02 is connected with the drain of the third switch M13, and the source of the second register transistor M02 is connected with the source of the fourth switch M14 and connected with a power supply. The gate of the first switch M11 is connected with a first reset signal Nrst, the gate of the second switch M12 is connected with a first write signal Nwrite, the gate of the third switch M13 is connected with a second write signal Pwrite, and the gate of the fourth switch M14 is connected with a second reset signal Prst.

[0071] And, in the embodiment, as shown in Figure 4 The transmission switch is a transistor group switch, and the transistor group switch comprises a first transmission transistor M21 and a second transmission transistor M22.

[0072] The drain of the first transmission transistor M21 is connected with the source of the second transmission transistor M22 and connected with the bus; the source of the first transmission transistor M21 is connected with the drain of the second transmission transistor M22 and connected with the drain of the first register transistor M01 and the drain of the second register transistor M02; the gate of the first transmission transistor M21 is connected with an enable signal EN, and the gate of the second transmission transistor M22 is connected with an inverse enable signal ENB.

[0073] In practical applications, the first register transistor is NMOS, the second register transistor is PMOS, the first switch and the second switch are both NMOS, the third switch and the fourth switch are both PMOS, the first transfer transistor is NMOS, and the second transfer transistor is PMOS. In addition, the inverse enable signal ENB is the inverse signal of the enable signal EN, that is, the inverse enable signal ENB can be obtained by inverting the enable signal EN.

[0074] Further, corresponding to Figure 4 the circuit structure of the current register shown in the figure, the embodiment provides corresponding signal control timing, as Figure 5 shown. The timing of the enable signal EN, the first reset signal Nrst, the first write signal Nwrite, the second write signal Pwrite, and the second reset signal Prst corresponding to the write, hold, read, inverse, inverse read, addition, and subtraction operations is provided. By the level input of each signal, the state control of the transistor switch is realized, and the above-mentioned working process is realized accordingly.

[0075] In practical applications, the signal timing corresponding to each process can be combined according to actual needs, so as to realize, for example, non-integer multiple multiplication data writing and reading, etc., which is not limited in the present application.

[0076] In another specific embodiment, as Figure 6 shown, the operation register module includes a first register transistor M01, a second register transistor M02, and a switch control unit, and the switch control unit includes a fifth switch M31, a sixth switch M32, a seventh switch M33, and an eighth switch M34, all of which are transistors.

[0077] The source of the first register transistor M01 is connected to ground, the gate of the first register transistor M01 is connected to the source of the fifth switch M31, and the drain of the first register transistor M01 is connected to the source of the sixth switch M32; the drain of the fifth switch M31 is connected to the drain of the sixth switch M32; the source of the second register transistor M02 is connected to a power supply, the gate of the second register transistor M02 is connected to the source of the seventh switch M33, and the drain of the second register transistor M02 is connected to the source of the eighth switch M34; the drain of the seventh switch M33 is connected to the drain of the eighth switch M34; the drain of the sixth switch M32 and the drain of the eighth switch M34 are connected and connected to the bus. The gate of the fifth switch M31 is connected to the first write signal Nwrite, the gate of the sixth switch M32 is connected to the first read signal Nread, the gate of the seventh switch M33 is connected to the second write signal Pwrite, and the gate of the eighth switch M34 is connected to the second read signal Pread.

[0078] In the embodiment, the sixth switch M32 and the eighth switch M34 are not only used for controlling the states of the first register transistor M01 and the second register transistor M02, but also used as the transmission module to realize the transmission of the signal current. Thus, compared with the current register shown in Figure 4 , the circuit structure of the current register shown in Figure 6 is more simple and the circuit area is smaller.

[0079] In practical application, the first register transistor M01 is NMOS, the second register transistor M03 is PMOS, the fifth switch M31 and the sixth switch M32 are both NMOS, and the seventh switch M33 and the eighth switch M34 are both PMOS.

[0080] Corresponding to the circuit structure of the current register shown in Figure 6 , the embodiment also provides corresponding signal control timing, as shown in Figure 7 . The timing of the first write signal Nwrite, the first read signal Nread, the second write signal Pwrite and the second read signal Pread corresponding to the write, hold, read, inversion, inverted read, addition, subtraction operations is provided. Through the level input of each signal, the state control of the transistor switch is realized, and then the above working process is realized.

[0081] Similarly, in practical application, the signal timing corresponding to each process can be combined according to actual needs, so as to realize, for example, the data writing and reading of non-integer multiple multiplication, etc., which is not limited in the present application.

[0082] In the following, the working principle of the current register provided by the embodiment to realize the inversion, addition, subtraction, accumulation operation and store the positive and negative currents is described in combination with the circuit schematic diagram of the current register shown in Figure 3 .

[0083] Referring to Figure 8 , the control method for realizing the positive current read-write of the current register provided by the embodiment mainly includes:

[0084] In the writing process, the state of the transmission module is controlled to make the operation register module connected with the bus, and the state of the switch control unit is controlled to make the gate-drain of the first register transistor short-circuited and the second register transistor in the off state. Specifically, as shown in Figure 8 .In the write process, the state of the transmission module is controlled to connect the operation register module with the bus; the state of the switch control unit is controlled to connect the gate and the drain of the first register transistor, and the second register transistor is kept in the off state. Specifically, as shown in (a) of the figure, the transmission switch Sc is controlled to be closed to connect the operation register module with the bus; at the same time, the first switch S1 is controlled to be disconnected, the second switch S2 is controlled to be connected, the third switch S3 is controlled to be disconnected, and the fourth switch S4 is controlled to be connected to connect the gate and the drain of the first register transistor M01, and the second register transistor M02 is in the off state.

[0085] In the holding state, the state of the transmission module is controlled to disconnect the operation register module from the bus; the state of the switch control unit is controlled to disconnect the gate and the drain of the first register transistor, and the second register transistor is kept in the off state. Specifically, as shown in (b) of the figure, the transmission switch Sc is controlled to be disconnected to disconnect the operation register module from the bus; at the same time, the second switch S2 is controlled to be disconnected, the first switch S1 and the third switch S3 are kept disconnected, and the fourth switch S4 is kept connected to disconnect the gate and the drain of the first register transistor M01, and the gate voltage Vx is saved in the gate of the first register transistor M01; at the same time, since the second register transistor M02 is in the off state, the transmission switch Sc is also in the open circuit, so at this time, after the first register transistor M01 discharges the charge of the drain, the drain voltage drops to 0, i.e. V2=0, so the static current of the first register transistor M01 is 0 in the holding stage. Figure 8

[0086] In the read process, the state of the transmission module is controlled to connect the operation register module with the bus; the state of the switch control unit is controlled to disconnect the gate and the drain of the first register transistor, and the second register transistor is kept in the off state. Specifically, as shown in (c) of the figure, the transmission switch Sc is controlled to be connected to connect the operation register module with the bus; at the same time, the states of the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are kept unchanged (the first switch S1, the second switch S2 and the third switch S3 are disconnected, and the fourth switch S4 is connected). At this time, since the second register transistor M02 is still in the off state, and the first register transistor M01 is in the saturation region, the positive current written from the first register transistor M01 is read, i.e. Iread=Iin. Figure 8 Referring to

[0087] , the control method for realizing negative current reading and writing provided by the current register mainly includes: Figure 9

[0088] ​​During the writing process, the state of the transmission module is controlled to connect the arithmetic register module to the bus; the state of the switch control unit is controlled to turn off the first register transistor and short-circuit the gate and drain of the second register transistor. Specifically, as follows... Figure 9 As shown in (a), the control transmission switch Sc is closed to connect the operational register module to the bus; simultaneously, the first switch S1 is closed, the second switch S2 is open, the third switch S3 is closed, and the fourth switch S4 is open, so that the gate-drain of the second register transistor M02 is short-circuited and in a diode connection state, while the first register transistor M01 is in a turn-off state, and the gate voltage V1 of the first register transistor M01 is 0. At this time, the negative current Iin at the bus is input to the second register transistor M02 through the transmission module (transmission switch Sc), and the gate voltage Vz is obtained at the gate of the second register transistor M02.

[0089] In the holding state, the state of the transmission module is controlled to disconnect the arithmetic register module from the bus; the state of the switch control unit is controlled to disconnect the gate and drain of the second register transistor, while the first register transistor remains in the off state. Specifically, as follows... Figure 9 As shown in (b), the control transmission switch Sc is opened to disconnect the arithmetic register module from the bus; at the same time, the control third switch S3 is opened, the first switch S1 remains closed, and the second switch S2 and the fourth switch S4 remain open, so that the gate and drain of the second register transistor M02 are disconnected, and the gate voltage Vz is stored in the gate of the second register transistor M02. Meanwhile, since the first register transistor M01 is in the off state and the transmission switch Sc is also in the open circuit, the drain voltage of the second register transistor M02 is charged to the power supply voltage, i.e., V2=VDD. Therefore, during the holding phase, the static current of the second register transistor M02 is 0.

[0090] During the readout process, the state of the transmission module is controlled to connect the arithmetic register module to the bus; the state of the switch control unit is maintained so that the gate and drain of the second register transistor remain open, and the first register transistor remains off. Specifically, as follows... Figure 9 As shown in (c), the control transmission switch Sc is closed to connect the operational register module to the bus; simultaneously, the states of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 remain unchanged (the first switch S1 is closed, and the second switch S2, the third switch S3, and the fourth switch S4 are open). At this time, since the first register transistor M01 is still in the off state and the second register transistor M02 is in the saturation region, the written negative current is read from the second register transistor M02, i.e., Iread = Iin.

[0091] Since the circuit structure of the current register provided in this embodiment is symmetrical, the reading and writing process of negative current is also completely symmetrical with that of positive current.

[0092] See Figure 10 The control method for implementing current inversion operation using a current register provided in this embodiment mainly includes:

[0093] A1 controls the state of the transmission module and the switch control unit so that the current register is in a holding state; at this time, the gate-drain and gate-source of the first register transistor are disconnected, the gate-drain of the second register transistor is disconnected, and the gate-source is short-circuited, and the signal current is stored in the gate of the first register transistor in the form of voltage.

[0094] Specifically, such as Figure 10 In (b), the holding state in the positive current read / write control method can be implemented based on the current register provided in this embodiment. Figure 8 In state (b), the transmission switch Sc is turned off, so that the operation register module is disconnected from the bus; at the same time, the first switch S1, the second switch S2 and the third switch S3 are turned off, and the fourth switch S4 is closed, so that the gate and drain of the first register transistor M01 are disconnected, the second register transistor M02 is in the off state, the gate voltage Vx is stored in the gate of the first register transistor M01, and the static current is 0.

[0095] A2 controls the state of the switch control unit so that the gate-drain of the first register transistor remains open and the gate-source remains open, while the gate-source of the second register transistor is open and the gate-drain is short-circuited. At this time, the first register transistor operates in the saturation region, and the first register transistor transmits the signal current to the second register transistor, generating a gate voltage at the gate of the second register transistor.

[0096] Specifically, such as Figure 10 In step (d), keep the transmission switch Sc open, first open the fourth switch S4, and then close the third switch S3 so that the first register transistor M01 works in the saturation region and the second register transistor M02 is in the diode connection state. At this time, the operating current of the current register is Iin, that is, the first register transistor M01 transmits the signal current to the second register transistor M02 and generates a gate voltage Vz at the gate of the second register transistor M02.

[0097] A3, control the state of the switch control unit, so that the gate-source of the second register transistor is kept off, the gate-drain is kept off, the gate-drain of the first register transistor is kept off, and the gate-source is shorted; at this time, the gate voltage of the first register transistor is discharged, and the first register transistor is in an off state, the current is transferred to the second register transistor for storage, and the current is reversed.

[0098] Specifically, as shown in (e) of FIG. 6, the transmission switch Sc is kept off, the third switch S3 is first opened, so that the gate voltage Vz is stored in the gate of the second register transistor M02; then the first switch S1 is closed, and the voltage Vx originally stored in the gate of the first register transistor M01 is discharged, so that the first register transistor M01 enters an off state, and the static current is 0. Figure 10

[0099] In this way, the current stored in the first register transistor M01 is transferred to the second register transistor M02 in the form of voltage, and the current direction is changed.

[0100] Referring to FIG. 6, Figure 11 The control method for implementing the current addition operation of the current register provided in the embodiment mainly includes the following steps:

[0101] B1, control the state of the transmission module and the switch control unit, so that the gate-drain of the first register transistor is kept off, the gate-source is shorted, the gate-source of the second register transistor is kept off, and the gate-drain is kept off; at this time, the second register transistor stores a signal current after the inversion operation.

[0102] Specifically, as shown in (e) of FIG. 6, the transmission switch Sc is kept off, the third switch S3 is first opened, so that the gate voltage Vz is stored in the gate of the second register transistor M02; then the first switch S1 is closed, and the voltage Vx originally stored in the gate of the first register transistor M01 is discharged, so that the first register transistor M01 enters an off state, and the static current is 0. Figure 11 Figure 10 (e) state in the control method for implementing the inversion operation of the current register provided in the embodiment, at this time, the transmission switch Sc is kept off, the first switch S1 is closed, the second switch S2, the third switch S3 and the fourth switch S4 are opened, and the second register transistor M02 has stored a current Iin1 after the inversion operation.

[0103] B2, control the state of the transmission module, so that the operation register module is connected with the bus; control the state of the switch control unit, so that the gate-drain of the first register transistor is shorted, the gate-source is kept off, the gate-source of the second register transistor is kept off, and the gate-drain is kept off; at this time, another signal current to be added at the bus is input to the first register transistor through the transmission module, so that the current flowing through the first register transistor is the sum of the signal current stored in the second register transistor after the inversion operation and the input another signal current to be added, and a corresponding gate voltage is generated at the gate of the first register transistor.​​

[0104] Specifically, as shown in (f) of Figure 11 , the transmission switch Sc is controlled to be closed, the first switch S1 is controlled to be open, the second switch S2 is controlled to be closed, and the third switch S3 and the fourth switch S4 are controlled to remain unchanged (remain open), so that the first register transistor M01 enters a write state, at this time, a signal current Iin2 to be added is refilled from the bus through the transmission switch Sc, so that the current flowing through the first register transistor M01 is Iin1+Iin2, and a corresponding self-bias voltage Vx2 is generated at the gate.

[0105] B3, the state of the switch control unit is controlled so that the gate-drain of the first register transistor is open, and the gate-source remains open, and then the state of the transmission module and the switch control unit is controlled so that the operation register module is disconnected with the bus, the gate-source of the second register transistor is short-circuited, and the gate-drain remains open; at this time, the second register transistor is in an off state, and the first register transistor stores the result of the current addition operation in the form of voltage at the gate.

[0106] Specifically, as shown in (g) of Figure 11 , the second switch S2 is first opened, so that the self-bias voltage Vx2 is saved at the gate of the first register transistor M01; then the transmission switch Sc is opened, and the fourth switch S4 is closed, and the first switch S1 and the third switch S3 remain in the open state. At this time, the second register transistor M02 is in an off state, and the static current is 0.

[0107] In this way, the addition operation of the two input signal currents Iin1 and Iin2 is realized, and the summed signal current is saved in the current register.

[0108] Referring to Figure 12 , the control method for realizing the current subtraction operation of the current register provided by the embodiment mainly includes:

[0109] C1, the state of the transmission module and the switch control unit is controlled so that the operation register module is connected with the bus, the gate-drain of the first register transistor is short-circuited, and the gate-source is open, and the gate-source of the second register transistor is short-circuited, and the gate-drain is open; at this time, the first register transistor stores the input signal current.

[0110] Specifically, as shown in (a) of Figure 12 , the write state (the (a) state of Figure 8 ) in the control method for realizing the positive current read-write of the current register provided by the embodiment can be realized, at this time, the signal current Iin1 is written into the current register, and a corresponding gate voltage Vx is generated at the gate of the first register transistor M01.

[0111] C2, controlling the state of the switch control unit, so that the gate-drain of the first register transistor is disconnected, the gate-source is kept disconnected, and the gate-source of the second register transistor is disconnected, and the gate-drain is shorted; at this time, the other signal current to be subtracted at the bus is input to the operation register module through the transmission module, and since the first register transistor is in the saturation region, the current flowing through the second register transistor is the difference between the signal current stored by the first register transistor and the other signal current to be subtracted input, and a corresponding gate voltage is generated at the gate of the second register transistor.

[0112] Specifically, as shown in (h) of FIG. 6, the second switch S2 is first disconnected, so that the gate voltage Vx is saved at the gate of the first register transistor M01; then the fourth switch S4 is disconnected, and the third switch S3 is closed, so that the second register transistor M02 enters the write state; at this time, a signal current Iin2 to be subtracted is recharged from the bus through the transmission switch Sc. Since the first register transistor M01 is in the saturation region, the current flowing through the first register transistor M01 is still Iin1, and according to Kirchhoff's current law, the current flowing through the second register transistor M02 is Iin1-Iin2, and a corresponding self-bias voltage Vz2 is generated at the gate of the second register transistor M02. Figure 12

[0113] C3, controlling the state of the switch control unit, so that the gate-source of the second register transistor is kept disconnected, and the gate-drain is disconnected; controlling the state of the transmission module and the switch control unit, so that the operation register module is disconnected from the bus, and the gate-drain of the first register transistor is kept disconnected, and the gate-source is shorted; at this time, the first register transistor is in the off state, and the second register transistor stores the result of the current subtraction operation in the form of voltage at the gate.

[0114] Specifically, as shown in (i) of FIG. 6, the third switch S3 is first disconnected, so that the self-bias voltage Vz2 is saved at the gate of the second register transistor M02; then the transmission switch Sc is disconnected, and the first switch S1 is closed, so that the first register transistor M01 is in the off state, and the static current is 0. Figure 12

[0115] In this way, the subtraction operation of the two input signal currents Iin1 and Iin2 is realized, and the subtracted signal current is saved in the current register.

[0116] ​​It should be noted that since the current of the second register transistor M02 cannot be negative, the signal current Iin2 must be less than or equal to the signal current Iin1 when performing subtraction. In practical applications, to achieve subtraction when the signal current Iin2 is greater than the signal current Iin1, another current register is needed. Iin1 is temporarily stored first, and then the order of subtraction is reversed (Iin2 as the minuend and Iin1 as the subtrahend) to obtain the result Iin2 - Iin1. Then, the result is inverted to obtain Iin1 - Iin2 (Iin2 > Iin1).

[0117] For the current register provided in this embodiment, current multiplication (accumulation) operations can be implemented through iterative addition. For example, first write the signal current Ix; then perform inversion and addition operations on the signal current Ix sequentially to obtain 2Ix; perform inversion and addition operations again to obtain 3Ix; and so on, thus achieving integer multiple current multiplication operations. Furthermore, based on the current register provided in this embodiment, multiplication operations can be completed with only one current register.

[0118] The current register provided in this embodiment requires multiple current registers to perform current division operations, such as... Figure 13 As shown, N+1 registers (AREG) are connected to the bus. A read operation is performed on AREG0, and write operations are performed on AREG1 through AREGN. According to Kirchhoff's Current Law, the current flowing out of a circuit node equals the current flowing into it. Therefore, when the current flowing out of AREG0 is I0, each register from AREG1 to AREGN shares the current I0 equally, resulting in each register receiving a current of I0 / N. This achieves division operations where the current is an integer multiple.

[0119] Furthermore, for multiplication or division operations that are not integer multiples, they can be obtained in fractional form by combining integer multiple multiplication and integer multiple division. For example, to achieve 1.5Iy, it can be decomposed into Iy × 3 / 2, that is, first perform a three-fold accumulation operation on Iy, and then perform a two-fold division operation to obtain 1.5Iy. Those skilled in the art can understand the implementation process of multiplication and division of other arbitrary multiples by the current register provided in this embodiment through the above examples, and this application will not elaborate further on this.

[0120] This embodiment also provides an image sensor, including the current register described above.

[0121] When the current register provided in this embodiment is used in an image sensor, the circuit complexity can be significantly reduced while ensuring the computational function, thereby reducing circuit area consumption, improving integration, and saving hardware costs.

[0122] It should be noted that the various embodiments described in the specification are progressive in nature, and each embodiment highlights the differences from other embodiments, and the same and similar parts between embodiments can be mutually referred to, and in addition, the different parts between the various embodiments can also be used in combination with each other, and the present application is not limited thereto.

[0123] The current register and the control method thereof and the image sensor provided by the embodiment comprise a transmission module configured to obtain a signal current; an operation register module comprising a first register transistor, a second register transistor and a switch control unit; by controlling the state of the switch control unit, the first register transistor and the second register transistor are enabled to perform the inverse, addition, subtraction or multiplication operation on the signal current to obtain a result current, and the result current is stored. By using only one operation register module, the inverse, addition, subtraction and accumulation operations can be realized, and the positive and negative currents can also be stored, so that the circuit complexity is greatly reduced while the operation function is ensured, and the circuit area consumption is reduced, the integration is improved, the hardware cost is saved, and the problem of large area overhead of the current register is solved.

[0124] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way, and any modification or modification of the present application by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A current register, characterized in that, include: The transmission module is used to acquire signal current; The arithmetic register module includes a first register transistor, a second register transistor, and a switch control unit; by controlling the state of the switch control unit, the first register transistor and the second register transistor perform inversion, addition, subtraction, or multiplication operations on the signal current to obtain a result current, and store the result current; The switch control unit includes a first switch, a second switch, a third switch, and a fourth switch; the source of the first registered transistor is grounded, the gate and source are connected through the first switch, and the gate and drain are connected through the second switch; the drain of the first registered transistor is also connected to the drain of the second registered transistor and is connected to the transmission module; the gate and drain of the second registered transistor are connected through the third switch, and the gate and source are connected through the fourth switch; the source of the second registered transistor is connected to a power supply.

2. The current register according to claim 1, characterized in that, The first switch, the second switch, the third switch, and the fourth switch are all transistors; The gate of the first register transistor is connected to the drain of the first switch and the source of the second switch; the source of the first register transistor is connected to the source of the first switch; and the drain of the first register transistor is connected to the drain of the second switch. The gate of the second register transistor is connected to the source of the third switch and the drain of the fourth switch; the drain of the second register transistor is connected to the drain of the third switch; and the source of the second register transistor is connected to the source of the fourth switch. The gate of the first switch is connected to a first reset signal, the gate of the second switch is connected to a first write signal, the gate of the third switch is connected to a second write signal, and the gate of the fourth switch is connected to a second reset signal.

3. The current register according to claim 2, characterized in that, The first register transistor is an NMOS, the second register transistor is a PMOS, the first switch and the second switch are both NMOS, and the third switch and the fourth switch are both PMOS.

4. The current register according to claim 1, characterized in that, The transmission module includes a transmission switch; one end of the transmission switch is connected to the drain of the first register transistor and the drain of the second register transistor, and the other end is connected to the bus.

5. The current register according to claim 4, characterized in that, The transmission switch is a transistor group switch, which includes a first transmission transistor and a second transmission transistor. The drain of the first transmission transistor is connected to the source of the second transmission transistor and connected to the bus; the source of the first transmission transistor is connected to the drain of the second transmission transistor and connected to the drain of the first register transistor and the drain of the second register transistor; the gate of the first transmission transistor is connected to an enable signal and the gate of the second transmission transistor is connected to an inverse enable signal.

6. The current register according to claim 5, characterized in that, The first transmission transistor is an NMOS, and the second transmission transistor is a PMOS.

7. A current register, characterized in that, include: The transmission module is used to acquire signal current; The arithmetic register module includes a first register transistor, a second register transistor, and a switch control unit; by controlling the state of the switch control unit, the first register transistor and the second register transistor perform inversion, addition, subtraction, or multiplication operations on the signal current to obtain a result current, and store the result current; The switch control unit includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch; the fifth switch, the sixth switch, the seventh switch, and the eighth switch are all transistors; The source of the first register transistor is grounded, the gate of the first register transistor is connected to the source of the fifth switch, and the drain of the first register transistor is connected to the source of the sixth switch; the drain of the fifth switch is connected to the drain of the sixth switch; the source of the second register transistor is connected to a power supply, the gate of the second register transistor is connected to the source of the seventh switch, and the drain of the second register transistor is connected to the source of the eighth switch; the drain of the seventh switch is connected to the drain of the eighth switch; the drains of the sixth switch and the eighth switch are connected and connected to a bus; the gate of the fifth switch is connected to a first write signal, the gate of the sixth switch is connected to a first read signal, the gate of the seventh switch is connected to a second write signal, and the gate of the eighth switch is connected to a second read signal.

8. The current register according to claim 7, characterized in that, The first register transistor is an NMOS, the second register transistor is a PMOS, the fifth switch and the sixth switch are both NMOS, and the seventh switch and the eighth switch are both PMOS.

9. The current register according to claim 7, characterized in that, The transmission module is composed of the sixth switch and the eighth switch.

10. A control method for a current register, used to implement positive current read / write of the current register as described in any one of claims 1 to 9, characterized in that, The control method includes: During the writing process, the state of the transmission module is controlled so that the arithmetic register module is connected to the bus; the state of the switch control unit is controlled so that the gate and drain of the first register transistor are shorted and the second register transistor is in the off state; at this time, the positive current at the bus is input to the first register transistor through the transmission module and is converted into the gate voltage at the gate of the first register transistor. While in the holding state, the state of the transmission module is controlled so that the arithmetic register module is disconnected from the bus; the state of the switch control unit is controlled so that the gate and drain of the first register transistor are disconnected, and the second register transistor is still in the off state; at this time, the drain voltage of the first register transistor is 0 and the quiescent current is 0. During the readout process, the state of the transmission module is controlled so that the arithmetic register module is connected to the bus; the state of the switch control unit is maintained so that the gate and drain of the first register transistor are still open and the second register transistor is still in the off state; at this time, the first register transistor is in the saturation region, and the positive current written is read out.

11. A control method for a current register, used to implement negative current read / write of the current register as described in any one of claims 1 to 9, characterized in that, The control method includes: During the writing process, the state of the transmission module is controlled so that the arithmetic register module is connected to the bus; the state of the switch control unit is controlled so that the first register transistor is in the off state and the gate and drain of the second register transistor are short-circuited; at this time, the negative current at the bus is input to the second register transistor through the transmission module and is converted into the gate voltage at the gate of the second register transistor. While in the holding state, the state of the transmission module is controlled so that the arithmetic register module is disconnected from the bus; the state of the switch control unit is controlled so that the gate and drain of the second register transistor are disconnected, and the first register transistor is still in the off state; at this time, the drain voltage of the second register transistor is charged to the power supply voltage and the quiescent current is 0. During the readout process, the state of the transmission module is controlled so that the arithmetic register module is connected to the bus; the state of the switch control unit is maintained so that the gate and drain of the second register transistor are still open and the first register transistor is still in the off state; at this time, the second register transistor is in the saturation region, and the negative current written is read out.

12. A control method for a current register, used to implement the current inversion operation of the current register as described in any one of claims 1 to 9, characterized in that, The control method includes: The states of the transmission module and the switch control unit are controlled so that the current register is in a holding state; at this time, the gate-drain and gate-source of the first register transistor are disconnected, the gate-drain of the second register transistor is disconnected, and the gate-source is short-circuited, and the signal current is stored in the gate of the first register transistor in the form of voltage. The state of the switch control unit is controlled such that the gate and drain of the first register transistor remain open and the gate and source remain open, while the gate and source of the second register transistor are open and the gate and drain are short-circuited. At this time, the first register transistor operates in the saturation region, and the first register transistor transmits the signal current to the second register transistor and generates a gate voltage at the gate of the second register transistor. The state of the switch control unit is controlled such that the gate-source and gate-drain of the second register transistor remain open, and the gate-drain of the first register transistor remains open and the gate-source is short-circuited. At this time, the gate voltage of the first register transistor is discharged and it is in the off state. The first register transistor transfers the current to the second register transistor for storage, and the current is inverted.

13. A control method for a current register, used to implement the current addition operation of the current register as described in any one of claims 1 to 9, characterized in that, The control method includes: The states of the transmission module and the switch control unit are controlled such that the gate-drain of the first register transistor is disconnected and the gate-source is shorted, and the gate-source and gate-drain of the second register transistor are disconnected; at this time, the second register transistor stores the signal current that has undergone inversion operation. The state of the transmission module is controlled so that the arithmetic register module is connected to the bus; the state of the switch control unit is controlled so that the gate-drain of the first register transistor is short-circuited and the gate-source is open, while the gate-source and gate-drain of the second register transistor remain open; at this time, another signal current to be added at the bus is input to the first register transistor through the transmission module, so that the current flowing through the first register transistor is the sum of the inverted signal current stored in the second register transistor and the input other signal current to be added, and a corresponding gate voltage is generated at the gate of the first register transistor; The state of the switch control unit is controlled so that the gate-drain of the first register transistor is disconnected and the gate-source remains disconnected. Then, the states of the transmission module and the switch control unit are controlled so that the operation register module is disconnected from the bus, the gate-source of the second register transistor is shorted, and the gate-drain remains disconnected. At this time, the second register transistor is in the off state, and the first register transistor stores the result of the current addition operation in the form of voltage at its gate.

14. A control method for a current register, used to implement the current subtraction operation of the current register as described in any one of claims 1 to 9, characterized in that, The control method includes: The states of the transmission module and the switch control unit are controlled so that the arithmetic register module is connected to the bus, the gate and drain of the first register transistor are shorted and the gate and source are open, and the gate and source of the second register transistor are shorted and the gate and drain are open; at this time, the first register transistor stores the input signal current. The state of the switch control unit is controlled so that the gate-drain of the first register transistor is disconnected and the gate-source remains disconnected, while the gate-source of the second register transistor is disconnected and the gate-drain is short-circuited. At this time, the other signal current to be subtracted at the bus is input to the operation register module via the transmission module. Since the first register transistor is in the saturation region, the current flowing through the second register transistor is the difference between the signal current stored in the first register transistor and the input other signal current to be subtracted, and a corresponding gate voltage is generated at the gate of the second register transistor. The state of the switch control unit is controlled so that the gate-source and gate-drain of the second register transistor remain open; the state of the transmission module and the switch control unit is controlled so that the operation register module is disconnected from the bus, the gate-drain of the first register transistor remains open, and the gate-source is short-circuited; at this time, the first register transistor is in the off state, and the second register transistor stores the result of the current subtraction operation in the form of voltage at its gate.

15. An image sensor, characterized in that, Including the current register as described in any one of claims 1 to 9.

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