A readout circuit for an infrared detector used in hyperspectral applications

Abstract

The present invention discloses a readout circuit for a hyperspectral infrared detector, comprising a row selection circuit and a circuit for independently configuring the gain of each row. The row selection circuit includes a counter, a decoder, a serial-to-parallel conversion circuit, a row selection address storage circuit, a row selection circuit, a trigger pulse generation circuit, a first-stage logic circuit, a latch, and a second-stage logic circuit. The circuit for independently configuring the gain of each row includes a gain address storage circuit and a gain selection circuit. This circuit has the function of independently configuring the gain of each row and the function of outputting arbitrary row selection. Implementing these functions within the readout circuit avoids sending the readout data to a subsequent imaging circuit, which then completes the above two functions. Therefore, it has the advantages of reducing the frame rate of the readout circuit and the circuit complexity of the imaging circuit, while also increasing the reliability of the entire device.

Description

Technical Field

[0001] The present invention belongs to the field of hyperspectral infrared detector readout circuit design, and relates to a hyperspectral infrared detector readout circuit, and specifically to a hyperspectral infrared detector readout circuit with arbitrary row selection function and independent gain configuration function for each row, which is used to meet the needs of hyperspectral detectors. Background Art

[0002] Hyperspectral remote sensing, a technology developed based on spectroscopy, uses narrow, continuous spectral channels to continuously image ground objects. Compared to traditional remote sensing technologies, hyperspectral imaging spectrometers have more imaging channels and can obtain more spectral and spatial information to improve recognition capabilities. They are widely used in many fields, including environmental monitoring, atmospheric exploration, Earth resource surveys, natural disaster assessments, and astronomical observations.

[0003] For example, hyperspectral integrated observation satellites can be used to acquire high-spectral-resolution remote sensing data from the ultraviolet to the long-wave infrared spectrum. Hyperspectral equipment uses a large number of spectral channels to generate images. Compared to other commonly used remote sensing methods, imaging spectroscopy data features multiple wavelengths and high spectral and spatial resolution. These channels typically include dozens to hundreds of channels covering a continuous spectrum; for example, a hyperspectral detector has 256 spectral bands. Hyperspectral spectroscopy achieves high resolution within the wavelength range of interest, typically on the order of nanometers.

[0004] Hyperspectral imaging principle Figure 1 As shown in the figure, the detector is divided into n spectral dimensions along the row direction, corresponding to n rows of readout circuits. Each spectral dimension has a different wavelength and carries different ground object information. The target's properties are ultimately determined based on the information in each wavelength. In readout circuits used for hyperspectral imaging, the spectral dimension determines the number of rows in the readout circuit array.

[0005] Because the spectral information of certain rows caused by spectrometry is more important, the readout circuit must be able to select any row. Since hyperspectral detectors usually have high resolution, that is, the wavelength of each row is narrow, and because each row carries different spectral information and photocurrent, the readout circuit requires multi-level gain, and the gain of each row can be configured separately.

[0006] Traditionally, circuit data information is transmitted to the imaging circuit. The readout circuit must transmit all gain data for each row of information to the imaging circuit, which then filters and processes each row of data, increasing the design difficulty of the imaging circuit. This patent provides a method that integrates row selection and independent gain configuration for each row within the readout circuit, reducing the readout circuit's frame rate and the complexity of the imaging circuit. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to overcome the deficiencies of the above-mentioned prior art and provide a hyperspectral infrared detector readout circuit, specifically a hyperspectral infrared detector readout circuit with an arbitrary row selection function and an independent gain configuration function for each row. Through the design of a row optional circuit and an independent gain configuration circuit for each row, the problems of row skipping information output and different row gain configuration are solved, thereby meeting the needs of hyperspectral detectors.

[0008] The present invention is achieved through the following technical solutions:

[0009] A hyperspectral infrared detector readout circuit includes a row selection circuit and a circuit for independently configuring the gain of each row; the row selection circuit includes: a counter, a decoder, a serial-to-parallel conversion circuit, a row selection address storage circuit, a row selection circuit, a trigger pulse generation circuit, a first-level logic circuit, a latch, and a second-level logic circuit.

[0010] The output of the counter is connected to the input of the decoder; the input of the serial-to-parallel conversion circuit is connected to the user input, and its output is connected to the row selection address storage circuit and the gain address storage circuit; the output of the row selection address storage circuit is connected to the row selection circuit together with the row selection default input, and the output of the row selection circuit is connected to the first-level logic circuit; the output of the decoder is connected to the first-level logic circuit; the first-level logic circuit performs logical calculation on the output of the row selection circuit and the output of the decoder, and feeds the calculation result back to the enable pin ENA of the counter through the pulse generated by the trigger pulse generation circuit; the output of the first-level logic circuit is connected to the latch, and the output of the latch is connected to the second-level logic circuit; the output of the second-level logic circuit is connected to the pixel array.

[0011] The circuit for independently configuring the gain of each row includes: a gain address storage circuit and a gain selection circuit; an output of the gain address storage circuit is connected to the gain selection circuit; and another input of the gain selection circuit is a gain default input.

[0012] Furthermore, the first-level logic circuit includes a logical addition operation and a logical exclusive-or / exclusive-or operation; the first-level logic circuit is used to perform logical calculations on the user input information and the decoder result. When decoding to a certain row, the first-level logic circuit determines whether the row is selected by the user. If the row is selected, the first-level logic circuit issues an instruction to command the counter to stop counting through the trigger pulse generated by the trigger pulse generating circuit, and the counter will maintain the current count; if the row is not selected, the counter continues counting until the user-specified row is found.

[0013] Furthermore, the second-level logic circuit is a logic gate circuit, which is used to calculate the row selection result and the external timing. When the timing requirement is met, the second-level logic circuit sends the calculated result to the pixel array.

[0014] Furthermore, the input of the decoder is connected to the output of the counter for decoding the count value, and as the count increases or decreases, the decoder sequentially outputs high levels.

[0015] Furthermore, the trigger pulse generating circuit includes a switch array and a logic operation module. The trigger pulse signal generated by the trigger pulse generating circuit is fed back to the enable terminal of the counter to control the counter to hold or count.

[0016] When an external signal comes, the latch saves the calculation result of the first-level logic circuit under the control of the LINE_PULSE signal and transmits it to the second-level logic circuit.

[0017] Furthermore, the gain selection circuit is used to select the values ​​of the gain default input and the gain address storage circuit and output them to the pixel; the row selection circuit is used to select the row selection address storage circuit and the row selection default input and send them to the first-level logic circuit for calculation.

[0018] Furthermore, the row selection default input and the gain default input have the function that, when the user inputs a default value, the row selection and each row gain selection can be controlled by the default value.

[0019] Furthermore, the input pins of the counter include a clock pin CLK, a clear pin CLR, and an enable pin ENA; the counter counts once each time a falling edge or a rising edge of the clock pin CLK comes; when the enable pin ENA is valid, the counter maintains the current count.

[0020] Furthermore, the latch's synchronization signal LINE_PULSE lags behind the main clock MC, so as to prevent glitches generated at the falling edge of MC from entering the pixel array and causing false triggering.

[0021] Furthermore, the data output sampling of the hyperspectral infrared detector readout circuit is in a line readout mode, and the user inputs a line readout signal LINE_PULSE to the circuit, and each time LINE_PULSE comes, a line is output.

[0022] Furthermore, in terms of timing, after integration is complete, the row selection circuit performs initial circuit configuration. After initial configuration is complete, the first row address is located. After the row selection circuit finds the user-set first row address, it stores the address and feeds it back to the counter to stop counting and wait for instructions to send the row address to the pixel array. After receiving the address information, the pixel array turns on the corresponding row switch and sends the information for all columns in that row to the column circuit, completing column-level data sampling. The stored column data is output upon the next row selection signal.

[0023] Beneficial effects of the present invention:

[0024] The readout circuit of the present invention features independent gain configuration for each row and arbitrary row selection output. Through the design of the row selection circuit and the circuit for independently configuring the gain of each row, the issues of skipped row information output and different row gain configurations are resolved, meeting the requirements of hyperspectral detectors. The present invention avoids feeding the readout data into the subsequent imaging circuit, which then performs the two aforementioned functions. This reduces the readout circuit frame rate and the circuit complexity of the imaging circuit, thereby increasing the reliability of the entire device. The present invention has been validated for imaging using actual detector assemblies, confirming that the results of its row selection function and independent gain configuration for each row fully meet design expectations. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram of the hyperspectral application scenario of the present invention.

[0026] Figure 2 It is a block diagram of the composition of the row selection circuit and the circuit for independently configuring the gain of each row of the present invention.

[0027] Figure 3 It is a block diagram of the design principle of the data storage circuit of the present invention.

[0028] Figure 4 It is a schematic diagram of the optional circuit of the present invention.

[0029] Figure 5 It is a flowchart of the readout circuit of the present invention.

[0030] Figure 6 It is a circuit timing diagram of the present invention. DETAILED DESCRIPTION

[0031] Example

[0032] A hyperspectral infrared detector readout circuit is specifically implemented. In this example, the spectral dimensions are 256.

[0033] like Figure 2 As shown, the readout circuit includes a row selection circuit and a gain independent configuration circuit for each row; the row selection circuit includes a counter, a decoder, a serial-to-parallel conversion circuit, a row selection address storage circuit, a row selection circuit, a trigger pulse generation circuit, a first-level logic circuit, a latch and a second-level logic circuit; the gain independent configuration circuit for each row includes: a gain address storage circuit and a gain selection circuit.

[0034] Figure 2 For the circuit framework, Figure 3 and Figure 4 for Figure 2 refinement. Figure 3The Q1, Q2, Q3...Q256 generated in is the row selection information. When the Qn (n=1, 2, 3...256) value is high, it indicates that the nth row is selected and needs to be output; when it is low, it indicates that the nth row is not selected and does not need to be output. In addition, Figure 3 Q1-Q256 is connected to Figure 4 Input terminal of logic circuit 1. Figure 3 Gn<0:2> in (n is the row address, n=1, 2, 3…256. <0:2> is the gain bit number of each pixel, and there are 6 optional gains in total).

[0035] like Figure 3 As shown in the figure, it is a schematic diagram of the storage circuit design. The function of this circuit is to generate the final row selection information and gain selection information. Gn<0:2> (where n is 1, 2, 3...256) is directly connected to the inside of the pixel. Q1, Q2, Q3...Q256 are connected to the following Figure 4 The input terminal of the logic circuit 1 shown in FIG. Figure 4 circuit, connected to the pixel. Figure 3 In the example, after counting, the counter generates enable signals ENA1 and ENA2 through the waveform generator. When the enable signals are high, the serial-to-parallel converter circuit begins operation. In this embodiment, the serial-to-parallel converter has 1024 bits, of which 256 are row select address bits and 768 are gain select bits (each pixel has six gain levels, requiring 3 bits per row to control. Therefore, 256 rows require 768 bits). When the enable signal ENA1 is pulled low, the serial-to-parallel converter stops transmitting data and maintains the current value. The register unit stores the serial-to-parallel converter result upon the falling edge of CLK. The circuit allows operation even when the configuration word is not used (i.e., when there is no user serial port input). The function of the gain<0:2> pins is that if the gain selector module selects gain<0:2> for output, the user serial port input data is invalid. The circuit gain is the same for each row, and the specific gain value is determined by the gain<0:2> pins. Similarly, when the row selector circuit selects SIZE, the circuit output row is determined by SIZE, and user input is invalid. When the gain selection circuit and the row selection circuit select the register unit, the gain of the circuit and the row to be output are determined by the serial word output by the user.

[0036] like Figure 4The figure shows the schematic diagram of the row selection circuit. As can be seen, each row of pixels is controlled by a set of circuits, and the control circuits are identical for all rows. The control circuit consists of a counter, a decoder unit, a logic operation module, and a latch. The number of bits in the decoder counter is related to the total number of rows, a binary relationship. For a 256-row hyperspectral circuit, the counter has 8 bits. The decoder unit decodes the counter output and can be composed of an N-input NAND gate (or NOT gate) to sequentially address all rows. The decoder output has 256 bits, one for each row. Each time the counter increments a bit, the corresponding bit in the decoder outputs a high level. Figure 4 Logic circuit 1 is the arithmetic circuit that determines whether the current row is the one specified by the user. If the decoder output of a row is high but the Qn of that row is low, the user has not selected that row, and the counter continues counting. If the decoder output of a row is high and the corresponding Qn is also high, indicating that the row requires an output, the switch array for the corresponding row opens, ROW_ENA goes high, and the counter enable signal goes high, stopping the counter and maintaining the current count. When the falling edge of LINE_PULSE arrives, the information in logic circuit 1 is fed into the latch. Simultaneously, the LINE_PULSE pulse controls the enable pin of the counter through the logic operation module, causing the counter to restart and search for the next valid row. Logic circuit 2 determines whether the current row is the last row. If not, the selected row is enabled based on the latch result. If it is the last row, the row select switches of all pixels are closed after the last row is output, invalidating the data in the latch.

[0037] like Figure 5 and Figure 6 As shown in the figure, it is the readout circuit flow chart and timing diagram, which are described in detail as follows:

[0038] 1) Initial reset state: After the readout circuit integration is completed, the readout circuit needs to reset the register, switch array, and timing circuit to prepare for reading.

[0039] 2) Addressing the first row to be output: The timing generator sends a signal to the counter, which begins counting, one count per clock cycle. Each count increments the row address by one row. The logic circuit determines the row address. If the current row is not selected, the counter increments by one on the next clock cycle and sends it to the logic circuit for further determination. If the current row is selected, the feedback circuit generates a pulse signal, which is then sent to the counter. Upon receipt of this pulse signal, the counter stops counting. Upon receipt of the row pulse signal, the row information is fed into the flip-flop, which is then calculated by the logic circuit and sent to the pixel array.

[0040] 3) Column-level circuit sampling: After the pixel array receives the row information, it turns on the corresponding row switch. At this time, the data information on the row is connected to the column-level circuit of the readout circuit and the information is transferred to the column-level capacitor.

[0041] 4) Data output: When the line pulse LINE_PULSE arrives again, the output stage amplifier of the readout circuit drives the signal mentioned in 3) to output.

[0042] For example, the line information entered by the user is as follows Figure 6 As shown, the rows to be output are row 3, row 4, row 8, row 10, and so on. After the falling edge of INT arrives, the readout circuit performs initialization operations, resetting the registers and amplifiers within the circuit. After resetting, the initial row addressing operation is carried out. When the initial row 3 is found, the row switch of this row is opened, and the information within the pixel is stored in the column-level capacitor. Then the addressing operation of the next row is carried out, and after finding the 4th row, the instructions are awaited. When the LINE_PULSE pulse signal is sent to the external pin of the circuit, that is, when the first LINE_PULSE signal arrives, the column amplifier sends the stored information of the 3rd row to the output amplifier for driving the output. At the same time, the circuit samples the 4th row and addresses the 8th row. When the next LINE_PULSE pulse signal arrives, the circuit outputs the 4th row and samples the 8th row at the same time, and so on.

Claims

1. A hyperspectral infrared detector readout circuit, characterized in that: The readout circuit includes a row selection circuit and a gain independent configuration circuit for each row; The row selection circuit includes: a counter, a decoder, a serial-to-parallel conversion circuit, a row selection address storage circuit, a row selection circuit, a trigger pulse generating circuit, a first-level logic circuit, a latch, and a second-level logic circuit; the output of the counter is connected to the input of the decoder; the input of the serial-to-parallel conversion circuit is connected to the user input, and its output is connected to the row selection address storage circuit and the gain address storage circuit; the row selection address storage circuit and the row selection default input are connected to the row selection circuit, and the output of the row selection circuit is connected to the first-level logic circuit; the output of the decoder is connected to the first-level logic circuit; the first-level logic circuit performs a logical calculation on the output of the row selection circuit and the output of the decoder, and feeds the calculation result back to the enable pin ENA of the counter through the pulse generated by the trigger pulse generating circuit; the output of the first-level logic circuit is connected to the latch, and the output of the latch is connected to the second-level logic circuit; the output of the second-level logic circuit is connected to the pixel array; The circuit for independently configuring the gain of each row includes: a gain address storage circuit and a gain selection circuit; an output of the gain address storage circuit is connected to the gain selection circuit; another input of the gain selection circuit is a gain default input; The first-level logic circuit includes a logical addition operation and a logical exclusive-or / exclusive-or operation. The first-level logic circuit is used to perform logical calculations on user input information and decoder results. When decoding a row, the first-level logic circuit determines whether the row is selected by the user. If the row is selected, the first-level logic circuit issues an instruction to stop counting via a trigger pulse generated by a trigger pulse generating circuit. The counter will maintain the current count and wait for instructions. If the row is not selected, the counter will continue counting until it finds the row specified by the user. The gain selection circuit is used to select the value of the gain default input and the gain address storage circuit and output them to the pixel; the row selection circuit is used to select the row selection address storage circuit and the row selection default input and send them to the first-level logic circuit for calculation; The row selection default input and gain default input are used to control the row selection and gain selection of each row by default values ​​when the user enters the default value.

2. The hyperspectral infrared detector readout circuit according to claim 1, characterized in that: The second-level logic circuit is a logic gate circuit, which is used to calculate the row selection result and the external timing. When the timing requirements are met, the second-level logic circuit sends the calculated result to the pixel array.

3. The hyperspectral infrared detector readout circuit according to claim 1, characterized in that: The input of the decoder is connected to the output of the counter and is used to decode the count value. As the count increases or decreases, the decoder sequentially outputs high levels.

4. The hyperspectral infrared detector readout circuit according to claim 1, characterized in that: The trigger pulse generating circuit includes a switch array and a logic operation module. The trigger pulse signal generated by the trigger pulse generating circuit is fed back to the enable terminal of the counter to control the counter to hold or count. When an external signal comes, the latch saves the calculation result of the first-level logic circuit under the control of the LINE_PULSE signal and transmits it to the second-level logic circuit.

5. The hyperspectral infrared detector readout circuit according to any one of claims 1 to 4, characterized in that: The input pins of the counter include a clock pin CLK, a clear pin CLR, and an enable pin ENA. The counter counts once every time a falling edge or a rising edge of the clock pin CLK comes. When the enable pin ENA is valid, the counter maintains the current count.

6. The hyperspectral infrared detector readout circuit according to any one of claims 1 to 4, characterized in that: The synchronous signal LINE_PULSE of the latch lags behind the main clock MC, so as to prevent the burrs generated at the falling edge of MC from entering the pixel array and causing false triggering.

7. The hyperspectral infrared detector readout circuit according to any one of claims 1 to 4, characterized in that: The data output sampling of the hyperspectral infrared detector readout circuit is in line readout mode. The user inputs a line readout signal LINE_PULSE to the circuit, and a line is output each time LINE_PULSE comes.

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