Read transistor structure, manufacturing method thereof, and memory

Abstract

The present invention relates to a read transistor structure, a preparation method thereof, and a memory. The read transistor structure includes: a substrate, a dielectric layer, a first transistor, a second transistor, and an isolation layer. The dielectric layer is located on the substrate. The first transistor is embedded in the dielectric layer. The second transistor is embedded in the dielectric layer, arranged opposite to the first transistor in the thickness direction of the dielectric layer, and the source of the second transistor is electrically connected to the source of the first transistor, and the drain of the second transistor is electrically connected to the drain of the first transistor. The isolation layer is located between the first transistor and the second transistor. The above-mentioned read transistor structure, the preparation method thereof, and the memory, by using the first transistor and the second transistor of the read transistor structure, one of which is used to form a storage node and is electrically connected to the write transistor structure, and the other is used to be connected to the read word line, can effectively reduce the mutual interference between the writing and reading of the memory, thereby improving the device performance.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a read transistor structure, a preparation method thereof, and a memory. Background Art

[0002] As memory size continues to shrink, the storage capacitance limitation of 1T1C memory becomes increasingly significant, leading to a scaling bottleneck for the 1T1C structure. Currently, 2T0C memory is becoming increasingly popular.

[0003] The 2T0C structure is a structure in which two connected transistors act as a memory cell. However, the performance of existing 2T0C structure memories still needs to be improved. Summary of the Invention

[0004] Based on this, it is necessary to provide a read transistor structure and a preparation method thereof to address the problem in the prior art that the number of memory cells connected to a read word line is limited.

[0005] In order to achieve the above object, the present invention provides a read transistor structure,

[0006] substrate;

[0007] a dielectric layer located on the substrate,

[0008] a first transistor embedded in the dielectric layer;

[0009] a second transistor embedded in the dielectric layer and arranged opposite to the first transistor in a thickness direction of the dielectric layer, with a source of the second transistor electrically connected to the source of the first transistor and a drain of the second transistor electrically connected to the drain of the first transistor;

[0010] An isolation layer is located between the first transistor and the second transistor.

[0011] In one embodiment, the read transistor structure includes:

[0012] A trench penetrates the dielectric layer in the thickness direction of the dielectric layer, and in the thickness direction of the dielectric layer, the trench includes a lower trench portion, a middle trench portion, and a middle trench portion arranged sequentially, the first transistor is embedded in the lower trench portion, the isolation layer is located in the middle trench portion, and the second transistor is embedded in the upper trench portion.

[0013] In one embodiment, the read transistor structure includes:

[0014] a common source electrode, penetrating the dielectric layer on one side of the trench and spaced apart from the trench, the common source electrode being connected to the first transistor and the second transistor;

[0015] A common drain penetrates the dielectric layer on the other side of the trench and is spaced apart from the trench. The common source is connected to the first transistor and the second transistor.

[0016] In one embodiment, the first transistor comprises:

[0017] a first gate located in the trench;

[0018] a first gate dielectric layer, located in the trench and on the sidewalls and top of the first gate;

[0019] a first active layer located in the trench, on the sidewalls and top of the first gate dielectric layer, and in a region between the sidewalls of the first gate and the sidewalls of the trench;

[0020] The first source and the first drain are respectively located between the dielectric layer and the substrate on both sides of the trench and connected to both ends of the first active layer. The first source is connected to the common source, and the first drain is connected to the common drain.

[0021] In one embodiment, the material of the first gate is the same as the material of the first source and / or the material of the first drain.

[0022] In one embodiment, the second transistor includes:

[0023] a second active layer, located on the upper surface of the dielectric layer, the sidewalls of the trench, and the upper surface of the isolation layer, with two ends thereof connected to the common source and the common drain respectively;

[0024] a second gate dielectric layer, located on the sidewalls of the second active layer and the upper surface of the second active layer in the trench;

[0025] The second gate is located on the surface of the second gate dielectric layer.

[0026] In one embodiment, the second gate fills the trench.

[0027] In one embodiment, the isolation layer includes a first nitride layer;

[0028] Alternatively, the isolation layer includes a first oxide layer, a second nitride layer, and a second oxide layer that are stacked;

[0029] Alternatively, the isolation layer includes a third nitride layer, a third oxide layer, and a fourth nitride layer that are stacked.

[0030] The present invention also provides a method for preparing a read transistor structure, comprising the following steps:

[0031] providing a substrate;

[0032] forming a dielectric layer on the substrate;

[0033] forming a first transistor embedded in the dielectric layer on the dielectric layer;

[0034] forming an isolation layer on the first transistor;

[0035] A second transistor embedded in the dielectric layer is formed on the isolation layer. The second transistor is arranged opposite to the first transistor, and the source of the second transistor is electrically connected to the source of the first transistor, and the drain of the second transistor is electrically connected to the drain of the first transistor.

[0036] In one embodiment, forming a dielectric layer on the substrate includes:

[0037] forming a dielectric material layer on the substrate;

[0038] Etching the dielectric material layer to form a groove penetrating the dielectric material layer, and the remaining dielectric material layer forms the dielectric layer, wherein the groove includes a groove lower portion, a groove middle portion, and a groove upper portion sequentially arranged in a thickness direction of the dielectric layer;

[0039] The step of forming a first transistor embedded in the dielectric layer on the dielectric layer includes:

[0040] forming the first transistor at a lower portion of the trench;

[0041] forming an isolation layer on the first transistor, comprising:

[0042] forming the isolation layer in the middle of the trench;

[0043] forming a second transistor embedded in the dielectric layer on the isolation layer;

[0044] The second transistor is formed on the upper portion of the trench.

[0045] In one embodiment, before forming the dielectric material layer on the substrate, the method includes:

[0046] forming a sacrificial material layer on the substrate;

[0047] Etching the dielectric material layer to form a groove penetrating the dielectric material layer includes:

[0048] Etching the dielectric material layer and the sacrificial material layer to form a groove penetrating the dielectric material layer and the sacrificial material layer, and the remaining sacrificial material layer forms a sacrificial layer;

[0049] The forming of the first transistor at the lower portion of the trench comprises:

[0050] removing the sacrificial layer;

[0051] forming a first source electrode and a first drain electrode between the dielectric layer and the substrate on both sides of the trench, respectively, and forming a first gate electrode at the bottom of the trench;

[0052] forming a first gate dielectric layer on the sidewalls and top of the first gate;

[0053] A first active layer is formed on the sidewalls and top of the first gate dielectric layer, and the first active layer fills the area between the sidewalls of the first gate and the sidewalls of the trench.

[0054] In one embodiment, a first source and a first drain are respectively formed between the dielectric layer and the substrate on both sides of the trench, and a first gate is formed at the bottom of the trench, comprising:

[0055] forming a conductive material layer on the surface of the substrate and the surface of the dielectric layer;

[0056] The conductive material layer is patterned to form the first gate, the first source, and the first drain.

[0057] In one embodiment, forming the second transistor on the upper portion of the trench includes:

[0058] forming a second active layer on the upper surface of the isolation layer, the sidewalls of the trench, and the upper surface of the dielectric layer;

[0059] forming a second gate dielectric layer on the sidewalls of the second active layer and on the upper surface of the second active layer in the trench;

[0060] A second gate is formed on the surface of the second gate dielectric layer.

[0061] In one embodiment, after forming the second transistor on the upper portion of the trench, the method includes:

[0062] Sequentially etching the second active layer and the dielectric layer on both sides of the trench to form a first interconnection hole and a second interconnection hole penetrating to the first source electrode and the first drain electrode respectively;

[0063] Conductive material is filled in the first interconnection hole and the second interconnection hole to form a common source and a common drain respectively.

[0064] In one embodiment,

[0065] The present invention also provides a memory, comprising: a write transistor structure and a read transistor structure; the read transistor structure comprises a first transistor and a second transistor, the source of the second transistor is electrically connected to the source of the first transistor, and the drain of the second transistor is electrically connected to the drain of the first transistor; the first electrode of the write transistor structure is connected to the gate of the first transistor or the gate of the second transistor, and the first electrode is the source or the drain.

[0066] The above-mentioned read transistor structure, preparation method thereof, and memory can effectively reduce the mutual interference between memory writing and reading by using the first transistor and the second transistor of the read transistor structure, one of which is used to form a storage node and is electrically connected to the write transistor structure, and the other is used to connect to the read word line, thereby improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0068] Figure 1 is a schematic diagram of a read transistor structure provided in one embodiment;

[0069] Figure 2 is a schematic diagram of a storage unit provided in one embodiment;

[0070] Figure 3 A schematic diagram of a storage array provided in one embodiment;

[0071] Figure 4 A schematic diagram of a storage unit in the related art provided in one embodiment;

[0072] Figure 5 A schematic diagram of a storage array in a related art provided in one embodiment;

[0073] Figure 6 is a flow chart of a method for preparing a read transistor structure provided in one embodiment;

[0074] Figure 7 is a schematic diagram of a substrate provided in one embodiment;

[0075] Figure 8 A schematic diagram of a groove provided in one embodiment;

[0076] Figure 9 A schematic diagram of a first gate, a first source, and a first drain provided in one embodiment;

[0077] Figure 10 is a schematic diagram of a first transistor provided in an embodiment;

[0078] Figure 11 is a schematic diagram of an isolation layer provided in one embodiment;

[0079] Figure 12 is a schematic diagram of a second transistor provided in one embodiment;

[0080] Figure 13 A schematic diagram of a first interconnection hole and a second interconnection hole provided in one embodiment;

[0081] Figure 14 A schematic diagram of a common source and a common drain provided in one embodiment;

[0082] Figure 15 Schematic diagram of a source conductive contact structure and a drain conductive contact structure provided in one embodiment;

[0083] Figure 16 Schematic diagram of the upper portion, middle portion and lower portion of the groove provided in one embodiment;

[0084] Figure 17 is a schematic diagram of a first active layer provided in one embodiment;

[0085] Figure 18 Schematic diagram of a second active layer provided in one embodiment.

[0086] Explanation of reference numerals: 10 - read transistor structure; 20 - write transistor structure; 21 - first electrode; 22 - second electrode; 30 - single-gate read transistor; 100 - substrate; 110 - trench; 111 - lower portion of the trench; 112 - middle portion of the trench; 113 - upper portion of the trench; 120 - first transistor; 121 - first gate; 122 - first drain; 123 - first source; 124 - first gate dielectric layer; 125 - first active layer; 130 - isolation layer; 140 -Second transistor; 141-second gate; 142-second drain; 143-second source; 144-second active layer; 145-second gate dielectric layer; 150-first interconnection hole; 151-second interconnection hole; 160-common source; 161-common drain; 170-source conductive contact structure; 171-drain conductive contact structure; 200-dielectric layer; 201-dielectric material layer; 300-photoresist layer; 400-sacrificial layer; 401-sacrificial material layer. DETAILED DESCRIPTION

[0087] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0088] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0089] It should be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, and layers, these elements, components, regions, and layers should not be limited by these terms. These terms are merely used to distinguish one element, component, region, or layer from another element, component, region, or layer. Thus, a first element, component, region, or layer discussed below may be referred to as a second element, component, region, or layer without departing from the teachings of the present invention.

[0090] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0091] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0092] While embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature and their shapes are not intended to represent the actual shapes of regions of a device and are not intended to limit the scope of the invention.

[0093] In one embodiment, see Figure 1 and Figure 2 , providing a memory. The memory includes a read transistor structure 10 and a write transistor structure 20. In addition, the memory may further include a bit line BL, a write word line WWL, and a read word line RWL.

[0094] The read transistor structure 10 includes a first transistor 120 and a second transistor 140. The source of the second transistor 140 is electrically connected to the source of the first transistor 120 to form the source of the read transistor structure 10. The drain of the second transistor 140 is electrically connected to the drain of the first transistor 120 to form the drain of the read transistor structure 10.

[0095] One of the source and drain of the read transistor structure 10 is connected to the bit line BL, and the other is connected to the ground terminal GND. At the same time, the gate of one of the first transistor 120 and the second transistor 140 is connected to the first electrode 21 of the write transistor structure 20, thereby forming a storage node SN. The first electrode 21 is the source or drain of the transistor structure 20. The gate of the other of the first transistor 120 and the second transistor 140 is connected to the read word line RWL. As an example, see Figure 2 The gate of the first transistor 120 is connected to the first electrode 21 of the write transistor structure 20, thereby forming a storage node SN of the memory cell, and the gate of the second transistor 140 is connected to the read word line RWL.

[0096] The gate of the write transistor structure 20 is connected to the write word line WWL. Meanwhile, the first electrode 21 of the write transistor structure 20 is connected to the gate of the first transistor 120, and the second electrode 22 of the write transistor structure 20 is connected to the bit line BL. One of the first electrode 21 and the second electrode 22 is the source of the write transistor structure 20, and the other is the drain of the write transistor structure 20.

[0097] See also Figure 3 The memory includes a plurality of memory cells arranged in an array. Each memory cell includes a read transistor structure 10 and a write transistor structure 20, thereby forming a 2TOC cell architecture.

[0098] For related technologies, see Figure 4 In a 2TOC cell architecture, the read transistor structure is often a single-gate read transistor 30. A read word line RWL and a read bit line RBL are connected to the source and drain of the single-gate read transistor 30, respectively. A first electrode 21 of a write transistor structure 20 is connected to the gate of the single-gate read transistor 30, thereby forming a storage node SN. Furthermore, a second electrode 22 of the write transistor structure 20 is connected to a write bit line WBL. The gate of the write transistor structure 20 is connected to a write word line WWL.

[0099] When writing to a memory cell, a corresponding voltage is applied to the write word line WWL to turn on the write transistor structure 20. A corresponding voltage is applied to the write bit line WBL to charge the storage node SN to a high voltage or a low voltage, thereby writing data "1" or "0" to the storage node SN.

[0100] When reading a memory cell, a voltage is applied to read word line RWL to create a voltage differential between it and read bit line RBL. When storage node SN is at a high voltage, single-gate read transistor 30 turns on. At this point, current flows through read bit line RWL, thus reading "1" data. Conversely, when storage node SN is at a low voltage, single-gate read transistor 30 turns off, and no current flows through read bit line RWL, thus reading "0" data.

[0101] However, see Figure 5When using a 2T0C cell architecture with a single-gate read transistor 30, the read word line RWL in the single-gate read transistor 30 is connected to the source of the single-gate read transistor 30, and current flows through it during a read operation. At this time, if each read word line RWL is connected to a large number of memory cells, the read word line RWL will experience a current accumulation effect and a voltage drop effect, thereby affecting memory performance. Therefore, when using a 2T0C cell architecture with a single-gate read transistor 30, the number of memory cells connected to each read word line RWL is limited. Furthermore, the read bit line RBL and the write bit line WBL are independently configured and connected to different signal amplifiers, which occupies a large chip area and affects storage density.

[0102] In this embodiment, see Figure 1 and Figure 2 The read transistor structure 10 includes a first transistor 120 and a second transistor 140. The gate of one of the first transistor 120 and the second transistor 140 is used to form a storage node SN, and the gate of the other is connected to a read word line RWL for controlling a read operation.

[0103] The following describes the reading and writing process of the memory cell by taking the example that the gate of the first transistor 120 is used to form the storage node SN and the gate of the second transistor 140 is connected to RWL.

[0104] When writing to a memory cell, a corresponding voltage is applied to the write word line WWL to turn on the write transistor structure 20. A corresponding voltage is applied to the bit line BL to charge the storage node SN to a high voltage or a low voltage, thereby writing data "1" or "0" to the storage node SN.

[0105] When the voltage written to the storage node SN is different, the first transistor 120 connected thereto will be in different conduction states.

[0106] When reading a memory cell, a corresponding voltage is applied to the read word line RWL to turn on the second transistor 140. At this time, because different voltages written to the storage node SN cause the first transistor 120 to be in different conduction states, different currents can be read on the bit line BL when different data is written to the storage node SN, thereby allowing the data "1" or "0" written to the storage node SN to be read.

[0107] In this embodiment, the read operation is controlled by connecting the gate of a transistor (the first transistor 120 or the second transistor 140) in the read transistor structure 10 via the read word line RWL, thereby making the read operation more efficient and flexible. At the same time, when the read word line RWL is connected to the gate of one of the transistors, the magnitude of the current flowing through the read word line RWL is very small, and it can be considered that no current flows through the read word line RWL. Therefore, at this time, the current accumulation effect and voltage reduction effect on the read word line RWL can be effectively avoided or reduced, thereby effectively increasing the number of memory cells connected to the read word line RWL, and thus effectively improving the storage density.

[0108] Furthermore, in this embodiment, the read transistor structure 10 and a write transistor structure 20 are connected to the same bit line BL, which can reduce the number of bit lines BL. In this case, the number of signal amplifiers connected to the bit lines BL is also reduced, and the memory chip area occupied by them is reduced, thereby effectively improving the storage density.

[0109] In addition, the read transistor structure 10 of this embodiment includes a first transistor 120 and a second transistor 140 that are independently arranged, one of which is used to form a storage node SN, and the other is used to connect to the read word line RWL, thereby effectively reducing the mutual interference between writing and reading, thereby improving device performance.

[0110] In one embodiment, see Figure 6 , a method for preparing a read transistor structure 10 is provided, comprising the following steps:

[0111] Step S100: providing a substrate 100.

[0112] Step S300 : forming a dielectric layer 200 on the substrate 100 .

[0113] Step S400 : forming a first transistor 120 embedded in the dielectric layer 200 on the dielectric layer 200 .

[0114] Step S500 : forming an isolation layer 130 on the first transistor 120 .

[0115] Step S600: forming a second transistor 140 embedded in the dielectric layer 200 on the isolation layer 130 , wherein the second transistor 140 is arranged opposite to the first transistor 120 , and the source of the second transistor 140 is electrically connected to the source of the first transistor 120 , and the drain of the second transistor 140 is electrically connected to the drain of the first transistor 120 .

[0116] In step S100, the base 100 may include a substrate. Of course, other structures such as bit lines may also be provided on the substrate.

[0117] In step S300, refer to Figure 8 The dielectric layer 200 may include one layer or multiple layers. For example, the dielectric layer 200 may include a silicon dioxide layer, a silicon oxide layer, a silicon oxynitride layer, or the like.

[0118] In step S400, refer to Figure 10 The dielectric layer 200 may include opposing lower and upper surfaces. The surface of the dielectric layer 200 facing the substrate 100 may be the lower surface, and the surface facing away from the substrate 100 may be the upper surface. The first transistor 120 may be partially embedded in the dielectric layer 200 and partially located below the lower surface. Of course, the first transistor 120 may also be entirely embedded in the dielectric layer 200.

[0119] In step S500, refer to Figure 11 , an isolation layer 130 may be formed above the first transistor 120. The isolation layer 130 is used to isolate the first transistor 120 from a second transistor 140 formed in a subsequent step.

[0120] The isolation layer 130 may have a single-layer structure or a multi-layer structure. For example, when the isolation layer 130 has a single-layer structure, the isolation layer 130 may include a first nitride layer. When the isolation layer 130 has a multi-layer structure, the isolation layer 130 may include a first oxide layer, a second nitride layer, and a second oxide layer stacked together, thereby forming an ONO (Oxide-Nitride-Oxide) structure. Alternatively, the isolation layer 130 may include a third nitride layer, a third oxide layer, and a fourth nitride layer stacked together, thereby forming a NON (Nitride Oxide Nitride) structure.

[0121] In step S600, refer to Figure 12 The second transistor 140 is disposed opposite to the first transistor 120. It is understood that the second transistor 140 may be partially embedded in the dielectric layer 200 and partially located on the upper surface of the dielectric layer 200. Of course, the second transistor 140 may also be fully embedded in the dielectric layer 200.

[0122] See also Figure 15 The source of the first transistor 120 is electrically connected to the source of the second transistor 140 , forming the source of the read transistor structure 10 . The drain of the first transistor 120 is electrically connected to the drain of the second transistor 140 , forming the drain of the read transistor structure 10 .

[0123] In this embodiment, the read transistor structure 10 includes a first transistor 120 and a second transistor 140 disposed opposite each other on the surface of a dielectric layer 200, with an isolation layer 130 positioned between the first transistor 120 and the second transistor 140. This effectively reduces coupling between the first transistor 120 and the second transistor 140, and reduces the degree of mutual influence between the first transistor 120 and the second transistor 140, thereby improving the performance of the read transistor structure 10. Furthermore, the first transistor 120 and the second transistor 140 are disposed opposite each other, facilitating the electrical connection of the source of the first transistor 120 to the source of the second transistor 140, and the electrical connection of the drain of the first transistor 120 to the drain of the second transistor 140.

[0124] In one embodiment, step S300 includes:

[0125] Step S310 : forming a dielectric material layer 201 on the substrate 100 .

[0126] Step S320: Etching the dielectric material layer 201 to form a trench 110 penetrating the dielectric material layer 201. The remaining dielectric material layer 201 forms the dielectric layer 200. In the thickness direction of the dielectric layer 200, the trench 110 includes an upper trench portion 113, a middle trench portion 112, and a lower trench portion 111.

[0127] Step S400 includes:

[0128] Step S410 : forming a first transistor 120 in the trench lower portion 111 .

[0129] Step S500 includes:

[0130] Step S510 : forming an isolation layer 130 in the middle portion 112 of the trench.

[0131] Step S600 includes:

[0132] Step S610 : forming a second transistor 140 in the trench lower portion 111 .

[0133] In step S310, refer to Figure 7 The dielectric material layer 201 may be formed by a deposition process, which may include but is not limited to one or more of chemical vapor deposition, atomic layer deposition, high-density plasma deposition, plasma-enhanced deposition, and spin-on insulating dielectric layer processes.

[0134] In step S320, refer to Figure 7 A photoresist layer 300 may be formed on the dielectric material layer 201. The photoresist layer 300 has an opening, which exposes the dielectric material layer 201 and defines the position of the trench 110 to be formed subsequently.

[0135] See also Figure 8 Based on the photoresist layer 300, the dielectric material layer 201 is etched to form a trench 110 penetrating the dielectric material layer 201. The remaining dielectric material layer 201 forms the dielectric layer 200. When etching the dielectric material layer 201, dry etching or wet etching can be used. For example, the dry etching method can include any one of reactive ion etching, inductively coupled plasma etching, or high concentration plasma etching.

[0136] See also Figure 16 In the thickness direction of the dielectric layer 200, the trench 110 includes an upper trench portion 113, a middle trench portion 112, and a lower trench portion 111, which are sequentially arranged. In this embodiment, the upper trench portion 113, the middle trench portion 112, and the lower trench portion 111 are merely exemplary and are not specifically limited to the upper trench portion 113, the middle trench portion 112, and the lower trench portion 111.

[0137] In step S410, refer to Figure 9 and Figure 10 , the first transistor 120 is formed in the lower portion 111 of the trench.

[0138] In step S510, refer to Figure 11 , the isolation layer 130 is formed in the middle portion 112 of the trench.

[0139] In step S610, refer to Figure 12 , the second transistor 140 is formed in the upper portion 113 of the trench 110 .

[0140] At this time, the first transistor 120 , the isolation layer 130 , and the second transistor 140 are all formed in the trench 110 , so that the first transistor 120 and the second transistor 140 are arranged relative to each other, and the first transistor 120 and the second transistor 140 can be effectively isolated by the isolation layer 130 .

[0141] In one embodiment, before step S300, the following steps are included:

[0142] Step S200 : forming a sacrificial material layer 401 on the substrate 100 .

[0143] Step S320 includes:

[0144] Step S321 : etching the dielectric material layer 201 and the sacrificial material layer 401 to form a trench 110 penetrating the dielectric material layer 201 and the sacrificial material layer 401 , and the remaining sacrificial material layer 401 forms a sacrificial layer 400 .

[0145] Step S410 includes:

[0146] Step S411 : removing the sacrificial layer 400 .

[0147] Step S412 : forming a first source 123 and a first drain 122 between the dielectric layer 200 and the substrate 100 on both sides of the trench 110 , respectively, and forming a first gate 121 at the bottom of the trench 110 .

[0148] Step S413 : forming a first gate dielectric layer 124 on the sidewalls and top of the first gate 121 .

[0149] Step S414 : forming a first active layer 125 on the sidewalls and top of the first gate dielectric layer 124 , wherein the first active layer 125 fills the area between the sidewalls of the first gate 121 and the sidewalls of the trench.

[0150] In step S200, refer to Figure 7 The sacrificial material layer 401 can be formed by chemical vapor deposition or physical vapor deposition, etc. The sacrificial material layer 401 can be a single-layer structure or a multi-layer structure.

[0151] In step S321, refer to Figure 7 , the photoresist layer 300 can be formed on the upper surface of the dielectric material layer 201. Figure 7 and Figure 8 Based on the photoresist layer 300 , the dielectric layer 200 and the sacrificial material layer 401 are etched to form a trench 110 penetrating the dielectric material layer 201 and the sacrificial material layer 401 . After etching, the remaining dielectric material layer 201 forms the dielectric layer 200 , and the remaining sacrificial material layer 401 forms the sacrificial layer 400 .

[0152] In step S411 , the sacrificial layer 400 may be removed by wet etching or the like.

[0153] In step S412, refer to Figure 9 After the sacrificial layer 400 is removed, a gap is formed between the lower surface of the dielectric layer 200 and the upper surface of the substrate 100. At this point, a first source electrode 123 and a first drain electrode 122 can be formed between the dielectric layer 200 and the substrate 100 on both sides of the trench 110, respectively. Simultaneously, a first gate electrode 121 can be formed at the bottom of the trench 110.

[0154] The first gate 121 may be formed simultaneously with the first source 123 and the first drain 122 , or may be formed in steps.

[0155] The material of the first gate 121 may include, but is not limited to, any one or more of titanium nitride, titanium, tungsten silicide, and tungsten.

[0156] In step S413, refer to Figure 10, forming a first gate dielectric layer 124 on the sidewalls and top of the first gate 121. As an example, a first gate dielectric material layer can be first deposited on the upper surface and sidewalls of the first gate 121, the bottom and sidewalls of the trench 110, and the entire upper surface of the dielectric layer 200. Then, the first gate dielectric material layer located on the upper surface of the dielectric layer 200 and a portion of the first gate dielectric material layer on the bottom and sidewalls of the trench 110 are removed by etching or other methods, leaving the first gate dielectric material layer covering the upper surface and sidewalls of the first gate 121 to form the first gate dielectric layer 124.

[0157] The material of the first gate dielectric layer 124 may include a material with a high-k dielectric constant, such as aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, or strontium titanium oxide.

[0158] In step S414, refer to Figure 10 A first active material layer can be deposited entirely on the surface of the first gate dielectric layer 124, the sidewalls of the trench 110, and the upper surface of the dielectric layer 200. The first active material layer on the upper surface of the dielectric layer 200 and a portion of the first active material layer on the sidewalls of the trench 110 are then removed by etching, leaving the first active material layer located on the upper surface of the first gate dielectric layer 124 and between the sidewalls of the first gate dielectric layer 124 and the sidewalls of the trench 110, thereby forming a first active layer 125. The first active layer 125 surrounds the first gate dielectric layer 124. Furthermore, the first active layer 125 can fill the area between the sidewalls of the first gate electrode 121 and the sidewalls of the trench, facilitating connection of the first active layer 125 to the first source electrode 123 and the first drain electrode 122. As an example, the material of the first active layer 125 can include indium gallium zinc oxide (IGZO).

[0159] In this embodiment, by forming a sacrificial layer 400, it is convenient to form a first source 123 and a first drain 122 at the bottom of both sides of the trench, thereby facilitating connection with the source and drain of the subsequently formed second transistor 140 to form the source and drain of the read transistor structure 10.

[0160] At the same time, the first active layer 125 is located on the sidewalls and top of the first gate dielectric layer 124. Figure 17 The channel length of the first transistor 120 is the sum of the lengths of region 1, region 2, and region 3. Compared to a planar transistor, within the same area, the first transistor 120 has a longer channel length, which can improve its gate control capability. Moreover, by adjusting the depth of the trench 110 and the height of the first gate 121, different channel lengths can be obtained, facilitating the miniaturization of the transistor planar size.

[0161] Of course, in other embodiments, the first transistor 120 may also be a planar transistor.

[0162] In one embodiment, step S412 includes:

[0163] Step S4121 : forming a conductive material layer on the surface of the substrate 100 and the surface of the dielectric layer 200 .

[0164] Step S4122 : performing patterning on the conductive material layer to form a first gate 121 , a first source 123 , and a first drain 122 .

[0165] In step S4121, a conductive material layer can be deposited on the entire upper surface of dielectric layer 200, the sidewalls of dielectric layer 200, the lower surface of dielectric layer 200, and the bottom of trench 110. Due to the removal of sacrificial layer 400 in the previous step, a gap exists between the lower surface of dielectric layer 200 and the upper surface of substrate 100. Therefore, the conductive material layer can now fill the gap between the lower surface of dielectric layer 200 and the upper surface of substrate 100.

[0166] In step S4122, refer to Figure 9 , a portion of the conductive material layer can be removed by etching or other methods, leaving the conductive material layer between the lower surface of the dielectric layer 200 and the upper surface of the substrate 100 to form the first source 123 and the first drain 122, and a portion of the conductive material layer at the bottom of the trench to form the first gate 121. In this case, the first gate 121, the first source 123, and the first drain 122 are made of the same material, which can be a conductive material.

[0167] After step S4122, a first gate dielectric layer 124 and a first active layer 125 may be formed to form the first transistor 120. Thereafter, an isolation layer 130 is formed in the trench.

[0168] In this embodiment, a conductive material layer is formed on the surface of the substrate 100 and the surface of the dielectric layer 200, and then the conductive material layer is patterned to simultaneously form the first gate 121, the first source 123, and the first drain 122. In this case, the process steps for forming the first gate 121, the first source 123, and the first drain 122 can be simplified.

[0169] In one embodiment, step S610 includes:

[0170] Step S611 : forming a second active layer 144 on the upper surface of the isolation layer 130 , the sidewalls of the trench, and the upper surface of the dielectric layer 200 .

[0171] Step S612 : forming a second gate dielectric layer 145 on the sidewalls of the second active layer 144 and the upper surface of the second active layer 144 in the trench 110 .

[0172] Step S613 : forming a second gate 141 on the surface of the second gate dielectric layer 145 .

[0173] In step S611, refer to Figure 13 The second active layer 144 may be formed on the upper surface of the isolation layer 130, the sidewalls of the trench, and the upper surface of the dielectric layer 200 by deposition or other methods. As an example, the material of the second active layer 144 may include IGZO.

[0174] The portion of the second active layer 144 located on the upper surface of the dielectric layer 200 may be formed into a second source electrode 143 and a second drain electrode 142 through steps such as doping.

[0175] In step S612, a second gate dielectric layer 145 is formed on the sidewalls and upper surface of the second active layer 144. Similar to the first gate dielectric layer 124, the material of the second gate dielectric layer 145 may also include a material having a high-k dielectric constant, such as aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, or strontium titanium oxide. The material of the second gate dielectric layer 145 may be the same as or different from that of the first gate dielectric layer 124.

[0176] In step S613, the second gate 141 is located on the surface of the second gate dielectric layer 145. At this point, the second gate 141, the second gate dielectric layer 145, and the second active layer 144 can completely fill the trench 110. The material of the second gate 141 can include, but is not limited to, any one or more of titanium nitride, titanium, tungsten silicide, and tungsten. The material of the second gate 141 can be the same as that of the first gate 121.

[0177] As an example, when forming the second gate dielectric layer 145, the second gate dielectric material layer can be first deposited on the entire surface of the second active layer 144, and then the second gate material layer can be deposited on the surface of the second gate dielectric material layer. Then, a planarization treatment is performed to remove the second gate dielectric material layer and the second gate material layer located on the upper surface of the dielectric layer 200. The remaining second gate dielectric material layer forms the second gate dielectric layer 145, and the remaining second gate material layer forms the second gate 141.

[0178] In this embodiment, similar to the first active layer 125, see Figure 18 The channel length of the second transistor 140 is the sum of the lengths of region 4, region 5, and region 6. Compared to a planar transistor, within the same area, the second transistor 140 has a longer channel length, which can improve its gate control capability. Moreover, by adjusting the depth of the upper portion 113 of the trench, different channel lengths can be obtained, facilitating the miniaturization of the transistor planar size.

[0179] Of course, in other embodiments, the second transistor 140 may also be a planar type.

[0180] Furthermore, the second source 143 and the second drain 142 formed by doping the second active layer 144 on the upper surface of the dielectric layer 200 can also be easily connected to the first transistor 120 .

[0181] In one embodiment, after step S610, the following steps are included:

[0182] Step S700 : etching the second active layer 144 and the dielectric layer 200 on both sides of the trench 110 to form a first interconnection hole 150 and a second interconnection hole 151 penetrating the first source 123 and the first drain 122 , respectively.

[0183] Step S710 : Filling the first interconnection hole 150 and the second interconnection hole 151 with a conductive material to form a common source 160 and a common drain 161 , respectively.

[0184] In step S700, refer to Figure 12 and Figure 13 The second source electrode 143 , the dielectric layer 200 and the first source electrode 123 may be sequentially etched from the upper surface of the second source electrode 143 to form the first interconnection hole 150 .

[0185] Similarly, the second drain electrode 142 , the dielectric layer 200 and the first drain electrode 122 may be etched in sequence from the upper surface of the second drain electrode 142 to form the second interconnection hole 151 .

[0186] In step S710, refer to Figure 14 , the first interconnection hole 150 and the second interconnection hole 151 may be filled with a conductive material to form a common source 160 and a common drain 161 .

[0187] At this time, the common source 160 is connected to the first source 123 and the second source 143 , and the common drain 161 is connected to the first drain 122 and the second drain 142 , thereby forming the source and drain of the read transistor structure 10 .

[0188] A metal barrier layer may also be provided between the common source 160, the common drain 161 and the dielectric layer 200. The metal barrier layer includes but is not limited to at least one of a titanium nitride layer, a cobalt layer, a platinum layer and a titanium tungsten layer.

[0189] In the memory, the common source 160 and the common drain 161 can control the turning on or off of the read transistor.

[0190] Of course, see Figure 15A source conductive contact structure 170 and a drain conductive contact structure 171 may be formed above the common source 160 and the common drain 161. Through the source conductive contact structure 170 and the drain conductive contact structure 171, one of the source conductive contact structure 170 or the drain conductive contact structure 171 may be connected to the bit line BL, and the other may be connected to the ground terminal GND.

[0191] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0192] Based on the same inventive concept, in one embodiment, please refer to Figure 1 , provides a read transistor structure 10 including a substrate 180 , a dielectric layer 200 , a first transistor 120 , an isolation layer 130 and a second transistor 140 .

[0193] The substrate 100 may include a substrate and may also be provided with a bit line structure or the like.

[0194] The dielectric layer 200 is located on the substrate 100. The dielectric layer 200 may include a single layer or multiple layers. For example, the dielectric layer 200 may include a silicon dioxide layer, a silicon oxide layer, a silicon oxynitride layer, or the like.

[0195] The first transistor 120 is embedded in the dielectric layer 200. The first transistor 120 may be partially embedded in the dielectric layer 200. Of course, the first transistor 120 may also be fully embedded in the dielectric layer 200.

[0196] The isolation layer 130 is located in the dielectric layer 200 between the first transistor 120 and the second transistor 140 , and is used to isolate the first transistor 120 from the second transistor 140 .

[0197] The second transistor 140 is embedded in the dielectric layer 200. The second transistor 140 may be partially embedded in the dielectric layer 200. Of course, the second transistor 140 may also be fully embedded in the dielectric layer 200.

[0198] The second transistor 140 is disposed opposite to the first transistor 120 in the thickness direction of the dielectric layer 200 , and the source of the second transistor 140 is electrically connected to the source of the first transistor 120 , and the drain of the second transistor 140 is electrically connected to the drain of the first transistor 120 .

[0199] In this embodiment, the read transistor structure 10 includes a first transistor 120 and a second transistor 140 disposed opposite each other on the surface of a dielectric layer 200. The corresponding electrodes of the first transistor 120 and the second transistor 140 are electrically connected to form the source and drain of the read transistor structure 10. The isolation layer 130 reduces coupling between the first transistor 120 and the second transistor 140, thereby reducing the degree of mutual influence between the first transistor 120 and the second transistor 140, thereby improving the performance of the read transistor structure 10.

[0200] In one embodiment, read transistor structure 10 includes trench 110 .

[0201] The trench 110 penetrates the dielectric layer 200 in the thickness direction of the dielectric layer 200. Figure 16 In the thickness direction of the dielectric layer 200, the trench 110 includes an upper trench portion 113, a middle trench portion 112, and a lower trench portion 111. In this case, the first transistor 120 is embedded in the upper trench portion 113, the isolation layer 130 is located in the middle trench portion 112, and the second transistor 140 is embedded in the lower trench portion 111.

[0202] In one embodiment, see Figure 1 , the read transistor structure 10 includes a common source 160 and a common drain 161 .

[0203] The common source 160 penetrates the dielectric layer 200 on one side of the trench 110 and is spaced apart from the trench 110. The common source 160 is connected to the first transistor 120 and the second transistor 140.

[0204] The common drain 161 penetrates the dielectric layer 200 on the other side of the trench 110 and is spaced apart from the trench 110. The common source 160 is connected to the first transistor 120 and the second transistor 140.

[0205] The common source 160 and the common drain 161 can be made of conductive materials. For example, the common source 160 and the common drain 161 can be made of metal materials such as cobalt, nickel, titanium, tungsten, copper, and aluminum.

[0206] The common source 160 is the source of the read transistor structure 10, and the common drain 161 is the drain of the common drain 161. In the memory, the common source 160 and the common drain 161 can control the disconnection or conduction of the read transistor.

[0207] Of course, a metal barrier layer may also be provided between the common source 160, the common drain 161 and the dielectric layer 200. The metal barrier layer includes but is not limited to at least one of a titanium nitride layer, a cobalt layer, a platinum layer and a titanium tungsten layer.

[0208] A source conductive contact structure 170 and a drain conductive contact structure 171 may also be formed above the common source 160 and the common drain 161. The read transistor structure 10 may be connected to other devices through the source conductive contact structure 170 and the drain conductive contact structure 171. For example, see Figure 4 One of the source conductive contact structure 170 and the drain conductive contact structure 171 may be connected to the bit line BL, and the other may be connected to the ground terminal GND.

[0209] In one embodiment, see Figure 1 The first transistor 120 includes a first gate 121 , a first gate dielectric layer 124 , a first active layer 125 , a first source 123 and a first drain 122 .

[0210] The first gate 121 is located in the trench 110. The material of the first gate 121 may include, but is not limited to, any one or more of titanium nitride, titanium, tungsten silicide, and tungsten.

[0211] The first gate dielectric layer 124 is located within the trench 110 and on the sidewalls and top of the first gate 121. The first gate dielectric layer 124 surrounds the first gate 121. The material of the first gate dielectric layer 124 may include a material with a high-k dielectric constant, such as aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, or strontium titanium oxide.

[0212] The first active layer 125 is located within the trench 110, on the sidewalls and top of the first gate dielectric layer 124, and in the region between the sidewalls of the first gate electrode 121 and the sidewalls of the trench 110. The first active layer 125 surrounds the first gate dielectric layer 124, further stabilizing the entire channel region. For example, the material of the first active layer 125 may include IGZO.

[0213] The first source electrode 123 and the first drain electrode 122 are respectively located between the dielectric layer 200 and the substrate 100 on both sides of the trench 110 and connect the two ends of the first active layer 125. As an example, the material of the first gate electrode 121 is the same as that of the first source electrode 123 and / or the first drain electrode 122.

[0214] Likewise, in one embodiment, see Figure 1 The second transistor 140 includes a second gate 141 , a second gate dielectric layer 145 , a second active layer 144 , a second source 143 and a second drain 142 .

[0215] The second active layer 144 may be located on the isolation layer 130 and on the upper surface and sidewalls of the trench of the dielectric layer 200. As an example, the material of the second active layer 144 may include IGZO.

[0216] The two portions of the second active layer 144 located on the upper surface of the dielectric layer 200 can be the second source 143 and the second drain 142, respectively. It is understood that the second source 143 and the second drain 142 can be formed by doping the two portions of the second active layer 144 located on the upper surface of the dielectric layer 200. Of course, doping can be divided into heavily doped regions and lightly doped regions.

[0217] The second gate dielectric layer 145 is located on the sidewalls of the second active layer 144 and on the upper surface of the second active layer 144 within the trench 110. The material of the second gate dielectric layer 145 may include a material with a high-k dielectric constant, such as aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, or strontium titanium oxide.

[0218] The second gate 141 is located on the surface of the second gate dielectric layer 145. The material of the second gate 141 may include, but is not limited to, any one or more of titanium nitride, titanium, tungsten silicide, and tungsten.

[0219] Exemplarily, the second gate 141 fills the trench 110. The upper surface of the second gate 141, the upper surface of the second gate dielectric layer 145, and the upper surface of the second active layer 144 may be flush.

[0220] In one embodiment, the isolation layer 130 includes a first nitride layer. Alternatively, the isolation layer 130 includes a first oxide layer, a second nitride layer, and a second oxide layer stacked together (ONO structure). Alternatively, the isolation layer 130 includes a third nitride layer, a third oxide layer, and a fourth nitride layer stacked together (NON structure). By stacking oxide and nitride to form the isolation layer 130, the electrical isolation effect of the isolation layer 130 can be improved.

[0221] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0222] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A read transistor structure, characterized in that: include: substrate; a dielectric layer located on the substrate, a first transistor embedded in the dielectric layer; a second transistor embedded in the dielectric layer and arranged opposite to the first transistor in a thickness direction of the dielectric layer, with a source of the second transistor electrically connected to the source of the first transistor and a drain of the second transistor electrically connected to the drain of the first transistor; an isolation layer, located between the first transistor and the second transistor; a trench, which penetrates the dielectric layer in a thickness direction of the dielectric layer, and includes a trench lower portion, a trench middle portion, and a trench middle portion sequentially arranged in the thickness direction of the dielectric layer, the first transistor is embedded in the trench lower portion, the isolation layer is located in the trench middle portion, and the second transistor is embedded in the trench upper portion; a common source electrode, penetrating the dielectric layer on one side of the trench and spaced apart from the trench, the common source electrode being connected to the first transistor and the second transistor; a common drain electrode, penetrating the dielectric layer on the other side of the trench and spaced apart from the trench; and the common source electrode connecting the first transistor and the second transistor; The second transistor includes: a second active layer, located on the upper surface of the dielectric layer, the sidewalls of the trench, and the upper surface of the isolation layer, with two ends thereof connected to the common source and the common drain respectively; a second gate dielectric layer, located on the sidewalls of the second active layer and the upper surface of the second active layer in the trench; The second gate is located on the surface of the second gate dielectric layer.

2. The read transistor structure according to claim 1, wherein: The first transistor includes: a first gate located in the trench; a first gate dielectric layer, located in the trench and on the sidewalls and top of the first gate; a first active layer located in the trench, on the sidewalls and top of the first gate dielectric layer, and in a region between the sidewalls of the first gate and the sidewalls of the trench; The first source and the first drain are respectively located between the dielectric layer and the substrate on both sides of the trench and connected to both ends of the first active layer. The first source is connected to the common source, and the first drain is connected to the common drain.

3. The read transistor structure according to claim 2, wherein: The material of the first gate is the same as the material of the first source and / or the material of the first drain.

4. The read transistor structure according to claim 1, wherein: The second gate fills the trench.

5. The read transistor structure according to claim 1, wherein: The isolation layer includes a first nitride layer; Alternatively, the isolation layer includes a first oxide layer, a second nitride layer, and a second oxide layer that are stacked; Alternatively, the isolation layer includes a third nitride layer, a third oxide layer, and a fourth nitride layer that are stacked.

6. A method for preparing a read transistor structure, characterized in that: The steps include: providing a substrate; forming a dielectric layer on the substrate; forming a first transistor embedded in the dielectric layer on the dielectric layer; forming an isolation layer on the first transistor; A second transistor embedded in the dielectric layer is formed on the isolation layer. The second transistor is arranged opposite to the first transistor, and the source of the second transistor is electrically connected to the source of the first transistor, and the drain of the second transistor is electrically connected to the drain of the first transistor.

7. The method for preparing a read transistor structure according to claim 6, wherein: The step of forming a dielectric layer on the substrate includes: forming a dielectric material layer on the substrate; Etching the dielectric material layer to form a groove penetrating the dielectric material layer, and the remaining dielectric material layer forms the dielectric layer, wherein the groove includes a groove lower portion, a groove middle portion, and a groove upper portion sequentially arranged in a thickness direction of the dielectric layer; The step of forming a first transistor embedded in the dielectric layer on the dielectric layer includes: forming the first transistor at a lower portion of the trench; forming an isolation layer on the first transistor, comprising: forming the isolation layer in the middle of the trench; forming a second transistor embedded in the dielectric layer on the isolation layer; The second transistor is formed on the upper portion of the trench.

8. The method for preparing a read transistor structure according to claim 7, wherein: Before forming a dielectric material layer on the substrate, the method includes: forming a sacrificial material layer on the substrate; Etching the dielectric material layer to form a groove penetrating the dielectric material layer includes: Etching the dielectric material layer and the sacrificial material layer to form a groove penetrating the dielectric material layer and the sacrificial material layer, and the remaining sacrificial material layer forms a sacrificial layer; The forming of the first transistor at the lower portion of the trench comprises: removing the sacrificial layer; forming a first source electrode and a first drain electrode between the dielectric layer and the substrate on both sides of the trench, respectively, and forming a first gate electrode at the bottom of the trench; forming a first gate dielectric layer on the sidewalls and top of the first gate; A first active layer is formed on the sidewalls and top of the first gate dielectric layer, and the first active layer fills the area between the sidewalls of the first gate and the sidewalls of the trench.

9. The method for preparing a read transistor structure according to claim 8, wherein: A first source and a first drain are respectively formed between the dielectric layer and the substrate on both sides of the trench, and a first gate is formed at the bottom of the trench, comprising: forming a conductive material layer on the surface of the substrate and the surface of the dielectric layer; The conductive material layer is patterned to form the first gate, the first source, and the first drain.

10. The method for preparing a read transistor structure according to claim 8, wherein: The forming of the second transistor on the upper portion of the trench comprises: forming a second active layer on the upper surface of the isolation layer, the sidewalls of the trench, and the upper surface of the dielectric layer; forming a second gate dielectric layer on the sidewalls of the second active layer and on the upper surface of the second active layer in the trench; A second gate is formed on the surface of the second gate dielectric layer.

11. The method for preparing a read transistor structure according to claim 10, wherein: After forming the second transistor on the upper portion of the trench, the method includes: Sequentially etching the second active layer and the dielectric layer on both sides of the trench to form a first interconnection hole and a second interconnection hole penetrating to the first source electrode and the first drain electrode respectively; Conductive material is filled in the first interconnection hole and the second interconnection hole to form a common source and a common drain respectively.

12. A memory, characterized in that: include: a write transistor structure and a read transistor structure; The read transistor structure includes a first transistor and a second transistor, wherein a source of the second transistor is electrically connected to a source of the first transistor, and a drain of the second transistor is electrically connected to a drain of the first transistor; The first electrode of the write transistor structure is connected to the gate of the first transistor or the gate of the second transistor, and the first electrode is a source or a drain.

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