Semiconductor memory device and manufacturing method thereof

Abstract

The invention relates to a semiconductor memory device and a manufacturing method thereof. There is provided a semiconductor memory device including: a substrate having a complementary metal oxide semiconductor (CMOS) circuit; a gate stack structure including interlayer insulating layers and conductive patterns alternately stacked on the substrate in a vertical direction; a channel structure having a first portion penetrating the gate stack structure and a second portion extending from one end of the first portion, the second portion extending beyond the gate stack structure; a common source line extending to overlap the gate stack structure, the common source line surrounding a second portion of the channel structure; a memory layer disposed between the first portion of the channel structure and the gate stack structure; and a bit line connected to the other end of the first portion of the channel structure, the bit line disposed between the substrate and the gate stack structure.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202010175082.9 (application date: March 13, 2020, invention name: semiconductor memory device and manufacturing method thereof). Technical Field

[0002] The present disclosure generally relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a three-dimensional semiconductor memory device and a method for manufacturing the same. Background Art

[0003] A semiconductor memory device may include a memory cell array having a plurality of memory cells. In order to improve the integration of the semiconductor memory device, the memory cells may be arranged three-dimensionally. Compared with a two-dimensional semiconductor memory device, a three-dimensional semiconductor memory device including three-dimensionally arranged memory cells may have a complicated manufacturing process for various reasons. Summary of the invention

[0004] According to one aspect of the present disclosure, a semiconductor memory device is provided, which includes: a substrate having a complementary metal oxide semiconductor (CMOS) circuit; a gate stack structure, which includes an interlayer insulating layer and a conductive pattern, and the interlayer insulating layer and the conductive pattern are alternately stacked on the substrate in a vertical direction; a channel structure, which has a first part penetrating the gate stack structure and a second part extending from one end of the first part, and the second part extends beyond the gate stack structure; a common source line, which extends to overlap with the gate stack structure, and the common source line surrounds the second part of the channel structure; a memory layer, which is arranged between the first part of the channel structure and the gate stack structure; and a bit line, which is connected to the other end of the first part of the channel structure, and the bit line is arranged between the substrate and the gate stack structure.

[0005] According to another aspect of the present disclosure, a method for manufacturing a semiconductor memory device is provided, the method comprising the following steps: forming a memory cell array on a first substrate, wherein the memory cell array comprises: a gate stack structure, the gate stack structure comprising an interlayer insulating layer and a conductive pattern, the interlayer insulating layer and the conductive pattern being alternately stacked in a vertical direction; a channel structure, the channel structure penetrating the gate stack structure, the end of the channel structure extending to the interior of the first substrate; and a memory layer, the memory layer extending from between the channel structure and the gate stack structure to between the end of the channel structure and the first substrate; forming a bit line connected to the memory cell array; removing the first substrate to expose the memory layer; removing a portion of the memory layer to expose the end of the channel structure; and forming a common source line around the end of the channel structure, the common source line extending to overlap with the gate stack structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure.

[0007] Figure 2 is shown with Figure 1 A cross-sectional view of an embodiment of a memory cell array is shown with a first region of a substrate overlapping.

[0008] Figure 3 It is shown Figure 2 A plan view of the gate stack structure shown.

[0009] Figure 4 yes Figure 2 An enlarged cross-sectional view of region A is shown.

[0010] Figure 5 is shown with Figure 1 A cross-sectional view of an embodiment of an interconnect array overlapping a second region of a substrate is shown.

[0011] Figure 6 yes Figure 5 An enlarged cross-sectional view of region D is shown.

[0012] Figure 7 and Figure 8 are cross-sectional views showing various embodiments of a channel structure.

[0013] Fig. 9 and Fig.10 is a cross-sectional view showing an embodiment of a common source line.

[0014] Fig.11 is a flowchart schematically illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E and Fig.12F , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 as well as Fig.18A , Fig.18B and Fig. 18C 2 is a cross-sectional view showing a process of a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Fig.19 is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure.

[0017] Fig. 20 is a block diagram showing a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The structural or functional descriptions disclosed herein are merely illustrative for describing the embodiments of the concepts according to the present disclosure. The embodiments of the concepts according to the present disclosure may be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein.

[0019] Hereinafter, various examples of the embodiments will be described below with reference to the accompanying drawings. Various examples of the embodiments are described here with reference to the cross-sectional views of the schematic diagrams of various examples of the embodiments (and intermediate structures). Thus, changes in the shape relative to the diagrams, for example due to manufacturing techniques and / or tolerances, are expected. Therefore, the embodiments should not be interpreted as being limited to the specific shapes of the regions shown here, but may include shape deviations, for example, caused by manufacturing. In the accompanying drawings, the lengths and sizes of the layers and regions may be exaggerated for clarity. The same reference numerals in the accompanying drawings represent the same elements. It should also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on another layer or substrate, or there can also be an intermediate layer. It should also be understood that when a structure is referred to as being "on" another structure or substrate, it can be directly on another structure or substrate, or there can also be an intermediate structure. It should be understood that when an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, it can be directly on another element or layer, directly connected to or coupled to another element or layer, or there can also be an intermediate element or layer. In contrast, when an element is referred to as being “directly on,” “directly connected to,” “directly contacting” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0020] Embodiments provide a semiconductor memory device capable of simplifying a manufacturing process and a manufacturing method of the semiconductor memory device.

[0021] Figure 1 is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure.

[0022] Reference Figure 1 , the semiconductor memory device may include a substrate 10, a first line array L1A, a memory cell array MCA, an interconnect array ICA, and a second line array L2A.

[0023] The substrate 10 may include a first region R1 overlapping the memory cell array MCA and a second region R2 overlapping the interconnect array ICA.

[0024] The first line array L1A may overlap the substrate 10 and be spaced apart from the substrate 10 in a vertical direction. The first line array L1A may include a plurality of first lines arranged at equal levels to each other and made of the same conductive material. The first lines may include a plurality of bit lines connected to the memory cell array MCA and a plurality of connection lines connected to the interconnect array ICA.

[0025] The memory cell array MCA and the interconnection array ICA may be disposed on the first line array L1A.

[0026] The memory cell array MCA may include a plurality of memory cell strings STR connected to the bit lines of the first line array L1A. Each of the memory cell strings STR may include a plurality of memory cells MC connected in series between a drain select transistor DST and a source select transistor SST. Each memory cell string STR may be connected to a drain select line DSL, a source select line SSL, and a word line WL corresponding thereto. The drain select line DSL may be used as a gate of the drain select transistor DST, the source select line SSL may be used as a gate of the source select transistor SST, and each word line WL may be used as a gate of a memory cell MC corresponding thereto.

[0027] The interconnection array ICA may include a plurality of vertical contact plugs extending parallel to the memory cell strings STR. Each vertical contact plug may be formed of a conductive material and may be connected to a connection line corresponding thereto among connection lines of the first line array L1A.

[0028] The second line array L2A may overlap the memory cell array MCA and the interconnect array ICA. The second line array L2A may include a common source line. The common source line may be connected to the memory cell array MCA. The common source line may be connected to at least one vertical contact plug of the interconnect array ICA. The common source line may be formed into various structures such as a grid structure and a line structure.

[0029] Figure 2 is shown with Figure 1 1 is a cross-sectional view of an embodiment of a memory cell array MCA in which a first region R1 of a substrate 10 is overlapped.

[0030] Reference Figure 2 , refer to Figure 1 The described memory cell array MCA may include gate stack structures GST separated by slits SI, channel structures CH penetrating the gate stack structures GST, and memory layers ML extending along sidewalls of each channel structure CH.

[0031] The gate stack structure GST may be spaced apart from the first region R1 of the substrate 10 in the vertical direction D3. Each gate stack structure GST may extend in the first direction D1 and the second direction D2 on a plane intersecting the vertical direction D3. The lines extending in the first direction D1 and the lines extending in the second direction D2 may intersect each other. In one embodiment, the lines extending in the first direction D1 and the lines extending in the second direction D2 may be orthogonal to each other.

[0032] Each gate stack structure GST may include a sidewall defined by a slit SI. The slit SI may extend in a vertical direction D3.

[0033] Figure 3 It is shown Figure 2 The plan view of the gate stack structure GST is shown, and the Figure 2 The cross section of each gate stack structure GST is taken along line II′.

[0034] Reference Figure 3 , the slit S1 may have a straight line shape extending in the second direction D2. However, the present disclosure is not limited thereto. For example, the slit S1 may be formed in various shapes such as a zigzag shape and a wavy shape extending in the second direction.

[0035] Each gate stack structure GST may be penetrated by a plurality of channel structures CH. The plurality of channel structures CH may be arranged in a zigzag shape. However, the present disclosure is not limited thereto. For example, the plurality of channel structures CH may be arranged in a matrix structure.

[0036] Refer again Figure 2 , a sidewall insulating layer 23 may be formed on the sidewall of each gate stack structure GST.

[0037] One end of each channel structure CH may be connected to a common source line CSL. The common source line CSL is a reference Figure 1The channel structure CH may be a portion of the second line array L2A described above and may extend to overlap the gate stack structure GST. The channel structure CH may be more prominent than the gate stack structure GST and may extend to the inside of the common source line CSL. The common source line CSL may be covered by a protective insulating layer 95. The protective insulating layer 95 may include an oxide layer.

[0038] The other end of each channel structure CH can be connected to the corresponding bit line 41A. The bit line 41A is a reference Figure 1 A portion of the first line array L1A is described and may extend in the first direction D1.

[0039] The first insulating layer 21, the second insulating layer 25, and the third insulating layer 27 may be disposed between the bit line 41A and the gate stack structure GST. The first insulating layer 21 may surround the lower end of each channel structure CH adjacent to the bit line 41A. The first insulating layer 21 may extend to overlap with the gate stack structure GST. The first insulating layer 21 may be penetrated by the slit SI. The sidewall insulating layer 23 may extend to the sidewall of the first insulating layer 21. The second insulating layer 25 may fill the slit SI and extend to cover the surface of the first insulating layer 21. The third insulating layer 27 may be disposed between the second insulating layer 25 and the bit line 41A. However, the present disclosure is not limited thereto. For example, at least one of the first to third insulating layers 21, 25, and 27 may be omitted.

[0040] The bit line 41A may be connected to the channel structure CH corresponding thereto via the first contact plug 31A. The first contact plug 31A may be formed of a conductive material penetrating the second insulating layer 25 and the third insulating layer 27 and may contact the bit line 41A and the channel structure CH corresponding thereto.

[0041] A reference line may be defined along each channel structure CH connected to the bit line 41A and the common source line CSL. Figure 1 A memory cell string STR is described. Region A represents a longitudinal cross-sectional structure of the memory cell string.

[0042] Figure 4 yes Figure 2 An enlarged cross-sectional view of region A is shown.

[0043] Reference Figure 4, the gate stack structure GST may include an interlayer insulating layer ILD and conductive patterns CP1 to CPn alternately stacked in a vertical direction D3. Each of the conductive patterns CP1 to CPn may include various conductive materials and barrier layers such as a doped silicon layer, a metal layer, and a metal silicide layer, and may include two or more conductive materials. For example, each of the conductive patterns CP1 to CPn may include tungsten and a titanium nitride layer (TiN) surrounding the surface of the tungsten. Tungsten is a low-resistance metal and can reduce the resistance of the conductive patterns CP1 to CPn. The titanium nitride layer (TiN) is a barrier layer and can prevent direct contact between tungsten and the interlayer insulating layer ILD.

[0044] The n-th conductive pattern CPn adjacent to the common source line CSL among the conductive patterns CP1 to CPn may be used as a reference. Figure 1 The source selection line SSL described in the conductive patterns CP1 to CPn is Figure 2 The first conductive pattern CP1 adjacent to the bit line 41A shown may be used as a reference. Figure 1 However, the present disclosure is not limited thereto. For example, two or more conductive patterns adjacent to and continuously stacked with the common source line CSL may be used as the source selection line, and the drain selection line DSL may be connected to the common source line CSL. Figure 2 The two or more conductive patterns shown adjacent to the bit line 41A and stacked continuously are used as drain selection lines. The conductive patterns (eg, CP2 to CPn-1) disposed between the source selection lines and the drain selection lines adjacent to each other can be used as reference lines. Figure 1 Described word line WL.

[0045] The channel structure CH may include a first portion P1A and a second portion P2A. The first portion P1A may be defined as a portion of the channel structure CH that penetrates the gate stack structure GST. The first portion P1A may extend to Figure 2 The second portion P2A may be defined as a portion of the channel structure CH that protrudes further toward the common source line CSL than the gate stack structure GST. In one embodiment, the channel structure CH has a first portion P1A that penetrates the gate stack structure GST and a second portion P2A that extends from one end of the first portion P1A, and the second portion P2A extends beyond the gate stack structure GST. The second portion P2A may be surrounded by the common source line CSL. The diameter WA of the first portion P1A may be greater than the diameter WB of the second portion P2A.

[0046] The sidewall of the channel structure CH may be surrounded by the memory layer ML. The memory layer ML may be disposed between the first portion P1A and the gate stack structure GST, and may be disposed between the first portion P1A and the gate stack structure GST. Figure 2The memory layer ML may include a tunnel insulating layer TI, a data storage layer DL, and a blocking insulating layer BI stacked from the sidewall of the first portion P1A toward the gate stack structure GST. The tunnel insulating layer TI may include a silicon oxide through which charges can tunnel. The data storage layer DL may be formed of a charge trapping layer. For example, the charge trapping layer may include silicon nitride. The blocking insulating layer BI may include an oxide capable of blocking charges. The data storage layer DL may be formed of various materials other than the charge trapping layer. For example, the data storage layer DL may be formed of a material layer including conductive nanodots, may be formed of a phase change material layer, or may be formed of a material layer for a floating gate. Depending on the structure of the unit to be implemented, the data storage layer DL may be formed in various forms between the tunnel insulating layer TI and the blocking insulating layer BI.

[0047] The channel structure CH may include a channel layer CL, a core insulating layer CO, and a doped semiconductor layer DS. The channel structure CH may be formed as a hollow structure. The core insulating layer CO and the doped semiconductor layer DS may be disposed in a central region of the channel structure CH. The doped semiconductor layer DS may be disposed between the core insulating layer CO and the doped semiconductor layer DS. Figure 2 In one embodiment, the doped semiconductor layer DS may be connected to the bit line 41A. Figure 2 The first contact plug 31A shown contacts and fills the central area of ​​the channel layer CL. The channel layer CL may extend between the doped semiconductor layer DS and the memory layer ML and between the core insulating layer CO and the memory layer ML. A portion of the channel layer CL may extend to the inside of the common source line CSL to constitute the second portion P2A of the channel structure CH. The portion of the channel layer CL constituting the second portion P2A may be in direct contact with the common source line CSL. In other words, the portion of the channel layer CL constituting the second portion P2A may be disposed between the common source line CSL and the core insulating layer CO.

[0048] The channel structure CH is not limited to the examples shown in the drawings. For example, the channel structure CH may include an embedded type channel layer embedded in a central region of the channel structure CH, and the core insulating layer CO may be omitted.

[0049] The channel layer CL serves as a channel region of a memory cell string corresponding thereto. The channel layer CL may be formed of a semiconductor material. In one embodiment, the channel layer CL may include a silicon layer. Conductive type dopants may be distributed at both ends of the channel layer CL. For example, conductive type dopants may be distributed at both ends of the channel layer CL indicated in region B and region C. Region B includes one end of the channel layer CL adjacent to the common source line CSL, and region C includes the other end of the channel layer CL adjacent to the doped semiconductor layer DS. The conductive type dopant may include an n-type dopant for a junction. The conductive type dopant may include a counter-doped p-type dopant.

[0050] According to the above structure, a memory cell can be defined at an intersection of the channel structure CH and a conductive pattern (e.g., CP2 to CPn-1) used as a word line, a drain selection transistor can be defined at an intersection of the channel structure CH and a conductive pattern (e.g., CP1) used as a drain selection line, and a source selection transistor can be defined at an intersection of the channel structure CH and a conductive pattern (e.g., CPn) used as a source selection line. The memory cell is connected in series between the drain selection transistor and the source selection transistor through the channel structure CH to form a reference Figure 1 Described is a memory cell string STR.

[0051] Return to reference Figure 2 , the memory layer ML shorter than the channel structure CH may be formed in the vertical direction D3.

[0052] The bit line 41A may be spaced apart from the substrate 10 by the first insulating structure 51 and the second insulating structure 81. The first insulating structure 51 may include two or more insulating layers. In one embodiment, the first insulating structure 51 may include insulating layers 51A to 51D stacked between the bit line 41A and the second insulating structure 81. The second insulating structure 81 may include two or more insulating layers. In one embodiment, the second insulating structure 81 may include insulating layers 81A to 81D stacked between the substrate 10 and the first insulating structure 51.

[0053] The substrate 10 may include a complementary metal oxide semiconductor (CMOS) circuit. The substrate 10 may be a bulk silicon substrate, a silicon on insulator substrate, a germanium substrate, a germanium on insulator substrate, a silicon germanium substrate, or an epitaxial film formed by a selective epitaxial growth process.

[0054] The CMOS circuit may include a plurality of transistors TR constituting a peripheral circuit for driving a memory cell array. The plurality of transistors TR may include an NMOS transistor and a PMOS transistor. The transistor TR may be disposed on an active region of the substrate 10 divided by an isolation layer 13. Each transistor TR may include a gate insulating layer 17 and a gate 19 disposed on an active region corresponding thereto, and may include a junction 15a and a junction 15b formed in an active region at both sides of the gate 19. The junctions 15a and 15b may include a conductive type dopant. For example, the conductive type dopant included in the junctions 15a and 15b may include at least one of an n-type dopant and a p-type dopant, depending on the characteristics of the transistor to be implemented.

[0055] The transistor TR of the CMOS circuit can be electrically connected to the reference MOSFET via the first connection structure C1 and the second connection structure C2. Figure 1 Referring to the memory cell array MCA described above. Figure 1 The described interconnect array ICA may be used for the purpose of electrical connection between the transistors TR of a CMOS circuit and the memory cell array MCA.

[0056] Figure 5 is shown with Figure 1 FIG. 1 is a cross-sectional view of an embodiment of an interconnect array ICA in which a second region R2 of a substrate 10 is overlapped.

[0057] Reference Figure 5 , refer to Figure 1 The described interconnection array ICA may include a dummy stack structure DM and a vertical contact plug VCT penetrating the dummy stack structure DM.

[0058] The dummy stack structure DM may overlap the second region R2 of the substrate 10 and may be disposed adjacent to the reference region R2. Figure 2 The levels of the gate stack structures GST described are substantially equal to each other. The dummy stack structure DM may be covered by a common source line CSL extending to be connected to the vertical contact plug VCT. The dummy stack structure DM may be disposed between the common source line CSL and the connection line 41B.

[0059] Connection line 41B is reference Figure 1 The connecting line 41B may be arranged at a position corresponding to the reference line L1A. Figure 2 The level of the bit line 41A described above is substantially equal to that of the bit line 41A, and may be formed of the same conductive material as the bit line 41A. Figure 2 The described first insulating layer 21 , second insulating layer 25 , and third insulating layer 27 may extend between the dummy stack structure DM and the connection line 41B.

[0060] The vertical contact plug VCT may penetrate the dummy stack structure DM. The vertical contact plug VCT may extend to the inside of the common source line CSL and may penetrate the first insulating layer 21 and the second insulating layer 25. The vertical contact plug VCT may be connected to the connection line 41B via the second contact plug 31B penetrating the third insulating layer 27. In another embodiment, the vertical contact plug VCT may extend to directly contact the connection line 41B. The vertical contact plug VCT may be formed of various conductive materials. The local length of the vertical contact plug VCT extending to the inside of the common source line CSL may be the same as the channel structure ( Figure 2 The local lengths of the CH) shown extending to the inside of the common source line CSL may be the same or different.

[0061] Reference Figure 2 The described insulation layers 51A to 51D of the first insulation structure 51 and the insulation layers 81A to 81D of the second insulation structure 81 may extend between the second region R2 of the substrate 10 and the connection line 41B.

[0062] Reference Figure 2 The protective insulating layer 95 described may extend to cover Figure 5 A common source line CSL and a dummy stack structure DM are shown.

[0063] Other transistors TR constituting the CMOS circuit may be disposed in the second region R2 of the substrate 10. In one embodiment, a discharge transistor DIS may be disposed in the second region R2 of the substrate 10.

[0064] Reference Figure 2 and Figure 5 , each of the first connection structures C1 may include various conductive patterns 61, 63, 65, 67, 69, and 71 embedded in the first insulating structure 51. Each of the second connection structures C2 may be connected to a corresponding one of the transistors TR constituting the CMOS circuit. Each of the second connection structures C2 may include various conductive patterns 83, 85, 87, 89, 91, and 93 embedded in the second insulating structure 81. The structure of each of the first connection structures C1 and the second connection structures C2 is not limited to Figure 2 and Figure 5 Examples are shown, and various modifications may be made.

[0065] Each of the first connection structures C1 may include a first bonding metal 71, and each of the second connection structures C2 may include a second bonding metal 93. The first bonding metal 71 and the second bonding metal 93 may be arranged to face each other, and may be attached to each other.

[0066] Return to reference Figure 5The discharge transistor DIS may be connected to the connection line 41B via the second connection structure C2 and the first connection structure C1 corresponding to the discharge transistor DIS. The connection line 41B, the second contact plug 31B, and the vertical contact plug VCT may connect the discharge transistor DIS to the common source line CSL.

[0067] Figure 6 yes Figure 5 An enlarged cross-sectional view of region D is shown.

[0068] Reference Figure 6 The dummy stack structure DM may include dummy interlayer insulating layers ILD′ and sacrificial layers SA1 to SAn alternately stacked in a vertical direction. The dummy interlayer insulating layers ILD′ may be disposed at Figure 4 The sacrificial layers SA1 to SAn may be disposed at substantially the same level as the interlayer insulating layers ILD shown. Figure 4 The levels of the conductive patterns CP1 to CPn are shown to be substantially equal.

[0069] The interlayer insulating layer ILD and the virtual interlayer insulating layer ILD' may be formed of the same material layer. The sacrificial layers SA1 to SAn may be formed of a material having an etching rate different from that of the interlayer insulating layer ILD and the virtual interlayer insulating layer ILD'. For example, the interlayer insulating layer ILD and the virtual interlayer insulating layer ILD' may include silicon oxide, and the sacrificial layers SA1 to SAn may include silicon nitride.

[0070] The virtual stack structure DM is not limited to Figure 6 For example, the dummy stack structure DM may include dummy interlayer insulating layers and dummy conductive patterns alternately stacked in a vertical direction. The dummy conductive patterns may be arranged at the same Figure 4 The conductive patterns CP1 to CPn shown have substantially equal levels and may be Figure 4 The illustrated conductive patterns CP1 to CPn are formed of the same conductive material. When the dummy stack structure DM includes the dummy conductive patterns, sidewalls of the vertical contact plugs VCT penetrating the dummy stack structure DM may be surrounded by an insulating material.

[0071] Figure 7 and Figure 8 are cross-sectional views showing various embodiments of a channel structure. Figure 7 and Figure 8 The gate stack structure GST and the memory layer ML shown are similar to those of the reference Figure 2 and Figure 4 The gate stack structure GST and the memory layer ML are described to be substantially similar. In one embodiment, the gate stack structure GST may include interlayer insulating layers and conductive patterns alternately stacked in a vertical direction.

[0072] Reference Figure 7 , the channel structure CHb may include a first portion P1B penetrating the gate stack structure GST and a second portion P2B extending from an end of the first portion P1B to the inside of the common source line CSLb.

[0073] The memory layer ML may surround the first portion P1B of the channel structure CHb, and the memory layer ML may include a tunnel insulating layer TI, a data storage layer DL, and a blocking insulating layer BI.

[0074] The second portion P2B of the channel structure CHb may have a sidewall SW2 aligned in a straight line with the sidewall SW1 of the first portion P1B. The diameter WC of the second portion P2B inserted into the common source line CSLb may be greater than Figure 4 The diameter WB of the second portion P2A is shown.

[0075] Reference Figure 8 , the channel structure CHc may include a first portion P1C penetrating the gate stack structure GST and a second portion P2C extending from an end of the first portion P1C to the inside of the common source line CSLc.

[0076] The first portion P1C of the channel structure CHc may be surrounded by a memory layer ML including a tunnel insulating layer TI, a data storage layer DL, and a blocking insulating layer BI.

[0077] The second portion P2C of the channel structure CHc may have a shape that is rounded toward the common source line CSLc. For example, the second portion P2C of the channel structure CHc may be formed in a spherical shape. The concave portion defined in the common source line CSLc into which the second portion P2C is inserted may be formed in a rounded shape. In one embodiment, the convex-shaped second portion P2C of the channel structure CHc may extend beyond the first portion P1C of the channel structure CHc, and the convex-shaped second portion P2C is defined by the concave portion located in the common source line CSLc.

[0078] Figure 2 , Figure 4 , Figure 5 and Figure 6 Each of the common source lines CSL shown in FIG. Figure 7 The common source line CSLb and Figure 8The common source line CSLc shown may include metal. In one embodiment, each of the common source lines CSL, CSLb, and CSLc may include a barrier layer and a metal layer. The barrier layer may be formed to prevent direct contact between the metal layer and the channel structure corresponding thereto and to prevent metal from diffusing into the channel structure. For example, the barrier layer may include a titanium nitride layer, etc. The metal layer may include various metals such as aluminum.

[0079] Fig. 9 and Fig.10 is a cross-sectional view showing an embodiment of a common source line CSL′. Fig. 9 The portion of the common source line CSL′ overlapping the gate stack structure GST is shown, and Fig.10 Another portion of the common source line CSL' is shown overlapping the dummy stack structure DM. Fig. 9 The gate stack structure GST shown is similar to the reference Figure 2 and Figure 4 The gate stack structure GST described is the same as that described above, and Fig.10 The virtual stacking structure DM shown is similar to the reference Figure 5 and Figure 6 The described virtual stacking structure DM is the same.

[0080] Reference Fig. 9 and Fig.10 , the common source line CSL' may include a source-side doped semiconductor layer SE in direct contact with the channel structure CH and the vertical contact plug VCT and a metal layer MT disposed on the surface of the source-side doped semiconductor layer SE. Although not shown in the drawings, a barrier layer such as a titanium nitride layer (TiN) may be further formed between the metal layer MT and the source-side doped semiconductor layer SE. The metal layer MT may include various metals such as aluminum.

[0081] The adhesion between the common source line CSL′ and the channel structure CH may be enhanced by the source-side doped semiconductor layer SE. The source-side doped semiconductor layer SE may include at least one of an n-type dopant and a p-type dopant.

[0082] The metal layer MT may be connected to the channel structure CH and the vertical contact plug VCT via the source-side doped semiconductor layer SE.

[0083] Fig.11 is a flowchart schematically illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0084] Reference Fig.11, a method for manufacturing a semiconductor memory device may include the following steps: step S1A, forming a memory cell array, a first line array and a first connection structure on a first substrate; step S2A, forming a CMOS circuit and a second connection structure on a second substrate; step S3, attaching the first connection structure and the second connection structure to each other; step S5, removing the first substrate; step S7, implanting conductive type dopants; step S9, exposing a channel structure of the memory cell array; and step S11, forming a common source line connected to the channel structure.

[0085] FIG. 12A to FIG. 12F , Figures 13 to 17 as well as 18A to 18C 2 is a cross-sectional view showing a process of a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0086] FIG. 12A to FIG. 12F It is shown Fig.11 A cross-sectional view of an embodiment of step S1A is shown.

[0087] Reference Fig. 12A , step S1A may include the following steps: alternately stacking first material layers 111 and second material layers 113 on the first substrate 101 including the cell region Ra and the interconnection region Rb.

[0088] The first substrate 101 may be formed of a material having an etching rate different from those of the first material layer 111 and the second material layer 113. For example, the first substrate 101 may include silicon.

[0089] In one embodiment, the first material layer 111 may be used for reference Figure 4 The interlayer insulating layer ILD described and the reference Figure 6 The second material layer 113 is used to refer to the insulating material of the virtual interlayer insulating layer ILD'. Figure 6 The materials of the sacrificial layers SA1 to SAn described above may be the same as those of reference Figure 4 The interlayer insulating layer ILD described and the reference Figure 6 The dummy interlayer insulating layer ILD' described above may have a material with a different etch rate. For example, the first material layer 111 may include silicon oxide, and the second material layer 113 may include silicon nitride. The following figures show an embodiment in which the first material layer 111 is formed of an insulating material and the second material layer 113 is formed of a sacrificial layer, but the present disclosure is not limited thereto. The properties of the first material layer 111 and the second material layer 113 may be modified differently. For example, the first material layer 111 may be a material for reference Figure 4 The interlayer insulating layer ILD described and the reference Figure 6The insulating material of the virtual interlayer insulating layer ILD' described above, and the second material layer 113 may be used for reference Figure 4 The conductive materials of the conductive patterns CP1 to CPn are described.

[0090] Reference Fig. 12B , a first mask pattern 121 including a first opening 125 may be formed on the stacked structure of the first material layer 111 and the second material layer 113. Subsequently, a channel hole 115 penetrating the first material layer 111 and the second material layer 113 may be formed through the first opening 125 of the first mask pattern 121. The channel hole 115 may extend to the inside of the unit area Ra of the first substrate 101. The channel hole 115 may be formed in various shapes according to an etching material used to form the channel hole 115.

[0091] In one embodiment, the channel hole 115 may be formed using a first etching material. The etching speed of the first material layer 111 and the second material layer 113 for the first etching material may be faster than the etching speed of the first substrate 101 for the first etching material. As a result, the width W1 of the end portion of the channel hole 115 extending to the inside of the first substrate 101 may be formed to be narrower than the width W2 of the main region of the channel hole 115 penetrating the first material layer 111 and the second material layer 113.

[0092] In another embodiment, the step of forming the channel hole 115 may include the step of performing an etching process using the above-mentioned first etching material and the step of widening the width of the end of the channel hole 115 by using a second etching material for isotropically etching the first substrate 101. The end of the channel hole 115 may be formed into various structures by isotropic etching. For example, the end of the channel hole 115 may have a Figure 7 or Figure 8 Various structures shown.

[0093] Reference Fig. 12C , a memory layer 137 and a channel structure 147A may be formed in the channel hole 115 . Sidewalls of the channel structure 147A and ends of the channel structure 147A extending to the inside of the first substrate 101 may be surrounded by the memory layer 137 .

[0094] The step of forming the memory layer 137 may include the step of sequentially stacking a blocking insulating layer 135, a data storage layer 133, and a tunnel insulating layer 131 on the surface of the channel hole 115. The blocking insulating layer 135, the data storage layer 133, and the tunnel insulating layer 131 may include the same Figure 4 The materials of the blocking insulating layer BI, the data storage layer DL, and the tunnel insulating layer TI are the same as described. The memory layer 137 may be formed in a liner shape, and a central area of ​​the channel hole 115 may be defined by the memory layer 137 .

[0095] The step of forming the channel structure 147A may include the step of forming a channel layer 141A on the surface of the memory layer 137. The channel layer 141A may include a semiconductor layer serving as a channel region. For example, the channel layer 141A may include silicon.

[0096] In one embodiment, the channel layer 141A may be formed in a liner shape, and the central area of ​​the channel hole 115 may include a portion not filled by the channel layer 141A. When the channel layer 141A is formed in a liner shape, the step of forming the channel structure 147A may include the following steps: a step of filling the central area of ​​the channel hole 115 with the core insulating layer 143 on the channel layer 141A; a step of defining a recessed area at a portion of the central area of ​​the channel hole 115 by etching a portion of the core insulating layer 143; and a step of filling the recessed area with the doped semiconductor layer 145. The core insulating layer 143 may include an oxide, and the doped semiconductor layer 145 may include a conductive type dopant. The conductive type dopant may include an n-type dopant for a junction. The conductive type dopant may include a reversely doped p-type dopant.

[0097] In another embodiment, the channel layer 141A may be formed to fill the central region of the channel hole 115, and the core insulating layer 143 and the doped semiconductor layer 145 may be omitted. When the core insulating layer 143 and the doped semiconductor layer 145 are omitted, the step of forming the channel structure 147A may further include the step of doping a conductive type dopant into the channel layer 141A.

[0098] Reference Fig.12D , you can remove Fig. 12C The first mask pattern 121 is shown followed by forming a first insulating layer 151 .

[0099] Subsequently, a slit 153 may be formed. The slit 153 may penetrate the first insulating layer 151 and may penetrate the stacked structure of the first material layer 111 and the second material layer 113. The slit 153 may be connected to Figure 2 and Figure 3 1. The slit SI shown corresponds to the slit SI shown. Subsequently, a horizontal space 155 can be defined by selectively removing the second material layer 113 overlapping the unit area RA of the first substrate 101 through the slit 153. The horizontal space 155 can be defined between the first material layers 111 overlapping the unit area Ra of the first substrate 101 and adjacent to each other in the vertical direction. The second material layer 113 overlapping the interconnection area Rb of the first substrate 101 is not removed and can be retained. The first material layer 111 and the second material layer 113 overlapping the interconnection area Rb of the first substrate 101 can be retained as a virtual stacked structure 110.

[0100] Reference Fig.12E , Fig.12D The horizontal spaces 155 shown are filled with third material layers 157 through the slits 153. The third material layers 157 may be reference Figure 4 The third material layer 157 may fill the horizontal space 155 to surround the channel structure 147A and the memory layer 137 .

[0101] As described above, by replacing the second material layer 113 as a sacrificial layer formed on the cell region Ra of the first substrate 101 with the third material layer 157 as a conductive pattern, a gate stack structure 150 can be formed on the cell region Ra of the first substrate 101. The gate stack structure 150 may include a structure in which the first material layer 111 as an interlayer insulating layer and the third material layer 157 as a conductive pattern are alternately stacked. The gate stack structure 150 may be penetrated by the channel structure 147A, and the channel structure 147A may extend to the inside of the cell region Ra of the first substrate 101. The memory layer 137 may extend from between the channel structure 147A and the gate stack structure 150 to between the end of the channel structure 147A and the first substrate 101.

[0102] By reference FIG. 12A to FIG. 12E The process described above can form a substrate 101 including a Figure 1 The memory cell array of the plurality of memory cell strings STR described. Figure 1 As described, each memory cell string may include a drain select transistor DST, a memory cell MC, and a source select transistor SST connected in series. Figure 1 The drain selection transistor DST, the memory cell MC, and the source selection transistor SST described may be defined in Fig.12E The channel structure 147A and the third material layer 157 as a conductive pattern are shown at an intersection and are connected in series through the channel structure 147A.

[0103] Subsequently, a sidewall insulating layer 161 covering the sidewalls of the gate stack structure 150 may be formed. Subsequently, a second insulating layer 163 filling the slit S1 and extending to cover the sidewall insulating layer 161 and the first insulating layer 151 may be formed.

[0104] Subsequently, a contact hole 165 penetrating the second insulating layer 163, the first insulating layer 151, and the dummy stack structure 110 may be formed. The contact hole 165 may extend to the inside of the interconnection region Rb of the first substrate 101. In the step of forming the contact hole 165, the depth of the contact hole 165 in the first substrate 101 may be variously controlled according to the etching amount of the first substrate 101. The depth of the contact hole 165 in the first substrate 101 may be equal to the depth of the channel hole 115 in the first substrate 101, or may be shallower or deeper than the depth of the channel hole 115 in the first substrate 101.

[0105] Subsequently, a vertical contact plug 167 may be formed by filling the contact hole 165 with a conductive material.

[0106] Reference Fig.12F , a third insulating layer 171 may be formed on the second insulating layer 163. The third insulating layer 171 may extend to cover the vertical contact plug 167. Subsequently, a contact plug 173A and a contact plug 173B penetrating the third insulating layer 171 or penetrating the third insulating layer 171 and the second insulating layer 163 may be formed.

[0107] The contact plug 173A and the contact plug 173B may include a first contact plug 173A extending to contact the channel structure 147A and a second contact plug 173B extending to contact the vertical contact plug 167 .

[0108] Subsequently, first line arrays 175A and 175B may be formed. The first line arrays 175A and 175B may include bit lines 175A connected to first contact plugs 173A and connection lines 175B connected to second contact plugs 173B. Subsequently, a first insulating structure 181 covering the first line arrays 175A and 175B may be formed.

[0109] The first insulating structure 181 may include two or more insulating layers 181A to 181D. The first connection structure 190 may be embedded in the first insulating structure 181. Each of the first connection structures 190 may include a plurality of conductive patterns 183, 185, 187, 189, 191, and 193. The first insulating structure 181 and the first connection structure 190 are not limited to the examples shown in the drawings, and various modifications may be made.

[0110] Some of the first connection structures 190 may be connected to the vertical contact plugs 167. Other first connection structures 190 may be connected to the memory cell array. The conductive patterns 183, 185, 187, 189, 191, and 193 included in each of the first connection structures 190 may include a first bonding metal 193 having a surface exposed to the outside of the first insulating structure 181.

[0111] Fig.13 It is shown Fig.11 A cross-sectional view of an embodiment of step S2A is shown.

[0112] Reference Fig.13 Step S2A may include forming a plurality of transistors 200 constituting a complementary metal oxide semiconductor (CMOS) circuit on a second substrate 201 including a first region R1 and a second region R2. In one embodiment, the CMOS circuit may include two or more transistors 200.

[0113] The second substrate 201 may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial film formed by a selective epitaxial growth process.

[0114] Each transistor 200 may be formed on an active region of the second substrate 201 divided by the isolation layer 203. Each transistor 200 may include: a gate insulating layer 207 and a gate 209, the gate insulating layer 207 and the gate 209 being stacked on the active region corresponding thereto; and junctions 205a and 205b, the junctions 205a and 205b being formed in the active region on both sides of the gate 209. The junctions 205a and 205b may include a conductive type dopant for realizing the transistor corresponding thereto. The junctions 205a and 205b may include any one of an n-type dopant and a p-type dopant.

[0115] Step S2A may include the steps of forming a second connection structure 220 connected to the transistor 200 constituting the CMOS circuit and a second insulation structure 211 covering the second connection structure 220 and the transistor 200 .

[0116] The second insulating structure 211 may include two or more insulating layers 211A to 211D. The second connection structure 220 may be embedded in the second insulating structure 211. Each second connection structure 220 may include a plurality of conductive patterns 213, 215, 217, 219, 221, and 223. The second insulating structure 211 and the second connection structure 220 are not limited to the examples shown in the drawings, and various modifications may be made.

[0117] Some of the second connection structures 220 may be connected to the discharge transistor 200d of the transistors 200. The conductive patterns 213, 215, 217, 219, 221, and 223 included in each of the second connection structures 220 may include a second bonding metal 223 having a surface exposed to the outside of the second insulation structure 211.

[0118] Fig.14 It is shown Fig.11 A cross-sectional view of an embodiment of step S3 is shown.

[0119] Reference Fig.14 , step S3 may include the step of aligning the first substrate 101 and the second substrate 201 so that the first bonding metal 193 on the first substrate 101 and the second bonding metal 223 on the second substrate 201 contact each other. The first substrate 101 and the second substrate 201 may be aligned so that the unit region Ra of the first substrate 101 overlaps with the first region R1 of the second substrate 201, and the interconnection region Rb of the first substrate 101 overlaps with the second region R2 of the second substrate 201. The first bonding metal 193 and the second bonding metal 223 may include various metals. For example, the first bonding metal 193 and the second bonding metal 223 may include copper.

[0120] Step S3 may include a step of attaching the first bonding metal 193 and the second bonding metal 223 to each other. To this end, the first bonding metal 193 and the second bonding metal 223 may be cured after heat is applied to the first bonding metal 193 and the second bonding metal 223. However, the present disclosure is not limited thereto, and various processes for connecting the first bonding metal 193 and the second bonding metal 223 may be introduced.

[0121] Through the above-described processes, the vertical contact plug 167 may be connected to the discharge transistor 200 d via the second contact plug 173B, the connection wire 175B, the first connection structure 190 , and the second connection structure 220 .

[0122] Fig.15 It is shown Fig.11 A cross-sectional view of an embodiment of step S5 is shown.

[0123] Reference Fig.15 , you can remove Fig.14 The first substrate 101 is shown. When the first substrate 101 is removed, the memory layer 137 may be used as an etch stop layer. Therefore, the channel layer 141A protruding more than the gate stack structure 150 may be protected by the memory layer 137. When the first substrate 101 is removed, the end of the vertical contact plug 167 penetrating the dummy stack structure 110 may be exposed.

[0124] Fig.16 It is shown Fig.11 A cross-sectional view of an embodiment of step S7 is shown.

[0125] Reference Fig.16 , the conductive type dopant 301 may be implanted into an end portion of the channel layer 141A that protrudes more than the gate stack structure 150. The conductive type dopant 301 may include an n-type dopant for junction. The conductive type dopant 301 may include a p-type dopant for reverse doping.

[0126] The conductive type dopant 301 may be implanted in a state where an end portion of the channel layer 141A is covered by at least one of the blocking insulating layer 135, the data storage layer 133, and the tunnel insulating layer 131. In one embodiment, before the conductive type dopant 301 is implanted, the tunnel insulating layer 131 may be exposed by removing portions of the blocking insulating layer 135 and the data storage layer 133 covering the end portion of the channel layer 141A. Subsequently, the conductive type dopant 301 may be implanted in a state where an end portion of the channel layer 141A is covered by the tunnel insulating layer 131.

[0127] Fig.17 It is shown Fig.11 A cross-sectional view of an embodiment of step S7 is shown.

[0128] In the following, reference will be made to Fig.16 A reference numeral describing a channel layer of the conductive type dopant 301 is defined as “ 141B”, and a reference numeral representing a channel structure including the conductive type dopant 301 is defined as “ 147B”.

[0129] Reference Fig.17 , a portion of the tunnel insulating layer 131 protrudes further than the gate stack structure 150. Therefore, an end portion of the channel structure 147B and an end portion of the channel layer 141B that protrude further than the gate stack structure 150 may be exposed.

[0130] 18A to 18C It is shown Fig.11 4 is a cross-sectional view of an embodiment of step S11 shown.

[0131] Reference Fig.18A The step S11 may include the steps of forming a conductive layer 303 to contact the exposed end of the channel structure 147B and forming a second mask pattern 305 on the conductive layer 303 . The layout of the common source line may be defined by the second mask pattern 305 .

[0132] In one embodiment, the conductive layer 303 may include Figure 2 , Figure 4 , Figure 5 and Figure 6 Each of the common source lines CSL shown in FIG. Figure 7 The common source line CSLb shown in FIG. Figure 8 The metal of the common source line CSLc shown in .

[0133] In another embodiment, the conductive layer 303 may include a reference Fig. 9 and Fig.10 The source-side doped semiconductor layer SE and the metal layer MT arranged on the surface of the source-side doped semiconductor layer SE are described.

[0134] Reference Fig.18B , you can use the reference Fig.18A The second mask pattern 305 is described as an etching barrier layer and is etched by the etching process. Fig.18A Thus, a common source line 303P is formed, which covers an end of the channel structure 147B that protrudes more than the gate stack structure 150 and extends to contact the vertical contact plug 167. The common source line 303P may overlap the gate stack structure 150 and the dummy stack structure 110.

[0135] Reference Fig. 18C , a protective insulating layer 307 covering the common source line 303P may be formed.

[0136] Fig.19 11 is a block diagram showing a configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0137] Reference Fig.19 , a memory system 1100 according to an embodiment of the present disclosure includes a memory device 1120 and a memory controller 1110 .

[0138] The memory device 1120 may be a multi-chip package configured with a plurality of flash memory chips. The memory device 1120 may include a reference Figures 1 to 10 At least one of the semiconductor memory devices described. For example, the memory device 1120 may include a channel structure that protrudes further toward the common source line than the gate stack structure.

[0139] The memory controller 1110 is configured to control the memory device 1120, and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 is used as a working memory of the CPU 1112, the CPU 1112 performs an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 includes a data exchange protocol for a host connected to the memory system 1100. The error correction block 1114 detects and corrects errors included in data read from the memory device 1120, and the memory interface 1115 interfaces with the memory device 1120. In addition, the memory controller 1110 may further include a ROM or the like for storing code data for interfacing with the host.

[0140] The memory system 1100 configured as described above may be a memory card or a solid state drive (SSD) in which the memory device 1120 is combined with the memory controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1110 may communicate with the outside (e.g., a host) through one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA (SATA) protocol, a parallel ATA (PATA) protocol, a small computer mini interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol.

[0141] Fig. 20 1 is a block diagram showing a configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0142] Reference Fig. 20 The computing system 1200 according to one embodiment of the present disclosure may include a CPU 1220 electrically connected to a system bus 1260, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210. When the computing system 1200 is a mobile device, a battery for providing an operating voltage to the computing system 1200 may also be included, and an application chipset, a camera image processor (CIS), a mobile D-RAM, and the like may also be included.

[0143] According to the present disclosure, the substrate is removed so that the channel structure can be exposed. In addition, a connection structure can be formed between the channel structure and the common source line.

[0144] According to the present disclosure, defects occurring in a process of connecting a channel structure and a common source line may be prevented, and it may be checked whether the channel structure and the common source line are connected to each other.

[0145] CROSS-REFERENCE TO RELATED APPLICATIONS

[0146] This application claims the priority of Korean Patent Application No. 10-2019-0094305 filed on August 2, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A substrate having a complementary metal oxide semiconductor (CMOS) circuit; A gate stack structure, the gate stack structure comprising an interlayer insulating layer and a conductive pattern, wherein the interlayer insulating layer and the conductive pattern are alternately stacked above the substrate in a vertical direction; a channel structure having a first portion penetrating the gate stack structure and a second portion extending from one end of the first portion, the second portion extending beyond the gate stack structure; a common source line extending to overlap the gate stack structure, the common source line surrounding the second portion of the channel structure, wherein the common source line includes a first surface facing the gate stack structure and a second surface opposite to the first surface; an insulating layer, the insulating layer directly contacting the second surface of the common source line; a memory layer disposed between the first portion of the channel structure and the gate stack structure; and a bit line connected to the other end of the first portion of the channel structure, the bit line being disposed between the substrate and the gate stack structure, The bit line, the gate stack structure and the transistor of the CMOS circuit are not arranged above the second surface of the common source line.

2. The semiconductor memory device according to claim 1, wherein The channel structure includes a core insulating layer and a channel layer, the core insulating layer being disposed in a central region of the channel structure and the channel layer forming outermost portions of the first portion and the second portion of the channel structure.

3. The semiconductor memory device according to claim 2, wherein: The core insulating layer includes an end portion disposed at a height between a height of the first surface and a height of the second surface of the common source line.

4. The semiconductor memory device according to claim 2, wherein: The channel layer has a hollow structure.

5. The semiconductor memory device according to claim 2, wherein: The channel structure further includes a doped semiconductor layer disposed between the core insulating layer and the bit line, and The channel layer is extended to be disposed between the core insulating layer and the memory layer, between the common source line and the core insulating layer, and between the doped semiconductor layer and the memory layer.

6. The semiconductor memory device according to claim 5, wherein: A portion of the channel layer adjacent to the common source line includes a conductive type dopant.

7. The semiconductor memory device according to claim 1, wherein: A diameter of the channel structure at a portion of the gate stack structure adjacent to the common source line is smaller than a diameter of the channel structure at a remaining portion of the gate stack structure.

8. The semiconductor memory device according to claim 1, wherein: The second portion of the channel structure has a convex shape extending from the first portion of the channel structure and extending into a concave portion of the common source line.

9. The semiconductor memory device according to claim 1, wherein: The common source line includes metal.

10. The semiconductor memory device according to claim 1, wherein The common source line comprises: a doped semiconductor layer directly contacting the second portion of the channel structure; and A metal layer is disposed above a surface of the doped semiconductor layer, the metal layer being connected to the channel structure via the doped semiconductor layer.

11. The semiconductor memory device according to claim 1, wherein: The memory layer is formed to be shorter than the channel structure in the vertical direction.

12. The semiconductor memory device according to claim 1, further comprising: a dummy stack structure, the dummy stack structure and the gate stack structure being disposed at substantially the same height; a conductive vertical contact plug, the conductive vertical contact plug penetrating the dummy stack structure; as well as A conductive connection line is connected to the conductive vertical contact plug, the conductive connection line and the bit line are disposed at substantially the same height.

13. The semiconductor memory device according to claim 12, further comprising: an insulating structure extending from between the substrate and the bit line to between the conductive connection line and the substrate; as well as A conductive connection structure penetrates the insulating structure, and the conductive connection structure connects the conductive connection line to the CMOS circuit.

14. The semiconductor memory device according to claim 12, wherein: The common source line extends to be connected to the conductive vertical contact plug.

15. A method for manufacturing a semiconductor memory device, the method comprising the steps of: A memory cell array is formed above a first substrate, wherein the memory cell array comprises: a gate stack structure, the gate stack structure comprising an interlayer insulating layer and a conductive pattern, the interlayer insulating layer and the conductive pattern being alternately stacked in a vertical direction; a channel structure, the channel structure penetrating the gate stack structure, an end of the channel structure extending to the inside of the first substrate; and a memory layer, the memory layer extending from between the channel structure and the gate stack structure to between the end of the channel structure and the first substrate; forming bit lines connected to the memory cell array; forming a first connection structure on the bit line; forming a complementary metal oxide semiconductor (CMOS) circuit including transistors over the second substrate; forming a second connection structure connected to the CMOS circuit; attaching the first connecting structure to the second connecting structure; removing the first substrate to expose the memory layer; removing a portion of the memory layer so that the end of the channel structure is exposed; forming a common source line surrounding the end of the channel structure, the common source line extending to overlap the gate stack structure, wherein the common source line includes a first surface facing the gate stack structure and a second surface opposite to the first surface; and forming an insulating layer directly contacting the second surface of the common source line, The bit line, the gate stack structure and the transistor of the CMOS circuit are arranged between the second substrate and the common source line, and are not arranged above the second surface of the common source line.

16. The method according to claim 15, wherein: The step of forming the memory cell array comprises the following steps: Alternatingly stacking first material layers and second material layers on the first substrate; forming a channel hole penetrating the first material layer and the second material layer, wherein the channel hole extends to the interior of the first substrate; forming the memory layer on a surface of the channel hole; and A channel layer is formed on a surface of the memory layer.

17. The method according to claim 16, wherein: The step of forming the memory cell array further comprises the following steps: forming a slit penetrating the first material layer and the second material layer; and replacing the second material layer with a third material layer through the slit, Wherein, the first material layer is the interlayer insulating layer, The second material layer is a sacrificial layer having an etching rate different from that of the interlayer insulating layer. wherein the third material layer is the conductive pattern, wherein the first substrate includes a cell region and an interconnection region, and Wherein, the step of replacing the second material layer with the third material layer is performed so that a portion of the second material layer disposed above the unit area of ​​the first substrate is replaced by the third material layer, and a portion of the second material layer disposed above the interconnection area of ​​the first substrate is retained as a virtual stacking structure.

18. The method according to claim 17, further comprising the steps of: forming a conductive vertical contact plug penetrating the dummy stack structure remaining on the interconnection region of the first substrate, The end of the conductive vertical contact plug is exposed by removing the first substrate.

19. The method according to claim 18, wherein: The common source line extends to be connected to the end portion of the conductive vertical contact plug.

20. The method according to claim 15, further comprising the steps of: Before forming the common source line, a conductive type dopant is implanted into the end portion of the channel structure.

21. The method according to claim 15, wherein: The channel structure includes a core insulating layer and a channel layer, the core insulating layer is disposed in a central region of the channel structure, and the channel layer forms an outermost portion of the channel structure.

22. The method according to claim 21, wherein: The core insulating layer includes an end portion disposed at a height between a height of the first surface and a height of the second surface of the common source line.

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