Semiconductor packaging structure and forming method thereof

Abstract

Various embodiments of the present disclosure are directed to a semiconductor package structure including a first integrated circuit (IC) chip overlying a substrate structure. An electrical IC chip is over the substrate structure and disposed around the first IC chip. The electrical IC chip is electrically coupled to the first IC chip. A photonic IC chip overlies the substrate structure and is electrically coupled to the electrical IC chip. The photonic IC chip is configured to receive an input optical signal. The photonic IC chip is adjacent to the electrical IC chip. The embodiment of the invention also relates to a semiconductor packaging structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor package structure and a method for forming the same. Background Art

[0002] A system in a package (SiP) may include multiple integrated circuit (IC) chips packaged together. The IC chips implement the functional blocks of the SiP. To facilitate high frequencies and / or high data rates, the SiP includes an electrical IC chip integrated with a photonic IC chip. In addition, the integration of the electrical IC chip and the photonic IC chip may reduce energy losses, increase the overall performance of the SiP, and allow for smaller components. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor packaging structure, including: a first integrated circuit (IC) chip, located on a substrate structure; an electrical integrated circuit chip, located on the substrate structure and arranged around the first integrated circuit chip, wherein the electrical integrated circuit chip is electrically coupled to the first integrated circuit chip; and a photonic integrated circuit chip, located on the substrate structure and electrically coupled to the electrical integrated circuit chip, wherein the photonic integrated circuit chip is configured to receive an input optical signal, wherein the photonic integrated circuit chip is adjacent to the electrical integrated circuit chip.

[0004] Other embodiments of the present application provide a semiconductor packaging structure, including: an interposer located on a packaging substrate; one or more electrical integrated circuit (IC) chips located on the interposer and coupled to the interposer; a first integrated circuit chip located on the interposer and coupled to the one or more electrical integrated circuit chips, wherein the first integrated circuit chip is laterally spaced between relative side walls of the one or more electrical integrated circuit chips; and a plurality of photonic integrated circuit chips located on the interposer and electrically coupled to the one or more electrical integrated circuit chips, wherein the plurality of photonic integrated circuit chips are arranged at a peripheral area of ​​the interposer and surround the first integrated circuit chip, wherein a lateral distance between each of the plurality of photonic integrated circuit chips and the one or more electrical integrated circuit chips is less than a width of an independent photonic integrated circuit chip among the plurality of photonic integrated circuit chips.

[0005] Still other embodiments of the present application provide a method for forming a semiconductor packaging structure, comprising: bonding one or more electrical integrated circuit (IC) chips to an interposer; bonding a memory integrated circuit chip to the interposer, wherein the memory integrated circuit chip is spaced apart between side walls of the one or more electrical integrated circuit chips; and bonding a plurality of photonic integrated circuit chips to the interposer, wherein the plurality of photonic integrated circuit chips are configured to receive an input optical signal and generate an electrical signal corresponding to the input optical signal, wherein the photonic integrated circuit chip is disposed adjacent to the one or more electrical integrated circuit chips, wherein the one or more electrical integrated circuit chips are configured to receive the generated electrical signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 Cross-sectional views of some embodiments of semiconductor package structures including a photonic integrated circuit (IC) chip directly adjacent to an electrical IC chip are shown.

[0008] Figure 2 Cross-sectional views of some embodiments of semiconductor package structures including a photonic IC chip directly above an electrical IC chip are shown.

[0009] Figure 3A Shows Figure 1 Cross-sectional views of some other embodiments of semiconductor package structures.

[0010] Figure 3B and Figure 3C Shows Figure 3A Various top views of some embodiments of semiconductor package structures.

[0011] Figure 4A Shows Figure 2 Cross-sectional views of some other embodiments of semiconductor package structures.

[0012] Figure 4B and Figure 4C Shows Figure 4A Various top views of some embodiments of semiconductor package structures.

[0013] Figure 5A Shows Figure 3A Cross-sectional views of some other embodiments of semiconductor package structures.

[0014] Figure 5B and Figure 5C Shows Figure 5A Various top views of some embodiments of semiconductor package structures.

[0015] Fig. 6A Shows Figure 4A Cross-sectional views of some other embodiments of semiconductor package structures.

[0016] Figure 6B and Figure 6C Shows Fig. 6A Various top views of some embodiments of semiconductor package structures.

[0017] 7A to 7E Various cross-sectional views of some embodiments of semiconductor package structures including heat dissipation structures located above multiple IC chips are shown.

[0018] FIG. 8A to FIG. 8E Various cross-sectional views of some embodiments of a semiconductor package structure including a heat dissipation structure located above a plurality of IC chips are shown, wherein the heat dissipation structure includes a heat sink structure located above a liquid cooling structure.

[0019] Figures 9 to 17 Cross-sectional views of some embodiments of methods for forming a semiconductor package structure including a photonic IC chip directly adjacent to an electrical IC chip are shown.

[0020] Fig.18 A flow chart illustrating some embodiments of a method of forming a semiconductor package structure including a photonic IC chip directly adjacent to an electrical IC chip. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0023] A system in a package (SiP) with a chiplet design may include multiple integrated circuit (IC) chiplets packaged together. For example, a SiP may include a memory IC chiplet, an electrical IC chiplet (e.g., including one or more processors, such as a graphics processing unit (GPU), a central processing unit (CPU), etc.), and a photonic IC chiplet packaged together on a packaging substrate. The IC chiplets implement the functional blocks of the SiP and communicate electrically with each other. The photonic IC chiplets utilize optical signals to provide high-speed signal communication. The use of optical signals provides lower power consumption and generates less heat than electrical signals. Therefore, the SiP can operate at high frequencies and / or high data rates with reduced heat and reduced transmission losses.

[0024] The photonic IC chiplet is configured to generate and / or detect optical signals and convert the optical signals into electrical signals (or vice versa), which are then provided to the electrical IC chiplet. The SiP includes an interposer above the packaging substrate, which facilitates electrical connections between the electrical IC chiplet and the photonic IC chiplet through a conductive interconnect structure. The IC chiplet is located above the interposer. In order to promote the high processing performance of the electrical IC chiplet, the memory IC chiplet is arranged to be directly adjacent to the electrical IC chiplet. For example, one or more memory IC chiplets may laterally surround the electrical IC chiplet and be directly adjacent to the electrical IC chiplet laterally. This reduces the distance that the electrical signal propagates between the memory IC chiplet and the electrical IC chiplet, thereby increasing the transmission efficiency and speed between the two IC chiplets. One or more photonic IC chiplets are spaced apart at the corners of the electrical IC chiplet, and / or the memory IC chiplets are spaced apart laterally between the photonic IC chiplet and the electrical IC chiplet. However, this increases the distance that the electrical signal propagates between the photonic IC chiplet and the electrical IC chiplet. The increased distance increases the number and / or size of conductive interconnect structures disposed in the interposer and / or the individual IC chiplets to carry the electrical signals. In addition, the electrical signals utilize high power to propagate over large distances (e.g., due to losses in the conductive interconnect structures). As a result, power consumption, heat generation, and delays are increased, thereby reducing the transmission efficiency and overall performance of the SiP.

[0025] In another example, the photonic IC chiplet is laterally spaced between the electrical IC chiplet and the memory IC chiplet. This increases the transmission efficiency between the electrical IC chiplet and the photonic IC chiplet, but reduces the processing performance of the electrical IC chiplet (e.g., because the latency in accessing data from the memory IC chiplet is increased). In addition, in such an example, an optical signal is transmitted to the photonic IC chiplet and / or received by the photonic IC chiplet (e.g., via a grating coupler) at the upper surface of the photonic IC chiplet. However, the grating coupler is wavelength sensitive and may reduce optical coupling. In addition, the transmission and / or reception of optical signals in the vertical direction reduces the ability to integrate a heat dissipation structure above the SiP, thereby reducing the overall performance and reliability of the SiP.

[0026] Various embodiments of the present disclosure are directed to a semiconductor package structure having a photonic IC chip directly adjacent to an electrical IC chip. The semiconductor package structure includes an interposer located above a package substrate. The memory IC chip and the electrical IC chip are located above the interposer and are electrically coupled to each other. The memory IC chip is spaced apart between the sidewalls of the electrical IC chip. The photonic IC chip is located above the interposer and is directly adjacent to the electrical IC chip. In an embodiment, the photonic IC chip is directly adjacent to the electrical IC chip laterally. In another embodiment, the photonic IC chip is directly located above the electrical IC chip. Therefore, the distance that the electrical signal propagates between the photonic IC chip and the electrical IC chip is reduced, thereby increasing the transmission efficiency. In addition, the photonic IC chip is disposed at a peripheral region of the interposer and includes an input / output (I / O) coupler (e.g., an edge coupler) configured to receive an optical signal on at least one side of the photonic IC chip. This facilitates the transmission and / or reception of optical signals in the horizontal direction, so that a heat sink can be disposed above the memory IC chip and / or the electrical IC chip. Therefore, high heat generated during operation of the semiconductor package structure can be effectively dissipated from the IC chip, thereby increasing the overall performance and reliability of the semiconductor package structure.

[0027] Figure 1 A cross-sectional view 100 of some embodiments of a semiconductor package structure including a photonic integrated circuit (IC) chip 106 directly adjacent to an electrical IC chip 108 is shown.

[0028] The semiconductor package structure includes a base structure 102. The base structure 102 includes an interposer 103 located above a package substrate 101. In some embodiments, the semiconductor package structure further includes a plurality of IC chips 106, 108, 110, the IC chips 106, 108, 110 including a photonic IC chip 106, an electrical IC chip 108, and a memory IC chip 110 located above the base structure 102. Each of the photonic IC chip 106, the electrical IC chip 108, and the memory IC chip 110 is configured to implement one or more independent functional blocks of the semiconductor package structure. In some embodiments, each of the IC chips 106, 108, 110 can be referred to as an IC chiplet. In some embodiments, the IC chips 106, 108, 110 of the semiconductor package structure are arranged in a 2.5D structure, wherein each of the IC chips 106, 108, 110 is arranged at the same height and / or has a bottom surface coplanar with each other.

[0029] The photonic IC chip 106, the electrical IC chip 108, and the memory IC chip 110 are coupled (e.g., electrically coupled) together through an electrical input / output (I / O) structure (not shown) on the interposer 103. The interposer 103 includes conductive interconnect wiring, through-substrate vias (TSVs), contact pads, etc. (not shown) configured to integrate the photonic IC chip 106, the electrical IC chip 108, and the memory IC chip 110 together. The photonic IC chip 106 is disposed at the periphery of the interposer 103, and each includes an optical I / O structure 112 disposed at an outer edge of the photonic IC chip 106. The optical I / O structure 112 is configured to facilitate receiving optical signals from and / or transmitting optical signals to the optical fiber structure 114. In some embodiments, the optical fiber structure 114 is coupled to a light source (not shown), which is configured to transmit optical signals to the photonic IC chip 106. In yet further embodiments, the optical fiber structure 114 is coupled to an optical receiver circuit (not shown) configured to receive an optical signal from the optical I / O structure 112 of the photonic IC chip 106. In various embodiments, the photonic IC chip 106 further includes structures or devices (not shown) that can generate optical signals, detect optical signals, modify optical signals, transmit optical signals, and / or convert optical signals into electrical signals (or vice versa). For example, the photonic IC chip 106 may include waveguides, photodetectors, lasers, optical modulators, other photonic devices, or any combination of the foregoing.

[0030] In some embodiments, each of the electrical IC chips 108 is configured as a system-on-chip (SoC) chip and includes an electrical integrated circuit (EIC) 104 and a functional IC 105. In various embodiments, the EIC 104 and the functional IC 105 may be or include one or more chiplets on the SoC, wherein the SoC has a chiplet design. The EIC 104 is electrically coupled to the photonic IC chip 106 through the interposer 103. In various embodiments, the EIC 104 is configured to receive an electrical signal from the photonic IC chip 106, the electrical signal corresponding to the optical signal received from the optical fiber structure 114. In further embodiments, the EIC 104 is configured to perform signal processing (e.g., amplification, filtering, etc.) on the electrical signal from the photonic IC chip 106, and provide the output electrical signal to the functional IC 105 for further processing. Therefore, the EIC 104 provides an electrical interface between the functional IC 105 and the photonic IC chip 106, and the photonic IC chip 106 provides an electrical interface between the EIC 104 and the optical fiber structure 114. The functional IC 105 may be, for example, or include a switch chip, an application specific integrated circuit (ASIC), a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), etc. The functional IC 105 is configured to receive an output electrical signal from the EIC 104. By embedding the EIC 104 and the functional IC 105 on the same chip (i.e., on the electrical IC chip 108), the transmission loss of the output electrical signal is reduced, thereby increasing the transmission efficiency.

[0031] The memory IC chip 110 is arranged to be directly adjacent to the electrical IC chip 108. In some embodiments, the memory IC chip 110 is electrically coupled to the electrical IC chip 108 through the interposer 103. In some embodiments, the memory IC chip 110 includes a memory controller circuit and one or more high-bandwidth memory layers. The memory IC chip 110 is configured to provide data to the functional IC 105 and / or store data from the functional IC 105. The memory IC chip 110 is arranged to be directly adjacent to the electrical IC chip 108 to increase the transmission efficiency between the memory IC chip 110 and the electrical IC chip 108. Therefore, the speed at which the electrical IC chip 108 (e.g., IC chip) can process stored data and / or write data is increased. For example, when the functional IC 105 is or includes a GPU, the increased transmission efficiency between the memory IC chip 110 and the electrical IC chip 108 increases the number of floating-point operations performed by the GPU per second.

[0032] Since the photonic IC chip 106 is arranged to be directly adjacent to the electrical IC chip 108 laterally, the distance that the electrical signal propagates between the photonic IC chip 106 and the electrical IC chip 108 is reduced. This is conducive to reducing the number of conductive wiring structures in the interposer 103, reducing power consumption, and reducing transmission losses, thereby increasing the transmission efficiency between the photonic IC chip 106 and the electrical IC chip 108. In addition, the IC chips 106, 108, and 110 are arranged at the same height (i.e., a semiconductor package structure with a 2.5D structure), which reduces the overall height of the semiconductor package structure. Therefore, the size of the semiconductor package structure can be reduced.

[0033] Figure 2 Shows Figure 1 200 of some optional embodiments of a semiconductor package structure, wherein the photonic IC chip 106 is directly located on the corresponding electrical IC chip 108. The photonic IC chip 106 is directly located on at least a portion of the EIC 104 of the electrical IC chip 108. In an embodiment, the photonic IC chip 106 can be directly electrically coupled to the EIC 104 through a plurality of solder balls or a plurality of solder microbumps disposed between the photonic IC chip 106 and the electrical IC chip 108. In another embodiment, the photonic IC chip 106 and the electrical IC chip 108 each include a hybrid bonding structure that facilitates electrical coupling between the photonic IC chip 106 and the electrical IC chip 108.

[0034] In some embodiments, placing the photonic IC chip 106 directly on the electrical IC chip 108 further reduces the distance that the electrical signal propagates between the photonic IC chip 106 and the electrical IC chip 108. Therefore, the transmission efficiency is further improved, and the power consumption of the semiconductor package structure is reduced. In addition, the number of conductive interconnect structures in the interposer 103 is reduced, thereby reducing the design complexity and / or lateral footprint of the semiconductor package structure.

[0035] Figure 3A Shows Figure 1 FIG. 3 is a cross-sectional view 300 a of some other embodiments of a semiconductor package structure.

[0036] The semiconductor package structure includes a plurality of IC chips 106, 108, 110 disposed above a base structure 102. The base structure 102 includes an interposer 103 located above a package substrate 101. In some embodiments, the package substrate 101 is or includes a printed circuit board (PCB) substrate or some other suitable substrate. The interposer 103 includes an interposer structure 308, a plurality of through-substrate vias (TSVs) 310, a plurality of conductive interconnect structures 312, 314, and a plurality of contact pads 315. In various embodiments, the interposer structure 308 includes a substrate (e.g., a silicon substrate) and a dielectric structure, wherein the TSVs 310 are disposed in the substrate, and the plurality of conductive interconnect structures 312, 314 and the contact pads 315 are disposed in the dielectric structure. The conductive components of the interposer 103 are configured to electrically couple the IC chips 106, 108, 110 to each other and to the package substrate 101. A plurality of first solder bumps 306 are disposed between the interposer 103 and the package substrate 101. The first solder bumps 306 facilitate bonding and electrical coupling between the interposer 103 and the package substrate 101. In further embodiments, the interposer 103 may be electrically coupled to the package substrate 101 via wire bonding (not shown).

[0037] A plurality of IC chips 106, 108, 110 are located on the interposer 103. A plurality of second solder bumps 316 are disposed between the interposer 103 and the plurality of IC chips 106, 108, 110. The second solder bumps 316 facilitate bonding and electrical coupling between the interposer 103 and the plurality of IC chips 106, 108, 110. In various embodiments, the second solder bumps 316 may be omitted (not shown), and the bonding pads of the plurality of IC chips 106, 108, 110 may be directly bonded to the contact pads 315 of the interposer 103. Thus, the interposer 103 is configured to integrate the IC chips 106, 108, 110 together.

[0038] The plurality of IC chips 106, 108, 110 include one or more photonic IC chips 106, one or more electrical IC chips 108, and one or more memory IC chips 110. In various embodiments, the semiconductor package structure has a 2.5D design, wherein the IC chips 106, 108, 110 are placed side by side, and are disposed at the same height, and are disposed along the same plane above the interposer 103. In such an embodiment, the bottom surfaces of the IC chips 106, 108, 110 are substantially aligned with each other. In yet further embodiments, the bottom surfaces of the IC chips 106, 108, 110 are each coplanar or substantially coplanar with each other.

[0039] In some embodiments, one or more memory IC chips 110 are or include multiple memory layers 322 stacked vertically with memory controller circuit 320. Multiple memory layers 322 may be, for example, or include high bandwidth memory, which may be read from and / or written to the high bandwidth memory by the IC chip 108 in conjunction with the memory controller circuit 320. The memory controller circuit 320 includes circuits (e.g., transistors, etc.) configured to read from and / or write to multiple memory layers 322. In some embodiments, the memory layer 322 includes one or more high bandwidth memories (HBM), static random access memories (SRAM), dynamic random access memories (DRAM), non-volatile memories (NVM), three-dimensional (3D) memories, computing in memory (CIM), some other suitable memories, or any combination of the foregoing. For example, the memory layer 322 includes multiple memory devices, which may be or include transistors, resistive random access memory (RRAM) cells, phase change memory (PCM) cells, magnetoresistive random access memory (MRAM) cells, some other suitable semiconductor devices, or any combination of the foregoing. In various embodiments, the electrical IC chip 108 is configured to send control signals and / or data to the memory controller circuit 320, and the memory controller circuit 320 is configured to write data to the memory layer 322 and / or read data from the memory layer 322 based on the control signals and / or data provided by the electrical IC chip 108. In some embodiments, the memory controller circuit 320 is configured to provide the stored data to the electrical IC chip 108 based at least in part on the control signals.

[0040] In some embodiments, one or more electrical IC chips 108 are configured as a system-on-chip (SoC) chip and include an electrical integrated circuit (EIC) 104 and a functional IC 105. The electrical IC chip 108 is electrically coupled to the photonic IC chip 106 through the interposer 103. The EIC 104 is laterally spaced between the corresponding photonic IC chip 106 and the functional IC 105, thereby increasing the transmission efficiency between the EIC 104 and the photonic IC chip 106. In some embodiments, the EIC 104 includes: circuits, including amplifier circuits, driver circuits, control circuits, digital processing circuits, etc. The EIC 104 is configured to receive electrical signals from the photonic IC chip 106, and the electrical signals correspond to the received optical signals. In addition, the EIC 104 includes circuits or other structures to generate electrical signals to control and / or provide power to components of the photonic IC chip 106.

[0041] Functional IC 105 may be, for example, or include one or more of a switch chip, an ASIC, a CPU, a GPU, a DPU, and the like. Functional IC 105 is configured to receive an output electrical signal from EIC 104, the output electrical signal corresponding to the received optical signal at photonic IC chip 106. In various embodiments, functional IC 105 is or includes one or more of a digital circuit, an analog circuit, a mixed signal circuit, and the like. In some embodiments, the circuits of functional IC 105 include complementary metal oxide semiconductor (CMOS) transistors, planar CMOS transistors, fin field effect transistors (FinFETs), gate-all-around (GAA) transistors, nanosheet transistors, two-dimensional (2D) semiconductor materials, some other electronic devices, or any combination of the foregoing. In various embodiments, functional IC 105 includes one or more processor circuits configured to perform operations on output electrical signals from EIC 104 and / or stored data from memory IC chip 110. In some embodiments, the devices of EIC 104 and the devices of functional IC 105 are disposed on the same semiconductor substrate and are electrically coupled to each other through a single interconnect structure. Therefore, transmission losses of electrical signals between the EIC 104 and the functional IC 105 are reduced, thereby increasing the performance of the one or more electrical IC chips 108 .

[0042] The photonic IC chip 106 is disposed at the periphery of the interposer 103. The photonic IC chip 106 includes one or more optical I / O structures 112 and other photonic devices, such as waveguides, photodetectors, light emitting units (e.g., laser diodes, light emitting diodes, etc.), optical modulators, other photonic devices, or any combination of the foregoing. The optical I / O structure 112 is disposed at the outer edge of the photonic IC chip 106 and is configured to receive optical signals from and / or transmit optical signals to the optical fiber structure 114. The housing structure 318 is disposed at the opposite end of the interposer 103. In some embodiments, the housing structure 318 includes an opening aligned with the optical I / O structure 112 and is configured to provide support for the optical fiber structure 114. In some embodiments, the optical fiber structure 114 includes one or more optical fibers that can each be a single-mode or multi-mode optical fiber. In various embodiments, the optical I / O structure 112 can each be or include an edge coupler or some other suitable optical I / O structure. In such an embodiment, the edge coupler may include multiple optical core segments that are polarization independent, so that the edge coupler can receive a wide range of wavelengths, thereby increasing the coupling efficiency between the optical I / O structure 112 and the corresponding optical fiber structure 114.

[0043] The photonic IC chip 106 is configured to provide high-speed signal communication between the semiconductor package structure and external IC devices using optical signals. The use of optical signals provides lower power consumption and generates less heat than communicating with external IC devices via electrical signals. Therefore, the photonic IC chip 106 facilitates the semiconductor package structure to operate at high frequencies and / or high data rates with reduced heat and reduced transmission losses.

[0044] During use of the semiconductor package structure, an optical signal received from an external device (e.g., including a light source) at one end of the optical fiber structure 114 is transmitted to the optical I / O structure 112. In some embodiments, the photonic IC chip 106 includes a waveguide optically coupled to the optical I / O structure 112 and a photodetector optically coupled to the waveguide. The input optical signal propagates from the optical I / O structure 112 through the waveguide to the photodetector. The photodetector is configured to convert the input optical signal from the optical fiber structure 114 into a detected electrical signal, which is provided to the EIC 104. For example, the detected electrical signal from the photodetector can be provided to the circuit (e.g., amplifier circuit) of the EIC 104 through the interconnect structure in the photonic IC chip 106 and the electrical IC chip 108 and the interposer 103. The EIC 104 is configured to receive the detected electrical signal and generate an output electrical signal corresponding to the input optical signal. Then, the EIC 104 provides the output electrical signal to the functional IC 105. In various embodiments, the functional IC 105 is configured to perform processing operations on the output electrical signals, generate control signals from the output electrical signals, etc. Thus, the EIC 104 provides an electrical interface between the functional IC 105 and the photonic IC chip 106 .

[0045] In various embodiments, since the photonic IC chip 106 and the electrical IC chip 108 are disposed at the same height, the photonic devices (e.g., waveguides, photodetectors, etc.) of the photonic IC chip 106 are vertically aligned with the electrical devices (e.g., transistors) of the EIC 104 and / or the electrical devices (e.g., transistors) of the functional IC 105 (i.e., disposed along the same plane as them). In various embodiments, the photonic IC chip 106 and the EIC 104 are disposed on IC chips separated from each other. In such an embodiment, the photonic devices (e.g., waveguides, photodetectors, lasers, optical modulators, optical I / O structures 112, etc.) of the photonic IC chip 106 are disposed on a first substrate, and the electrical devices (e.g., transistors) of the EIC 104 are disposed on a second substrate that is different from and / or separated from the first substrate.

[0046] In addition, during use of the semiconductor package structure, the EIC 104 can provide control and / or power signals (e.g., through a driver circuit) to the light emitting unit and / or optical modulator on the photonic IC chip 106. The photonic IC chip 106 is configured to generate an output optical signal based on the control and / or power signal provided by the EIC 104. For example, the output optical signal is generated by the light emitting unit of the photonic IC chip 106 and propagates across the waveguide to the optical I / O structure 112. In various embodiments, the optical modulator disposed in the photonic IC chip 106 is configured to modulate the output optical signal according to the control and / or power signal from the EIC 104. The optical I / O structure 112 provides the output optical signal to the optical fiber structure 114, and the output optical signal is further transmitted to an external device.

[0047] Each photonic IC chip 106 is directly adjacent to a corresponding electrical IC chip 108. For example, the photonic IC chip 106 is directly adjacent to the electrical IC chip 108 laterally, wherein the lateral distance between the photonic IC chip 106 and the corresponding electrical IC chip 108 is substantially small or zero. In some embodiments, the sidewalls of the photonic IC chip 106 directly contact the sidewalls of the electrical IC chip 108. In another embodiment, the lateral distance between the photonic IC chip 106 and the corresponding electrical IC chip 108 is less than about 0.1% to 5% of the width of the photonic IC chip 106. Since the photonic IC chip 106 is directly adjacent to the electrical IC chip 108 and spaced apart laterally, the distance that the electrical signal propagates between the photonic IC chip 106 and the electrical IC chip 108 is reduced. This simplifies the electrical wiring between the photonic IC chip 106 and the electrical IC chip 108, reduces power consumption, and reduces transmission loss, thereby increasing the transmission efficiency between the photonic IC chip 106 and the electrical IC chip 108, and reducing the power consumption of the semiconductor package structure. Furthermore, the EIC 104 is advantageously spaced between the photonic IC chip 106 and the functional IC 105. This facilitates the EIC 104 to efficiently provide output electrical signals to the functional IC 105 with minimal transmission losses, the output electrical signals corresponding to the input optical signals received at the photonic IC chip 106. Thus, the layout and / or placement of the plurality of IC chips 106, 108, 110 as described above increases the overall performance of the semiconductor package structure.

[0048] In some embodiments, a lateral distance between each photonic IC chip in the plurality of photonic IC chips 106 and the one or more electrical IC chips 108 is less than half the width of the individual photonic IC chips 106. In yet further embodiments, an outer sidewall of each photonic IC chip in the plurality of photonic IC chips 106 is aligned with a corresponding sidewall of the interposer 103.

[0049] Figure 3B Shows Figure 3AA top view 300b of some embodiments of a semiconductor package structure.

[0050] like Figure 3B As shown in , one or more electrical IC chips 108 laterally surround the memory IC chip 110. In some embodiments, the memory IC chip 110 is spaced apart between the opposing side walls of the one or more electrical IC chips 108. In various embodiments, the electrical IC chip 108 is shown as a plurality of separate chips disposed around the outer periphery of the memory IC chip 110. In further embodiments, it should be understood that the electrical IC chip 108 is a single IC chip having an opening in the central region of the single IC chip, wherein the memory IC chip 110 is disposed in the opening. In some embodiments, the housing structure 318 surrounds the outer periphery of the interposer 103 and provides support for the optical fiber structure 114. A plurality of photonic IC chips 106 are disposed around the outer periphery of the one or more electrical IC chips 108. The photonic IC chip 106 is spaced apart directly adjacent to the corresponding EIC 104 of the one or more electrical IC chips 108. In some embodiments, the photonic IC chip 106 is spaced apart between the outer periphery of the one or more electrical IC chips 108 and the outer periphery of the interposer 103.

[0051] The plurality of photonic IC chips 106 include a first photonic IC chip 106a adjacent to a second photonic IC chip 106b. In some embodiments, a first lateral distance 324 between the first photonic IC chip 106a and the second photonic IC chip 106b is greater than a second lateral distance 326 between each of the plurality of photonic IC chips 106 and the one or more electrical IC chips 108. In further embodiments, a lateral distance between the plurality of photonic IC chips 106 and the memory IC chip 110 is greater than the second lateral distance 326. In yet further embodiments, a lateral distance between the memory IC chip 110 and the one or more electrical IC chips 108 is less than the second lateral distance 326.

[0052] Figure 3C Shows Figure 3A 300 c of some other embodiments of a semiconductor package structure, wherein the semiconductor package structure includes a plurality of memory IC chips 110 arranged in an array including columns and rows. The plurality of memory IC chips 110 are spaced apart between opposing sidewalls of the one or more electrical IC chips 108. In various embodiments, a lateral distance between adjacent memory IC chips in the plurality of memory IC chips 110 is greater than a second lateral distance 326 between each photonic IC chip in the plurality of photonic IC chips 106 and the one or more electrical IC chips 108.

[0053] Figure 4A Shows Figure 2400a of some other embodiments of the semiconductor package structure. In some embodiments, Figure 4A The semiconductor package structure may include Figure 3A and therefore, the above aspects of the semiconductor package structure Figure 3A The components and / or reference numerals explained also apply to Figure 4A Semiconductor packaging structure.

[0054] Each photonic IC chip 106 is directly adjacent to a corresponding electrical IC chip 108. For example, the photonic IC chips 106 are respectively directly located above the corresponding electrical IC chips 108. In some embodiments, the semiconductor package structure includes a plurality of third solder bumps 402 disposed along the top surface of the electrical IC chip 108. The third solder bumps 402 are disposed between each photonic IC chip 106 and the electrical IC chip 108 below. The third solder bumps 402 provide electrical coupling between the photonic IC chip 106 and the electrical IC chip 108. In yet further embodiments, the third solder bumps 402 are omitted (not shown), and the bonding structure of the photonic IC chip 106 directly contacts the bonding structure of the electrical IC chip 108. In such an embodiment, the bottom surface of the photonic IC chip 106 directly contacts the top surface of the corresponding electrical IC chip 108. In addition, the photonic IC chips 106 are respectively located above the corresponding EICs 104 of the electrical IC chips 108, so that the photonic IC chips 106 are directly electrically coupled to the EICs 104.

[0055] In some embodiments, placing the photonic IC chip 106 directly on the electrical IC chip 108 further reduces the distance that the electrical signal propagates between the photonic IC chip 106 and the electrical IC chip 108. Therefore, the transmission efficiency is further improved, and the power consumption of the semiconductor package structure is reduced, thereby increasing the overall performance of the semiconductor package structure. In some embodiments, the photonic IC chip 106 and the electrical IC chip 108 are vertically stacked on each other in a 3D structure, and the electrical IC chip 108 and the memory IC chip 110 have a 2.5D structure. This partially reduces the lateral footprint of the semiconductor package structure.

[0056] Figure 4B Shows Figure 4A A top view 400b of some embodiments of a semiconductor package structure.

[0057] like Figure 4B, one or more electrical IC chips 108 laterally surround the memory IC chip 110. In various embodiments, the electrical IC chips 108 are shown as multiple separate chips disposed around the outer perimeter of the memory IC chip 110. In further embodiments, it should be understood that the electrical IC chip 108 is a single IC chip having an opening in the central region of the single IC chip, wherein the memory IC chip 110 is disposed in the opening. The photonic IC chip 106 is directly above the electrical IC chip 108.

[0058] Figure 4C Shows Figure 4A 400 c of some other embodiments of a semiconductor package structure, wherein the semiconductor package structure includes a plurality of memory IC chips 110 arranged in an array including columns and rows. The plurality of memory IC chips 110 are spaced apart between opposing sidewalls of one or more electrical IC chips 108 .

[0059] Figure 5A Shows the corresponding Figure 3A FIG. 5 is a cross-sectional view 500 a of some other embodiments of a semiconductor package structure, wherein the semiconductor package structure includes a single electrical IC chip 108 and a plurality of memory IC chips 110 .

[0060] In some embodiments, the electrical IC chip 108 is disposed above the central region of the interposer 103 and extends between the photonic IC chips 106. The photonic IC chip 106 is disposed around the outer periphery of the electrical IC chip 108. The electrical IC chip 108 includes a functional IC 105 and an EIC 104. The functional IC 105 is disposed at the middle region of the electrical IC chip 108, and the EIC 104 is disposed at the peripheral region of the electrical IC chip 108 directly adjacent to the photonic IC chip 106. In various embodiments, the photonic IC chip 106 and the electrical IC chip 108 are disposed at the same height, and a plurality of memory IC chips 110 are directly located above the electrical IC chip 108. The memory IC chip 110 is directly electrically coupled to the electrical IC chip 108. Therefore, the transmission efficiency between the memory IC chip 110 and the electrical IC chip 108 is increased.

[0061] Figure 5B Shows Figure 5A A top view 500b of some embodiments of a semiconductor package structure.

[0062] like Figure 5B As shown in FIG. 1 , EIC 104 laterally surrounds functional IC 105. In some embodiments, memory IC chip 110 is directly above functional IC 105 and is spaced between opposing side walls of electrical IC chip 108. Photonic IC chip 106 is spaced around the outer perimeter of electrical IC chip 108.

[0063] Figure 5C Shows Figure 5A 500c of some other embodiments of a semiconductor package structure, wherein the semiconductor package structure includes a single memory IC chip 110 above an electrical IC chip 108. In various embodiments, the area of ​​the memory IC chip 110 is equal to or approximately equal to the area of ​​the functional IC 105 of the electrical IC chip 108.

[0064] Fig. 6A Shows Figure 4A FIG. 6 is a cross-sectional view 600 a of some other embodiments of a semiconductor package structure, wherein a plurality of memory IC chips 110 are directly located above a power IC chip 108 .

[0065] In some embodiments, the semiconductor package structure includes a single electrical IC chip 108 located above the interposer 103. In various embodiments, the functional IC 105 is disposed in the middle region of the electrical IC chip 108, and the EIC 104 is disposed in the peripheral region of the electrical IC chip 108. A plurality of third solder bumps 402 are disposed between the electrical IC chip 108 and the memory IC chip 110. In various embodiments, the photonic IC chip 106 is directly located above the electrical IC chip 108 and is directly laterally adjacent to the plurality of memory IC chips 110. In some embodiments, the photonic IC chip 106 and the memory IC chip 110 are disposed at the same height. In yet further embodiments, the bottom surfaces of the photonic IC chip 106 and the memory IC chip 110 are aligned or coplanar with each other. The third solder bumps 402 provide electrical coupling between the electrical IC chip 108 and the memory IC chip 110. In yet further embodiments, the third solder bumps 402 are omitted (not shown), and the bonding structure of each memory IC chip 110 directly contacts the bonding structure of the electrical IC chip 108. In such an embodiment, the bottom surface of the memory IC chip 110 directly contacts the top surface of the electrical IC chip 108. Placing multiple memory IC chips 110 directly above the electrical IC chip 108 increases the transmission efficiency of the semiconductor package structure and reduces the power consumption of the semiconductor package structure.

[0066] Figure 6B Shows Fig. 6A A top view 600b of some embodiments of a semiconductor package structure.

[0067] like Figure 6B As shown in FIG. 1 , a plurality of memory IC chips 110 are spaced apart between opposing sidewalls of the electrical IC chip 108. In some embodiments, the EIC 104 laterally wraps around the outer perimeter of the functional IC 105. A plurality of photonic IC chips are located directly above the EIC 104 at the peripheral region of the electrical IC chip 108.

[0068] Figure 6C Shows Fig. 6A FIG. 6 is a top view 600 c of some other embodiments of a semiconductor package structure, wherein the semiconductor package structure includes a single memory IC chip 110 above a power IC chip 108 .

[0069] Fig. 7A Shows FIG. 3A to FIG. 3C FIG. 7 is a cross-sectional view 700 a of some other embodiments of a semiconductor package structure, wherein a heat dissipation structure 701 is located above a plurality of IC chips 106 , 108 , and 110 .

[0070] In some embodiments, the heat dissipation structure 701 includes a first thermal interface layer 702, a heat diffusion layer 704, a second thermal interface layer 706, and a heat sink structure 708. The first thermal interface layer 702 is disposed between the heat diffusion layer 704 and the plurality of IC chips 106, 108, 110. In some embodiments, the first thermal interface layer 702 extends along and directly contacts the top surface of the housing structure 318 and the top surfaces of the plurality of IC chips 106, 108, 110. In various embodiments, the first thermal interface layer 702 directly contacts the opposite sidewalls of the memory IC chip 110. In yet further embodiments, the first thermal interface layer 702 is disposed in an opening between the plurality of IC chips 106, 108, 110 such that the first thermal interface layer 702 contacts one or more sidewalls (not shown) of the photonic IC chip 106 and the electrical IC chip 108. The heat diffusion layer 704 is located on the first thermal interface layer 702 and is configured to diffuse and / or absorb heat from the plurality of IC chips 106, 108, 110. The heat diffusion layer 704 extends along opposite sidewalls of the housing structure 318. In some embodiments, the heat diffusion layer 704 continuously wraps around the plurality of IC chips 106, 108, 110 laterally. The second thermal interface layer 706 is located on the top surface of the heat diffusion layer 704. The heat sink structure 708 is located on the second thermal interface layer 706.

[0071] In some embodiments, during operation of the semiconductor package structure, the plurality of IC chips 106, 108, 110 generate heat directed toward the heat diffusion layer 704. The heat diffusion layer 704 is configured to diffuse and / or absorb the generated heat across the heat diffusion layer 704, thereby reducing the temperature of the plurality of IC chips 106, 108, 110. The heat from the plurality of IC chips 106, 108, 110 is propagated from the heat diffusion layer 704 to the heat sink structure 708. The heat sink structure 708 is configured to dissipate the heat from the plurality of IC chips 106, 108, 110, thereby reducing the temperature of the semiconductor package structure. For example, the heat sink structure 708 includes a plurality of heat sink fins 710 extending vertically from the base of the heat sink structure 708 in a direction away from the package substrate 101. The heat sink fins 710 are laterally spaced apart from each other. Air can be transmitted between the heat sink fins 710 and dissipate the heat collected at the heat sink fins 710 and / or cool the heat sink fins 710. For example, a fan (not shown) can be configured to direct air between heat sink fins 710 to remove heat from heat sink structure 708, thereby reducing the temperature of heat sink structure 708. Thus, heat dissipation structure 701 reduces the temperature of the semiconductor package structure, thereby increasing reliability.

[0072] In addition, the photonic IC chip 106 is disposed at a peripheral region of the interposer 103 and includes an optical I / O structure 112 (e.g., an edge coupler) configured to receive optical signals along the side of the semiconductor package structure. This facilitates the transmission and / or reception of optical signals in the horizontal direction, so that the heat dissipation structure 701 can be disposed directly above the multiple IC chips 106, 108, 110. Therefore, the heat dissipation structure 701 can effectively dissipate the heat generated by the multiple IC chips 106, 108, 110. Therefore, the position and / or layout of the photonic IC chip 106 increases the transmission efficiency of the semiconductor package structure while increasing the ability to dissipate heat from the semiconductor package structure, thereby increasing the overall performance of the semiconductor package structure.

[0073] In some embodiments, the first thermal interface layer 702 and the second thermal interface layer 706 may be, for example, or include a polymer, a wax, aluminum, a viscous silicone compound, or any combination of the foregoing. In some embodiments, the viscous silicone compound has mechanical properties similar to grease or gel. In various embodiments, the heat diffusion layer 704 may be, for example, or include a metal such as aluminum, copper, nickel, cobalt, some other metal, or an alloy thereof. In further embodiments, the heat diffusion layer 704 may be, for example, or include a composite material from the group consisting of silicon carbide, aluminum nitride, graphite, etc. In some embodiments, the heat sink structure 708 may be, for example, or include copper, aluminum, some other material, or any combination of the foregoing materials.

[0074] Figure 7B Shows Fig. 7A 700 b of some other embodiments of a semiconductor package structure, wherein the height of the memory IC chip 110 is equal to the height of the photonic IC chip 106 and the electrical IC chip 108. In some embodiments, the top surface of the memory IC chip 110 is coplanar with the top surfaces of the photonic IC chip 106 and the electrical IC chip 108. This facilitates, in part, reducing the overall height of the semiconductor package structure and / or increasing the ability to dissipate heat from the multiple IC chips 106, 108, 110.

[0075] Figure 7C Shows Fig. 7A FIG. 7 is a cross-sectional view 700 c of some other embodiments of a semiconductor package structure, wherein the height 714 of the memory IC chip 110 is less than the heights of the photonic IC chip 106 and the electrical IC chip 108. In some embodiments, the height 714 of the memory IC chip 110 is less than the height 712 of the photonic IC chip 106. In various embodiments, the height of the electrical IC chip 108 is equal to the height 712 of the photonic IC chip 106.

[0076] Fig.7D Shows FIG. 4A to FIG. 4C FIG. 7 is a cross-sectional view of some other embodiments of a semiconductor package structure, wherein a heat dissipation structure 701 is located above a plurality of IC chips 106, 108, 110. In some embodiments, the heat dissipation structure 701 is configured as above. Fig. 7A As shown and / or described in.

[0077] Fig. 7E Shows FIG. 6A to FIG. 6C 700e of some other embodiments of the semiconductor package structure, wherein the heat dissipation structure 701 is located above the plurality of IC chips 106, 108, 110. In some embodiments, the heat dissipation structure is configured as above Fig. 7A In various embodiments, the first thermal interface layer 702 is disposed directly between adjacent memory IC chips 110 and between the memory IC chip 110 and the photonic IC chip 106 .

[0078] FIG. 8A to FIG. 8E Shows 7A to 7E Some other embodiments of the semiconductor package structure are shown in cross-sectional views 800a-800e, wherein the heat dissipation structure 701 further includes a liquid cooling structure 801 disposed on the second thermal interface layer 706. For example, Fig. 8A Shows the corresponding Fig. 7A Some other embodiments of the semiconductor package structure are cross-sectional views 800a, Figure 8B Shows the corresponding Figure 7B Some other embodiments of the semiconductor package structure are shown in cross-sectional view 800b. Figure 8CShows the corresponding Figure 7C Cross-sectional views 800c and the like of some other embodiments of semiconductor package structures.

[0079] In some embodiments, a liquid cooling structure 801 is disposed between the heat sink structure 708 and the second thermal interface layer 706. The liquid cooling structure 801 includes a liquid housing structure 802 and a liquid channel structure 804. The liquid channel structure 804 is disposed in the liquid housing structure 802. In some embodiments, during operation of the heat dissipation structure 701, a liquid pump (not shown) is configured to circulate a liquid (e.g., water or another coolant) across the liquid channel structure 804. The liquid absorbs heat generated from the plurality of IC chips 106, 108, 110 and is configured to be transported away to an external cooler or heat exchanger (not shown), and / or configured to be cooled by the heat sink structure 708 above. This facilitates further reducing the temperature of the plurality of IC chips 106, 108, 110, thereby further increasing the overall performance of the semiconductor package structure. In yet further embodiments, the heat dissipation structure 701 may be provided to the semiconductor package 706. FIG. 8A to FIG. 8E The semiconductor package structure omits the heat sink structure 708 (not shown).

[0080] Figures 9 to 17 Cross-sectional views 900-1700 of some embodiments of methods for forming a semiconductor package structure including a photonic IC chip directly adjacent to an electrical IC chip are shown. Figures 9 to 17 The cross-sectional views 900-1700 shown in the reference method are described, but it should be understood that Figures 9 to 17 The structure shown in is not limited to this method, but can exist independently of this method. Figures 9 to 17 Described as a series of steps, it should be understood that these steps are not limited to the order of the steps that can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some steps shown and / or described can be omitted in whole or in part.

[0081] like Fig. 9 As shown in cross-sectional view 900 of FIG. 1 , an interposer 103 is provided or otherwise formed over a carrier substrate 902. In some embodiments, the interposer 103 includes an interposer structure 308, a plurality of through substrate vias (TSVs) 310, a plurality of conductive interconnect structures 312, 314, and a plurality of contact pads 315. A plurality of first solder bumps 306 are formed on a lower surface of the interposer 103. The plurality of first solder bumps 306 may be or include solder bumps, microbumps, copper rods, or some other suitable bump structures.

[0082] like Fig.10As shown in the cross-sectional view 1000 of , one or more electrical IC chips 108 arranged above and bonded to the contact pads 315 of the interposer 103 are provided or otherwise formed. In some embodiments, the one or more electrical IC chips 108 are configured as a system-on-chip (SoC) chip and include an electrical integrated circuit (EIC) 104 and a functional IC 105. In various embodiments, bonding the one or more electrical IC chips 108 to the interposer 103 includes: forming a plurality of second solder bumps 316 above the interposer 103; and implementing a bonding process (e.g., a welding process). In yet further embodiments, the one or more electrical IC chips 108 are bonded to the interposer 103 by a eutectic bonding process or some other suitable bonding process. The plurality of second solder bumps 316 may be, for example, or include solder bumps, microbumps, copper rods, or some other suitable bump structures. In some embodiments, the EIC 104 includes circuits for a photonic IC chip, including amplifiers, control circuits, digital processing circuits, drivers, and the like. The functional IC 105 may be, for example, or include one or more of a switch chip, an ASIC, a CPU, a GPU, a DPU, and the like.

[0083] like Fig.11 As shown in the cross-sectional view 1100 of , one or more memory IC chips 110 arranged over and bonded to the contact pads 315 of the interposer 103 are provided or otherwise formed. In some embodiments, the one or more memory IC chips 110 are or include a plurality of memory layers 322 stacked vertically with the memory controller circuit 320. In various embodiments, bonding the one or more memory IC chips 110 to the interposer 103 includes: forming a plurality of second solder bumps 316 over the interposer 103; and performing a bonding process (e.g., a welding process). In yet further embodiments, the one or more memory IC chips 110 are bonded to the interposer 103 by a eutectic bonding process or some other suitable bonding process. The one or more memory IC chips 110 are arranged over the interposer 103 so that the one or more memory IC chips 110 are directly adjacent to the one or more electrical IC chips 108. In various embodiments, the one or more electrical IC chips 108 laterally surround the one or more memory IC chips 110 and / or are directly laterally adjacent to the one or more memory IC chips 110. In yet further embodiments, one or more memory IC chips 110 are directly located above and directly bonded to one or more electrical IC chips 108 (not shown) (e.g., FIG. 5A to FIG. 5C or FIG. 6A to FIG. 6C ).

[0084] like Fig.12As shown in the cross-sectional view 1200 of , a plurality of photonic IC chips 106 arranged above and bonded to the contact pads 315 of the interposer 103 are provided or otherwise formed. In some embodiments, the photonic IC chip 106 includes one or more optical I / O structures 112 and other photonic devices, such as waveguides, photodetectors, light-emitting units (e.g., laser diodes, light-emitting diodes, etc.), optical modulators, other photonic devices, or any combination of the foregoing. In various embodiments, bonding the plurality of photonic IC chips 106 to the interposer 103 includes: forming a plurality of second solder bumps 316 above the interposer; and performing a bonding process (e.g., a welding process). In yet further embodiments, the photonic IC chip 106 is bonded to the interposer 103 by a eutectic bonding process or some other suitable bonding process. The photonic IC chip 106 is disposed at the periphery of the interposer 103 and is directly adjacent to one or more electrical IC chips 108. In some embodiments, the photonic IC chip 106 is directly adjacent to the one or more electrical IC chips 108. In yet further embodiments, the photonic IC chip 106 is directly located above and directly bonded to one or more electrical IC chips 108 (not shown) (e.g., FIG. 4A to FIG. 4C , FIG. 5A to FIG. 5C or FIG. 6A to FIG. 6C 108). Placing the photonic IC chip 106 directly adjacent to one or more electrical IC chips 108 increases the transmission efficiency of the semiconductor package structure. In addition, in some embodiments, the top layout of the semiconductor package structure is configured as follows Figure 3B , Figure 3C , Figure 4B , Figure 4C , Figure 5B , Figure 5C , Figure 6B or Figure 6C As shown in .

[0085] like Fig.13 As shown in the cross-sectional view 1300, the carrier substrate is removed ( Fig.12 902), and the interposer 103 is bonded to the package substrate 101. In some embodiments, the interposer 103 is bonded to the package substrate 101 by, for example, a welding process or some other suitable process.

[0086] like Fig.14As shown in the cross-sectional view 1400 of FIG. 14 , a plurality of optical fiber structures 114 are formed adjacent to and / or next attached to the optical I / O structure 112 of the photonic IC chip 106. In addition, a housing structure 318 is formed over the package substrate 101 and around the interposer 103. The housing structure 318 is disposed along the sidewalls of each photonic IC chip 106 and provides support for the plurality of optical fiber structures, wherein the housing structure 318 provides support for the optical fiber structure 114. In various embodiments, the housing structure 318 may be, for example, epoxy resin or some other suitable material.

[0087] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 15 , a first thermal interface layer 702 is formed over the package substrate 101, a heat diffusion layer 704 is formed over the first thermal interface layer 702, and a second thermal interface layer 706 is formed over the heat diffusion layer 704. In various embodiments, the first thermal interface layer 702 and the second thermal interface layer 706 may be formed, for example, by a screen printing process, a spraying process, a paste or grease application process, a sputtering process, a physical vapor deposition (PVD) process, or some other suitable manufacturing process. In yet further embodiments, the heat diffusion layer 704 may be formed, for example, by a screen printing process, a lamination process, a deposition process (e.g., a PVD process), or some other suitable manufacturing process.

[0088] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 16 , a liquid cooling structure 801 is formed above the second thermal interface layer 706, and a heat sink structure 708 is formed above the liquid cooling structure 801, thereby defining the heat sink structure 701. The liquid cooling structure 801 includes a liquid housing structure 802 and a liquid channel structure 804. The heat sink structure 708 includes a plurality of heat sink fins 710 extending upward from the base of the heat sink structure 708. In some embodiments, forming the heat sink structure 701 includes Fig.15 and Fig.17 The processing and / or manufacturing steps shown and / or described in .

[0089] like Fig.17 As shown in the cross-sectional view 1700 of , a plurality of lower solder bumps 1702 are formed along the lower surface of the package substrate 101 .

[0090] Fig.18A flow chart of some embodiments of a method 1800 for forming a semiconductor package structure including a photonic IC chip directly adjacent to an electrical IC chip is shown. Although method 1800 is shown and / or described as a series of steps or events, it should be understood that the method is not limited to the order or steps shown. Therefore, in some embodiments, the steps may be performed in an order different from that shown, and / or may be performed simultaneously. In addition, in some embodiments, the steps or events shown may be subdivided into multiple steps or events, which may be performed at different times or simultaneously with other steps or sub-steps. In some embodiments, some of the steps or events shown may be omitted, and other steps or events not shown may be included.

[0091] In step 1802, an interposer including a plurality of contact pads is provided or otherwise formed. Fig. 9 A cross-sectional view 900 corresponding to some embodiments of step 1802 is shown.

[0092] In step 1804, one or more electrical integrated circuit (IC) chips are provided or otherwise formed.

[0093] In step 1806 , one or more electrical IC chips are bonded to the interposer. Fig.10 A cross-sectional view 1000 corresponding to some embodiments of steps 1804 and 1806 is shown.

[0094] In step 1808, one or more memory IC chips are provided or otherwise formed.

[0095] In step 1810, one or more memory IC chips are bonded to an interposer such that the one or more memory IC chips are surrounded by the one or more electrical IC chips. Fig.11 A cross-sectional view 1100 corresponding to some embodiments of steps 1808 and 1810 is shown.

[0096] In step 1812 , a plurality of photonic IC chips are provided or otherwise formed.

[0097] In step 1814 , a plurality of photonic IC chips are bonded to the interposer, wherein the photonic IC chips are disposed at a peripheral region of the interposer and are directly adjacent to one or more electrical IC chips. Fig.12 A cross-sectional view 1200 corresponding to some embodiments of steps 1812 and 1814 is shown.

[0098] In step 1816 , the interposer is bonded to the package substrate. Fig.13 A cross-sectional view 1300 corresponding to some embodiments of step 1816 is shown.

[0099] In step 1818, a plurality of optical fiber structures are formed adjacent to the photonic IC chip.

[0100] In step 1820, a housing structure is formed around the interposer and over the plurality of optical fiber structures. Fig.14 A cross-sectional view 1400 corresponding to some embodiments of steps 1818 and 1820 is shown.

[0101] In step 1822, a heat sink structure is formed over the electrical IC chip, the memory IC chip, and the photonic IC chip. Fig.15 and Fig.16 Cross-sectional views 1500 and 1600 corresponding to some embodiments of step 1822 are shown.

[0102] Thus, in some embodiments, the disclosed embodiments are directed to a semiconductor package structure that includes an electrical IC chip located above a packaging substrate and a photonic IC chip located above the packaging substrate and directly adjacent to the electrical IC chip.

[0103] In some embodiments, the present application provides a semiconductor packaging structure, including: a first integrated circuit (IC) chip, located on a substrate structure; an electrical IC chip, located on the substrate structure and arranged around the first IC chip, wherein the electrical IC chip is electrically coupled to the first IC chip; and a photonic IC chip, located on the substrate structure and electrically coupled to the electrical IC chip, wherein the photonic IC chip is configured to receive an input optical signal, wherein the photonic IC chip is adjacent to the electrical IC chip. In an embodiment, the first IC chip is configured as a memory IC chip, and the photonic IC chip is arranged at the same height as the electrical IC chip and the first IC chip. In an embodiment, the bottom surface of the photonic IC chip is coplanar with the bottom surface of the electrical IC chip. In an embodiment, the photonic IC chip is directly located above the electrical IC chip. In an embodiment, the photonic IC chip includes an optical input / output (I / O) structure arranged at a peripheral area of ​​the photonic IC chip, a waveguide optically coupled to the I / O structure, and a photodetector optically coupled to the waveguide, wherein the I / O structure is configured to receive an input optical signal, and wherein the photodetector is configured to convert the input optical signal into an electrical signal. In an embodiment, the electrical IC chip includes an electrical integrated circuit (EIC) and a functional IC laterally adjacent to the EIC, wherein the EIC includes one or more electrical components configured to receive an electrical signal from the photonic IC chip and generate an output electrical signal, wherein the functional IC is configured to receive the output electrical signal, wherein the EIC is directly spaced apart between the functional IC and the photonic IC chip. In an embodiment, the one or more electrical components include one or more of an amplifier circuit and / or a driver circuit, and wherein the functional IC includes one or more of a central processing unit (CPU), a graphics processing unit (GPU), and / or a data processing unit (DPU), wherein the EIC is configured to provide an electrical interface between the functional IC and the photonic IC chip. In an embodiment, the semiconductor package structure further includes: an optical fiber structure attached to the photonic IC chip and coupled to the optical I / O structure, wherein the optical fiber structure is elongated in a first direction parallel to an upper surface of the substrate structure. In an embodiment, the semiconductor package structure further includes: a heat dissipation structure located above the first IC chip, the electrical IC chip, and the photonic IC chip, wherein the heat dissipation structure includes a heat diffusion layer located above the first IC chip, the electrical IC chip, and the photonic IC chip, and a heat sink structure located above the heat diffusion layer.

[0104] In some embodiments, the present application provides a semiconductor package structure, including: an interposer, located on a packaging substrate; one or more electrical integrated circuit (IC) chips, located on the interposer and coupled to the interposer; a first IC chip, located on the interposer and coupled to the one or more electrical IC chips, wherein the first IC chip is laterally spaced between opposite sidewalls of the one or more electrical IC chips; and a plurality of photonic IC chips, located on the interposer and electrically coupled to the one or more electrical IC chips, wherein the plurality of photonic IC chips are arranged at a peripheral region of the interposer and surround the first IC chip, wherein a lateral distance between each of the plurality of photonic IC chips and the one or more electrical IC chips is less than a width of an independent photonic IC chip in the plurality of photonic IC chips. In an embodiment, the bottom surfaces of the electrical IC chip, the first electrical IC chip, and the photonic IC chip are substantially coplanar with each other, wherein the one or more electrical IC chips laterally wrap around the outer periphery of the first IC chip, and wherein the photonic IC chip is spaced between the outer periphery of the one or more electrical IC chips and the outer periphery of the interposer. In an embodiment, the plurality of photonic IC chips are directly located on the one or more electrical IC chips, wherein the outer sidewalls of each photonic IC chip are aligned with the corresponding sidewalls of the one or more electrical IC chips. In an embodiment, the plurality of photonic IC chips include a first photonic IC chip adjacent to a second photonic IC chip, wherein a first distance between the first photonic IC chip and the second photonic IC chip is less than a lateral distance. In an embodiment, the one or more electrical IC chips include a single electrical IC chip disposed above a middle region of an interposer, wherein the first IC chip is directly above the single electrical IC chip, wherein the plurality of photonic IC chips are disposed above a peripheral region of the interposer, wherein the photonic IC chips are adjacent to four sides of the single electrical IC chip. In an embodiment, the one or more electrical IC chips include a single electrical IC chip disposed above an interposer, wherein the first IC chip is directly above a middle region of the single electrical IC chip, wherein the plurality of photonic IC chips are directly above a peripheral region of the single electrical IC chip, wherein the plurality of photonic IC chips surround the first IC chip. In an embodiment, the semiconductor package structure further includes: a housing structure disposed around an outer periphery of the interposer, wherein the housing structure extends from a sidewall of the interposer along a sidewall of the single electrical IC chip to a sidewall of each photonic IC chip; and a plurality of optical fiber structures attached to the plurality of photonic IC chips, wherein the optical fiber structures are disposed in the housing structure. In an embodiment, the plurality of photonic IC chips respectively include a plurality of edge couplers vertically aligned with the plurality of optical fiber structures. In an embodiment, the first IC chip is configured as a memory IC chip, and the lateral distance is less than half the width of an individual photonic IC chip of the plurality of photonic IC chips.

[0105] In some embodiments, the present application provides a method for forming a semiconductor package structure, the method comprising: bonding one or more electrical integrated circuit (IC) chips to an interposer; bonding a memory IC chip to the interposer, wherein the memory IC chip is spaced apart between sidewalls of the one or more electrical IC chips; and bonding a plurality of photonic IC chips to the interposer, wherein the plurality of photonic IC chips are configured to receive an input optical signal and generate an electrical signal corresponding to the input optical signal, wherein the photonic IC chip is disposed adjacent to the one or more electrical IC chips, wherein the one or more electrical IC chips are configured to receive the generated electrical signal. In an embodiment, the method further comprises: attaching a plurality of optical fiber structures to the plurality of photonic IC chips, wherein the plurality of photonic IC chips are spaced apart directly between the plurality of optical fiber structures and the one or more electrical IC chips.

[0106] Some embodiments of the present application provide a semiconductor packaging structure, including: a first integrated circuit (IC) chip, located on a substrate structure; an electrical integrated circuit chip, located on the substrate structure and arranged around the first integrated circuit chip, wherein the electrical integrated circuit chip is electrically coupled to the first integrated circuit chip; and a photonic integrated circuit chip, located on the substrate structure and electrically coupled to the electrical integrated circuit chip, wherein the photonic integrated circuit chip is configured to receive an input optical signal, wherein the photonic integrated circuit chip is adjacent to the electrical integrated circuit chip.

[0107] In some embodiments, the first integrated circuit chip is configured as a memory integrated circuit chip, wherein the photonic integrated circuit chip is disposed at the same height as the electrical integrated circuit chip and the first integrated circuit chip. In some embodiments, the bottom surface of the photonic integrated circuit chip is coplanar with the bottom surface of the electrical integrated circuit chip. In some embodiments, the photonic integrated circuit chip is directly above the electrical integrated circuit chip. In some embodiments, the photonic integrated circuit chip includes an optical input / output (I / O) structure disposed at a peripheral region of the photonic integrated circuit chip, a waveguide optically coupled to the input / output structure, and a photodetector optically coupled to the waveguide, wherein the input / output structure is configured to receive the input optical signal, and wherein the photodetector is configured to convert the input optical signal into an electrical signal. In some embodiments, the electrical integrated circuit chip includes an electrical integrated circuit (EIC) and a functional integrated circuit laterally adjacent to the electrical integrated circuit, wherein the electrical integrated circuit includes one or more electrical components configured to receive the electrical signal from the photonic integrated circuit chip and generate an output electrical signal, wherein the functional integrated circuit is configured to receive the output electrical signal, and wherein the electrical integrated circuit is spaced directly between the functional integrated circuit and the photonic integrated circuit chip. In some embodiments, the one or more electrical components include one or more of an amplifier circuit and / or a driver circuit, and wherein the functional integrated circuit includes one or more of a central processing unit (CPU), a graphics processing unit (GPU), and / or a data processing unit (DPU), wherein the electrical integrated circuit is configured to provide an electrical interface between the functional integrated circuit and the photonic integrated circuit chip. In some embodiments, the semiconductor packaging structure further includes: an optical fiber structure attached to the photonic integrated circuit chip and coupled to the optical input / output structure, wherein the optical fiber structure is elongated in a first direction parallel to the upper surface of the substrate structure. In some embodiments, the semiconductor packaging structure further includes: a heat dissipation structure located above the first integrated circuit chip, the electrical integrated circuit chip, and the photonic integrated circuit chip, wherein the heat dissipation structure includes a heat diffusion layer located above the first integrated circuit chip, the electrical integrated circuit chip, and the photonic integrated circuit chip, and a heat sink structure located above the heat diffusion layer.

[0108] Other embodiments of the present application provide a semiconductor packaging structure, including: an interposer located on a packaging substrate; one or more electrical integrated circuit (IC) chips located on the interposer and coupled to the interposer; a first integrated circuit chip located on the interposer and coupled to the one or more electrical integrated circuit chips, wherein the first integrated circuit chip is laterally spaced between relative side walls of the one or more electrical integrated circuit chips; and a plurality of photonic integrated circuit chips located on the interposer and electrically coupled to the one or more electrical integrated circuit chips, wherein the plurality of photonic integrated circuit chips are arranged at a peripheral area of ​​the interposer and surround the first integrated circuit chip, wherein a lateral distance between each of the plurality of photonic integrated circuit chips and the one or more electrical integrated circuit chips is less than a width of an independent photonic integrated circuit chip among the plurality of photonic integrated circuit chips.

[0109] In some embodiments, the bottom surfaces of the electrical integrated circuit chip, the first electrical integrated circuit chip, and the photonic integrated circuit chip are substantially coplanar with each other, wherein the one or more electrical integrated circuit chips laterally wrap around the outer periphery of the first integrated circuit chip, and wherein the photonic integrated circuit chip is spaced between the outer periphery of the one or more electrical integrated circuit chips and the outer periphery of the interposer. In some embodiments, the plurality of photonic integrated circuit chips are directly above the one or more electrical integrated circuit chips, wherein the outer sidewall of each photonic integrated circuit chip is aligned with the corresponding sidewall of the one or more electrical integrated circuit chips. In some embodiments, the plurality of photonic integrated circuit chips include a first photonic integrated circuit chip adjacent to a second photonic integrated circuit chip, wherein a first distance between the first photonic integrated circuit chip and the second photonic integrated circuit chip is less than the lateral distance. In some embodiments, the one or more electrical integrated circuit chips include a single electrical integrated circuit chip disposed above a middle region of the interposer, wherein the first integrated circuit chip is directly above the single electrical integrated circuit chip, wherein the plurality of photonic integrated circuit chips are disposed above a peripheral region of the interposer, wherein the photonic integrated circuit chip is adjacent to four sides of the single electrical integrated circuit chip. In some embodiments, the one or more electrical integrated circuit chips include a single electrical integrated circuit chip located above the interposer, wherein the first integrated circuit chip is directly located above a middle region of the single electrical integrated circuit chip, wherein the plurality of photonic integrated circuit chips are directly located above a peripheral region of the single electrical integrated circuit chip, and wherein the plurality of photonic integrated circuit chips surround the first integrated circuit chip. In some embodiments, the semiconductor package structure further includes: a housing structure disposed around an outer periphery of the interposer, wherein the housing structure extends from a sidewall of the interposer along a sidewall of the single electrical integrated circuit chip to a sidewall of each photonic integrated circuit chip; and a plurality of optical fiber structures attached to the plurality of photonic integrated circuit chips, wherein the optical fiber structures are disposed in the housing structure. In some embodiments, the plurality of photonic integrated circuit chips respectively include a plurality of edge couplers vertically aligned with the plurality of optical fiber structures. In some embodiments, the first integrated circuit chip is configured as a memory integrated circuit chip, wherein the lateral distance is less than half of the width of the individual photonic integrated circuit chips among the plurality of photonic integrated circuit chips.

[0110] Still other embodiments of the present application provide a method for forming a semiconductor packaging structure, comprising: bonding one or more electrical integrated circuit (IC) chips to an interposer; bonding a memory integrated circuit chip to the interposer, wherein the memory integrated circuit chip is spaced apart between side walls of the one or more electrical integrated circuit chips; and bonding a plurality of photonic integrated circuit chips to the interposer, wherein the plurality of photonic integrated circuit chips are configured to receive an input optical signal and generate an electrical signal corresponding to the input optical signal, wherein the photonic integrated circuit chip is disposed adjacent to the one or more electrical integrated circuit chips, wherein the one or more electrical integrated circuit chips are configured to receive the generated electrical signal.

[0111] In some embodiments, the method further comprises attaching a plurality of optical fiber structures to the plurality of photonic integrated circuit chips, wherein the plurality of photonic integrated circuit chips are spaced directly between the plurality of optical fiber structures and the one or more electrical integrated circuit chips.

[0112] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor packaging structure, include: A first integrated circuit (IC) chip is located on the substrate structure; an electrical integrated circuit chip located on the base structure and disposed around the first integrated circuit chip, wherein the electrical integrated circuit chip is electrically coupled to the first integrated circuit chip; and A photonic integrated circuit chip is located on the base structure and electrically coupled to the electrical integrated circuit chip, wherein the photonic integrated circuit chip is configured to receive an input optical signal, wherein the photonic integrated circuit chip is adjacent to the electrical integrated circuit chip.

2. The semiconductor package structure according to claim 1, in, The first integrated circuit chip is configured as a memory integrated circuit chip, wherein the photonic integrated circuit chip is disposed at the same height as the electrical integrated circuit chip and the first integrated circuit chip.

3. The semiconductor package structure according to claim 2, in, The bottom surface of the photonic integrated circuit chip is coplanar with the bottom surface of the electrical integrated circuit chip.

4. The semiconductor package structure according to claim 1, in, The photonic integrated circuit chip is located directly on top of the electrical integrated circuit chip.

5. The semiconductor package structure according to claim 1, in, The photonic integrated circuit chip includes an optical input / output (I / O) structure disposed at a peripheral region of the photonic integrated circuit chip, a waveguide optically coupled to the input / output structure, and a photodetector optically coupled to the waveguide, wherein the input / output structure is configured to receive the input optical signal, and wherein the photodetector is configured to convert the input optical signal into an electrical signal.

6. The semiconductor package structure according to claim 5, in, The electrical integrated circuit chip includes an electrical integrated circuit (EIC) and a functional integrated circuit laterally adjacent to the electrical integrated circuit, wherein the electrical integrated circuit includes one or more electrical components configured to receive the electrical signal from the photonic integrated circuit chip and generate an output electrical signal, wherein the functional integrated circuit is configured to receive the output electrical signal, and wherein the electrical integrated circuit is spaced directly between the functional integrated circuit and the photonic integrated circuit chip.

7. The semiconductor package structure according to claim 6, in, The one or more electrical components include one or more of an amplifier circuit and / or a driver circuit, and wherein the functional integrated circuit includes one or more of a central processing unit (CPU), a graphics processing unit (GPU) and / or a data processing unit (DPU), wherein the electrical integrated circuit is configured to provide an electrical interface between the functional integrated circuit and the photonic integrated circuit chip.

8. The semiconductor package structure according to claim 5, further comprising: include: An optical fiber structure is attached to the photonic integrated circuit chip and coupled to the optical input / output structure, wherein the optical fiber structure is elongated in a first direction parallel to the upper surface of the base structure.

9. A semiconductor packaging structure, include: An interposer, located on top of the package substrate; one or more electrical integrated circuit (IC) chips located on and coupled to the interposer; a first integrated circuit chip located above the interposer and coupled to the one or more electrical integrated circuit chips, wherein the first integrated circuit chip is laterally spaced between opposing sidewalls of the one or more electrical integrated circuit chips; and A plurality of photonic integrated circuit chips are located on the interposer and electrically coupled to the one or more electrical integrated circuit chips, wherein the plurality of photonic integrated circuit chips are arranged at a peripheral area of ​​the interposer and surround the first integrated circuit chip, wherein a lateral distance between each of the plurality of photonic integrated circuit chips and the one or more electrical integrated circuit chips is less than a width of an independent photonic integrated circuit chip of the plurality of photonic integrated circuit chips.

10. A method of forming a semiconductor package structure, include: bonding one or more electrical integrated circuit (IC) chips to the interposer; bonding a memory integrated circuit chip to the interposer, wherein the memory integrated circuit chip is spaced between sidewalls of the one or more electrical integrated circuit chips; and A plurality of photonic integrated circuit chips are bonded to the interposer, wherein the plurality of photonic integrated circuit chips are configured to receive input optical signals and generate electrical signals corresponding to the input optical signals, wherein the photonic integrated circuit chips are disposed adjacent to the one or more electrical integrated circuit chips, wherein the one or more electrical integrated circuit chips are configured to receive the generated electrical signals.

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