Baseband processing board based on single Beidou and data processing method

Abstract

The invention relates to a baseband processing board based on a single Beidou and a data processing method, which are realized through an FPGA (Field Programmable Gate Array) processing chip and comprise a programmable logic part, a Core0 and a Core1, a programmable logic part of the FPGA processing chip is used for capturing and tracking Beidou signals; the Core1 is used for capturing and tracking control of baseband signals and writing generated navigation messages and observed quantity into a shared memory for processing of the Core0; and the Core0 reads conformal memory data, analyzes navigation messages and performs PVT resolving, receives external control instructions, outputs NMEA and RTCM protocols, configures capture tracking parameters of the Core1, receives RTCM data to realize RTK positioning, and realizes system upgrading, data backup recovery and log storage. According to the invention, signal processing is completed through cooperation of the double ARM cores and the logic processing unit in the FPGA chip, navigation information can be extracted more effectively, and the positioning efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular to a baseband processing board and a data processing method based on a single Beidou. Background Art

[0002] Existing baseband processing boards generally focus on satellite system signal reception and processing, usually adopting a solution architecture of a general-purpose motherboard CPU + dedicated PVT processing module; however, existing technologies fail to give full play to the advantages of a single Beidou system, lack specialized processing of a single Beidou signal, and the overall performance and efficiency of the system are not high, and the power consumption and size of the single board are relatively large. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a baseband processing board and a data processing method based on a single Beidou, thereby solving the deficiencies of the prior art.

[0004] The object of the present invention is achieved through the following technical solutions: a data processing method based on a single Beidou baseband processing board, the method is implemented by an FPGA processing chip, the FPGA processing chip includes a programmable logic part and two ARM cores, Core0 and Core1; The programmable logic part of the FPGA processing chip completes the capture and tracking of Beidou signals; The Core 1 is used for the acquisition, tracking and control of the baseband signal, and writes the generated navigation message and observation quantity into the shared memory for processing by the Core 0; The Core0 reads conformal memory data, performs navigation message parsing and PVT solution, receives external control instructions, outputs NMEA, RTCM protocols and protocols in other formats, configures the capture and tracking parameters of Core1 in a shared memory manner, receives RTCM data to achieve RTK positioning, and realizes system upgrades, data backup and recovery, and log storage.

[0005] The data processing process between Core0 and Core1 includes: Core0 sends a capture command to Core1, Core1 starts the channel module, controls the pseudo code generator to generate pseudo code, and starts the capture module; The programmable logic part completes the signal search through the capture module matched filter and FFT, while Core0 maintains and refreshes the capture and tracking status of the channel; The programmable logic part determines whether the search is successful. If successful, Core1 obtains the signal code phase data and Doppler shift data, and completes the loop filter parameter calculation and loop control. Then the programmable logic part processes the NCO of the signal code and the NCO of the signal carrier through the tracking channel module to complete the signal synchronization tracking. At the same time, Core0 performs the channel capture and tracking status maintenance and refresh; Core1 completes bit synchronization, frame synchronization, telegram decoding and parsing, and then performs subsequent data processing through Core0.

[0006] The subsequent data processing by Core0 includes: Core0 obtains the message sent by Core1, and at the same time obtains the pseudo code NCO count, bit count, frame calculation and carrier NCO count sent by the programmable logic part to perform positioning, speed measurement and timing operations; Core0 sends the set local time to the programmable logic part. The programmable logic part completes the internal time counting through the TIC module, generates an observation sampling interrupt signal to the tracking channel module, and Core0 performs data protocol framing and output.

[0007] A single Beidou baseband processing board includes an FPGA processing chip and a peripheral circuit connected thereto, wherein the FPGA processing chip includes a programmable logic part and two ARM cores, Core0 and Core1; The programmable logic part completes the capture and tracking of Beidou signals; The Core 1 is used for the acquisition, tracking and control of the baseband signal, and writes the generated navigation message and observation quantity into the shared memory for processing by the Core 0; The Core0 reads conformal memory data, performs navigation message parsing and PVT solution, receives external control instructions, outputs NMEA, RTCM protocols and protocols in other formats, configures the capture and tracking parameters of Core1 in a shared memory manner, receives RTCM data to achieve RTK positioning, and realizes system upgrades, data backup and recovery, and log storage.

[0008] The data processing process between Core0 and Core1 includes: Core0 sends a capture command to Core1, Core1 starts the channel module, controls the pseudo code generator to generate pseudo code, and starts the capture module; The programmable logic part completes the signal search through the capture module matched filter and FFT, while Core0 maintains and refreshes the capture and tracking status of the channel; The programmable logic part determines whether the search is successful. If successful, Core1 obtains the signal code phase data and Doppler shift data, and completes the loop filter parameter calculation and loop control. Then the programmable logic part processes the NCO of the signal code and the NCO of the signal carrier through the tracking channel module to complete the signal synchronization tracking. At the same time, Core0 performs the channel capture and tracking status maintenance and refresh; Core1 completes bit synchronization, frame synchronization, telegram decoding and parsing, and then performs subsequent data processing through Core0.

[0009] The subsequent data processing by Core0 includes: Core0 obtains the message sent by Core1, and at the same time obtains the pseudo code NCO count, bit count, frame calculation and carrier NCO count sent by the programmable logic part to perform positioning, speed measurement and timing operations; Core0 sends the set local time to the programmable logic part. The programmable logic part completes the internal time counting through the TIC module, generates an observation sampling interrupt signal to the tracking channel module, and Core0 performs data protocol framing and output.

[0010] The peripheral circuit includes a power supply part, a radio frequency part, an interface part, an RTC and a clock part connected to the FPGA processing chip; the interface part includes a network interface, a USB interface, and an RS422 / 232 interface.

[0011] The present invention has the following advantages: a baseband processing board and data processing method based on a single Beidou, which completes signal processing through the collaboration of dual ARM cores + logic processing units in an FPGA chip. Compared with a traditional multi-satellite system receiver, the two cores in the ARM perform their respective duties, and cooperate with the FPGA logic part to complete the various functions of the entire receiver, which can more effectively extract navigation information, improve positioning efficiency, and achieve more efficient and more accurate signal processing capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a schematic diagram of the structure of the baseband processing board of the present invention; Figure 2 It is a schematic diagram of the process of the present invention; Figure 3 This is the circuit diagram of the radio frequency part; Figure 4 This is the circuit diagram of the clock part. DETAILED DESCRIPTION

[0013] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application provided below in conjunction with the drawings is not intended to limit the scope of protection of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application. The present invention is further described below in conjunction with the drawings.

[0014] like Figure 1 As shown, the baseband processing board based on a single Beidou in the present invention mainly includes a power supply part, a radio frequency part, an FPGA, an RTC (real-time clock), a network interface, a USB interface, a 422 / 232 interface and peripheral circuits, etc.; the Beidou satellite signal received by the antenna first passes through a low noise amplifier, and then is distributed to 6 channels by a power divider. After passing through a bandpass filter (SAW), it enters the radio frequency chip, and the radio frequency chip digitizes the signal and sends it to the FPGA to complete the positioning solution; among them, the number of signal tracking channels is 256, supporting a single Beidou BDS, and each tracking channel can complete the carrier tracking, pseudo code tracking, and telegram demodulation of the Beidou satellite signal, and provide the original observation amount for positioning solution.

[0015] Furthermore, in the FPGA processing chip, the embedded SOC processing system is used for PVT and protocol processing, which includes two ARM Cortex-A9 processors, Core0 and Core1, both running at 800MHz. The FPGA's programmable logic (PL) part completes the capture and tracking of Beidou signals. Core1 is used for the capture and tracking control of baseband signals, and writes the generated navigation messages and observations into shared memory for processing by Core0. Core0 is equipped with a lightweight embedded operating system to implement the network protocol stack and FAT file system. Core0 reads shared memory data for navigation message parsing and PVT solution, receives external control instructions, outputs NMEA, RTCM protocols and other formats of protocols, configures Core1's capture and tracking parameters in a shared memory manner, receives RTCM data to achieve RTK positioning, and implements system upgrades, data backup and recovery, and log storage.

[0016] like Figure 2 As shown, the data processing process between Core0 and Core1 includes: Core0 sends a capture command to Core1, Core1 starts the channel module, controls the pseudo code generator to generate pseudo code, and starts the capture module; The programmable logic part completes the signal search through the capture module matched filter and FFT, while Core0 maintains and refreshes the capture and tracking status of the channel; The programmable logic part determines whether the search is successful. If successful, Core1 obtains the signal code phase data and Doppler shift data, and completes the loop filter parameter calculation and loop control. Then the programmable logic part processes the NCO of the signal code and the NCO (digital control oscillator) of the signal carrier through the tracking channel module to complete the signal synchronization tracking. At the same time, Core0 performs the channel capture and tracking status maintenance and refresh; Core1 completes bit synchronization, frame synchronization, message decoding and analysis. Core0 obtains the message sent by Core1, and at the same time obtains the pseudo code NCO count, bit count, frame calculation and carrier NCO count sent by the programmable logic part to perform positioning, speed measurement and timing operations. Core0 sends the set local time to the programmable logic part. The programmable logic part completes the internal time counting through the TIC module, generates an observation sampling interrupt signal to the tracking channel module, and Core0 performs data protocol framing and output.

[0017] like Figure 3 As shown in the figure, the Beidou signal first reaches the antenna module. The weak satellite signal received by the antenna is amplified by the amplifier and sent to the power divider, and then the satellite signal is split by the filter. The six satellite signals split out enter the RF chip A and RF chip B respectively, and after down-conversion, amplification and analog-to-digital conversion inside the RF chip, the digital intermediate frequency is output.

[0018] like Figure 4 As shown in the figure, the clock circuit is divided into RF clock and baseband clock. The RF clock is 10MHz and the baseband clock is 33.33MHz. The RF clock has internal and external clocks. When the FPGA detects the external clock input, it can control CTRL to complete the clock switching.

[0019] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used for various other combinations, modifications and improvements, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art do not deviate from the spirit and scope of the present invention, and should be within the scope of protection of the claims attached to the present invention.

Claims

1. A data processing method based on a single Beidou baseband processing board, characterized in that: The method is implemented by an FPGA processing chip, which includes a programmable logic part and two ARM cores, Core0 and Core1; The programmable logic part of the FPGA processing chip completes the capture and tracking of Beidou signals; The Core 1 is used for the acquisition, tracking and control of the baseband signal, and writes the generated navigation message and observation quantity into the shared memory for processing by the Core 0; The Core0 reads conformal memory data, performs navigation message parsing and PVT solution, receives external control instructions, outputs NMEA, RTCM protocols and protocols in other formats, configures the capture and tracking parameters of Core1 in a shared memory manner, receives RTCM data to achieve RTK positioning, and realizes system upgrades, data backup and recovery, and log storage.

2. The data processing method based on a single Beidou baseband processing board according to claim 1, characterized in that: The data processing process between Core0 and Core1 includes: Core0 sends a capture command to Core1, Core1 starts the channel module, controls the pseudo code generator to generate pseudo code, and starts the capture module; The programmable logic part completes the signal search through the capture module matched filter and FFT, while Core0 maintains and refreshes the capture and tracking status of the channel; The programmable logic part determines whether the search is successful. If successful, Core1 obtains the signal code phase data and Doppler shift data, and completes the loop filter parameter calculation and loop control. Then the programmable logic part processes the NCO of the signal code and the NCO of the signal carrier through the tracking channel module to complete the signal synchronization tracking. At the same time, Core0 performs the channel capture and tracking status maintenance and refresh; Core1 completes bit synchronization, frame synchronization, telegram decoding and parsing, and then performs subsequent data processing through Core0.

3. The data processing method based on a single Beidou baseband processing board according to claim 2 is characterized in that: The subsequent data processing by Core0 includes: Core0 obtains the message sent by Core1, and at the same time obtains the pseudo code NCO count, bit count, frame calculation and carrier NCO count sent by the programmable logic part to perform positioning, speed measurement and timing operations; Core0 sends the set local time to the programmable logic part. The programmable logic part completes the internal time counting through the TIC module, generates an observation sampling interrupt signal to the tracking channel module, and Core0 performs data protocol framing and output.

4. A single Beidou baseband processing board, comprising an FPGA processing chip and peripheral circuits connected thereto, characterized in that: The FPGA processing chip includes a programmable logic part and two ARM cores, Core0 and Core1; The programmable logic part completes the capture and tracking of Beidou signals; The Core 1 is used for the acquisition, tracking and control of the baseband signal, and writes the generated navigation message and observation quantity into the shared memory for processing by the Core 0; The Core0 reads conformal memory data, performs navigation message parsing and PVT solution, receives external control instructions, outputs NMEA, RTCM protocols and protocols in other formats, configures the capture and tracking parameters of Core1 in a shared memory manner, receives RTCM data to achieve RTK positioning, and realizes system upgrades, data backup and recovery, and log storage.

5. The single Beidou baseband processing board according to claim 4, characterized in that: The data processing process between Core0 and Core1 includes: Core0 sends a capture command to Core1, Core1 starts the channel module, controls the pseudo code generator to generate pseudo code, and starts the capture module; The programmable logic part completes the signal search through the capture module matched filter and FFT, while Core0 maintains and refreshes the capture and tracking status of the channel; The programmable logic part determines whether the search is successful. If successful, Core1 obtains the signal code phase data and Doppler shift data, and completes the loop filter parameter calculation and loop control. Then the programmable logic part processes the NCO of the signal code and the NCO of the signal carrier through the tracking channel module to complete the signal synchronization tracking. At the same time, Core0 performs the channel capture and tracking status maintenance and refresh; Core1 completes bit synchronization, frame synchronization, telegram decoding and parsing, and then performs subsequent data processing through Core0.

6. The single Beidou baseband processing board according to claim 5, characterized in that: The subsequent data processing by Core0 includes: Core0 obtains the message sent by Core1, and at the same time obtains the pseudo code NCO count, bit count, frame calculation and carrier NCO count sent by the programmable logic part to perform positioning, speed measurement and timing operations; Core0 sends the set local time to the programmable logic part. The programmable logic part completes the internal time counting through the TIC module, generates an observation sampling interrupt signal to the tracking channel module, and Core0 performs data protocol framing and output.

7. The single Beidou baseband processing board according to claim 4, characterized in that: The peripheral circuit includes a power supply part, a radio frequency part, an interface part, an RTC and a clock part connected to the FPGA processing chip; the interface part includes a network interface, a USB interface, and an RS422 / 232 interface.

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