Timing method, equipment and timing system

Abstract

The invention provides a timing method, equipment and a timing system, belongs to the technical field of timing, and can remarkably shorten the time consumption of a fine timing process and improve the timing efficiency. According to the method, the time of at least one of the following stages in the transmission process of the pulse signal to be measured can be accurately timed: in the first stage, the target equipment generates the pulse signal to be measured and transmits the pulse signal to be measured; and in the second stage, the target equipment detects the reflected pulse signal to be detected until the target equipment receives the reflected pulse signal to be detected. And in the third stage, the target device sends the pulse signal to be measured to the received reflected pulse signal to be measured.

Description

Technical Field

[0001] The present invention relates to the field of timing technology, and in particular to a timing method, device and timing system. Background Art

[0002] In the technology of determining distance by measuring the propagation time of pulse signals such as laser or sound waves, the timing system is used to accurately record the time from the target device transmitting the pulse signal to the time it receives the pulse signal to be measured, so that the product of the timing time and the signal propagation speed is used as the distance measurement result.

[0003] With the rapid development of digital cities, assisted driving, and smart transportation, the measurement results of laser ranging and radar detection are required to have higher accuracy. For example, the time consumption of some stages in the process of pulse signal generation, transmission, reflection, detection, and reception is in the picosecond level, and the timing system needs to perform high-precision (high-resolution) fine timing. However, in the existing timing methods, the fine timing process takes a long time, resulting in low timing efficiency. Summary of the invention

[0004] The present invention provides a timing method, a device and a timing system, which can significantly shorten the time consumption of a precise timing process and improve the timing efficiency.

[0005] In order to achieve the above object, the present invention adopts the following technical solution:

[0006] In the first aspect, the present invention provides a timing system, including: for timing a pulse signal to be measured, the timing system includes: a control module, a fine timing module and a timing solution module connected in sequence; the fine timing module includes a plurality of delay coding unit groups connected in sequence, and each delay coding unit group includes a plurality of delay coding units connected in sequence. The control module is used to control the fine timing module to output a first timing code when the pulse signal to be measured and the first clock signal are in a preset state; the pulse signal to be measured is input from the first input end of the fine timing module, and the first clock signal is input from the second input end of the fine timing module, and the control module is connected to the first input end of the fine timing module; the first timing code includes the state code of each delay coding unit in the fine timing module into which the pulse signal to be measured flows. The timing solution module is used to obtain the first timing code output by the fine counting module, and extract the first simplified code and the first critical code from the first timing code; and parse the first simplified code and the first critical code to obtain the first time, which is the time between the target device generating the pulse signal to be measured and transmitting the pulse signal to be measured. Among them, the first simplified code includes a state code for indicating the state of a delay coding unit group into which a pulse signal to be tested flows, and the first critical code includes the state codes of multiple delay coding units in a critical coding unit group in the delay coding unit group into which a pulse signal to be tested flows, and the time for the pulse signal to be tested to flow through each delay coding unit is equal.

[0007] The timing system provided by the present invention does not need to parse the first timing code representing the state of each delay coding unit in the fine timing module where the pulse signal to be tested flows in during the process of determining the first time. Instead, it only needs to parse the first simplified code describing the state of the delay coding unit group into which the pulse signal to be tested flows, and the first critical code describing the state of multiple delay coding units in the critical coding unit group. Compared with the first timing code, the length of the first simplified code and the first critical code extracted from the first timing code is shorter. In this way, the first simplified code and the first critical code can be quickly parsed, thereby significantly shortening the time consumption of the fine timing process and improving the timing efficiency.

[0008] In an implementation of the first aspect, the preset state is that the pulse signal to be tested is at a high level and the first clock signal is at a rising edge. The target device transmits the pulse signal to be tested at the rising edge of the pulse signal to be tested, and the target device receives the reflected pulse signal to be tested at the rising edge of the reflected pulse signal to be tested.

[0009] In an implementation of the first aspect, the timing solution module is specifically used to obtain a state code after the state code of the critical coding unit group from the first simplified code to obtain a first valid state code; and obtain a state code identical to the first valid state code from the first critical code to obtain a second valid state code. The first timing is determined according to the time when the pulse signal to be tested flows through each delay coding unit and the first valid state code. The second timing is determined according to the time when the pulse signal to be tested flows through each delay coding unit and the second valid state code; the first time is the sum of the first timing and the second timing.

[0010] In an implementation of the first aspect, each delay coding unit in the fine timing module includes a delayer and a first register, the first input end of the first register is connected to the output end of the delayer; the input end of the delayer in the first delay coding unit in the fine timing module is coupled to the first input end of the fine timing module, the second input end of the first register is coupled to the second input end of the fine timing module; the output end of the first register is coupled to the output end of the fine timing module. Multiple delayers in the fine timing module are connected in series in sequence to form a carry chain, the output end of each delayer is connected to the input end of the next delayer, the pulse signal to be tested flows into each delayer in the carry chain in sequence, and the output end of each delayer outputs the pulse signal to be tested; the output end of each first register outputs the state code of each delay coding unit.

[0011] In an implementation of the first aspect, the control module is further used to control the fine timing module to output a second timing code when the reflected pulse signal to be tested and the second clock signal are in a preset state. The timing resolution module is also used to obtain the second timing code output by the fine counting module, and extract the second simplified code and the second critical code from the second timing code; and parse the second simplified code and the second critical code to obtain a second time, which is the time from when the target device detects the reflected pulse signal to when the target device receives the reflected pulse signal to be tested. The second simplified code includes a status code for indicating the status of multiple delay coding unit groups, and the second critical code includes the status codes of multiple delay coding units in the critical coding unit group in the multiple delay coding unit groups.

[0012] In an implementation of the first aspect, the timing system further includes a coarse timing module connected to the control module and the timing solution module, the input end of the coarse timing module is connected to the control module, and the output end of the coarse timing module is connected to the timing solution module; the coarse timing module includes a second register and a timer connected to the second register, the first input end of the second register is coupled to the input end of the coarse timing module, the second input end of the second register is connected to the output end of the timer, and the output end of the second register is coupled to the output end of the coarse timing module. The control module is also used to control the second register of the coarse timing module to register the first count of the timer at the rising edge / falling edge of the pulse signal to be measured; and control the second register of the coarse timing module to register the second count of the timer at the rising edge / falling edge of the reflected pulse signal to be measured. The timing solution module is also used to obtain the first count and the second count output by the coarse timing module, and determine the third time according to the first count and the second count, and the third time is the time between the target device transmitting the pulse signal to be measured and receiving the reflected pulse signal to be measured.

[0013] In an implementation of the first aspect, the timing solution module is also used to determine the time between the target device generating the pulse signal to be tested and the target device receiving the reflected pulse signal to be tested based on the third time and the first time; or, to determine the time between the target device transmitting the pulse signal to be tested and detecting the reflected pulse signal to be tested based on the third time and the second time.

[0014] In an implementation manner of the first aspect, the timing system includes multiple fine timing modules.

[0015] In a second aspect, the present invention provides a timing device, which includes a controller, a processor, a delay device, a register, and a timer. Each device in the timing device is used to implement the functions of each module in the above-mentioned timing system.

[0016] In a third aspect, the present invention provides a timing method, which is performed by the timing device to time at least one of the following stages in the transmission process of the pulse signal to be measured:

[0017] In the first stage, the target device generates a pulse signal to be tested and transmits the pulse signal to be tested;

[0018] In the second stage, the target device detects the reflected pulse signal to be tested and the target device receives the reflected pulse signal to be tested;

[0019] In the third stage, the target device transmits a pulse signal to be tested until it receives a reflected pulse signal to be tested.

[0020] In a fourth aspect, the present invention provides a computer-readable storage medium, comprising computer program instructions, which, when executed by a computer, enable the computer to execute the method in the first aspect or any one of its implementations.

[0021] In a fifth aspect, the present invention provides a computer program product, comprising computer program instructions, which, when executed on a computer, enable the computer to execute the method in the first aspect or any one of its implementations.

[0022] The technical effects corresponding to the above-mentioned second to fifth aspects and their possible implementations can refer to the above-mentioned description of the technical effects of the first aspect and its possible implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a schematic diagram of an application scenario of a timing system provided in an embodiment of the present application;

[0024] Figure 2 This is one of the schematic diagrams of the architecture of a timing system provided in an embodiment of the present application;

[0025] Figure 3 It is a first timing coding schematic diagram provided in an embodiment of the present application;

[0026] Figure 4 This is the second schematic diagram of the architecture of a timing system provided in an embodiment of the present application;

[0027] Figure 5 This is a third schematic diagram of the architecture of a timing system provided in an embodiment of the present application;

[0028] Figure 6 This is a fourth schematic diagram of the architecture of a timing system provided in an embodiment of the present application;

[0029] Figure 7 This is a fifth schematic diagram of the architecture of a timing system provided in an embodiment of the present application;

[0030] Figure 8 This is one of the schematic diagrams of the transmission process of the pulse signal to be tested provided in the embodiment of the present application;

[0031] Fig. 9 This is the second schematic diagram of the transmission process of the pulse signal to be tested provided in the embodiment of the present application;

[0032] Fig.10 This is the sixth architectural diagram of a timing system provided in an embodiment of the present application;

[0033] Fig.11 It is a schematic diagram of the architecture of a timing device provided in an embodiment of the present application;

[0034] Among them, 1-control module, 2-fine timing module, 21-delay coding unit group, 211-delay coding unit, 2111-delay, 2112-first register, 3-timing solution module, 4-clock network, 5-coarse timing module, 51-timer, 52-second register. DETAILED DESCRIPTION

[0035] The terms "first" and "second" etc. in the description and claims of the present invention are used to distinguish different objects rather than to describe a specific order of the objects.

[0036] "And / or" in the embodiments of the present application indicates the relationship between objects. For example, the first clock signal and / or the second clock signal can represent the following three situations: the first clock signal exists alone, the second clock signal exists alone, and the first clock signal and the second clock signal exist at the same time.

[0037] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0038] In the description of the present invention, unless otherwise specified, the meaning of "multiple" refers to two or more. For example, multiple delay coding unit groups refer to two or more delay coding unit groups, and multiple delay coding units refer to two or more delay coding units.

[0039] The timing method, device and timing system provided in the embodiments of the present application can be used to precisely time the propagation process of the laser or sound wave waiting to be tested pulse signal. Specifically, multiple delay coding units are used to precisely time the transmission process of the pulse signal to be tested, and the timing time is obtained by parsing the timing codes generated by the multiple delay coding units. Among them, the transmission process of the pulse signal to be tested may include multiple stages from the generation, emission, detection to reception of the pulse signal to be tested, and some of these stages take picoseconds, that is, the above-mentioned precise timing can achieve timing of picoseconds or even shorter time periods than picoseconds.

[0040] It is understandable that in scenarios where distance is determined by measuring the propagation time of pulse signals such as lasers or sound waves, the timing method provided in the embodiments of the present application can be used for high-precision distance measurement. For example, it can be used to build three-dimensional city models, restore cultural relics, or assist driving.

[0041] Exemplary, reference Figure 1When the embodiment of the present application is used for assisted driving, the distance between vehicle C1 and vehicle C2 is measured by a target device (e.g., a laser radar) mounted on the outside of the front of vehicle C1, where L1 represents the transmission distance of the signal from the target device generating the pulse signal to be measured to the transmission of the pulse signal to be measured, and L2 represents the distance between the target device and vehicle C2. Figure 1 It can be seen that the sum of L1 and L2 is closer to the actual distance between vehicle C1 and vehicle C2 than L2. On this basis, the embodiment of the present application can perform fine timing on the stage from the target device generating the pulse signal to the stage from the stage of transmitting the pulse signal to be tested to determine L1, and then use the sum of L1 and L2 as the distance measurement result between vehicle C1 and vehicle C2.

[0042] On the basis of the above content, in order to solve the defect that the fine timing process takes a long time and leads to low timing efficiency in the timing method described in the background technology, the embodiment of the present application provides a timing method, device and timing system, which adopts a fine timing module composed of delay coding units for fine timing, and simplifies the first timing code output by the fine timing module into a first simplified code and a first critical code through a timing solution module, and then solves the first simplified code and the first critical code through the timing solution module to obtain the first time from generating the pulse signal to be tested to transmitting the pulse signal to be tested. In the embodiment of the present application, in the process of determining the first time, it is not necessary to parse the first timing code representing the state of each delay coding unit in the fine timing module into which the pulse signal to be tested flows, but only the first simplified code describing the state of the delay coding unit group into which the pulse signal to be tested flows, and the first critical code describing the state of multiple delay coding units in the critical coding unit group need to be parsed. Compared with the first timing code, the length of the first simplified code and the first critical code extracted from the first timing code is shorter, so that the first simplified code and the first critical code can be quickly parsed, thereby significantly shortening the time consumption of the fine timing process and improving the timing efficiency.

[0043] The timing system provided in the embodiment of the present application can time the pulse signal to be tested, especially to perform precise timing on the transmission process of the pulse signal to be tested; it can be understood that the transmission process of the pulse signal to be tested includes the following stages;

[0044] In the first stage, the target device generates a pulse signal to be tested and transmits the pulse signal to be tested;

[0045] In the second stage, the target device detects the reflected pulse signal to be tested and the target device receives the reflected pulse signal to be tested;

[0046] In the third stage, the target device transmits a pulse signal to be tested until it receives a reflected pulse signal to be tested.

[0047] like Figure 2 As shown, an embodiment of the present application provides a timing system, which includes a control module 1, a fine timing module 2 and a timing solution module 3 connected in sequence;

[0048] The fine timing module 2 includes a first input terminal and a second input terminal, and the control module 1 is connected to the first input terminal of the fine timing module; wherein the first input terminal of the fine timing module 2 inputs a pulse signal to be measured, and the second input terminal of the fine timing module 2 inputs a first clock signal; optionally, the pulse signal to be measured can be generated by the control module 1;

[0049] Continue to refer Figure 2 , the fine timing module 2 in the timing system includes a plurality of delay coding unit groups 21 connected in sequence, and each delay coding unit group 21 includes a plurality of delay coding units 211 connected in sequence; wherein, the first input end of the first delay coding unit group 21 is coupled to the first input end of the fine timing module 2 (i.e., one input signal of the first delay coding unit group 21 is a pulse signal to be measured), and the second input end of each delay coding unit group is coupled to the second input end of the fine timing module (i.e., another input signal of each delay coding unit group 21 is a first clock signal); the last delay coding unit 211 in one delay coding unit group 21 is connected to the first delay coding unit 211 in the next delay coding unit group 21;

[0050] The above timing system can be used to time the first stage of the transmission process of the pulse signal to be measured, which is a fine timing stage; Figure 2 The functions of each module of the timing system shown are described in detail.

[0051] The control module 1 is used to control the fine timing module 2 to output a first timing code when the pulse signal to be measured and the first clock signal are in a preset state, and the first timing code includes a state code of each delay coding unit 211 in the fine timing module 2 into which the pulse signal to be measured flows;

[0052] Optionally, the preset states of the pulse signal to be measured and the first clock signal are: the pulse signal to be measured is at a high level and the first clock signal is at a rising edge; in the embodiment of the present application, the target device transmits the pulse signal to be measured at the rising edge of the pulse signal to be measured, and the target device receives the reflected pulse signal to be measured at the rising edge of the reflected pulse signal to be measured;

[0053] Of course, the above-mentioned preset state may also be defined as other states. For example, the above-mentioned preset state may also be any one of the following preset states 1 or 3;

[0054] Preset state 1. The pulse signal to be tested is at a high level and the first clock signal is at a falling edge; the target device transmits the pulse signal to be tested at the rising edge of the pulse signal to be tested, and the target device receives the reflected pulse signal to be tested at the rising edge of the reflected pulse signal to be tested;

[0055] Preset state 2. The pulse signal to be tested is at a low level and the first clock signal is at a rising edge; the target device transmits the pulse signal to be tested at the falling edge of the pulse signal to be tested, and the target device receives the reflected pulse signal to be tested at the falling edge of the reflected pulse signal to be tested;

[0056] Preset state 3. The pulse signal to be tested is at a low level and the first clock signal is at a falling edge; the target device transmits the pulse signal to be tested at the falling edge of the pulse signal to be tested, and the target device receives the reflected pulse signal to be tested at the falling edge of the reflected pulse signal to be tested;

[0057] In the following embodiments, the preset state is that the pulse signal to be tested is at a high level and the first clock signal is at a rising edge.

[0058] Based on the description of the above embodiments, the timing system provided by the embodiment of the present application includes a plurality of delay coding unit groups 21, that is, a plurality of delay coding units 211 connected in sequence. After the pulse signal to be measured flows into the delay coding unit group 21, it flows into each delay coding unit 211 in sequence; in the embodiment of the present application, after the pulse signal to be measured is generated, it is emitted when the pulse signal to be measured reaches the rising edge; in the process of timing the stage from generation to emission of the pulse signal to be measured, after the pulse signal to be measured is generated, the pulse signal to be measured is controlled to flow into the delay coding unit group 21 in the fine timing module 2 in sequence; in this process, the delay coding unit 211 in the first part of the delay coding unit group 21 has the signal to be measured flowing into it, and the delay coding unit 211 in the second part of the delay coding unit group 21 may not have the pulse signal to be measured flowing into it. Based on this, the transmission time of the pulse signal to be measured in the fine timing module 2 can be obtained according to the number of delay coding units 211 into which the pulse signal to be measured flows and the time when the pulse signal to be measured flows through each delay coding unit 211;

[0059] In the embodiment of the present application, after the pulse signal to be measured flows into the fine timing module 2, when the pulse signal to be measured is at a high level and the first clock signal reaches a rising edge, the fine timing module 2 outputs the state code of all delay coding units 211 into which the pulse signal to be measured flows, and obtains a first timing code;

[0060] Optionally, the state code of the delay coding unit 211 can be represented by 1 bit, for example, it can be represented by "1" or "0", wherein "1" indicates that the rising edge of the pulse signal to be measured passes through the delay coding unit 211, and "0" indicates that the rising edge of the pulse signal to be measured does not pass through the delay coding unit; Figure 3 , assuming that the fine timing module 2 outputs the first timing code consisting of the state code of the 48-bit delay coding unit 211, it can be seen that the rising edge of the pulse signal to be measured flows into the first 25 delay coding units 211;

[0061] Optionally, the time for the pulse signal to be tested to flow through each delay coding unit 211 is equal. For example, the time for the signal to flow through each delay coding unit 211 may be 8 ps or 15 ps. For ease of description, the time for the pulse signal to be tested to flow through each delay coding unit 211 is referred to as unit delay time.

[0062] Based on the above content, it can be known that in the first timing code, the product of the length of the state code of the delay coding unit 211 coded as 1 and the unit delay time is the time when the rising edge of the pulse signal to be tested flows into the fine timing module 2; the product of the length of the state code of the delay coding unit 211 with a value of 0 in the first timing code and the unit delay time is the time from the generation of the pulse signal to be tested to the arrival of the rising edge of the pulse signal to be tested; after the pulse signal to be tested is generated, since the target device only transmits the pulse signal to be tested at the rising edge of the pulse signal to be tested, the time from the generation of the pulse signal to be tested to the arrival of the rising edge of the pulse signal to be tested is the time from the generation of the pulse signal to be tested to the transmission of the pulse signal to be tested (i.e., the first time);

[0063] The timing solution module 3 is used to obtain the first timing code output by the above-mentioned fine counting module, and extract the first simplified code and the first critical code from the first timing code, wherein the first simplified code includes a state code for indicating the state of the delay coding unit group 21 into which the pulse signal to be tested flows, and the first critical code includes the state code of multiple delay coding units 211 of the critical coding unit group in the delay coding unit group 21 into which the pulse signal to be tested flows; and the first simplified code and the first critical code are analyzed to obtain the first time, which is the time between the target device generating the pulse signal to be tested and transmitting the pulse signal to be tested (i.e., the timing result of the above-mentioned first stage);

[0064] It should be understood that the above-mentioned first simplified code is used to describe the state of multiple delay coding unit groups 21 into which the pulse signal to be tested flows, and the above-mentioned first critical code is used to describe the state of multiple delay coding units 211 in the critical coding unit group 21; wherein, in the critical coding unit group, the rising edge of the pulse signal to be tested flows through some of the delay coding units 211, and the rising edge of the pulse signal to be tested does not flow through some of the delay coding units 211 (that is, the low level of the pulse signal to be tested flows through some of the delay coding units 211), then there are two types of state codes in the critical coding unit group (1 and 0), thus, it can be known that the first critical code is composed of the state code (1) of the delay coding unit 211 through which the rising edge of the pulse signal to be tested passes, and the state code (0) of the delay coding unit 211 through which the rising edge of the pulse signal to be tested does not pass;

[0065] For each delay coding unit group 21, a state code of a delay coding unit 211 in the delay coding unit group 21 is extracted from the first timing code as a state code indicating the state of the delay coding unit group 21, thereby obtaining a first simplified code indicating the states of the plurality of delay coding unit groups 21; illustratively, refer to Figure 3 , if a delay coding unit group 21 includes 16 delay coding units 211, then in the first timing code, one state code is extracted from each 16-bit state code corresponding to a delay coding unit group. For example, the state code at the first position in each 16-bit state code can be extracted as the state code of the delay coding unit group 21, thereby obtaining a first simplified code, such as Figure 3 110; optionally, the state code at the last bit or other position in the 16-bit state code can also be extracted as the state code of the delay coding unit group 21, which is not limited in the embodiment of the present application;

[0066] In the above-mentioned first simplified code, when the state code changes, the state code at the critical point where the change occurs is used as the critical code (the state code is the same as the state code of the previous bit and different from the state code of the next bit), and then the state code of the 16-bit delay code unit 211 of the delay code unit group 21 in the first timing code corresponding to the critical code is extracted to obtain the first critical code; for example, if the first simplified code is 110, the critical code is the second bit (i.e., 1) in the first simplified code, and the first critical code extracted from the first timing code is Figure 3 1111111110000000 shown in

[0067] The timing calculation module 3 is specifically used to obtain a first valid state code that is the same as a state code (1 or 0) of the critical code unit group from the first simplified code; then obtain a second valid state code that is the same as the first valid state code from the first critical code; and then calculate the first time (i.e., obtain the timing result of the first stage) according to the first valid state code and the second valid state code;

[0068] Based on the description of the above embodiment, it can be known that when the pulse signal to be measured is at a high level and the first clock signal reaches the rising edge, the first timing code is output; it can be known from the fact that the pulse signal to be measured is at a high level when the first timing code is output that the rising edge of the pulse signal to be measured has entered the fine timing module 2 when the first timing code is output; and since the first timing code includes the status code of each delay coding unit 211 in the fine timing module 2 into which the pulse signal to be measured flows, it means that the first timing code includes the status code (1) of the delay coding unit 211 through which the rising edge of the pulse signal to be measured passes and the status code (0) of the rising edge of the pulse signal to be measured not passing through the delay coding unit 211;

[0069] On this basis, since the time from when the pulse signal to be tested is generated to when the pulse signal to be tested reaches the rising edge is the time from when the pulse signal to be tested is generated to when the pulse signal to be tested is emitted (i.e., the first time), the state code of the delay coding unit 211 before the rising edge of the pulse signal to be tested in the first timing code arrives (i.e., the state code (0) that the rising edge of the pulse signal to be tested has not passed through the delay coding unit 211) indicates the first time;

[0070] Therefore, the first simplified code and the first critical code extracted from the first timing code can be processed to obtain the number of delay code units 211 (i.e., the state code with a value of 0 in the first timing code) into which the rising edge of the pulse signal to be tested in the first timing code does not flow; the product of the number of delay code units 211 into which the rising edge of the pulse signal to be tested in the first timing code does not flow and the unit delay time is the first time;

[0071] In one implementation, the timing solution module 3 is specifically used to:

[0072] Acquire a state code after the state code of the critical coding unit group from the first simplified code to obtain a first valid state code; and acquire a state code identical to the first valid state code from the first critical code to obtain a second valid state code;

[0073] According to the unit delay time and the first valid state code, the product of the unit delay time, the length of the first valid state code and the number of delay coding units 211 in each delay coding unit group 21 is determined as a first timing;

[0074] According to the waiting unit delay time and the second valid state code, the product of the unit delay time and the length of the second valid state code is determined as a second timing;

[0075] The sum of the first timing and the second timing is the time from when the pulse signal to be measured flows into the fine timing module 2 to when the rising edge of the pulse signal to be measured arrives, and the time during which the pulse signal to be measured is transmitted in the fine timing module 2, that is, the first time from when the pulse signal to be measured is generated to when it is emitted, that is, the first time is the sum of the first timing and the second timing;

[0076] For example, continue to refer to Figure 3 , when the first valid state code is the state code after the state code of the critical coding unit group, according to Figure 3 It can be obtained that the first valid state code is 0 (corresponding to the state code 00000000000000000 of the rightmost 16-bit critical coding unit in the first timing code), the length of the first valid state code is 1, the number of delay coding units 211 in each delay coding unit group 21 is 16, and the unit delay time is 10ps, then the first timing is 1×16×10ps; the second valid state code is the same state code as the first valid state code in the first critical code, according to Figure 3 The second valid state code is 0000000, and the length of the second valid state code is 7, so the second timing is 7×10ps;

[0077] It can be seen that the first valid state code and the second valid state code record the duration corresponding to the state code of the delay coding unit 211 whose value is 0 in the first timing code, and the sum of the first timing and the second timing is 230ps, which is the first time;

[0078] In another implementation, the timing solution module 3 is specifically used for:

[0079] Obtaining a state code before the state code of the critical coding unit group from the first simplified code to obtain a first valid state code; and obtaining a state code identical to the first valid state code from the first critical code to obtain a second valid state code;

[0080] According to the unit delay time and the first valid state code, the product of the unit delay time, the length of the first valid state code and the number of delay coding units 211 in each delay coding unit group 21 is determined as a first timing;

[0081] According to the unit delay time and the second valid state code, the product of the unit delay time and the length of the second valid state code is determined as a second timing;

[0082] The product of the unit delay time and the first timing code is determined as a third timing, wherein the third timing is the total transmission time of the pulse signal to be tested in the delay coding unit group 21 from the generation of the pulse signal to the rising edge of the pulse signal to be tested reaching and flowing into the delay coding unit group 21;

[0083] The sum of the first timing and the second timing is the transmission time of the rising edge of the pulse signal to be measured in the delay coding unit group 21;

[0084] The timing difference obtained by subtracting the sum of the first timing and the second timing from the third timing is the time when the pulse signal to be tested flows into the delay coding unit group 21 and the rising edge of the pulse signal to be tested arrives, and the pulse signal to be tested is transmitted in the delay coding unit group 21, that is, the first time;

[0085] For example, continue to refer to Figure 3 , when the first valid state code is the state code before the state code of the critical coding unit group, according to Figure 3 The first valid state code is 1 (corresponding to the state code 11111111111111111 of the leftmost 16-bit critical code unit in the first timing code), and the first timing is 1×16×10ps; when the second valid state code is the same as the first valid state code in the first critical code, according to Figure 3 The second valid state code is 111111111, the second timing is 9×10ps, and the third timing is 48×10ps, which is the total duration of the first timing coding record.

[0086] It can be seen that the duration corresponding to the state code of the delay coding unit 211 with a value of 1 in the first timing code (i.e., the sum of the first timing and the second timing) can be obtained by subtracting the duration corresponding to the state code of the delay coding unit 211 with a value of 0 in the first timing code (i.e., the first time); therefore, the first time is 48×10 ps-1×16×10 ps-9×10 ps=230 ps;

[0087] In the timing method provided in the embodiment of the present application, a fine timing module composed of delay coding units is used for fine timing, and the first timing code output by the fine timing module is simplified into a first simplified code and a first critical code by a timing solution module, and then the first simplified code and the first critical code are solved by the timing solution module to obtain the first time from the generation of the pulse signal to be tested to the emission of the pulse signal to be tested. In the embodiment of the present application, in the process of determining the first time, it is not necessary to parse the first timing code representing the state of each delay coding unit in the fine timing module into which the pulse signal to be tested flows, but only the first simplified code describing the state of the delay coding unit group into which the pulse signal to be tested flows, and the first critical code describing the state of multiple delay coding units in the critical coding unit group need to be parsed. Compared with the first timing code, the length of the first simplified code and the first critical code extracted from the first timing code is shorter, so that the first simplified code and the first critical code can be parsed more quickly, thereby significantly shortening the time consumption of the fine timing process and improving the timing efficiency.

[0088] Optionally, combined Figure 2 ,like Figure 4 As shown, the timing system further includes a clock network 4, which is used to provide a clock signal; for example, the second input terminal of the fine timing module 2 is connected to the output terminal of the clock network 4, and at this time, the clock network 4 provides a first clock signal to the fine timing module 2;

[0089] Combination Figure 4 ,like Figure 5 As shown, each delay coding unit 211 in the fine timing module 2 includes a delayer 2111 and a first register 2112, and the first input end of the first register 2112 is connected to the output end of the delayer 2111; the input end of the delayer 2111 in the first delay coding unit 211 in the fine timing module 2 is coupled to the first input end of the fine timing module 2 (i.e., receiving the pulse signal to be measured output by the control module 1), the second input end of the first register 2112 is coupled to the second input end of the fine timing module 2 (i.e., receiving the first clock signal output by the clock network 4), and the output end of the first register 2112 is coupled to the output end of the fine timing module 2 (i.e., Figure 5 The output ends of all the first registers 2112 together constitute the output end of the fine timing module 2);

[0090] On this basis, continue to refer to Figure 5, the multiple delayers 2111 in the fine timing module 2 are connected in series in sequence to form a carry chain, the output end of each delayer 2111 is connected to the input end of the next delayer 2111, the pulse signal to be measured flows into each delayer 2111 in the carry chain in sequence, and the output end of each delayer 2111 outputs the pulse signal to be measured; the output end of each first register 2112 outputs the state code of each delay encoding unit 211; Figure 5 It can be seen that the state codes of all delay coding units 211 output by the fine timing module 2 constitute the first timing code. Figure 4 The state codes output by the first registers 2112 are (Q1, Q2, ..., Q i-1 ,Q i …), the first timing code is Q1Q2…Q i-1 Q i …;

[0091] In the embodiment of the present application, the above timing system can be used to time the second stage of the transmission process of the pulse signal to be tested (the stage from when the pulse signal to be tested is reflected from another device to when the target device detects the pulse signal to be tested to when the target device receives the pulse signal to be tested), and this timing stage is a fine timing stage; Figure 6 The functions of each module of the timing system shown are described in detail.

[0092] The control module 1 is further used to control the fine timing module 2 to output a second timing code when the reflected pulse signal to be tested and the second clock signal are in a preset state, the second timing code including the state codes of all delay coding units 211 into which the reflected pulse signal to be tested flows;

[0093] Optionally, the preset state of the second stage is the same as the preset state of the first stage;

[0094] In the embodiment of the present application, when the target device detects the reflected pulse signal to be tested, the control module 1 controls the reflected pulse signal to be tested to flow into the fine timing module 2, and the target device receives the reflected pulse signal to be tested when the reflected pulse signal to be tested reaches the rising edge; therefore, according to the timing result from the reflected pulse signal to be tested entering the fine timing module 2 to the rising edge of the reflected pulse signal to be tested arriving, the timing result of the second stage can be obtained;

[0095] Optionally, the second clock signal may be provided by a clock network 4, and the first clock signal and the second clock signal may be the same or different;

[0096] The timing solution module 3 is also used to obtain the second timing code output by the fine counting module, and extract the second simplified code and the second critical code from the second timing code; and parse the second simplified code and the second critical code to obtain the second time; the second time is the time between the target device detecting the reflected pulse signal to be tested and the target device receiving the reflected pulse signal to be tested;

[0097] Wherein, the second simplified code includes a state code for indicating the state of multiple delay coding unit groups 21, and the second critical code includes the state code of multiple delay coding units 211 in the critical coding unit group in the multiple delay coding unit groups 21; the second simplified code includes a state code for indicating the state of the delay coding unit group 21 into which the reflected pulse signal to be tested flows, and the second critical code includes the state code of multiple delay coding units 211 in the critical coding unit group in the delay coding unit group 21 into which the reflected pulse signal to be tested flows; and the second simplified code and the second critical code are parsed to obtain a second time, which is the time between the target device detecting the reflected pulse signal to be tested and the target device receiving the reflected pulse signal to be tested (i.e., the timing result of the above-mentioned second stage);

[0098] In the embodiment of the present application, when the target device detects the reflected pulse signal to be tested, the reflected pulse signal to be tested flows into the delay coding unit group 21 in the fine timing module 2 in sequence; when the reflected pulse signal to be tested is at a high level and the second clock signal reaches the rising edge, the second timing code is output;

[0099] On this basis, the second simplified coding is used to describe the state of the multiple delay coding unit groups 21 into which the reflected pulse signal to be tested flows, and the second critical coding is used to describe the state of the multiple delay coding units 211 in the critical coding unit group; wherein, in the critical coding unit group, the rising edge of the pulse signal to be tested flows through some of the delay coding units 211, and the rising edge of the pulse signal to be tested does not flow through some of the delay coding units 211 (that is, the low level of the pulse signal to be tested flows through some of the delay coding units 211), then there are two types of state codes in the critical coding unit group (1 and 0), thus, it can be known that the second critical coding is composed of the state code (1) of the delay coding unit 211 through which the rising edge of the reflected pulse signal to be tested passes, and the state code (0) of the delay coding unit 211 through which the rising edge of the pulse signal to be tested does not pass;

[0100] The timing calculation module 3 is specifically used to obtain a third valid state code that is the same as a state code (1 or 0) of the critical code unit group from the second simplified code; then obtain a fourth valid state code that is the same as the third valid state code from the second critical code; and then calculate the second time (i.e., obtain the timing result of the second stage) according to the third valid state code and the fourth valid state code;

[0101] Based on the description of the above embodiment, it can be known that when the reflected pulse signal to be measured is at a high level and the second clock signal reaches the rising edge, the second timing code is output; it can be known from the fact that the reflected pulse signal to be measured is at a high level when the second timing code is output that the rising edge of the pulse signal to be measured has entered the fine timing module 2 when the second timing code is output, which means that the second timing code includes the state code (1) of the delay coding unit 211 that the rising edge of the pulse signal to be measured passes through and the state code (0) of the rising edge of the pulse signal to be measured not passing through the delay coding unit 211;

[0102] On this basis, since the time from when the reflected pulse signal to be tested is detected to when the reflected pulse signal to be tested reaches the rising edge is the time between when the target device detects the reflected pulse signal to be tested and when the target device receives the reflected pulse signal to be tested (i.e., the second time), the state code of the delay coding unit 211 before the rising edge of the reflected pulse signal to be tested in the second timing code arrives (i.e., the state code (0) that the rising edge of the reflected pulse signal to be tested has not passed through the delay coding unit 211) indicates the second time;

[0103] Therefore, the second simplified code and the second critical code extracted from the second timing code can be processed to obtain the number of state codes (i.e., the number of state codes with a value of 0 in the second timing code) of the delay coding unit 211 into which the rising edge of the pulse signal to be tested in the second timing code does not flow; the product of the number of delay coding units 211 into which the rising edge of the pulse signal to be tested in the second timing code does not flow and the unit delay time is the second time;

[0104] In one implementation, the timing solution module 3 is specifically used to obtain a state code after the state code of the critical coding unit group from the second simplified code to obtain a third valid state code; and obtain a state code that is the same as the first valid state code from the second critical code to obtain a fourth valid state code;

[0105] According to the unit delay time and the third valid state code, a product of the unit delay time, the length of the third valid state code, and the number of delay coding units 211 in each delay coding unit group 21 is determined as a fourth timing;

[0106] According to the waiting unit delay time and the fourth valid state code, the product of the unit delay time and the length of the fourth valid state code is determined as a fifth timing;

[0107] The sum of the fourth timing and the fifth timing is the time from when the reflected pulse signal to be measured flows into the fine timing module 2 to when the rising edge of the pulse signal to be measured arrives, and the reflected pulse signal to be measured is transmitted in the fine timing module 2, that is, the second time from when the reflected pulse signal to be measured is generated to when it is emitted, that is, the second time is the sum of the fourth timing and the fifth timing;

[0108] In another implementation, the timing solution module 3 is specifically used to obtain a state code before the state code of the critical coding unit group from the second simplified code to obtain a third valid state code; and obtain a state code that is the same as the first valid state code from the second critical code to obtain a fourth valid state code;

[0109] According to the unit delay time and the first valid state code, a product of the unit delay time, the length of the third valid state code, and the number of delay coding units 211 in each delay coding unit group 21 is determined as a fourth timing;

[0110] According to the waiting unit delay time and the fourth valid state code, the product of the unit delay time and the length of the fourth valid state code is determined as a fifth timing;

[0111] The product of the unit delay time and the second timing code is determined as the sixth timing, wherein the sixth timing is the total transmission time of the reflected pulse signal to be tested in the delay coding unit group 21 from the detection of the reflected pulse signal to be tested to the rising edge of the pulse signal to be tested reaching and flowing into the delay coding unit group 21;

[0112] The sum of the fourth timing and the fifth timing is the transmission time of the rising edge of the reflected pulse signal to be tested in the delay coding unit group 21;

[0113] The timing difference obtained by subtracting the sum of the fourth timing and the fifth timing from the sixth timing is the time when the reflected pulse signal to be tested flows into the delay coding unit group 21 and the rising edge of the reflected pulse signal to be tested arrives, and the reflected pulse signal to be tested is transmitted in the delay coding unit group 21, that is, the second time;

[0114] It should be understood that the timing process of the first stage is similar to the timing process of the second stage. For the functions and timing principles of each module of the timing system in the second stage, reference may be made to the relevant description in the above embodiment.

[0115] The timing system provided in the embodiment of the present application may further include a coarse timing module 5. On this basis, the timing system may also be used to time the third stage of the transmission process of the pulse signal to be measured, which is a coarse timing stage. Figure 7 The functions of each module in the timing system shown are described in detail.

[0116] The timing system further comprises a coarse timing module 5 connected to the control module 1 and the timing solution module 3, wherein the input end of the coarse timing module 5 is connected to the control module 1, and the output end of the coarse timing module 5 is connected to the timing solution module 3; the coarse timing module 5 comprises a second register 52 connected to the control module 1, and a timer 51 connected to the second register 52; the first input end of the second register 52 is coupled to the input end of the coarse timing module 5, the second input end of the second register 52 is connected to the output end of the timer 51, and the output end of the second register 52 is coupled to the output end of the coarse timing module 5;

[0117] Optionally, the timer 51 may receive a clock signal output by the clock network 4 and perform timing based on the clock signal (ie, at each rising edge / falling edge of the clock signal, the count of the timer 51 is increased by one);

[0118] The control module 1 is also used to control the second register 52 of the coarse timing module 5 to store the first count of the timer 51 at the rising edge / falling edge of the pulse signal to be measured; and control the second register 52 of the coarse timing module 5 to store the second count of the timer 51 at the rising edge / falling edge of the reflected pulse signal to be measured;

[0119] In the embodiment of the present application, after the pulse signal to be measured is generated, the target device inputs the pulse signal to be measured into the coarse timing module 5 through the control module 1. When the pulse signal to be measured reaches the rising edge / falling edge, the target device will send the pulse signal to be measured, and the coarse timing module 5 records the moment when the pulse signal to be measured is sent (i.e., the first count) and inputs it to the timing solution module 3; after the device to be detected reflects the pulse signal to be measured, the reflected pulse signal to be measured enters the target device, and the target device inputs the reflected pulse signal to be measured into the coarse timing module 5 through the control module 1. When the pulse signal to be measured reaches the rising edge / falling edge, the target device receives the reflected pulse signal to be measured, and the coarse timing module 5 records the moment when the target device receives the reflected pulse signal to be measured (i.e., the second count) and inputs it to the timing solution module 3;

[0120] Optionally, the second register 52 may also store the first count and the second count at the falling edge of the pulse signal to be measured;

[0121] The timing solution module 3 is also used to obtain the first count and the second count output by the rough timing module 5, and determine the third time by subtracting the difference between the second count and the first count according to the first count and the second count. The third time is the time between the target device transmitting the pulse signal to be tested and receiving the reflected pulse signal to be tested, and the third time is the timing result of the third stage mentioned above;

[0122] Based on the above content of the embodiment of the present application, when the first input end of the second register 52 receives the rising edge / falling edge of the pulse signal to be tested output by the control module 1, the second input end of the second register 52 obtains the first count output by the timer 51, the first count is the time when the rising edge / falling edge of the pulse signal to be tested arrives (that is, the moment of transmitting the pulse signal to be tested can be obtained according to the first count), and the output end of the second register 52 outputs the first count to the timing solution module 3, and the timing solution module 3 obtains the time when the rising edge / falling edge of the pulse signal to be tested arrives, that is, the moment when the target device transmits the pulse signal to be tested;

[0123] When the first input end of the second register 52 receives the rising edge / falling edge of the reflected pulse signal to be measured output by the control module 1, the second input end of the second register 52 obtains the second count output by the timer 51, and the second count is the time when the rising edge / falling edge of the reflected pulse signal to be measured arrives. The output end of the second register 52 outputs the second count to the timing solution module 3, and the timing solution module 3 obtains the time when the rising / falling edge of the reflected pulse signal to be measured arrives, that is, the moment when the target device receives the reflected pulse signal to be measured;

[0124] The difference between the time when the target device receives the reflected pulse signal to be tested and the time when the target device transmits the pulse signal to be tested is the time between the target device transmitting the pulse signal to be tested and receiving the reflected pulse signal to be tested, thus realizing the timing of the third stage;

[0125] In one case, if Figure 8 As shown, after obtaining the first time (i.e., the timing result of the first stage) and the third time (i.e., the timing result of the third stage), the timing solution module 3 is further used to determine, according to the third time and the first time, the sum of the third time and the first time as the time from when the target device generates the pulse signal to be measured to when the target device receives the reflected pulse signal to be measured;

[0126] In another case, if Fig. 9 As shown, after obtaining the second time (the timing result of the second stage) and the third time (the timing result of the third stage), the timing solution module 3 is also used to determine, according to the third time and the second time, the difference obtained by subtracting the first time from the third time as the time between the target device transmitting the pulse signal to be measured (that is, the signal transmitting end transmits the pulse signal to be measured) and detecting the reflected pulse signal to be measured (that is, the signal receiving end detects the pulse signal to be measured reflected by the ranging object);

[0127] Based on the contents of the above embodiments, Figure 7 ,like Fig.10As shown, the timing system may further include a plurality of fine timing modules 2; the timing system can use the plurality of fine timing modules 2 to perform parallel measurement of a plurality of pulse signals to be measured (i.e. Fig. 9 The pulse signal to be tested 1, the pulse signal to be tested 2 ... the pulse signal to be tested i) are timed, and at the same time, multiple fine timing modules 2 can share the coarse timing module 5 for coarse timing, thereby realizing multi-channel fine timing of the timing system.

[0128] Accordingly, the embodiments of the present application provide Fig.11 The timing system shown can be implemented by a timing device with processing function, and the timing device is an embedded device implemented based on an FPGA chip; at the same time, the timing device can be located in the target device or can be independent of the target device;

[0129] For example, Fig.11 is a schematic diagram of the framework of the timing device located in the target device, such as Fig.11 As shown, the hardware part of the timing device usually includes a controller, a processor, a delay device, a register, and a timer;

[0130] The controller is used to implement the functions of the control module in the timing system, for example, to control the fine timing module to output a first timing code when the pulse signal to be measured and the first clock signal are in a preset state; to control the fine timing module to output a second timing code when the reflected pulse signal to be measured and the second clock signal are in a preset state; and to control the second register of the coarse timing module to store a first count of the timer at the rising edge / falling edge of the pulse signal to be measured; and to control the second register of the coarse timing module to store a second count of the timer at the rising edge / falling edge of the reflected pulse signal to be measured;

[0131] The processor is used to implement the functions of the timing solution module in the timing system, for example, obtaining the first timing code output by the fine counting module, and extracting the first simplified code and the first critical code from the first timing code; and parsing the first simplified code and the first critical code to obtain the first time; obtaining the second timing code output by the fine counting module, and extracting the second simplified code and the second critical code from the second timing code; and parsing the second simplified code and the second critical code to obtain the second time; obtaining the first count and the second count output by the coarse timing module, and determining the third time according to the first count and the second count; determining the time from the target device generating the pulse signal to be measured to the target device receiving the reflected pulse signal to be measured according to the third time and the first time; determining the time from the target device transmitting the pulse signal to be measured to detecting the reflected pulse signal to be measured according to the third time and the second time;

[0132] The processor / controller is a field programmable logic array (FPGA), and its resources include programmable logic units (CLBs), logic cells, distributed RAM, PLL (DCM) or other logic resources; the processor / controller can be a traditional FPGA or a Zynq series FPGA containing an ARM core;

[0133] The delayer is used to realize the function of the delay coding unit, and a plurality of delayers are arranged in the timing device; the delayer can be a transistor, an operational amplifier integrated circuit (IC) delayer or a Carry module in an FPGA;

[0134] The register is used to implement the functions of the first register and the second register, for example, to store and output the state code of the delay coding unit, and to store and output the first count and the second count of the timer; the register may be a general-purpose register (GPRs), a flip-flop (Flip Flops), etc.;

[0135] The timer is used to roughly time the signal to be measured, for example, to obtain a first count and a second count by timing; the timer may be a 555 timer, a clock chip DS1302, a clock chip PCF8563 or a clock chip DS3231, etc.; optionally, the timer may be integrated in the processor or may be independent of the processor;

[0136] Optionally, the timing device further includes a clock network, a network interface, a communication bus and a user interface;

[0137] The clock network is used to provide a clock signal, for example, a first clock signal and a second clock signal; the clock network may be a clock management unit (DCM) in the FPGA;

[0138] The network interface is used for the computer to communicate with other devices or communication networks. The network interface may be a transceiver with transceiver functions; optionally, the network interface may include a standard wired interface or a wireless interface (such as a WI-FI interface, a Bluetooth interface, or a 5G interface);

[0139] The communication bus is used to realize the connection and communication between various components. For example, the processor, memory, network interface and user interface mentioned above can be interconnected through the communication bus;

[0140] The user interface may include a display screen and an input unit (such as a keyboard). Optionally, the user interface may also include a standard wired interface and a wireless interface.

[0141] Accordingly, an embodiment of the present application provides a timing method, which is executed by the above-mentioned timing device to time at least one of the following stages in the transmission process of the pulse signal to be tested:

[0142] In the first stage, the target device generates a pulse signal to be tested and transmits the pulse signal to be tested;

[0143] In the second stage, the target device detects the reflected pulse signal to be tested and the target device receives the reflected pulse signal to be tested;

[0144] In the third stage, the target device transmits a pulse signal to be tested until it receives a reflected pulse signal to be tested;

[0145] Optionally, the timing method includes S101-S109;

[0146] S101, obtaining a first timing code, and extracting a first simplified code and a first critical code from the first timing code;

[0147] S102, obtaining a state code after the state code of the critical coding unit group from the first simplified code to obtain a first valid state code; and obtaining a state code identical to the first valid state code from the first critical code to obtain a second valid state code;

[0148] S103, determining a first timing according to the time when the pulse signal to be tested flows through each delay coding unit and the first valid state code; determining a second timing according to the time when the pulse signal to be tested flows through each delay coding unit and the second valid state code; the first time is the sum of the first timing and the second timing;

[0149] The above S101-S103 realizes the timing of the above first stage (first time), that is, the time between the target device generating the pulse signal to be tested and transmitting the pulse signal to be tested is obtained;

[0150] S104, obtaining a first count and a second count, and determining a third time by subtracting a difference between the second count and the first count according to the first count and the second count, where the third time is the time from when the target device transmits the pulse signal to be tested to when it receives the reflected pulse signal to be tested;

[0151] The above S104 can be executed by a processor in the timing device and implemented by the timing solution module 3 in the timing system; the above S104 implements the timing of the above third stage (third time), that is, the time between the target device transmitting the pulse signal to be measured and receiving the reflected pulse signal to be measured is obtained;

[0152] S105, obtaining a second timing code, and extracting a second simplified code and a second critical code from the second timing code;

[0153] S106, obtaining a state code after the state code of the critical coding unit group from the second simplified code to obtain a third valid state code; and obtaining a state code identical to the first valid state code from the second critical code to obtain a fourth valid state code;

[0154] S107, determining a third timing according to the time when the pulse signal to be tested flows through each delay coding unit and the third valid state code; determining a fourth timing according to the time when the pulse signal to be tested flows through each delay coding unit and the fourth valid state code; the second time is the sum of the third timing and the fourth timing;

[0155] The above S105-S107 realizes the timing of the above second stage (second time), that is, the time from when the target device detects the reflected pulse signal to be measured to when the target device receives the reflected pulse signal to be measured is obtained;

[0156] S108. Determine, according to the third time and the first time, the sum of the third time and the first time as the time from when the target device generates the pulse signal to be tested to when the target device receives the reflected pulse signal to be tested;

[0157] The above S108 realizes the timing of the above first stage and third stage;

[0158] S109, according to the third time and the second time, determining the difference obtained by subtracting the first time from the third time as the time between the target device transmitting the pulse signal to be tested and detecting the reflected pulse signal to be tested;

[0159] The above S109 realizes the timing of the above first stage and second stage;

[0160] The above S101-S109 may be executed by a processor in the timing device and implemented by the timing solution module 3 in the timing system.

[0161] An embodiment of the present application further provides a computer-readable storage medium, which includes a computer program. When the computer program runs on a computer, the method described in the above embodiment is executed.

[0162] An embodiment of the present application further provides a computer program product, which includes computer program instructions. When the computer program instructions are run on a computer, the method described in the above embodiment is executed.

[0163] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0164] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A timing system, characterized in that: Used to time the pulse signal to be measured, the timing system includes: a control module, a fine timing module and a timing solution module connected in sequence; the fine timing module includes a plurality of delay coding unit groups connected in sequence, and each delay coding unit group includes a plurality of delay coding units connected in sequence; The control module is used to control the fine timing module to output a first timing code when the pulse signal to be measured and the first clock signal are in a preset state; the pulse signal to be measured is input from the first input end of the fine timing module, the first clock signal is input from the second input end of the fine timing module, and the control module is connected to the first input end of the fine timing module; the first timing code includes a state code of each delay coding unit in the fine timing module into which the pulse signal to be measured flows; The timing solution module is used to obtain the first timing code output by the fine counting module, and extract a first simplified code and a first critical code from the first timing code; and parse the first simplified code and the first critical code to obtain a first time, wherein the first time is the time from when the target device generates the pulse signal to be tested to when it transmits the pulse signal to be tested; Among them, the first simplified code includes a status code for indicating the status of the delay coding unit group into which the pulse signal to be tested flows, and the first critical code includes the status codes of multiple delay coding units of the critical coding unit group in the delay coding unit group into which the pulse signal to be tested flows, and the time for the pulse signal to be tested to flow through each delay coding unit is equal.

2. The timing system according to claim 1, characterized in that: The preset state is that the pulse signal to be tested is at a high level and the first clock signal is at a rising edge; The target device transmits the pulse signal to be measured at the rising edge of the pulse signal to be measured, and the target device receives the reflected pulse signal to be measured at the rising edge of the reflected pulse signal to be measured.

3. The timing system according to claim 1, characterized in that: The timing solution module is specifically used for: Acquire a state code after the state code of the critical coding unit group from the first simplified code to obtain a first valid state code; and acquire a state code identical to the first valid state code from the first critical code to obtain a second valid state code; Determine a first timing according to the time when the pulse signal to be tested flows through each delay coding unit and the first valid state code; The second timing is determined according to the time for the pulse signal to be tested to flow through each delay coding unit and the second valid state code; the first time is the sum of the first timing and the second timing.

4. The timing system according to claim 1, wherein: Each delay coding unit in the fine timing module includes a delayer and a first register, wherein the first input end of the first register is connected to the output end of the delayer; the input end of the delayer in the first delay coding unit in the fine timing module is coupled to the first input end of the fine timing module, and the second input end of the first register is coupled to the second input end of the fine timing module; the output end of the first register is coupled to the output end of the fine timing module; The multiple delays in the fine timing module are connected in series in sequence to form a carry chain, the output end of each delay is connected to the input end of the next delay, the pulse signal to be tested flows into each delay in the carry chain in sequence, and the output end of each delay outputs the pulse signal to be tested; the output end of each first register outputs the state code of each delay coding unit.

5. The timing system according to claim 1, characterized in that: The control module is further used to control the fine timing module to output a second timing code when the reflected pulse signal to be measured and the second clock signal are in a preset state; The timing solution module is also used to obtain the second timing code output by the fine counting module, and extract the second simplified code and the second critical code from the second timing code; and parse the second simplified code and the second critical code to obtain a second time, wherein the second time is the time from when the target device detects the reflected pulse signal to be measured to when the target device receives the reflected pulse signal to be measured; The second simplified code includes a state code for indicating the states of the plurality of delay coding unit groups, and the second critical code includes state codes of a plurality of delay coding units in a critical coding unit group among the plurality of delay coding unit groups.

6. The timing system according to claim 1 or 3, characterized in that: The timing system further comprises a coarse timing module connected to the control module and the timing solution module, wherein an input end of the coarse timing module is connected to the control module, and an output end of the coarse timing module is connected to the timing solution module; the coarse timing module comprises a second register, and a timer connected to the second register, wherein a first input end of the second register is coupled to an input end of the coarse timing module, a second input end of the second register is connected to an output end of the timer, and an output end of the second register is coupled to an output end of the coarse timing module; The control module is also used to control the second register of the coarse timing module to store the first count of the timer at the rising edge / falling edge of the pulse signal to be measured; and control the second register of the coarse timing module to store the second count of the timer at the rising edge / falling edge of the reflected pulse signal to be measured; The timing solution module is also used to obtain the first count and the second count output by the rough timing module, and determine a third time based on the first count and the second count, wherein the third time is the time between the target device transmitting the pulse signal to be tested and receiving the reflected pulse signal to be tested.

7. The timing system according to claim 6, characterized in that: The timing solution module is also used to determine the time from when the target device generates the pulse signal to be tested to when the target device receives the reflected pulse signal to be tested according to the third time and the first time; Alternatively, the time from when the target device transmits the pulse signal to be measured to when the target device detects the reflected pulse signal to be measured is determined according to the third time and the second time.

8. The timing system according to claim 1, wherein: The timing system includes a plurality of the fine timing modules.

9. A timing device, characterized in that: The timing device comprises a controller, a processor, a delay device, a register and a timer, and each device in the timing device is used to implement the function of each module in the timing system according to any one of claims 1 to 8.

10. A timing method, characterized in that: The timing method is performed by the timing device according to claim 9 to time at least one of the following stages in the transmission process of the pulse signal to be tested: In the first stage, the target device generates the pulse signal to be tested and transmits the pulse signal to be tested; In the second stage, the target device detects the reflected pulse signal to be measured and the target device receives the reflected pulse signal to be measured; In the third stage, the target device transmits the pulse signal to be tested until the target device receives the reflected pulse signal to be tested.

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